Vlisi Course project presentation:Keypad Scanner
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This document describes a keypad scanner project implemented on an FPGA board. It includes the truth table and equations for scanning the keys of a 3x4 keypad to drive 4 LEDs. The Verilog code implements this design using logic gates and assigns statements. The code was submitted by 3 students for their VLSI design course, overseen by instructor Dr. Dipti Sakhare. References on Verilog, digital design, and the FPGA board used are also listed.
![References
[1] Verilog HDL synthesis, A practical primer, Author: J. Bhasker.
[2] Fundamentals of digital logic with Verilog design, Author: Stephen brown, Zvonko Vranesic.
[3] Verilog digital system design,second edition, Author:Zainalabeddin Navabi.
[4] Neil Weste and David Harris, “Principles of CMOS Design”, 4th Edition, Pearson Education, 2010, ISBN:
9780321547743
[5] John F Wakerly, “Digital Design-Principles and Practices”, 4th Edition Pearson education, ISBN :
9780131863897.
[6] Charles H. Roth,“Digital systems design using VHDL”, PWS. ISBN : 978-8131500279.
[7] Samir Palnitkar,” Verilog HDL: A Guide to Digital Design and Synthesis”,2nd Edition Publisher: Prentice
Hall PTR Publication, February 21, 2003, ISBN: 978-0132599702.
[8] Digilent Nexys ddr (Artix 7 based) FPGA board datasheet.](https://image.slidesharecdn.com/vlisiproject-191127153527/85/Vlisi-Course-project-presentation-Keypad-Scanner-10-320.jpg)
Vlisi Course project presentation:Keypad Scanner
- 1. Keypad Scanner Course Project in VLSI Design Chaitanya Deshpande B197001 BETB119 Omkar Rane B197026 BETB118 Nitesh Mandal B197063 BETB108 Submitted by, Course instructor Dr. Dipti Sakhare
- 2. FPGA Board
- 3. C0 C1 C2 Truth Table & Equations: Rows Column LED’s
- 4. module key(input r0, input r1, input r2, input r3,input c0, input c1, input c2,output n3, output n2, output n1, output n0 ); assign n3= (r2 & ~c0) | (r3 & ~c1); assign n2= r1 | (r2 & c0); assign n1=(r0 & ~c0)|(~r2 & c2)|(~r1 & ~r0 & c0); assign n0=(r1 & c1)|(~r1 & c2)|(~r3 & ~r1 & ~c1); endmodule Verilog code in dataflow modelling
- 10. References [1] Verilog HDL synthesis, A practical primer, Author: J. Bhasker. [2] Fundamentals of digital logic with Verilog design, Author: Stephen brown, Zvonko Vranesic. [3] Verilog digital system design,second edition, Author:Zainalabeddin Navabi. [4] Neil Weste and David Harris, “Principles of CMOS Design”, 4th Edition, Pearson Education, 2010, ISBN: 9780321547743 [5] John F Wakerly, “Digital Design-Principles and Practices”, 4th Edition Pearson education, ISBN : 9780131863897. [6] Charles H. Roth,“Digital systems design using VHDL”, PWS. ISBN : 978-8131500279. [7] Samir Palnitkar,” Verilog HDL: A Guide to Digital Design and Synthesis”,2nd Edition Publisher: Prentice Hall PTR Publication, February 21, 2003, ISBN: 978-0132599702. [8] Digilent Nexys ddr (Artix 7 based) FPGA board datasheet.