DDAA FPGA - Multiplexor De Numeros en Display 7 Segmentos En Tiempo
0 likes236 views
This document describes the design of a 4-display multiplexing system to sequentially display the values of a 8-bit incrementing counter. The design includes: 1) An 8-bit incrementing counter module 2) A hexadecimal to 7-segment display decoder 3) A 4-input multiplexer to sequentially activate each display The modules are instantiated and interconnected in a top level module to increment the counter value and sequentially multiplex the output to the four displays on the Nexys 2 board. Simulation waveforms verify the correct functionality of incrementing the counter value and sequentially multiplexing the displays.
DDAA FPGA - Multiplexor De Numeros en Display 7 Segmentos En Tiempo
- 1. qwertyuiopasdfghjklzxcvbnmqwertyui opasdfghjklzxcvbnmqwertyuiopasdfgh jklzxcvbnmqwertyuiopasdfghjklzxcvb nmqwertyuiopasdfghjklzxcvbnmqwer tyuiopasdfghjklzxcvbnmqwertyuiopas dfghjklzxcvbnmqwertyuiopasdfghjklzx cvbnmqwertyuiopasdfghjklzxcvbnmq wertyuiopasdfghjklzxcvbnmqwertyuio pasdfghjklzxcvbnmqwertyuiopasdfghj klzxcvbnmqwertyuiopasdfghjklzxcvbn mqwertyuiopasdfghjklzxcvbnmqwerty uiopasdfghjklzxcvbnmqwertyuiopasdf ghjklzxcvbnmqwertyuiopasdfghjklzxc vbnmqwertyuiopasdfghjklzxcvbnmrty uiopasdfghjklzxcvbnmqwertyuiopasdf ghjklzxcvbnmqwertyuiopasdfghjklzxc Universidad Autónoma de Baja California ECITEC Valle de las Palmas Ingeniería en Electrónica Diseño Digital a Alta Escala Reporte Practica 2 Marcos Marcos Fernando 5 Octubre del 2015
- 2. Planteamiento del problema Diseñar un sistema de multiplex ión en el tiempo que controle 4 displays enrutando 4 señales a una salida. Diseñe un circuito de incremento unitario de 8 bits, como se observa en el siguiente diagrama de la figura 1, y que muestre su salida en los 4 displays del tablero Nexys 2. Figura 1.
- 3. DESARROLLO Se inicio desarrollando cada uno de los programas necesarios para crear el programa final (conjunto de programas o instancias). Incrementador unitario de 8 bits library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity incremento_unitario_8bits is generic(N:integer:=8); PORT( sw1: in STD_LOGIC_VECTOR(N-1 downto 0); swout: out STD_LOGIC_VECTOR(N-1 downto 0) ); end incremento_unitario_8bits; architecture Behavioral of incremento_unitario_8bits is begin swout <= std_logic_vector(unsigned(sw1) + 1); end Behavioral; Convertidor Hexadecimal a siente segmentos library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PRACTICA2_02 is port( hex: in std_logic_vector(3 downto 0); -- dp1: in std_logic; sseg: out std_logic_vector(7 downto 0) end PRACTICA2_02; architecture Behavioral of PRACTICA2_02 is begin process(hex) begin case hex is when "0000" => sseg(6 downto 0) <= "0000001"; --0 when "0001" => sseg(6 downto 0) <= "1001111"; --1 when "0010" => sseg(6 downto 0) <= "0010010"; --2 when "0011" => sseg(6 downto 0) <= "0000110"; --3 when "0100" => sseg(6 downto 0) <= "1001100"; --4 when "0101" =>
- 4. sseg(6 downto 0) <= "0100100"; --5 when "0110" => sseg(6 downto 0) <= "0100000"; --6 when "0111" => sseg(6 downto 0) <= "0001111"; --7 when "1000" => sseg(6 downto 0) <= "0000000"; --8 when "1001" => sseg(6 downto 0) <= "0000100"; --9 when "1010" => sseg(6 downto 0) <= "0001000"; --A when "1011" => sseg(6 downto 0) <= "1100000"; --b when "1100" => sseg(6 downto 0) <= "0110001"; --C when "1101" => sseg(6 downto 0) <= "1000010"; --d when "1110" => sseg(6 downto 0) <= "0110000"; --E when others => sseg(6 downto 0) <= "1111110"; --F end case; end process; sseg(7) <= dp1; end Behavioral; Multiplexor de displays en el tiempo library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity mux4display is Generic(N:integer:=8); PORT( in1,in2,in3,in4: in STD_LOGIC_VECTOR(N-1 downto 0); clk,rst1: in STD_LOGIC; sseg1: out STD_LOGIC_VECTOR(N-1 downto 0); an: out STD_LOGIC_VECTOR(3 downto 0) ); end mux4display; architecture Behavioral of mux4display is CONSTANT N1:integer:=18; signal count1,count: unsigned(N1-1 downto 0); signal sel: std_logic_vector(1 downto 0); signal s1: std_logic_vector(3 downto 0); begin process(clk,rst1) begin if(rst1 = '1') then
- 5. count1 <= (others => '0'); --sseg1 <= "11111111"; an <= "1111"; elsif(clk'event and clk = '1') then count1 <= count; an <= s1; end if; end process; count <= count1 + 1; sel <= STD_LOGIC_VECTOR(count1(N-1 downto N-2)); process(in1,in2,in3,in4,sel) begin case sel is when "00" => sseg1 <= in1; s1 <= "1110"; when "01" => sseg1 <= in2; s1 <= "1101"; when "10" => sseg1 <= in3; s1 <= "1011"; when others => sseg1 <= in4; s1 <= "0111"; end case; end process; end Behavioral; Realizados los programas necesario, ahora solo falta hacer el programa de mayor jerarquía, el cual contendrá las instancias de cada uno de los tres programa anterior, en esta parte lo único que se realiza es la asignación de señales entre cada instancia, el programa realizado es el siguiente. library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity sistem_mux4display_time is PORT( sw: in STD_LOGIC_VECTOR(7 downto 0); clk,rst,dp: in STD_LOGIC; sseg_out: out STD_LOGIC_VECTOR(7 downto 0); an_out: out STD_LOGIC_VECTOR(3 downto 0) );
- 6. end sistem_mux4display_time; architecture Behavioral of sistem_mux4display_time is signal swin,disp1,disp2,disp3,disp4: STD_LOGIC_VECTOR(7 downto 0); begin --INSTANCIA SUMADOR UNITARIO DE 8 BITS sum: entity work.incremento_unitario_8bits(Behavioral) PORT MAP(sw1 => sw, swout => swin); --INSTANCIA HEX_TO_SEG1 hex_to_sseg1: entity work.PRACTICA2_02(Behavioral) PORT MAP(hex => sw(7 downto 4), sseg => disp1, dp1 => dp); --INSTANCIA HEX_TO_SEG2 hex_to_sseg2: entity work.PRACTICA2_02(Behavioral) PORT MAP(hex => sw(3 downto 0), sseg => disp2, dp1 => dp); --INSTANCIA HEX_TO_SEG1 hex_to_sseg3: entity work.PRACTICA2_02(Behavioral) PORT MAP(hex => swin(7 downto 4), sseg => disp3, dp1 => dp); --INSTANCIA HEX_TO_SEG1 hex_to_sseg4: entity work.PRACTICA2_02(Behavioral) PORT MAP(hex => swin(3 downto 0), sseg => disp4, dp1 => dp); --INTANCIA MULTIPLEXOR DE DISPLAYS disp_mux: entity work.mux4display(Behavioral) PORT MAP(in1 => disp1, in2 => disp2, in3 => disp3, in4 => disp4, clk => clk, rst1 => rst, sseg1 => sseg_out, an => an_out); end Behavioral; El esquemático RTL es el siguiente. Figura 2.
- 7. Asignación de pines en PlanAhead Figura 3. Evidencia de Funcionamiento Figura 4. Figura 5.