dokumen.tips_vhdl-0-introduction-to-vhdl.ppt
- 1. VHDL 0 INTRODUCTION TO VHDL K H Wong khwong@cse 3943-8397, Room 907 SHB-Engineering building http://www.cse.cuhk.edu.hk/~khwong/www2/ceng3430/ceng3430.html VHDL 0 (v.6A) : Introduction 1
- 2. CENG3430 Rapid Prototyping of Digital Systems • You will learn: • The hardware description language VHDL • Techniques to build a Logic system e.g. building blocks of a Central Processing Unit (CPU) • High speed logic circuits analysis: time delay estimation, testing, power supply stability, etc. 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch Write VHDL code, then it will generate the hardware chip automatically Example: A VHDL AND-gate Program VHDL 0 (v.6A) : Introduction 2
- 3. A QUICK RUN THROUGH Overview VHDL 0 (v.6A) : Introduction 3
- 4. Overview •What is VHDL used for? • To design • Hardware systems (an industrial standard) • Microprocessors: Arm7 etc. • Design new Digital systems: e.g. mobile phone, camera chips VHDL 0 (v.6A) : Introduction 4
- 5. Motivations • Learn to design digital systems. • Provide knowledge for you to : • Design products: • Robots controllers, media players, portable games, mobile phones. • Advanced examples • Image processing • Computer vision • Super computer • Start a business. VHDL 0 (v.6A) : Introduction 5
- 6. Examples of digital system design • Mass products • Media players • Mobile phones • Novel products • Wearable computer • Robots • Research • Real time edge detection for computer vision VHDL 0 (v.6A) : Introduction 6 www.cnn.com/.../06/10/mars.rover/index.html
- 7. To learn • Design digital processing components using programmable logic • Two existing Methods • (a) Schematic, (too complicated • But is suitable to describe the top level design like a data flow block diagram • (b) Language (e.g. VHDL--Very-High-Speed-Integrated-Circuits Hardware Description Language): Each module in the schematic can be written in VHDL. VHDL 0 (v.6A) : Introduction 7 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch
- 8. DIGITAL DESIGN Work Flow VHDL 0 (v.6A) : Introduction 8
- 9. Digital Design Work Flow • Idea generation • Drafting on paper • Design the chip (use VHDL) • Test • Manufacturing production line design • Quality control VHDL 0 (v.6A) : Introduction 9 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch
- 10. WE USE IN OUR LAB Hardware: FPGA (Field Programmable Gate Array) The hardware can be reprogrammable , so you can change your design rapidly and easily with no additional hardware manufacturing cost. Software: VHDL (Very-High-Speed-Integrated- Circuits Hardware Description Language) VHDL 0 (v.6A) : Introduction 10
- 11. Re-programmable Hardware: FPGAField Programmable GateArray • So what is inside an FPGA • IOB=Input/Output block • CLB=Configurable Logic block (static ram based) • Change the CLBs to get the desired functions VHDL 0 (v.6A) : Introduction 11 From http://www.alldatasheet.co.kr/datasheet- pdf/pdf_kor/49173/XILINX/XCS10-3PC84C.html
- 12. Inside a CLB (Configurable Logic block ) • The CLB is a fixed design but you can change the logic function for generating output from input G1-G4 by reprogramming the bits in the logic function lookup table. • This will change the overall logic function of the CLB • Re-programming the logic table VHDL 0 (v.6A) : Introduction 12 http://www.design-reuse.com/news_img/20100913_1.gif http://pldworld.biz/html/technote/pldesignline/bobz-02.gif CLB FPGA CLB (Configurable Logic block )
- 13. Software: to program an FPGA • VHDL 0 (v.6A) : Introduction 14 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch Use a schematic: (Top level design to merge modules) Use a language VHDL (for each module) or/and
- 14. VHDL 0 (v.6A) : Introduction 15 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch Development cycle VHDL language Schematic (diagram)
- 15. Timing simulation • VHDL 0 (v.6A) : Introduction 16
- 16. Summary of VHDL • For hardware Design • Parallel language (not sequential) • Different! (not the same as C++ or Java) • VHDL is the industrial standard for CE. VHDL 0 (v.6A) : Introduction 17
- 17. An example: “And” gate in VHDL • 1 entity and2 is port (a,b : in std_logic; • 2 c : out std_logic); • 3 end and2 • 4 architecture and2_arch of and2 • 5 begin • 6 c <=a and b; • 7 end and2_arch VHDL 0 (v.6A) : Introduction 18 a b c The chip C<=a and b
- 18. COMPUTER ENGINEERING MARKET and VHDL VHDL 0 (v.6A) : Introduction 19
- 19. TSMC(TaiwanSemicon.ManufacturingComp.) 台灣積體電路製造股份有限公司 http://www.tsmc.com • From Wiki: • Has the largest asset in Taiwan stock market, • One of the World's largest dedicated independent semiconductor foundry. • Products: Apple iphone6 plus A8-cpu • Relation to VHDL • Design ideaWrite VHDL TSMC chips VHDL 0 (v.6A) : Introduction 20
- 20. Huawei Technologies Co. Ltd http://www.huawei.com/en/ • From wiki: • Telecom equipment manufacture • China large private company--http://money.163.com 500 (2011-08- 25) • Products: the second-largest supplier of mobile telecommunications infrastructure equipment in the world (after Ericsson). VHDL 0 (v.6A) : Introduction 21
- 21. References • See course web page • Digital Systems Design Using VHDL, Charles H. Roth (first or second edition) • Rapid Prototyping of Digital Systems, by Hamblen, James etal. Springer 2008. (read_online) • Digital Design: Principles and Practices, 4/E John F. Wakerly, Prentice Hall. • High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham Prentice Hall. • BOOKBOON (Free text books) • http://www.alldatasheet.com/ VHDL 0 (v.6A) : Introduction 22
- 22. APPENDIX VHDL 0 (v.6A) : Introduction 23
- 23. Major companies , a comparison in 2011 (from wiki) • Company Boeing Nestle Honda Toyota Ford HS BC Len ovo BP Sony Revenue US Billion 68.5 125 120 235 128 98. 9 21. 59 308 .9 86.64 Asset 64.3 126 125 370 166 24 54 10. 71 272 .2 155.9 4 Profit US Billion 3.3 39 1.39 5.07 6.56 13. 15 0.2 73 3.3 2.96 VHDL 0 (v.6A) : Introduction 24
- 24. (from wiki) Wiki: 2009年資本額約新台幣2,589.6億元,市值約1兆6,000億元，為台灣股市中市值最大的公司。 http://money.163.com中国民营企业500强榜单发布,华为第一(2011-08-25) • Company Apple IBM Microsoft Intel HP TSMC 台灣積 體電路 (largest asset in Taiwan stock market) Huawei 华为 (Telecom equipm’t, China large private company) Revenue US Billion 65.23 99 69.94 43.6 99.87 13.98 21.8 Asset 75.1 113.5 108.7 63.2 124.5 20.43 Not known Profit US Billion 14.01 14 23.15 11.46 14.83 5.55 2.67 VHDL 0 (v.6A) : Introduction 25
- 25. TRI-STATE LOGIC A revision:’ The concept of tri-state logic is essential in computer design, so we want to revise these techniques before we move on. VHDL 0 (v.6A) : Introduction 26
- 26. Appendix 1:Tri-state logic **At the float state, the wire is cut • VHDL 0 (v.6A) : Introduction 27 Input Output enable (OE) Output Input OE (input) Output 0 0 Z(Float) 1 0 Z(Float) 0 1 0 1 1 1
- 27. Tri-state equivalent circuit (using output connect/cut view) • VHDL 0 (v.6A) : Introduction 28 Input Output enable (OE) Output Input Output enable (OE) Output OE=1, switch close OE=0, switch open Same as
- 28. Alternatively: we can treat the Tri-state equivalent circuit using the Rout impedance view • VHDL 0 (v.6A) : Introduction 29 Input Output enable (OE) Output Input Output enable (OE) Output When OE=1, Rout= small, (e.g. 50 Ω ) When OE=0, Rout=infinity (e.g. 10 MΩ) Same as Rout OE (output enable) controls the value of Rout Tri-state equivalent circuit : Rout impedance view to explain the concept of tri-stat A tri-state circuit diagram
- 29. Student ID: ___________,Date:_____________ Name: _______________ Exercise0.1:Tri-state logic with pull up resistor • VHDL 0 (v.6A) : Introduction 30 Input1 Output-Enable (OE) Output 5V 10K Input1 Output-Enable OE (input) Output 0 0 ? ___ 1 0 ? ___ 0 1 ? ___ 1 1 ? ___ **At float the wire is cut
- 30. Exercise0.2: Use Rout ( Impedance view) to explain the result of exercise 0.1 • VHDL 0 (v.6A) : Introduction 31 Input1 Output- Enable OE (input) Output Equivalent Rout (10M or 50) Draw equivalent circuit and find output Voltage 0 0 ? _1__ ? ? 1 0 ? _1__ ? ? 0 1 ? _0__ ? ? 1 1 ? _1__ ? ? Resistance view
- 31. Exercise 0.3 Application 1 of Tri-state logic: Input/Output pin • OE1 controls the traffic. • Fill in the cells with ‘?’. VHDL 0 (v.6A) : Introduction 32 Directional control(OE1) A B A Output Enable OE1 (input) B 0 0 ? 1 0 ? ? 1 0 ? 1 1
- 32. Exercise 0.4 Application 2 of Tri-state logic: Transceivers for I/O data pins • When T =1, A->B; T controls the traffic, • when /OE=1, IO pins A,B are disabled • Fill in the cells with ‘?’. • VHDL 0 (v.6A) : Introduction 33 A B /OE T T A Output Enable /OE1 (input) B Which controls which 1 0 0 ? ? 0 1 0 ? ? ? ? 1 Float ? ? Float 1 ? ?
- 33. All data-lines are transceiver buffers • A good controller will enable the CPU to • read/write RAM, and read ROM • VHDL 0 (v.6A) : Introduction 34 CPU data lines transceivers ROM data lines RAM data lines transceivers transceivers /OE1, T1 /OE2, T2 /OE3, T3
- 34. Exercise 0.5 : List OE1,2,3 and T1,2,3 for the followings cases • a) CPU writes to RAM: • /OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____ • b) CPU reads from ROM • /OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____ • c) CPU reads from RAM • /OE1=___ , /OE2___, /OE3=___, T1___, T2=____, T3_____ VHDL 0 (v.6A) : Introduction 35 CPU data lines transceivers ROM data lines RAM data lines transceivers transceivers /OE1, T1 /OE2, T2 /OE3, T3 A B A B B A
- 35. Exercise 0.6 Application 3 of Tri-state logic: Selectionofcontrolsignal(resolvedlogic) • Output depends on Input_A if OE is _?___ • Output depends on Input_B if OE is _?___ • Discuss the operation of this circuit. VHDL 0 (v.6A) : Introduction 36 Input_B Input_A Output OE
- 36. Exercise 0.7 • Fill in ‘?’. Is it a “nor-gate” or an “or-gate”? • Discuss the operation of this circuit. • Answer : VHDL 0 (v.6A) : Introduction 37 Output OE2 5V 10K OE1 0V 0V OE1 OE2 Output 0 0 ? 1 0 ? 0 1 ? 1 1 ?