EE8551 mpmc unit 1 module 5

8085
MICROPROCESSORS
BY
MS.K.R.CHAIRMA LAKSHMI
ASSISTANT PROFESSOR
DEAPARTMENT OF ELECTRONCS AND INSTRUMENTATION ENGINEERING
R.M.K ENGINEERING COLLEGE

CONTENT
➢Module 5: Timing Diagram
1.OPCODE FETCH CYCLE (4T)
2.MEMORY READ CYCLE (3 T)
3.MEMORY WRITE CYCLE (3 T)
4.I/O READ CYCLE (3 T)
5.I/O WRITE CYCLE (3 T)
➢ EXAMPLE TIMING DIAGRAMS FOR FEW INSTRUCTIONS
CHAIRMA LAKSHMI K R AP/EIE/RMKEC 2

MODULE 5 : TIMING DIAGRAM
OF 8085

MACHINE CYCLES AND THEIR TIMING OF
8085
Timing Diagram: It represents the execution time taken by each instruction in a
graphical format. The execution time is represented in T-states.
Instruction Cycle: The time required to execute an instruction is called instruction
cycle.
Machine Cycle: The time required to access the memory or input/output devices
is called machine cycle.
T-State: A portion of an operation carried out in one system clock period is called
as T-state.

MACHINE CYCLES OF 8085:
• THE 8085 MICROPROCESSOR HAS 5 (SEVEN) BASIC MACHINE CYCLES. THEY
ARE
1.OPCODE FETCH CYCLE (4T)
2.MEMORY READ CYCLE (3 T)
3.MEMORY WRITE CYCLE (3 T)
4.I/O READ CYCLE (3 T)
5.I/O WRITE CYCLE (3 T)
• INTR ACKNOWLEDGE(3 T)
• BUS IDLE(3 T)

OPCODE FETCH MACHINE CYCLE
• The first step of executing any instruction is the Opcode fetch cycle.
• In this cycle, the microprocessor brings in the instruction’s Opcode from
memory.
• To differentiate this machine cycle from the very similar “memory
read” cycle, the control & status signals are set as follows:
• IO/M=0, s0 and s1 are both 1.
• This machine cycle has four T-states.
• The 8085 uses the first 3 T-states to fetch the opcode.
• T4 is used to decode and execute it.
• It is also possible for an instruction to have 6 T-states in an opcode fetch
machine cycle.

OPCODE FETCHT1 State
During the T1 state, the contents of the program counter are placed on the 16 bit address bus.
The higher order 8 bits are transferred to address bus (A8-A15) and lower order 8 bits are transferred to multiplexed A/D (AD0-AD7) bus.
After the address bits are transferred, the ALE (address latch enable) signal goes high.
 As soon as ALE goes high, the memory latches the AD0-AD7 bus.
At the middle of the T state the ALE goes low and the complete 16-bit address is made available for the Opcode fetch machine cycle.
T2 State
 During the beginning of this state, the RD signal goes low to enable memory.
It is during this state, the selected memory location is placed on D0-D7 of the Address/Data multiplexed bus.
T3 State
In the previous state the Opcode is placed in D0-D7 of the A/D bus.
In this state of the cycle, the Opcode of the A/D bus is transferred to the instruction register of the microprocessor.
Now the RD’ goes high after this action and thus disables the memory from A/D bus.
T4 State
 In this state the Opcode which was fetched from the memory is decoded.

MEMORY READ MACHINE CYCLE
• The memory read machine cycle is exactly the same as the
opcode fetch except:
• It only has 3 T-states
• The s0 signal is set to 0 instead.

T1 state:
The higher order address bus (A8-A15) and lower order address and data multiplexed (AD0-AD7) bus. ALE
goes high so that the memory latches the (AD0-AD7) so that complete 16-bit address are available. The mp
identifies the memory read machine cycle from the status signals IO/M’=0, S1=1, S0=0. This condition indicates
the memory read cycle.
T2 state:
Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus. RD’ goes LOW
T3 State:
The data which was loaded on the previous state is transferred to the microprocessor. In the middle of the T3
state RD’ goes high and disables the memory read operation. The data which was obtained from the memory is
then decoded.

THE MEMORY READ MACHINE CYCLE
• To understand the memory read machine cycle, let’s study the execution of the following instruction:
• MVI A, 32
• In memory, this instruction looks like:
• The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A), the
second byte is the data to be loaded.
• The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it
will need at least two machine cycles.
• The first machine cycle is the opcode fetch discussed earlier.
• The second machine cycle is the Memory Read Cycle.
2000H
2001H
3E
32

THE MEMORY WRITE OPERATION
• In a memory write operation:
• The 8085 places the address on the address bus
• Identifies the operation as a ‘memory write’ (IO/M=0, s1=0, s0=1).
• Places the contents of the accumulator on the data bus and asserts the
signal WR.
• During the last T-state, the contents of the data bus are saved into the
memory location.

T1 state:
The higher order address bus (A8-A15) and lower order address and data multiplexed
(AD0-AD7) bus. ALE goes high so that the memory latches the (AD0-AD7) so that complete
16-bit address are available.
 The mp identifies the memory read machine cycle from the status signals IO/M’=0,
S1=0, S0=1. This condition indicates the memory read cycle.
T2 state:
Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus. WR’ goes
LOW
T3 State:
In the middle of the T3 state WR’ goes high and disables the memory write operation. The
data which was obtained from the memory is then decoded.

I/O READ CYCLE OF 8085
• The I/O Read cycle is executed by the processor to read a data byte from
I/O port or from the peripheral, which is I/O, mapped in the system.
• The processor takes 3T states to execute this machine cycle.
• The IN instruction uses this machine cycle during the execution.

I/O READ CYCLE OF 8085

I/O WRITE MACHINE CYCLE OF 8085
• The I/O write machine cycle is executed by the processor to write a data
byte in the I/O port or to a peripheral, which is I/O, mapped in the system.
• The processor takes 3T states to execute this machine cycle.

I/O WRITE MACHINE CYCLE OF 8085

MVI B, data

8085 TIMING DIAGRAM FOR OPCODE FETCH CYCLE FOR MOV C, A .

INR M

ADD M

STA addr

IN Byte

RELATION BETWEEN INSTRUCTION
AND MACHINE CYCLE
Clock Signal Representation:
The 8085 divides the clock frequency provided at X1 and
X2 inputs by 2, which is called operating frequency.

TIMING DIAGRAM FOR MEMORY READ
MACHINE CYCLE

TIMING DIAGRAM FOR MEMORY
WRITE MACHINE CYCLE

I/O PORTS
There are two methods in which I/O devices can be connected to microprocessor.
• Memory mapped I/O
• I/O mapped I/O
Memory mapped I/O:
• In this method I/O device is treated like the memory. Here there is no IO/M signal.
• If the processor wants to read the data from a I/O device it will place the address of the I/O device on
the address bus.
• Then the I/O device will get selected. The memory which is having the same address will also get
selected. Hence we have to use separate address for memory and separate address for I/O device.
I/O mapped I/O:
• Here we have the IO/M signal. So we can select either the memory or I/O device for read and write
operation.CHAIRMA LAKSHMI K R AP/EIE/RMKEC 31

OTHER MODULES
• Module 1: Introduction of 8085
• Module 2: Architecture of & Pinout diagram 8085
• Module 3: Interrupts
• Module 4: Data transfer Concepts
• Module 5: Timing Diagram
• Module 6: Memory Organization

THANK YOU

EE8551 mpmc unit 1 module 5

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EE8551 mpmc unit 1 module 5