EE8551 mpmc unit 1 module 3
- 1. 8085 MICROPROCESSORS BY MS.K.R.CHAIRMA LAKSHMI ASSISTANT PROFESSOR DEAPARTMENT OF ELECTRONCS AND INSTRUMENTATION ENGINEERING R.M.K ENGINEERING COLLEGE
- 2. CONTENT • Module 3: Interrupts • HARDWARE INTERRUPTS • SOFTWARE INTERRUPTS CHAIRMA LAKSHMI K R AP/EIE/RMKEC 2
- 4. FIVE HARDWARE INTERRUPTS IN 8085 TRAP RST 7.5 RST 6.5 RST 5.5 INTRCHAIRMA LAKSHMI K R AP/EIE/RMKEC 4
- 5. INTERRUPT 12 • It means interrupting the normal execution of the microprocessor. • When microprocessor receives interrupt signal, it discontinues whatever it was executing. • It starts executing new program indicated by the interrupt signal. • Interrupt signals are generated by external peripheral devices. • After execution of the new program, microprocessor goes back to the previous program. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 5
- 6. SEQUENCE OF STEPS WHENEVER THERE IS AN INTERRUPT Microprocessor completes execution of current instruction of the program. PC contents are stored in stack. PC is loaded with address of the new program. After executing the new program, the microprocessor returns back to the previous program. It goes to the previous program by reading the top value of stack. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 6
- 7. FIVE HARDWARE INTERRUPTS IN 8085 TRAP RST 7.5 RST 6.5 RST 5.5 INTRCHAIRMA LAKSHMI K R AP/EIE/RMKEC 7
- 8. CLASSIFICATION OF INTERRUPTS Maskable and Non-Maskable Vectored and Non-Vectored Edge Triggered and Level Triggered Priority Based Interrupts CHAIRMA LAKSHMI K R AP/EIE/RMKEC 8
- 9. MASKABLE INTERRUPTS Maskable interrupts are those interrupts which can be enabled or disabled. Enabling and Disabling is done by software instructions. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 9
- 10. MASKABLE INTERRUPTS List of Maskable Interrupts: • RST 7.5 • RST 6.5 • RST 5.5 • INTRCHAIRMA LAKSHMI K R AP/EIE/RMKEC 10
- 11. NON-MASKABLE INTERRUPTS The interrupts which are always in enabled mode are called non- maskable interrupts. These interrupts can never be disabled by any software instruction. TRAP is a non-maskable interrupt. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 11
- 12. VECTORED INTERRUPTS The interrupts which have fixed memory location for transfer of control from normal execution. Each vectored interrupt points to the particular location in memory. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 12
- 13. VECTORED INTERRUPTS List of vectored interrupts: • RST 7.5 • RST 6.5 • RST 5.5 • TRAPCHAIRMA LAKSHMI K R AP/EIE/RMKEC 13
- 14. VECTORED INTERRUPTS The addresses to which program control goes: Absolute address is calculated by multiplying the RST value with 0008 H. Other name for TRAP is RST 4.5 Name VectoredAddress RST 7.5 003C H (7.5 x 0008 H) RST 6.5 0034 H (6.5 x 0008 H) RST 5.5 002C H (5.5 x 0008 H) TRAP 0024 H (4.5 x 0008 H) CHAIRMA LAKSHMI K R AP/EIE/RMKEC 14
- 15. NON-VECTORED INTERRUPTS The interrupts which don't have fixed memory location for transfer of control from normal execution. The address of the memory location is sent along with the interrupt. INTR is a non-vectored interrupt. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 15
- 16. EDGE TRIGGERED INTERRUPTS The interrupts which are triggered at leading or trailing edge are called edge triggered interrupts. RST 7.5 is an edge triggered interrupt. It is triggered during the leading (positive) edge. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 16
- 17. LEVEL TRIGGERED INTERRUPTS The interrupts which are triggered at high or low level are called level triggered interrupts. RST 6.5 RST 5.5 INTR TRAP is edge and level triggered interrupt. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 17
- 18. PRIORITY BASED INTERRUPTS Whenever there exists a simultaneous request at two or more pins then the pin with higher priority is selected by the microprocessor. Priority is considered only when there are simultaneous requests. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 18
- 19. PRIORITY BASED INTERRUPTS Priority of interrupts: Interrupt Priority TRAP 1 RST 7.5 2 RST 6.5 3 RST 5.5 4 INTR 5 CHAIRMA LAKSHMI K R AP/EIE/RMKEC 19
- 20. TRAP Pin 6 (Input) It is an non-maskable interrupt. It has the highest priority. It cannot be disabled. It is both edge and level triggered. It means TRAP signal must go from low to high. And must remain high for a certain period of time. TRAP is usually used for power failure and emergency shutoff. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 20
- 21. RST 7.5 Pin 7 (Input) It is a maskable interrupt. It has the second highest priority. It is positive edge triggered only. The internal flip-flop is triggered by the rising edge. The flip-flop remains high until it is cleared by RESET IN. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 21
- 22. RST 6.5 Pin 8 (Input) It is a maskable interrupt. It has the third highest priority. It is level triggered only. The pin has to be held high for a specific period of time. RST 6.5 can be enabled by EI instruction. It can be disabled by DI instruction. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 22
- 23. RST 5.5 Pin 9 (Input) It is a maskable interrupt. It has the fourth highest priority. It is also level triggered. The pin has to be held high for a specific period of time. This interrupt is very similar to RST 6.5. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 23
- 24. INTR Pin 10 (Input) It is a maskable interrupt. It has the lowest priority. It is also level triggered. It is a general purpose interrupt. By general purpose we mean that it can be used to vector microprocessor to any specific subroutine having any address. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 24
- 25. INTA Pin 11 (Output) It stands for interrupt acknowledge. It is an out going signal. It is an active low signal. Low output on this pin indicates that microprocessor has acknowledged the INTR request. CHAIRMA LAKSHMI K R AP/EIE/RMKEC 25
- 26. TYPES OF INTERRUPT INTERR UPT VECTOR ADDRESS MASKABLE / NON- MASKABLE INTERRUPT VECTOR / NON VECTOR INTERRUPT HARDWARE INTERRUPT TRAP 0024 Non-Maskable Interrupt Vector interrupt RST7.5 003C Maskable Interrupt Vector interrupt RST6.5 0034 Maskable Interrupt Vector interrupt RST5.5 002C Maskable Interrupt Vector interrupt INTR NON Maskable Interrupt Non Vector interrupt SOFTWARE INTERRUPT RST0 0000 Non-Maskable Interrupt Vector interrupt RST1 0008 Non-Maskable Interrupt Vector interrupt RST2 0010 Non-Maskable Interrupt Vector interrupt RST3 0018 Non-Maskable Interrupt Vector interrupt RST4 0020 Non-Maskable Interrupt Vector interrupt RST5 0028 Non-Maskable Interrupt Vector interrupt RST6 0030 Non-Maskable Interrupt Vector interrupt RST7 0038 Non-Maskable Interrupt Vector interrupt CHAIRMA LAKSHMI K R AP/EIE/RMKEC 26
- 27. OTHER MODULES • Module 1: Introduction of 8085 • Module 2: Architecture of & Pinout diagram 8085 • Module 4: Data transfer Concepts • Module 5: Timing Diagram • Module 6: Memory Organization CHAIRMA LAKSHMI K R AP/EIE/RMKEC 27
- 28. THANK YOU CHAIRMA LAKSHMI K R AP/EIE/RMKEC 28