Microcontroller 8085.ppt mmmmmmmmmmmmmmmmmm

Interrupts
2
 Interrupt is a process where an external device can get the
attention of the microprocessor.
 The process starts from the I/Odevice
 The process is asynchronous, means can occur at any time
during execution of program.
 In order to communicate with μP & I/O devices either Polling
or Interrupt method isused.
 An interrupt is considered to be an emergency signal. The
Microprocessorshould respond to itas soon as possible.

1. Polling Method
3
 In polling, μP polls i.e. ask each device in sequence whether it is ready
for communication (datatransfer).
 If device is ready, thendata transfertakes place betweendevice & μP.
 If device is not ready or completed its data transfer, then μP asks the
next device inchain.
 Main disadvantage of this method is that most of the time μP
remains busy in polling. So someuseful tasksget less time toexecute.
 This method is useful only if μP hascontains few I/O devices.

2. Interrupt Method
 Interrupt is signal send by an external device to the microprocessor to request
the processorto perform a particular task orwork.
 It is a simple routine program that keeps a check for the occurrence of the
interrupt.
 Mainly in the microprocessor based system the interrupts are used for data
transfer between the peripheral (I/O) and themicroprocessor.
 If the μP accept the interrupt and send the INTA (active low) signal to the
peripheral.
 When interrupt is received, μP suspends its current activity and upon
completion, it resumes the suspendedactivity.
 The processor executes an interrupt service routine (ISR) addressed in program
counter.
 It returned to main program by RETinstruction.
4Advantage is that μP need notwaste time in polling thedevices.

Interrupt Process
5
1. When the MPU is executing a program it checks all the interrupt lines during the execution of each
instruction.
2. If any Interruptline is enables, theprocessorcompletesthecurrentgoing instruction execution.
3. If more than one lines are enabled simultaneously then the processor pick up the request which have
the highestpriorityand all otherarediscarded.
4. After completion of the current instruction execution, processor checks for the respective conditions
fortheactivated interruptorselected interruptin caseof morethanone.
5. If condition are not favorable then request is discarded or stored or if the condition are favorable then
the processor generates an external INTA or internal acknowledges signal to insert a RST(restart)
instruction or the vector location respectively.
6. Now the processor save the address of the next instruction (program counter value) on to stack and
switch to the related RST location or vector location.
7. Service routine written on the location is completed which have RET as its last instruction which
returns theprogram controlto the main program by retrieving thereturnaddressfrom thestack.

Types of Interrupt
7
 Software Interrupt [RST-restart]
 Hardware Interrupt [TRAP, RST7.5,
RST6.5, RST5.5,INTR]

1. Software Interrupt:
8
 It is a instruction based Interruptwhich iscompletelycontrol by software.
 That means programmer can use this instruction to execute interrupt in
main program.
 There are eight software interrupt available in μP that are RST0 to RST7.
Thevectoraddress for these interruptscan becalculateas
Interrupt number * 8 = vectoraddress
For RST 5 5*8 = 40(in decimal) =28H (inHexa)
Vector address for interrupt RST5 is 0028H. This vector address is stored in
ProgramCounter(PC).
 These instruction allow transfer of program control from the main program
to predefined service routine is also referred to as ISR(Interrupt Service
Routine).

Software Interrupt…cont..
See the example with their hex code and vector address.
RST n Interrupt vectoraddress
9

2. Hardware Interrupt:
 This interrupt is caused by sending a signal on one of the interrupt pins of
the microprocessor.
 An external device initiates the hardware interrupts and placing an
appropriatesignal at the interruptpin of the processor.
 If the interrupt is accepted then the process or executes an interruptservice
routine (ISR).
 Hardware interrupt is Asynchronous(itcan occuratany time).
 The 8085 has five hardwareinterrupts
(1)TRAP
(2)RST7.5
(3)RST6.5
(4)RST5.5
(5)INTR(address is suppliedexternally)
10

8085 Interrupts
8085
TRAP
RST7.5
RST6.5
RST5.5
INTR
INTA
11

Hardware Interrupt.. cont..
12
The hardware interrupts are classifiedTwotypes–
(1)Maskable Interrupts (Can be delayed or Rejected) :
 An interruptwhich can be disabled by software that means we can disable the
interrupt bysending appropriate instruction, is called a maskable interrupt.
 RST 7.5, RST 6, RST 5.5 , INT R are theexampleof Maskable Interrupt.
(2)Non-Maskable Interrupts (Can not bedelayed or Rejected):
 Cannot disable the interrupt by sending any instruction is called Non Maskable
Interrupt.
 TRAP interrupt is the non-maskable interrupt for 8085. It means that if an
interrupt comes via TRAP, 8085 will have to recognize the interrupt we cannot
mask it.

Hardware Interrupt... cont..
13
Interrupts can also beclassified into:
(1) Vectored (theaddressof the serviceroutineis hard-wired) :
 In vectored interrupts, the processorautomatically branches to the specific address in
responseto aninterrupt.
 In vectored interrupts, the manufacturer fixes the addressof the ISR to which the
program control is to betransferred.
 The TRAP, RST 7.5, RST 6.5 and RST 5.5 arevectored interrupts.
(1) Non-Vectored (the addressof the service routine needs to be supplied externally by
thedevice):
 In non-vectored interruptsthe interrupted device should give theaddressof the
interrupt service routine(ISR).
 The INTR is a non-vectored interrupt. Hencewhen a device interrupts through INTR, it
has tosupply theaddressof ISR afterreceiving interruptacknowledge signal.

Interrupts
14
What happens when MP is interrupted?
When the Microprocessor receives an interrupt signal, it
suspends the currently executing program and jumps to
an Interrupt Service Routine (ISR) to respond to the
incoming interrupt.
Each interruptwill most probably have its own ISR.

Interrupt.. cont..
15
What happenswhen MP is responded to interrupt?
 Responding to an interrupt may be immediateor delayed depending on whether the
interruptis maskableor non-maskableand whetherinterruptsare being maskedor not.
 There are two ways of redirecting the execution to the ISR depending on whether the
interrupt is vectored ornon-vectored.
 Thevectoris already known to the Microprocessor
 Thedevicewill have tosupplythevectorto the Microprocessor.
 The maskable interrupt process in the 8085 is controlled by a single flip flop inside
the microprocessor. This Interrupt Enable flip flop is controlled using the two
instructions “EI” and “DI”.
 The 8085 has a single Non-Maskable interrupt. The non-maskable interrupt is not
affected by thevalueof the Interrupt Enable flip flop.

Interrupt.. cont..
16
When a device interrupts, it actually wants the MP to give a
service which is equivalent to asking the MP to call a
subroutine. This subroutine is called ISR (Interrupt Service
Routine).
This interrupts can be enable and disable by using EI (enable
interrupt) & DI (disable interrupt) instructions.
The ‘EI’ instruction is a one byte instruction and is used to
Enable the non-maskableinterrupts.
The ‘DI’ instruction is a one byte instruction and is used to
Disable the non-maskableinterrupts.

Enable Interrupt(EI)
17
 The interrupt process is enable by using EI instruction in the
main program.
 It is 1-byte instruction.
 It enables the interruptprocess.
 Enabling will save the current status and jumps to an interrupt
service routine (ISR). After completion it will return back to the
main programagain.

Disable Interrupt(DI)
18
 This DI instruction is used to disable theinterrupt.
 It is 1-byte instruction.
 This instruction reset the interrupt enable and disables the
interrupt.
 Both EI & DI are used to enable and disable the interrupts. If the
interrupt is masked (disabled), they will not be recognized by
microprocessor.
 Toenable Itagain they must be unmasked (enabled) by using EI.

8085 Interrupt
19
Interrupt name Maskable Vectored
INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes

TRAP
20
 This interrupt is a Non-Maskable interrupt. It is unaffected by any mask or interrupt
enable.
 TRAP is the highest priority and vectored interrupt (as vector address is fixed i.e.memory
location where to transfercontrol).
 TRAP interrupt is edge and level triggered. This means that the TRAP must go high and
remain high until it isacknowledged.
 In sudden power failure, it executes a ISR and send the data from main memory to back
up memory.
 The signal, which over rides the TRAP, is HOLD signal. (i.e., If the process or receives
HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is
recognized).However, TRAP has lower priority than the HLD signal used for DMA.
 Thereare two ways toclearTRAP interrupt.
1. By resetting microprocessor (Externalsignal)
2. Bygiving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5
21
 The RST7.5 interrupt is a Maskableinterrupt.
 It has the second highestpriority.
 It is edge sensitive .i.e. Input goes to high and no need to
maintain high state until itrecognized.
 Maskable interrupt. It is disabled by,
1. DI instruction
2. System or process orreset.
3. After reorganization of interrupt.

RST 6.5 and 5.5
22
 The RST 6.5 AND 5.5 interrupt is a Maskableinterrupt.
 It RST 6.5 has the third and RST 5.5 has forth highestpriority.
 It is level triggered. i.e. Input goes to high stay high state until
it recognized.
 Enable by EI instruction.
 Maskable interrupt. It is disabled by,
1. DI, SIM instruction

INTR
23
 The INTR interrupt is a Maskable interrupt. It is disabled by,
1. DI, SIM instruction
 Enable by EI instruction. Has lowest Priority.
 Non-Vectored interrupt After receiving INTA(active low) Signal, It has to supply the address of ISR. It is a
level sensitive interrupts .i.e. Input goes to high and it is necessary to maintain high state until it recognized.
 The following sequenceof events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high , then 8085 complete its current instruction and sends active low interrupt
acknowledge signal, if the interrupt isenabled
3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data
bus. In the case of multi byte instruction, additional interrupt acknowledge machine cycles are
generated by the 8085 to transferthe additional bytes in to the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute
received instruction.

Interrupt Vectors & the VectorTable
An interrupt vector is a pointer to where the ISR is stored
in memory.
All interrupts (vectored or otherwise) are mapped onto a
memory areacalled the Interrupt VectorTable (IVT).
 The IVT is usually located in (0000H -00FFH).
Vector Address = Interrupt number *8
24
Interrupt Name Calculation VectorAddress
INTR -- --
TRAP ( RST 4.5) 4.5x8=36(Decimal)) 0024H(Hexa)
RST 5.5 5.5x8=44 002CH
RST 6.5 6.5x8=52 0034H
RST 7.5 7.5x8=60 003CH

The 8085 Interrupts
Interrupt
Name
Maskable
Masking
Method
Vectored Priority
ISR
address
Triggering
Method
TRAP No None Yes
1st
(Highest)
0024H
Level & Edge
Sensitive
RST 7.5 Yes
DI / EI
SIM
Yes 2nd
003CH
Positive Edge
Sensitive
RST 6.5 Yes
DI / EI
SIM
Yes 3rd 0034H Level Sensitive
RST 5.5 Yes
DI / EI
SIM
Yes 4th 002CH Level Sensitive
INTR Yes DI / EI No 5th (lowest)
Nospecific
location
Level Sensitive
Level Triggered:- The signal at these pins must be maintained until the interrupt is acknowledged. External
interrupt request flip-flops arerequired.
Edge Triggered: - Only a pulse is required to set the interrupt request  this request is remembered until the
8085A responds to the interrupt or until the request is reset by the SIM instruction or a /RESET IN signal. The
interrupt request flip-flops for RST7.5 is internal to the microprocessor.
25

26
1. The interrupt process should be enabled using the EIinstruction.
2. The 8085 checks for an interrupt during the execution of everyinstruction.
3. If INTR is high, MP completescurrent instruction, disables the interruptand sends INTA
(Interrupt acknowledge) signal to the device thatinterrupted
4. INTA allowsthe I/O device tosend a RST instruction throughdata bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the
stack and the program is transferred to ‘call’ location (ISR Call) specified by the RST
instruction.
6. Microprocessor Performs theISR.
7. ISR must includethe ‘EI’ instruction toenable the furtherinterruptwithin theprogram.
8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the
stackand theprogram is transferred back towheretheprogramwas interrupted.
The 8085 Non-Vectored Interrupt Process

The 8085 Maskable/Vectored Interrupt
Process
1. The interrupt process should be enabled using the EIinstruction.
2. The 8085 checks foran interruptduring theexecutionof every instruction.
3. If there is an interrupt, and if the interruptis enabled using the interrupt mask, the
microprocessor will complete the executing instruction, and reset the interrupt flipflop.
4. The microprocessor then executesa call instruction that sends the execution to the
appropriate location in the interruptvectortable.
5. When the microprocessorexecutes the call instruction, it saves the address of the next
instruction on thestack.
6. The microprocessor jumps to the specific serviceroutine.
7. Theserviceroutinemust includethe instruction EI tore-enabletheinterruptprocess.
8. At the end of the service routine, the RET instruction returns the execution to where the
program was interrupted.
27

SIM for interrupt
 8085 providethe additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using SIM
instruction.
 The status of these interruptscan be read by executing RIMinstruction.
 The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interruptscan be performed by
moving an 8-bit data to accumulator and thenexecuting SIM instruction.
 The format of the 8 bit data isshown below
28

RIM for interrupt
pending interrupts can be read from accumulator after executing RIM
 The status of
instruction.
2 Identify pending interrupts (bit 6, 5, 4).
 Actually RIM does the following threetasks:
1 Read the interrupt mask (bit 2, 1, 0).
3 Receive serial input data bit (bit7).
 When RIM instruction is executed an 8-bit data is loaded in accumulator, which can be
interpreted as shown infig.
29

The 8085 Maskable/Vectored
Interrupts
30
 The 8085 has 4 Masked/Vectored interruptinputs.
 RST 5.5, RST 6.5, RST 7.5
 They are allmaskable.
 Theyareautomaticallyvectored according to the following table:
 The vectors for these interrupt fall in between the vectors for the
RST instructions. That’s why they have names like RST 5.5 (RST 5
and a half).
Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

Masking RST 5.5, RST 6.5 and RST
7.5
31
 These three interrupts are masked at two levels:
 Through the Interrupt Enable flip flop and the EI/DI
instructions.
 The InterruptEnable flip flopcontrolsthewholemaskable
interruptprocess.
 Through individual mask flip flops thatcontrol the
availability of the individual interrupts.
 Theseflip flops control the interrupts individually.

Maskable Interrupts and vector
locations
Interrupt
Enable
Flip Flop
INTR
RST 5.5
RST 6.5
RST 7.5
M 5.5
M 6.5
M 7.5
RST7.5 Memory
32
** See Fig 12.5 ofthe
Text Book for a
detailed look

The 8085 Maskable/Vectored Interrupt Process
33
1. The interrupt process should be enabled using theEI
instruction.
2. The 8085 checks foran interruptduring theexecution
of every instruction.
3. If there is an interrupt, and if the interrupt isenabled
using the interrupt mask, the microprocessor will
complete the executing instruction, and reset the
interrupt flip flop.
4. The microprocessor then executes a call instruction
that sends the execution to the appropriate locationin
the interrupt vectortable.

The 8085 Maskable/Vectored Interrupt Process
34
5. When the microprocessor executes the callinstruction,
it saves the addressof the next instruction on the stack.
6. The microprocessor jumps to the specificservice
routine.
7. The service routine must include the instruction EIto
re-enable the interruptprocess.
8. At the end of the service routine, the RETinstruction
returns the execution to where the program was
interrupted.

Manipulating the Masks
35
 The Interrupt Enable flip flop is manipulated using
the EI/DI instructions.
 The individual masks for RST 5.5, RST 6.5 and RST 7.5
are manipulated using the SIM instruction.
 This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt mask
enabling and disabling the specificinterrupts.

How SIM Interprets the
Accumulator
SDO
SDE
XXX
R7.5
MSE
M7.5
M6.5
M5.5
7 6 5 4 3 2 1 0
RST5.5 Mask
RST6.5 Mask
RST7.5 Mask
}1 -Available
2 - Masked
Mask Set Enable
0 - Ignore bits 0-2
1 - Set the masks according
to bits 0-2
Force RST7.5 Flip Flop to reset
Not Used
Enable Serial Data
0 - Ignore bit 7
1 - Send bit 7 to SOD pin
Serial Data Out
36

SIM and the Interrupt Mask
37
 Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit
2 is the mask for RST7.5.
 If the mask bit is 0, the interrupt isavailable.
 If the mask bit is 1, the interrupt ismasked.
 Bit 3 (Mask Set Enable - MSE) is an enable forsetting the mask.
 If it is set to 0 the mask is ignored and the old settings remain.
 If it is set to 1, the newsetting areapplied.
 The SIM instruction is used for multiple purposes and notonly for
setting interrupt masks.
 It is alsoused tocontrol functionalitysuch as Serial DataTransmission.
 Therefore, bit 3 is necessaryto tell the microprocessor whetheror not the
interrupt masks should bemodified

SIM and the Interrupt Mask
38
 The RST 7.5 interrupt is theonly 8085 interruptthat has
memory.
 If a signal on RST7.5 arriveswhile it is masked, a flip flop will
remember thesignal.
 When RST7.5 is unmasked, the microprocessor will beinterrupted
even if thedevice has removed the interruptsignal.
 This flip flop will be automaticallyresetwhen the microprocessor
responds to an RST 7.5interrupt.
 Bit 4 of the accumulator in the SIM instruction allows explicitly
resetting the RST 7.5 memoryeven if the microprocessordid not
respond to it.
 Bit 5 is not used by the SIMinstruction

Using the SIM Instruction to Modify the InterruptMasks
39
0 0 0 0 1 0 1 0
SDO
SDE
XXX
R7.5
MSE
M7.5
M6.5
M5.5
 Example: Set the interrupt masksso that RST5.5 is
enabled, RST6.5 is masked, and RST7.5 isenabled.
- E
n
a
Fb
l
ie
r5
s.
t5
,determine thb
ei
t0c=o0ntentsof the accumulator
- Disable 6.5
- Enable 7.5
- Allow setting the masks
- Don’t reset the flip flop
- Bit 5 is not used
- Don’t use serial data
- Serial data is ignored
bit 1 = 1
bit 2 = 0
bit 3 = 1
bit 4 = 0
bit 5 = 0
bit 6 = 0
bit 7 = 0
Contents of accumulator are:0AH
EI
MVI A, 0A
SIM
; Enable interrupts including INTR
; Prepare the mask to enable RST 7.5, and 5.5, disable6.5
; Apply the settings RSTmasks

Triggering Levels
40
 RST 7.5 is positive edgesensitive.
 When a positive edge appears on the RST7.5 line, a logic 1 is
stored in the flip-flop as a “pending” interrupt.
 Since the value has been stored in the flip flop, the line does
not have to be high when the microprocessor checks for the
interrupt to berecognized.
 The line must go to zero and back to one before a new
interrupt isrecognized.
 RST 6.5 and RST 5.5 are levelsensitive.
 The interrupting signal must remain present until the
microprocessorchecks forinterrupts.

Determining the Current Mask
Settings
 RIM instruction: Read Interrupt Mask
 Load theaccumulator with an 8-bitpatternshowing the
as
RST 5.5
RST 6.5
status of each interrupt R
pS
iT
n7
.
a5
ndm
M 5.5
Interrupt Enable
Flip Flop
M 6.5
M 7.5
kR
.ST7.5Memory
SDI
P7.5
P6.5
P5.5
IE
M7.5
M6.5
M5.5
7 6 5 4 3 2 1 0
41

How RIM sets the Accumulator’s different bits
SDI
P7.5
P6.5
P5.5
IE
M7.5
M6.5
M5.5
7 6 5 4 3 2 1 0
RST5.5 Mask
RST6.5 Mask
RST7.5 Mask
}1 -Available
2 - Masked
Interrupt Enable
Value of the Interrupt Enable
Flip Flop
Serial Data In
RST5.5 Interrupt Pending
42

The RIM Instruction and the Masks
43
 Bits 0-2 show the current setting of the mask foreach
of RST 7.5, RST 6.5 and RST5.5
 Theyreturnthecontentsof thethreemask flip flops.
 Theycan beused bya program to read the mask settings in
orderto modify only therightmask.
 Bit 3 showswhetherthe maskable interrupt process is
enabled ornot.
 Itreturnsthecontentsof the InterruptEnable Flip Flop.
 Itcan beused bya program todeterminewhetheror not
interrupts areenabled.

The RIM Instruction and the Masks
44
 Bits 4-6 show whetheror not thereare pending
interrupts on RST 7.5, RST 6.5, and RST5.5
 Bits 4 and 5 return thecurrentvalueof the RST5.5 and RST6.5
pins.
 Bit 6 returnsthecurrentvalueof the RST7.5 memory flip flop.
 Bit 7 is used for Serial DataInput.
 The RIM instruction readsthevalueof the SID pin on the
microprocessorand returns it in thisbit.

Pending Interrupts
45
 Since the 8085 has five interrupt lines, interruptsmay
occurduring an ISR and remain pending.
 Using the RIM instruction, it is possible tocan read the
status of the interrupt lines and find if there are any
pending interrupts.
 See the example of theclass

Microcontroller 8085.ppt mmmmmmmmmmmmmmmmmm

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