![Mohd. Moinul Hoque,
Lecturer, CSE, AUST
Issues in Implementing INTR Interrupts
15
How long must INTR remain high?
The microprocessor checks the INTR line one clock cycle before the
last T-state of each instruction.
The INTR must remain active long enough to allow for the longest
instruction.
The longest instruction for the 8085 is the conditional CALL
instruction which requires 18 T-states.
Therefore, the INTR must remain active for 17.5 T-states.
If f= 3MHZ then T=1/f and so, INTR must remain active for
[ (1/3MHZ) * 17.5 ≈ 5.8 micro seconds].](https://image.slidesharecdn.com/mippt-161015113056/85/Types-of-Interrupts-with-details-Mi-ppt-15-320.jpg)
Types of Interrupts with details Mi ppt
- 1. MAHATMA GANDHI INSTITUTE OF TECHNICAL EDUCATION & RESEARCH CENTER ELECTRONICS & COMMUNICATIONELECTRONICS & COMMUNICATION SUB:MICROPROCESSOR AND INTERFACING 2ND YEAR (4TH SEM)
- 2. ENROLLMENT NO. : NAME: 140330111001 AMETA KRUSHNAKANT G. 140330111009 POTTBATNI SANJAY A. 140330111012 YAGNIK GAGAN R. Guided by: Prof.Sapna Garde
- 3. TYPE OF INTERRUPTS WITHTYPE OF INTERRUPTS WITH DETAILSDETAILS
- 4. Mohd. Moinul Hoque, Lecturer, CSE, AUST Interrupts 4 Interrupt is a process where an external device can get the attention of the microprocessor. The process starts from the I/O device The process is asynchronous. Classification of Interrupts Interrupts can be classified into two types: Maskable Interrupts (Can be delayed or Rejected) Non-Maskable Interrupts (Can not be delayed or Rejected) Interrupts can also be classified into: Vectored (the address of the service routine is hard-wired) Non-vectored (the address of the service routine needs to be supplied externally by the device)
- 5. Mohd. Moinul Hoque, Lecturer, CSE, AUST Interrupts 5 An interrupt is considered to be an emergency signal that may be serviced. The Microprocessor may respond to it as soon as possible. What happens when MP is interrupted ? When the Microprocessor receives an interrupt signal, it suspends the currently executing program and jumps to an Interrupt Service Routine (ISR) to respond to the incoming interrupt. Each interrupt will most probably have its own ISR.
- 6. Mohd. Moinul Hoque, Lecturer, CSE, AUST Responding to Interrupts 6 Responding to an interrupt may be immediate or delayed depending on whether the interrupt is maskable or non- maskable and whether interrupts are being masked or not. There are two ways of redirecting the execution to the ISR depending on whether the interrupt is vectored or non-vectored. Vectored: The address of the subroutine is already known to the Microprocessor Non Vectored: The device will have to supply the address of the subroutine to the Microprocessor
- 7. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Interrupts 7 When a device interrupts, it actually wants the MP to give a service which is equivalent to asking the MP to call a subroutine. This subroutine is called ISR (Interrupt Service Routine) The ‘EI’ instruction is a one byte instruction and is used to Enable the non-maskable interrupts. The ‘DI’ instruction is a one byte instruction and is used to Disable the non-maskable interrupts. The 8085 has a single Non-Maskable interrupt. The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop.
- 8. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Interrupts 8 The 8085 has 5 interrupt inputs. The INTR input. The INTR input is the only non-vectored interrupt. INTR is maskable using the EI/DI instruction pair. RST 5.5, RST 6.5, RST 7.5 are all automatically vectored. RST 5.5, RST 6.5, and RST 7.5 are all maskable. TRAP is the only non-maskable interrupt in the 8085 TRAP is also automatically vectored
- 9. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Interrupts Interrupt name Maskable Vectored INTR Yes No RST 5.5 Yes Yes RST 6.5 Yes Yes RST 7.5 Yes Yes TRAP No Yes 9
- 10. Mohd. Moinul Hoque, Lecturer, CSE, AUST 8085 Interrupts 10 8085 TRAP RST7.5 RST6.5 RST 5.5 INTR INTA
- 11. Mohd. Moinul Hoque, Lecturer, CSE, AUST Interrupt Vectors and the Vector Table 11 An interrupt vector is a pointer to where the ISR is stored in memory. All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT). The IVT is usually located in memory page 00 (0000H - 00FFH). The purpose of the IVT is to hold the vectors that redirect the microprocessor to the right place when an interrupt arrives.
- 12. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Non-Vectored Interrupt Process 12 1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If INTR is high, MP completes current instruction, disables the interrupt and sends INTA (Interrupt acknowledge) signal to the device that interrupted 4. INTA allows the I/O device to send a RST instruction through data bus. 5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the stack and the program is transferred to ‘call’ location (ISR Call) specified by the RST instruction
- 13. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Non-Vectored Interrupt Process 13 6. Microprocessor Performs the ISR. 7. ISR must include the ‘EI’ instruction to enable the further interrupt within the program. 8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack and the program is transferred back to where the program was interrupted. ** See the example of the Class that showed how interrupt process works for this 8 steps **
- 14. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Non-Vectored Interrupt Process 14 The 8085 recognizes 8 RESTART instructions: RST0 - RST7. each of these would send the execution to a predetermined hard-wired memory location: Restart Instruction Equivalent to RST0 CALL 0000H RST1 CALL 0008H RST2 CALL 0010H RST3 CALL 0018H RST4 CALL 0020H RST5 CALL 0028H RST6 CALL 0030H RST7 CALL 0038H
- 15. Mohd. Moinul Hoque, Lecturer, CSE, AUST Issues in Implementing INTR Interrupts 15 How long must INTR remain high? The microprocessor checks the INTR line one clock cycle before the last T-state of each instruction. The INTR must remain active long enough to allow for the longest instruction. The longest instruction for the 8085 is the conditional CALL instruction which requires 18 T-states. Therefore, the INTR must remain active for 17.5 T-states. If f= 3MHZ then T=1/f and so, INTR must remain active for [ (1/3MHZ) * 17.5 ≈ 5.8 micro seconds].
- 16. Mohd. Moinul Hoque, Lecturer, CSE, AUST Issues in Implementing INTR Interrupts 16 How long can the INTR remain high? The INTR line must be deactivated before the EI is executed. Otherwise, the microprocessor will be interrupted again. Once the microprocessor starts to respond to an INTR interrupt, INTA becomes active (=0). Therefore, INTR should be turned off as soon as the INTA signal is received.
- 17. Mohd. Moinul Hoque, Lecturer, CSE, AUST Issues in Implementing INTR Interrupts 17 Can the microprocessor be interrupted again before the completion of the ISR? As soon as the 1st interrupt arrives, all maskable interrupts are disabled. They will only be enabled after the execution of the EI instruction. Therefore, the answer is: “only if we allow it to”. If the EI instruction is placed early in the ISR, other interrupt may occur before the ISR is done.
- 18. Mohd. Moinul Hoque, Lecturer, CSE, AUST Multiple Interrupts & Priorities 18 Note that the opcodes for the different RST instructions follow a set pattern. Bit D5, D4 and D3 of the opcodes change in a binary sequence from RST 7 down to RST 0. The other bits are always 1. This allows the code generated by the 74366 to be used directly to choose the appropriate RST instruction. The one draw back to this scheme is that the only way to change the priority of the devices connected to the 74366 is to reconnect the hardware.
- 19. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Maskable/Vectored Interrupts 19 The 8085 has 4 Masked/Vectored interrupt inputs. RST 5.5, RST 6.5, RST 7.5 They are all maskable. They are automatically vectored according to the following table: The vectors for these interrupt fall in between the vectors for the RST instructions. That’s why they have names like RST 5.5 (RST 5 and a half). Interrupt Vector RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH
- 20. Mohd. Moinul Hoque, Lecturer, CSE, AUST Masking RST 5.5, RST 6.5 and RST 7.5 20 These three interrupts are masked at two levels: Through the Interrupt Enable flip flop and the EI/DI instructions. The Interrupt Enable flip flop controls the whole maskable interrupt process. Through individual mask flip flops that control the availability of the individual interrupts. These flip flops control the interrupts individually.
- 21. Mohd. Moinul Hoque, Lecturer, CSE, AUST Maskable Interrupts and vector locations 21 Interrupt Enable Flip Flop INTR RST 5.5 RST 6.5 RST 7.5 M 5.5 M 6.5 M 7.5 RST7.5 Memory **See Fig 12.5 of the Text Book for a detailed look
- 22. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Maskable/Vectored Interrupt Process 22 1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop. 4. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table.
- 23. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Maskable/Vectored Interrupt Process 23 5. When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack. 6. The microprocessor jumps to the specific service routine. 7. The service routine must include the instruction EI to re-enable the interrupt process. 8. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.
- 24. Mohd. Moinul Hoque, Lecturer, CSE, AUST SIM and the Interrupt Mask 24 Bit 0 is the mask for RST 5.5, bit 1 is the mask for RST 6.5 and bit 2 is the mask for RST 7.5. If the mask bit is 0, the interrupt is available. If the mask bit is 1, the interrupt is masked. Bit 3 (Mask Set Enable - MSE) is an enable for setting the mask. If it is set to 0 the mask is ignored and the old settings remain. If it is set to 1, the new setting are applied. The SIM instruction is used for multiple purposes and not only for setting interrupt masks. It is also used to control functionality such as Serial Data Transmission. Therefore, bit 3 is necessary to tell the microprocessor whether or not the interrupt masks should be modified
- 25. Mohd. Moinul Hoque, Lecturer, CSE, AUST SIM and the Interrupt Mask 25 The RST 7.5 interrupt is the only 8085 interrupt that has memory. If a signal on RST7.5 arrives while it is masked, a flip flop will remember the signal. When RST7.5 is unmasked, the microprocessor will be interrupted even if the device has removed the interrupt signal. This flip flop will be automatically reset when the microprocessor responds to an RST 7.5 interrupt. Bit 4 of the accumulator in the SIM instruction allows explicitly resetting the RST 7.5 memory even if the microprocessor did not respond to it. Bit 5 is not used by the SIM instruction
- 26. Mohd. Moinul Hoque, Lecturer, CSE, AUST The RIM Instruction and the Masks 26 Bits 0-2 show the current setting of the mask for each of RST 7.5, RST 6.5 and RST 5.5 They return the contents of the three mask flip flops. They can be used by a program to read the mask settings in order to modify only the right mask. Bit 3 shows whether the maskable interrupt process is enabled or not. It returns the contents of the Interrupt Enable Flip Flop. It can be used by a program to determine whether or not interrupts are enabled.
- 27. Mohd. Moinul Hoque, Lecturer, CSE, AUST The RIM Instruction and the Masks 27 Bits 4-6 show whether or not there are pending interrupts on RST 7.5, RST 6.5, and RST 5.5 Bits 4 and 5 return the current value of the RST5.5 and RST6.5 pins. Bit 6 returns the current value of the RST7.5 memory flip flop. Bit 7 is used for Serial Data Input. The RIM instruction reads the value of the SID pin on the microprocessor and returns it in this bit.
- 28. Mohd. Moinul Hoque, Lecturer, CSE, AUST TRAP 28 TRAP is the only non-maskable interrupt. It does not need to be enabled because it cannot be disabled. It has the highest priority amongst interrupts. It is edge and level sensitive. It needs to be high and stay high to be recognized. Once it is recognized, it won’t be recognized again until it goes low, then high again. TRAP is usually used for power failure and emergency shutoff.
- 29. Mohd. Moinul Hoque, Lecturer, CSE, AUST The 8085 Interrupts Interrupt Name Maskable Masking Method Vectored Memory Triggering Method INTR Yes DI / EI No No Level Sensitive RST 5.5 / RST 6.5 Yes DI / EI SIM Yes No Level Sensitive RST 7.5 Yes DI / EI SIM Yes Yes Edge Sensitive TRAP No None Yes No Level & Edge Sensitive 29
- 30. Mohd. Moinul Hoque, Lecturer, CSE, AUST 30