interrupts.ppt
- 2. INTERRUPTS When a microprocessor is interrupted, it stops executing its current program and calls a special routine which “services” the interrupt The event that causes the interruption is called Interrupt or mechanism by which the processor is made to transfer its control from its current execution to another program. The special routine executed to service the interrupt is called ISR - Interrupt Service Routine/Procedure i.e program which is executed upon the interrupt. 2
- 3. INTERRUPT CLASSIFICATION Hardware Interrupt An interrupt caused by an “External signal ” Software Interrupt An interrupt caused by “Special Instruction” Maskable Interrupts Can be delayed or Rejected Non-Maskable Interrupts Can not be delayed or Rejected (Service must) Vectored Where the subroutine starts is referred to as Vector Location Non-vectored The address of the service routine needs to be supplied externally by the device 3
- 4. 8085 INTERRUPTS 4 8085 TRAP RST7.5 RST6.5 RST 5.5 INTR INTA The ‘EI’ instruction is a one byte instruction and is used to Enable the non-maskable interrupts. The ‘DI’ instruction is a one byte instruction and is used to Disable the non-maskable interrupts.
- 6. 6 Interrupt Name Maskable Vectored INTR Yes No RST 5.5 Yes Yes RST 6.5 Yes Yes RST 7.5 Yes Yes TRAP No Yes
- 7. INTERRUPT VECTORS & THE VECTOR TABLE An interrupt vector is a pointer to where the ISR is stored in memory. All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT). The IVT is usually located in (0000H - 00FFH). Vector Address = Interrupt number * 8 7
- 8. 8 Interrupt Name Calculation Vector Address INTR -- -- TRAP ( RST 4.5) 4.5x8=36 0024H RST 5.5 5.5x8=44 002CH RST 6.5 6.5x8=52 0034H RST 7.5 7.5x8=60 003CH
- 9. 8085 INTERRUPTS SUMMARY Interrupt Name Triggering Method Priority Maskable Masking Method Vector Address TRAP RST 4.5 Edge & Level Sensitive 1st Highest No None 0024H RST 7.5 Edge Sensitive 2nd Yes DI / EI SIM 003CH RST 6.5 Level Sensitive 3rd Yes DI / EI SIM 0034H RST 5.5 Level Sensitive 4th Yes DI / EI SIM 002CH INTR Level Sensitive 5th Lowest Yes Pin ( INTR & INTA) -- 9
- 10. SOFTWARE INTERRUPT The 8085 recognizes 8 RESTART instructions: RST n ( RST0 - RST7) Each of these would send the execution to a redetermined hard-wired memory location: 10 Restart Instruction Vector Address RST 0 CALL 0000H RST 1 CALL 0008H RST 2 CALL 0010H RST 3 CALL 0018H RST 4 CALL 0020H RST 5 CALL 0028H RST 6 CALL 0030H RST 7 CALL 0038H
- 11. THE 8085 MASKABLE/VECTORED INTERRUPT PROCESS 1. The interrupt process should be enabled using the EI instruction. 2. The 8085 checks for an interrupt during the execution of every instruction. 3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop. 4. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table. 11
- 12. THE 8085 MASKABLE/VECTORED INTERRUPT PROCESS 5. When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack. 6. The microprocessor jumps to the specific service routine. 7. The service routine must include the instruction EI to re-enable the interrupt process. 8. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted. 12
- 13. SIM VALUE MUST BE LOADED IN ACCUMULATOR 13 SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 0 1 2 3 4 5 6 7 RST5.5 Mask RST6.5 Mask RST7.5 Mask }0 - Available 1 - Masked Mask Set Enable 0 - Ignore bits 0-2 1 - Set the masks according to bits 0-2 Force RST7.5 Flip Flop to reset Not Used Enable Serial Data 0 - Disable 1 - Enable Serial Data Out Either 0 or 1 SIM – SERIAL INTERRUPT MASK Used to mask or unmask the restart hardware interrupts.
- 14. Example MSE Mask Set Enable RST 6.5 Mask RST 5.5 & 7.2 Unmask RST FF Don’t Reset Serial Data Igonered 14 SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 0 1 0 0 0 0 0 1 Contents of accumulator are: 0AH EI ; Enable interrupts including INTR MVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5 SIM ; Apply the settings RST masks
- 15. Example MSE Mask Set Disable RST FF Reset Serial Data Enable Serial Data output is 0 15 SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 1 0 0 1 0 1 0 0 Contents of accumulator are: 54H
- 16. 16 SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5 0 1 2 3 4 5 6 7 RST5.5 Mask RST6.5 Mask RST7.5 Mask }0 - Available 1 - Masked Interrupt Enable Value of the Interrupt Enable Flip Flop Serial Data In RST5.5 Interrupt Pending RST6.5 Interrupt Pending RST7.5 Interrupt Pending RIM – READ INTERRUPT MASK Set – 1 Reset - 0 COPIES THE STATUS OF THE INTERRUPTS INTO THE ACCUMULATOR To read the status of interrpt mask bits EI/DI
- 17. Example Interrupt Enable RST 5.5 & 6.5 Masked RST 7.5 Pending Serial Input Data is 0 17 SID P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5 0 1 1 0 0 1 0 1 Contents of accumulator are: 4BH