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This document discusses interrupts in the 8086 microprocessor. It begins by defining an interrupt as an event that temporarily halts normal program execution to divert control to an interrupt service routine. The document then discusses the different types of interrupts in 8086, including hardware interrupts from devices, software interrupts from the INT instruction, maskable interrupts, and non-maskable interrupts. It provides details on how the 8086 handles different interrupt types, such as pushing register values to the stack and jumping to specific memory locations defined in the interrupt vector table.
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- 1. INTERRUPTS OF 8086 NAME- RAJEEV KUMAR REGNO- 20UGELE08 DEPARTMENT- ELECTRICAL ENGINEERING SEMESTER- IV
- 2. CONTENTS 1. INTERRUPTS 2. TYPES OF INTERRUPTS 3. Interrupt instruction of 8086 4. Instruction of interrupt 5. Reference
- 3. INTERRUPT An Interrupt is used to cause a temporary halt in the execution of program. The meaning of ‘interrupts’ is to break the sequence of operation. When the Microprocessor is executing a program, an ‘interrupt’ breaks the normal sequence of execution of instruction, diverts its execution to some other program called Interrupt Service Routine (ISR). After executing ISR, IRET return the control back again to the main program Interrupt Processing is an alternative to, the polling.
- 5. HARDWARE INTERRUPT . The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge. The primary sources of interrupts, however, are the PCs timer chip, Keyboard, serial port, parallel port, disk drives, CMOS real-time clock, Mouse, Sound Card and other Peripheral devices.
- 7. NON-MASKABLE INTERRUPT It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt. When this interrupt is activated, these actions take place − •Completes the current instruction that is in progress. •Pushes the Flag register values on to the stack. •Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack. •IP is loaded from the contents of the word location 00008H. •CS is loaded from the contents of the next word location 0000AH . •Interrupt flag and trap flag are reset to 0.
- 8. MASKABLE INTERRUPT The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction. The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt controller. These actions are taken by the microprocessor − •First completes the current instruction. •Activates INTA output and receives the interrupt type, say X. •Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack. •IP value is loaded from the contents of word location X × 4 •CS is loaded from the contents of the next word location. •Interrupt flag and trap flag is reset to 0
- 9. SOFTWARE INTERRUPT When the source of interrupt is the execution of interrupt instruction, this interrupt is known as software interrupt. . IN 8086 there are about 256 interrupt such as INT 00H, INT 01H, INT 02H to INT FFH Whenever the INT interrupt instruction is executed, the microprocessor automatically saves the contents of the flag register, Instruction Pointer(IP) and the code segment register on the stack and jump to specified memory location. Software Interrupt are always generated by INT instruction and Used for divided- by- Zero error, single step, NMI, break point, and overflow interrupt.
- 10. Interrupt Type 0- INT 00H(Divide by zero Error) The 8086 generates a type 0 interrupt, if the result of DIV or IDV operation is too large to fit in the destination register. For this interrupt ,8086 push the content of the flag register on the stack, reset IF and TF and also pushes the content of CS and IP onto the stack. Then 8086 gets the starting address of the interrupt service procedure from the interrupt pointer table. Therefore, Load the new value of CS from addresses 00002H and 00003H; also load the new value of IP from addresses 00000H and 00001H.
- 11. Interrupt Type-INT 01H(Single Step) During execution of sequence of instruction, there is frequently a need to examine the content of CPU’s register and system memory. This is done by executing one instruction at a time and then inspecting the registers and memory. If they are correct, the user can give the command to go on and execute the next generation. This is called single stepping. When the CPU gets a type 1 interrupt, initially it pushes the flag register onto the stack, changing the trap bit and pops the flag register back from the stack. Then it loads the CS value from starting address 00006H and IP value from starting address 00004H for the type 1 interrupt service routine.
- 13. Interrupt Instruction of 8086 The interrupt instruction of 8086 microprocessor are CLI, STI, INT n INTO, HLT and WAIT. Mnemonics Function Operation CLI Clear interrupt instruction, IF affected. IF 0 STI Set Interrupt flag, IF affected IF 1 INTO Interrupt overflow. TF and IF affected. Same as INT4
- 14. Reference Soumitra Kumar Mandal Microprocessor - 8086 Interrupts (tutorialspoint.com)
- 15. This Photo by Unknown Author is licensed under CC BY-NC-ND