Efficient Soft Cancelation Decoder Architectures for Polar Codes
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The document proposes two improved belief propagation algorithms - reduced complexity soft cancelation (RCSC) and reduced latency soft cancelation (RLSC) - for decoding polar codes. RCSC requires over 50% less memory than the standard SCAN algorithm while achieving comparable or better performance. RLSC further reduces decoding latency and improves throughput with some performance sacrifice compared to RCSC. VLSI architectures for both algorithms are presented, with synthesis results demonstrating their efficiency in terms of logic size, area, and power consumption compared to existing techniques. The algorithms and architectures were implemented and tested using Modelsim and Xilinx ISE software.
Efficient Soft Cancelation Decoder Architectures for Polar Codes
- 1. Efficient Soft Cancelation Decoder Architectures for Polar Codes ABSTRACT: The flooding belief propagation (FO-BP) and the soft-cancelation (SCAN) algorithms are the two most popular soft-output BP algorithms for the decoding of capacity-achieving polar codes. The FO-BP algorithm has high throughput at the cost of performance degradation in high signal-to-noise ratio (SNR) region or with large block length. The SCAN algorithm has much better decoding performance while suffering from long decoding latency and low throughput. In this paper, an improved BP algorithm, named reduced complexity softcancelation (RCSC) algorithm, is proposed. Compared with the SCAN algorithm, the number of memory entries required by the RCSC algorithm is reduced by more than 50% in general, while achieving comparable or even better (e.g., when block size N=215) decoding performance. When block size is large(e.g., N ≥215), the proposed RCSC algorithm reduces the required memory entries by more than 23% compared with the state-of-the-art FO-BP algorithm. The numerical results show that the error performance improvement of the RCSC algorithm is more significant when the SNR increases. For a different tradeoff, a reduced latency soft-cancelation (RLSC) algorithm is proposed to reduce the decoding latency and increase the throughput of the RCSC algorithm while slightly sacrificing decoding performance. Finally,
- 2. the optimized VLSI architectures are presented for the RCSC and RLSC algorithms, respectively. The synthesis results demonstrate the efficiency of the proposed algorithms and architectures. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2. SOFTWARE IMPLEMENTATION: Modelsim Xilinx ISE