Energy saving through load balancing of 3-wire loads

International Journal of Electrical and Computer Engineering (IJECE)
Vol. 13, No. 4, August 2023, pp. 3857~3875
ISSN: 2088-8708, DOI: 10.11591/ijece.v13i4.pp3857-3875  3857
Journal homepage: http://ijece.iaescore.com
Energy saving through load balancing of 3-wire loads
Abdulkareem Mokif Obais1
, Ali Abdulkareem Mukheef2
1
Department of Biomedical Engineering, College of Engineering, University of Babylon, Hillah, Iraq
2
English Department, Almustaqbal University College, Babylon, Iraq
Article Info ABSTRACT
Article history:
Received Nov 16, 2022
Revised Dec 18, 2022
Accepted Jan 30, 2023
In this paper, static var compensators (SVCs) and many load compensation
techniques are reviewed. A continuously and linearly controlled
compensating susceptance is devised from a switched capacitor bank and a
switched reactor bank. The switched capacitor bank is built of four binary
weighted thyristor switched capacitors, while the switched reactor bank is
built of three binary weighted thyristor switched reactors. Although few
switched capacitors and reactor are used, their binary weighted values beside
their control scheme make them respond as a continuously and linearly
controlled reactive device in capacitive and inductive modes of operation. A
load balancing system is constructed of three identical devised compensating
susceptances connected in delta-form. It is designed for balancing an 11 kV
50 Hz distribution station. The proposed system is designed and tested on
PSpice which is a computer program equivalent in performance to real
hardware design. The simulation results of the proposed system have
showed significant treatment of severe imbalance conditions.
Keywords:
Current balancing
Energy saving
Harmonic treatment
Load compensation
Reactive power compensation
This is an open access article under the CC BY-SA license.
Corresponding Author:
Abdulkareem Mokif Obais
Department of Biomedical Engineering, College of Engineering, University of Babylon
Babylon, Iraq
Email: karimobais@yahoo.com
1. INTRODUCTION
Traditional static var compensators (SVCs) and synchronous static compensators (STATCOMs) are
the basic means used for power quality purposes [1]–[25]. Traditional static var compensators are represented
by thyristor-controlled reactor (TCR), thyristor switched reactor (TSR), and thyristor switched capacitor
(TSC). Static compensators are represented by power converter based static var compensators and
STATCOMs. Load compensation and power factor correction systems have great impact in transmission
losses reduction and energy saving in power generation stations [1]–[25] . The minimization of current
harmonics released from the operation of TSC-TCR based SVC into the distribution systems at low voltage
distribution level was discussed by [1]. In the proposed study, intelligent control was used to determine the
TCR triggering signals required for minimal harmonic injection. A three-phase STATCOM based
compensation system was introduced by [2] for compensating unbalanced voltage and current. By choosing
appropriate control schemes, the proposed compensation system can achieve voltage regulation in addition to
certain limit of current balancing and power factor correction.
In [3], a new type of STATCOM designed for high-power applications was proposed for fully
compensating the imbalanced and disfigured nonlinear loads operating in large-current medium-voltage
grids. Hagiwara et al. [4] introduced an application using a modular multilevel cascade converter on basis of
the single-delta bridge-cells to synchronized STATCOM, especially for the control of negative-sequence var.
A DSTATCOM in [5] was capable of real-time compensation for unbalanced loads in 4-wire distribution
systems. The method of symmetrical components was exploited for devising the controlling scheme for this

 ISSN: 2088-8708
Int J Elec & Comp Eng, Vol. 13, No. 4, August 2023: 3857-3875
3858
DSTATCOM. In [6] a new configuration of harmonic suppression circuitries was proposed to a TCR, which
promoted it to respond linearly to reactive current demand without harmonic association.
A simulation package depending on LABVIEW was developed by [7] for reduction of energy loss
purposes. The work in [8] discussed safe operation of grid-connected power converters with related to peak
current limitation as well as maximum permissible fluctuations of the direct current (DC) voltage. Balancing
of load currents can be accomplished via correction process of power factor and compensation of load active
current components [9]. Many researches exploited converter-based static compensators for harmonic
reduction, voltage regulation, and current compensation [9]–[13], [22]. Compensators built of separate
susceptances in star and delta configurations showed more compensation flexibility than traditional lumped
systems represented by DSTATCOMs [9], [15]–[20]. A 3-phase load current balancing scheme in a
transmission system having distributed static compensators connected in series and using the method of
variable quadrature voltage injection was proposed by [14]. This topology either exhibits capacitive or
inductive impedance into the alternating current (AC) grid lines for current balancing purposes. The works in
[21], introduced reactances for 3-phase load compensation. The reactances connected in star form were used
for compensating reactive currents, whereas those connected in delta for were exploited for balancing the
active components of line currents. Active filters were introduced in [23] for the purposes of treating
harmonic current components associating nonlinear loads, whereas in [24], a shunt active filter was provided
to a single-phase converter to achieve significant reduction in harmonic current components. A DSTATCOM
was introduced in [25] for power quality purposes. It was suggested to enhance the improvement of power
factor, voltage regulation, current balancing, and harmonic minimization.
In this paper, a continuously and linearly controlled SVC is devised from a new configuration of
TSCs and TSRs. The new configuration is built of a binary weighted switched capacitor bank (BWSCB) and
a binary weighted switched reactor bank (BWSRB). Even though the devised SVC is built of limited number
of stepping response TSCs and TSRs, it shows a performance of a continuously and linearly controlled
compensating susceptance. A static compensator is built of three identical compensating susceptances
connected in delta-form. It is designed for load currents balancing for an 11 kV 50 Hz distribution station.
The station involves five feeders. The average line current drawn from this station varies in the range of
1,200 to 1,300 A (rms values) depending on the daily loading conditions. A 30% unbalance in line currents is
permissible there.
2. THE ADOPTED LOAD BALANCING STRATEGY
Figure 1 shows the layout of the balancing mechanism of an ungrounded load fed by a balanced
three phase voltage. BSAB, BSBC, and BSCA are the compensating susceptances of the static compensator power
circuit. ISA, ISB, and ISC are the static compensator line currents. The AC power system phase voltages VA, VB,
and VC can be given by (1), (2), and (3).
𝑉𝐴 = 𝑉 (1)
𝑉𝐵 = 𝑉𝑒𝑗
−2𝜋
3 (2)
𝑉𝐵 = 𝑉𝑒𝑗
−4𝜋
3 (3)
where, V is the rms magnitude of each phase voltage. The line currents of the unbalanced three-phase load
can be given by (4), (5), dan (6).
𝐼𝐿𝐴 = |𝐼𝐿𝐴|∠𝜙𝐿𝐴 = |𝐼𝐿𝐴| 𝑐𝑜𝑠 𝜙𝐿𝐴 + |𝐼𝐿𝐴| 𝑠𝑖𝑛 𝜙𝐿𝐴 𝑒𝑗
𝜋
2 (4)
𝐼𝐿𝐵 = |𝐼𝐿𝐵|∠𝜙𝐿𝐵 = |𝐼𝐿𝐵| 𝑐𝑜𝑠 𝜙𝐿𝐵 𝑒𝑗
−2𝜋
3 + |𝐼𝐿𝐵| 𝑠𝑖𝑛 𝜙𝐿𝐵 𝑒𝑗
−𝜋
6 (5)
𝐼𝐿𝐶 = |𝐼𝐿𝐶|∠𝜙𝐿𝐶 = |𝐼𝐿𝐶| 𝑐𝑜𝑠 𝜙𝐿𝐶 𝑒𝑗
−4𝜋
3 + |𝐼𝐿𝐶| 𝑠𝑖𝑛 𝜙𝐿𝐶 𝑒𝑗
−5𝜋
6 (6)
where, φLA, φLB, and φLC are the power factor angles of phases A, B, and C respectively. |ILA|, |ILB|, and |ILC|,
are the absolute rms values of ILA, ILB, and ILC respectively. The active current components of line currents are
in phase with their corresponding phase voltages, while reactive current components lead them by π/2.
Similarly, the static compensator rms currents ISA, ISB, and ISC can be expressed in terms of their active and
reactive current components as (7), (8), and (9).

Int J Elec & Comp Eng ISSN: 2088-8708 
Energy saving through load balancing of 3-wire loads (Abdulkareem Mokif Obais)
3859
𝐼𝑆𝐴 = √3𝑉 𝑐𝑜𝑠 (
𝜋
3
) (𝐵𝑆𝐶𝐴 − 𝐵𝑆𝐴𝐵) + √3𝑉 𝑠𝑖𝑛 (
𝜋
3
) (𝐵𝑆𝐴𝐵 + 𝐵𝑆𝐶𝐴)𝑒𝑗
𝜋
2 (7)
𝐼𝑆𝐵 = √3𝑉 𝑐𝑜𝑠 (
𝜋
3
) (𝐵𝑆𝐴𝐵 − 𝐵𝑆𝐵𝐶)𝑒𝑗
−2𝜋
3 + √3𝑉 𝑠𝑖𝑛 (
𝜋
3
)(𝐵𝑆𝐵𝐶 + 𝐵𝑆𝐴𝐵)𝑒𝑗
−𝜋
6 (8)
𝐼𝑆𝐶 = √3𝑉 𝑐𝑜𝑠 (
𝜋
3
) (𝐵𝑆𝐵𝐶 − 𝐵𝑆𝐶𝐴)𝑒𝑗
−4𝜋
3 + √3𝑉 𝑠𝑖𝑛 (
𝜋
3
)(𝐵𝑆𝐶𝐴 + 𝐵𝑆𝐵𝐶)𝑒𝑗
−5𝜋
6 (9)
IA, IB, and IC are the rms line currents of the AC source. According to the main objective of this
research, these currents should be balanced and active. Consequently, they can be given by (10), (11), (12).
𝐼𝐴 = 𝐼 (10)
𝐼𝐵 = 𝐼𝑒𝑗
−2𝜋
3 (11)
𝐼𝐶 = 𝐼𝑒𝑗
−4𝜋
3 (12)
where, I is the rms magnitude of each line current. The active power PL supplied to the unbalanced load can
be given by (13) and (14).
𝑃𝐿 = 𝑉(|𝐼𝐿𝐴| 𝑐𝑜𝑠 𝜙𝐿𝐴 + |𝐼𝐿𝐵| 𝑐𝑜𝑠 𝜙𝐿𝐵 + |𝐼𝐿𝐶| 𝑐𝑜𝑠 𝜙𝐿𝐶) (13)
The active power P supplied by the AC source can be given by (14).
𝑃 = 3𝑉𝐼 (14)
Figure 1. The mechanism of balancing an ungrounded load
The active power supplied by the AC source should be equal to the power consumed by the
unbalanced load or in other words:
𝑃 = 3𝑉𝐼 = 𝑃𝐿 (15)
equating the (15) for I, gives (16).

 ISSN: 2088-8708
3860
𝐼 =
1
3
(|𝐼𝐿𝐴| 𝑐𝑜𝑠 𝜙𝐿𝐴 + |𝐼𝐿𝐵| 𝑐𝑜𝑠 𝜙𝐿𝐵 + |𝐼𝐿𝐶| 𝑐𝑜𝑠 𝜙𝐿𝐶) (16)
Applying Kirchhoff’s current law at nodes A, B, and C on reactive current components of load and
compensator currents for obtaining BSAB, BSBC, and BSCA gives
𝐵𝑆𝐴𝐵 = −
1
3𝑉
(|𝐼𝐿𝐴| 𝑠𝑖𝑛 𝜙𝐿𝐴 + |𝐼𝐿𝐵| 𝑠𝑖𝑛 𝜙𝐿𝐵 − |𝐼𝐿𝐶| 𝑠𝑖𝑛 𝜙𝐿𝐶) (17)
𝐵𝑆𝐵𝐶 = −
1
3𝑉
(|𝐼𝐿𝐵| 𝑠𝑖𝑛 𝜙𝐿𝐵 + |𝐼𝐿𝐶| 𝑠𝑖𝑛 𝜙𝐿𝐶 − |𝐼𝐿𝐴| 𝑠𝑖𝑛 𝜙𝐿𝐴) (18)
𝐵𝑆𝐶𝐴 = −
1
3𝑉
(|𝐼𝐿𝐶| 𝑠𝑖𝑛 𝜙𝐿𝐶 + |𝐼𝐿𝐴| 𝑠𝑖𝑛 𝜙𝐿𝐴 − |𝐼𝐿𝐵| 𝑠𝑖𝑛 𝜙𝐿𝐵) (19)
2.1. Layout of the 11 kV 50 Hz BWSCB-BWSRB based SVC
The power circuit of this SVC is shown in Figure 2. It is constructed of the BWSCB represented by
the switched capacitors C1 to C4 and the BWSRB represented by the switched reactors L1 to L3. The inductors
LC1 to LC4 are used as current limiters for the solid-state switching devices of the switched capacitors. The
switched capacitor and reactor banks are designed such that,
𝜔𝐶 = 1 𝜔𝐿
⁄ (20)
where, ω is the angular frequency of the AC power system voltage Vac. C and L are the basic capacitance and
inductance of the BWSCB and BWSRB, respectively.
Figure 2. Layout of BWSCB and BWSRB based SVC
This SVC is designed such that its reactive current response to reactive current demand follows the
response indicated in Figure 3. The minus sign refers to inductive reactive current. The maximum deviation
of BWSCB-BWSRB based SVC current from the required linear reactive current response is within ±0.5IBB.
Where, IBB is current magnitude between two adjacent current levels of BWSCB capacitive reactive current
response. This current can be expressed as (21).
𝐼𝐵𝐵 = 𝑉
𝑎𝑐
𝜔𝐶
2
(21)

3861
Since the absolute deviation of the SVC total current from the required linear response is negligible
compared to its absolute reactive current rating, the proposed SVC can be considered to some extent as
continuously and linearly controlled compensating susceptance. The maximum capacitive and inductive
current ratings of this SVC are 15IBB and -14IBB respectively.
Figure 3. The current of BWSCB-BWSRB based SVC against reactive current demand
The switching status of the binary switched capacitor and reactor banks are shown in Table 1. The
table states the variations of the reactive current demand (ID) from maximum inductive to maximum
capacitive. The DATA of this table were exploited to draw Figure 3.
2.2. Circuit design of 11 kV 50 Hz BWSCB-BWSRB based SVC
There are no separate thyristors that can handle a line-to-line voltage of the 11 kV. Therefore, the
switching devices X1+ to X7- of Figure 2 are built by using arrays of thyristors. Figure 4 shows these arrays.
The circuit diagram of the 11 kV 50 Hz BWSCB-BWSRB based SVC is shown in Figure 5. The circuit is
designed and built on PSpice. In this circuit, the line-to-line AC voltage is detected by using a potential
transformer which is generated as electronic part and saved as a separate library on PSpice. The output of the
potential transformer is the voltage signal k3vac, which has amplitude of 5 V. Where, vac represents the
instantaneous line to line voltage exerted on the compensator. The controller of this SVC is represented by
the electronic part “BINARY SVC CONTROLLING CCT” which is responsible for generating the
controlling signals required for the SVC triggering circuit. The triggering circuit of the BWSCB-BWSRB
based SVC is represented by the electronic part “TRIGGERING CCT” which is responsible for generating
the triggering signals of the thyristor switching arrays X1+ to X7-. The thyristor and its driving circuit are
merged together in its corresponding switching array. The anti-parallel switching arrays with their driving
circuits are represented by the electronic parts “SCR ARR-1IB”, “SCR ARR-2IB”, “SCR ARR-4IB”, and
“SCR ARR-8IB”.

 ISSN: 2088-8708
3862
Table 1. The switching status of switched capacitors and reactors
Reactive current demand (ID)
Capacitors switching status Reactors switching status
C1 C2 C3 C4 L1 L2 L3
-j14IBB≤ID<-j13.5IBB OFF OFF OFF OFF ON ON ON
-j13.5IBB≤ID<-j12.5IBB ON OFF OFF OFF ON ON ON
-j12.5IBB≤ID<-j11.5IBB OFF OFF OFF OFF OFF ON ON
-j11.5IBB≤ID<-j10.5IBB ON OFF OFF OFF OFF ON ON
-j10.5IBB≤ID<-j9.5IBB OFF OFF OFF OFF ON OFF ON
-j9.5IBB≤ID<-j8.5IBB ON OFF OFF OFF ON OFF ON
-j8.5IBB≤ID<-j7.5IBB OFF OFF OFF OFF OFF OFF ON
-j7.5IBB≤ID<-j6.5IBB ON OFF OFF OFF OFF OFF ON
-j6.5IBB≤ID<-j5.5IBB OFF OFF OFF OFF ON ON OFF
-j5.5IBB≤ID<-j4.5IBB ON OFF OFF OFF ON ON OFF
-j4.5IBB≤ID<-j3.5IBB OFF OFF OFF OFF OFF ON OFF
-j3.5IBB≤ID<-j2.5IBB ON OFF OFF OFF OFF ON OFF
-j2.5IBB≤ID<-j1.5IBB OFF OFF OFF OFF ON OFF OFF
-j1.5IBB≤ID<-j0.5IBB ON OFF OFF OFF ON OFF OFF
-j0.5IBB≤ID<0 OFF OFF OFF OFF OFF OFF OFF
0≤ID<j0.5IBB OFF OFF OFF OFF OFF OFF OFF
j0.5IBB≤ID<j1.5IBB ON OFF OFF OFF OFF OFF OFF
j1.5IBB ≤ID<j2.5IBB OFF ON OFF OFF OFF OFF OFF
j2.5IBB≤ID<j3.5IBB ON ON OFF OFF OFF OFF OFF
j3.5IBB≤ID<j4.5IBB OFF OFF ON OFF OFF OFF OFF
j4.5IBB≤ID<j5.5IBB ON OFF ON OFF OFF OFF OFF
j5.5IBB≤ID<j6.5IBB OFF ON ON OFF OFF OFF OFF
j6.5IBB≤ID<j7.5IBB ON ON ON OFF OFF OFF OFF
j7.5IBB≤ID<j8.5IBB OFF OFF OFF ON OFF OFF OFF
j8.5IBB≤ID<j9.5IBB ON OFF OFF ON OFF OFF OFF
j9.5IBB≤ID<j10.5IBB OFF ON OFF ON OFF OFF OFF
j10.5IBB≤ID<j11.5IBB ON ON OFF ON OFF OFF OFF
j11.5IBB≤ID<j12.5IBB OFF OFF ON ON OFF OFF OFF
j12.5IBB≤ID<j13.5IBB ON OFF ON ON OFF OFF OFF
j13.5IBB≤ID<j14.5IBB OFF ON ON ON OFF OFF OFF
j14.5IBB≤ID<j15IBB ON ON ON ON OFF OFF OFF
Figure 4. Thyristors arrays of 11 kV 50 Hz BWSCB-BWSRB based SVC

3863
Figure 5. Circuit diagram of 11 kV 50 Hz BWSCB and BWSRB based SVC
2.2.1. Current controller of BWSCB-BWSRB based SVC
The electronic circuit of this current controller is designed such that the reactive current response of
the SVC follows the response indicated in Figure 3. The electronic circuit of this controller is shown in
Figure 6. In this figure, the DC voltage source k2BS represents an analogue signal proportional to the reactive
current demand. This signal varies in the range of -9.333 to +10 V. Its negative sign denotes inductive
reactive current demand, while its positive sign is related to capacitive reactive current demand. In this
controlling circuit, two 8-bit analogue-to-digital converters (8-bit ADCs) are employed to control the
capacitor and the reactor banks. The 8-bit ADC digital outputs are all logic one, when its analogue input VADC
is 10 V and are all logic zero when its input is zero. Logics zero and one correspond to voltage levels of zero
and +5 V respectively. The two ADCs input voltages VADC1 and VADC2 are related to k2BS by (22) and (23).
𝑉𝐴𝐷𝐶1 = 0.9375𝑘2𝐵𝑆 + 0.3125 (22)
𝑉𝐴𝐷𝐶2 = −0.9375𝑘2𝐵𝑆 + 0.3125 (23)
Only the four most significant digits of each ADC are employed in the SVC current controller. This
makes each 8-bit ADC equivalent to 4-bit ADC. The first 4-bit ADC output digits are D1C, D2C, D3C, and D4C,
while the second 4-bit output digits are D1L, D2L, D3L, and D4L. Note that D4C and D4L are representing the
most significant digits of the first and the second equivalent 4-bit ADCs respectively. The controlling signals
VX1 to VX7 are the triggering signals of X1 to X7 respectively. These signals are defined by (24)–(30).

 ISSN: 2088-8708
3864
𝑉𝑋1 = 𝐷1𝐶 + 𝐷1𝐿 (24)
𝑉𝑋2 = 𝐷2𝐶 (25)
𝑉𝑋3 = 𝐷3𝐶 (26)
𝑉𝑋4 = 𝐷4𝐶 (27)
𝑉𝑋5 = 𝐷1𝐿 ⊕ 𝐷2𝐿 (28)
𝑉𝑋6 = (𝐷1𝐿 ⊕ 𝐷3𝐿)𝐷2𝐿 + 𝐷2𝐿𝐷3𝐿 (29)
𝑉𝑋7 = 𝐷1𝐿𝐷2𝐿𝐷3𝐿𝐷4𝐿 + 𝐷4𝐿 (30)
Figure 6. The current controller of BWSCB and BWSRB based SVC
2.2.2. Triggering circuit of BWSCB-BWSRB based SVC
Figure 7 shows the BWSCB and BWSRB based SVC triggering circuit. The controlling signals of
this circuit are the output signals of the current controller which are represented by VS1 and VX1-VX7. VS1 is a
rectangular waveform denoting the zero crossing points and polarity of k3vA.C. It is delayed by a time of 5 ms
which corresponds to lagging phase shift angle of π/2. The resulting signal is designated by VS2. The latter
VCNV
VCNV
+15V
-15V
R25
32k
R23
2k
R18
3.9k
R19
32k
-5V
0
U9
LM675
+
1
-
2
V+
5
V-
3
OUT
4
U3
ADC8break
DB7
16
DB6
15
DB5
14
DB4
13
DB3
12
DB2
11
DB1
10
DB0
9
AGND
8
IN
1
CNVRT
2
STAT
3
OVER
4
REF
5
R9
4k
R11
4k
0
0
0
R14
5k
R15
10k
0
V2
15V
0
+15V
R34
0.001
U11
ADC8break
DB7
16
DB6
15
DB5
14
DB4
13
DB3
12
DB2
11
DB1
10
DB0
9
AGND
8
IN
1
CNVRT
2
STAT
3
OVER
4
REF
5
R29
4.7k
V3
15V
0
R30
4.7k
0
-15V
R35
0.001
0 0
R31
5k
0
R32
10k
R20
5.6k
+15V
+15V
0
C6
100nF
R21
1k
0
C7
100nF
R28
1k
0
C8
100nF
R33
1k
0
C9
100nF
R38
1k
U6C
74ACT04
5 6
U6D
74ACT04
9 8
U6E
74ACT04
11 10
U6F
74ACT04
13 12
+5V
U14A
74ACT04
1 2
-5V
U14B
74ACT04
3 4
R10
1k
R8
5k
U14C
74ACT04
5 6
R12
5k
U14D
74ACT04
9 8
0
U13B
74ACT86
4
5
6
C3
1uF
U7B
74ACT32
4
5
6
-15V
+15V
R24
10k
R22
10k
U8
LM675
+
1
-
2
V+
5
V-
3
OUT
4
0
D4
BAW62
0
0
R3
5.6k
D1
BAW62
0
k2BS
U10C
74ACT08
10
9
8
k3VA.C
VADC1
VADC2
D1C
D4C
D3C
D2C
D3L
D4L
D1L
D2L
0
R13
33
VS1
0
V1
5V
+5V
R36
0.001
V4
5V
0
-5V
R37
0.001
U10A
74ACT08
1
2
3
U4
max998/mxm
+
3
-
2
V+
7
V-
4
OUT
6
U7A
74ACT32
1
2
3
C1
100nF
U7C
74ACT32
10
9
8
R4
1k
0
C2
100nF
R7
1k
0
C4
100nF
R16
1k
0
C5
100nF
R17
1k
U2A
74ACT04
1 2
D5
BAW62
U2B
74ACT04
3 4
0
R27
10k
U2C
74ACT04
5 6
+15V
U2D
74ACT04
9 8
R26
7k
U2E
74ACT04
11 10
U2F
74ACT04
13 12
U6A
74ACT04
1 2
U6B
74ACT04
3 4
U12A
74ACT11
1
12
2
13
U13A
74ACT86
1
2
3
U10B
74ACT08
4
5
6
-15V
+15V
R6
32k
R5
2k
VX1
D3
BAW62
0 VX2
D2
BAW62
R1
3.9k
VX3
R2
32k VX4
0
VX5
VX6
VX7
-5V
-5V
+5V
U5
max998/mxm
+
3
-
2
V+
7
V-
4
OUT
6
U1
LM675
+
1
-
2
V+
5
V-
3
OUT
4

3865
signal is processed digitally with VX1-VX7 as shown in Figure 7 for generating the triggering signals of the
positive and negative half-cycles of thyristors arrays depicted in Figure 4.
Figure 7. The triggering circuit of the BWSCB and BWSRB based SVC
2.2.3. Combined driving and power circuit of BWSCB-BWSRB based SVC
There are four types of thyristor arrays in Figure 4. Each one of them has a different current rating.
Merging the positive and negative half-cycles switching devices in each branch into a single device and
combining them with their corresponding driving circuits, result in seven bipolar switching devices X1 to X7
as shown in Figure 5.
Since X1 has a current rating of IBB, its device type is referred to as SCR ARR-1IB. X2 and X5 have
the same current rating of 2IBB, thus their device type is referred to as SCR ARR-2IB. Subsequently, the
device types of X3, X6 and X4, X7 are referred to as SCR ARR-4IB and SCR ARR-8IB respectively. Figure 8
shows the exact circuit diagram of the bipolar switching device X1 which is of the type SCR ARR-1IB. In this
figure, each thyristor is shunted by its own snubber circuit. The rms current IS of 11 kV 50 Hz BWSCB and
BWSRB based SVC can be expressed in terms of the switched capacitor bank rms current ICB and the
switched reactor bank rms current IRB as (31).
𝐼𝑆 = 𝐼𝐶𝐵 + 𝐼𝑅𝐵 (31)
ICB and IRB can be expressed in terms of controlling signals VX1 to VX7 as (32), (33).
𝐼𝐶𝐵 =
𝑗𝐼𝐵𝐵
5
(𝑉𝑋1 + 2𝑉𝑋2 + 4𝑉𝑋3 + 8𝑉𝑋4) (32)
𝐼𝑅𝐵 = −
𝑗𝐼𝐵𝐵
5
(2𝑉𝑋5 + 4𝑉𝑋6 + 8𝑉𝑋7) (33)
where, IBB is defined in (21). Substituting (32) and (33) into (31) yields.
𝐼𝑆 =
𝑗𝐼𝐵𝐵
5
(𝑉𝑋1 + 2𝑉𝑋2 + 4𝑉𝑋3 + 8𝑉𝑋4 − 2𝑉𝑋5 − 4𝑉𝑋6 − 8𝑉𝑋7) (34)

 ISSN: 2088-8708
3866
Figure 8. Combined driving and power circuit of X1 anti-parallel thyristor array
2.3. Circuit design of the proposed 11 kV 50 Hz load currents balancing system for ungrounded loads
This system is designed such that it can correct to unity the 0.707 lagging power of a balanced
three-phase load of 1,270 A (rms value). Such a strategy makes it possible for the load currents balancing
system to involve the unbalance cases of about 30% of the line current in the 11 kV 50 Hz power distribution
station. Figure 9 shows the load currents balancing system for ungrounded loads in 11 kV 50 Hz distribution
network. The distribution station is represented here by an unbalanced ungrounded three-phase load. The
power circuit of this compensating system is constructed of three combined driving and power circuits
connected in delta-form. Each combined driving and power circuit is the same as that of the 11 kV 50 Hz
BWSCB and BWSRB based SVC depicted in Figure 5. This load currents balancing system can be imagined
as three 11 kV 50 Hz continuously and linearly controlled harmonic-free compensating susceptances
connected in delta-form. The instantaneous load currents iLA, iLB, and iLC are detected using three identical
current transformers. The outputs of these current transforms are converted to the analogue voltages k1iLA,
k1iLB, and k1iLC. These voltages are processed by the computation circuit in the three-phase controlling circuit
to produce three analogue signals proportional to the required compensating susceptances BSAB, BSBC, and
BSCA. These signals are k2BSAB, k2BSBC, and k2BSCA. The computation circuit is represented by the electronic
part “COMPUTATION CCT”. The three-phase controlling circuit comprises in addition to the computation
circuit, three current controlling circuits represented by the electronic parts “BINARY SVC
CONTROLLING CCT”, three triggering circuits represented by the electronic parts “TRIGGERING CCT”,
and the AC voltages detection circuit represented by the electronic part “AC VOLTAGES DETECTION
CCT” which produces low level analogue signals proportional to the phase and line voltages.
The controlling and triggering circuits are as the same as those depicted in Figures 6 and 7,
respectively. The currents iSA, iSB, and iSC represent the instantaneous compensating currents of the static
compensator built of the delta-connected BWSCB and BWSRB based SVCs. The currents iA, iB, and iC
represent the instantaneous line currents of the AC power system network. These currents are intended to be
balanced and pure active. The AC voltage’s detection circuit is shown in Figure 10. The potential
0
V12
10V
R84
47
R85
1k Q20
Q2N2222A
R86
1k
R77
1k
0
U14
A4N26
VX1-
R63
56
Q14
Q2N2222A
R57
1k
R56
22k
R66
5.6k
0
V9
10V
R61
47 Q13
Q2N2222A
R70
1k
R17
1k
R20
1k
0
R36
1k
R38
1k
0
R58
1k
R55
1k
0
R73
1k
R74
1k
0
R91
1k
R92
1k
0
S1
GA040TH65
S3
GA040TH65
S5
GA040TH65
S8
GA040TH65
S7
GA040TH65
S6
GA040TH65
S4
GA040TH65
S2
GA040TH65
C1 5nF
R8 100
U1
LM675
+
1
-
2
V+
5
V-
3
OUT
4
U5
LM675
+
1
-
2
V+
5
V-
3
OUT
4
U9
LM675
+
1
-
2
V+
5
V-
3
OUT
4
C3 5nF
U13
LM675
+
1
-
2
V+
5
V-
3
OUT
4
R28 100
U17
LM675
+
1
-
2
V+
5
V-
3
OUT
4
C6 5nF
R50 100
U4
LM675
+
1
-
2
V+
5
V-
3
OUT
4
C7 5nF
R67 100
U7
LM675
+
1
-
2
V+
5
V-
3
OUT
4
U18
A4N26
R81
56
U11
LM675
+
1
-
2
V+
5
V-
3
OUT
4
Q18
Q2N2222A
R76
1k
U16
LM675
+
1
-
2
V+
5
V-
3
OUT
4
R75
22k
R87
5.6k
0
V11
10V
U20
LM675
+
1
-
2
V+
5
V-
3
OUT
4
R79
47 Q17
Q2N2222A
R88
1k
S10
GA040TH65
C9 5nF
R82 100
R23
0.001
R45
0.001
-15V
+15V
+15V
+15V
+15V
+15V
+15V
-15V
-15V
-15V
-15V
-15V
S9
GA040TH65
C2 5nF
R9 100
C4 5nF
R29 100
C5 5nF
R47 100
C8 5nF
R64 100
C10 5nF
R83 100
VX1+
0
U2
A4N26
D2
120NQ045
1
2
D4
120NQ045
1
2
R7
56
D6
120NQ045
1
2
D8
120NQ045
1
2
D10
120NQ045
1
2
D1
120NQ045
1
2
D3
120NQ045
1
2
Q2
Q2N2222A
D5
120NQ045
1
2
D7
120NQ045
1
2
D9
120NQ045
1
2
R2
1k
R1
22k
R13
5.6k
0
V1
10V
R5
47 Q1
Q2N2222A
R14
1k
V8
15V
0
V4
15V
A+K-
+15V
-15V
U3
A4N26
R6
56
Q3
Q2N2222A
R15
1k R16
22k
R4
5.6k
0
V2
10V
R10
47
Q4
Q2N2222A
R3
1k
A-K+
+15V
-15V
U8
A4N26
R25
56
Q6
Q2N2222A
R34
1k R35
22k
R22
5.6k
0
V5
10V
R27
47
Q8
Q2N2222A
R21
1k
+15V
-15V
U12
A4N26
R43
56
U6
A4N26
Q11
Q2N2222A
R53
1k R54
22k
R26
56
R41
5.6k
Q7
Q2N2222A
0
V7
10V
R19
1k
R18
22k
R51
47
Q12
Q2N2222A
R32
5.6k
R40
1k
0
V3
10V
R24
47 Q5
Q2N2222A
R33
1k
+15V
-15V
U15
A4N26
R62
56
Q15
Q2N2222A
R71
1k R72
22k
R60
5.6k
0
V10
10V
R68
47
Q16
Q2N2222A
U10
A4N26
R59
1k
R44
56
Q10
Q2N2222A
R37
1k
R39
22k
R46
5.6k
0
V6
10V
R42
47 Q9
Q2N2222A
R49
1k
R11
1k
R12
1k
0
R30
1k
R31
1k
0
R52
1k
R48
1k
+15V
0
-15V
U19
A4N26
R80
56
R65
1k
Q19
Q2N2222A
R69
1k
R89
1k
0
R90
22k
R78
5.6k

3867
transformers are represented by three potential dividers. The potential dividers output signals k3vA, k3vB, and
k3vC are proportional to power system instantaneous phase voltages vA, vB, and vC respectively. According to
this circuit, k3 is computed as 3.2×10-4
. These voltages signals are processed through the difference amplifiers
to obtain the voltage signals k3vAB, k3vBC, and k3vCA which are proportional to the AC power system
instantaneous line voltages vAB, vBC, and vCA respectively. These groups of voltage signals are necessary for
both triggering and computation circuits.
The computation circuit is shown in Figure 11. In this circuit, the voltage signals k1iLA, k1iLB, and
k1iLC`are sampled at the negative slope zero-crossing points of k3vA, k3vB, and k3vC respectively. The sampled
voltage signals are -k1√2|ILA|sinφLA, -k1√2|ILB|sinφLB, and -k1√2|ILC|sinφLC. The above compensating
susceptances can be expressed in terms of the instantaneous line currents iLA, iLB, and iLC and the latter signals
are processed in summing amplifiers to compute k2BSAB, k2BSBC, and k2BSCA which are analogue voltages
proportional to the required compensating susceptances. The maximum positive value of each analogue
voltage of k2BSAB, k2BSBC, and k2BSCA is 10 V. The maximum magnitude of the capacitive susceptance is
733 A/15,556 V=0.0471 S which corresponds to a capacitive reactive current demand of 733 A (peak value).
Consequently, the constant k2 is computed by dividing the analogue voltage k2BS which corresponds to 10 V
by the value of the compensating susceptance BS as: k2=k2BS/BS=10 V/0.0471 S=212.22 VΩ.
Figure 9. Circuit design of the proposed 11 kV 50 Hz load currents balancing system for ungrounded loads
VX5BC+ VX6BC+
VX2BC+ VX6BC-
VX4BC+ VX4BC- VX7BC+ VX7BC-
VX2BC-
VX1BC- VX5BC-
VX3BC-
C1BC 10uF C2BC 20uF C3BC 40uF C4BC 80uF
L1BC 500mH
1
2
R1BC 5
L2BC 250mH
1
2
R2BC 2.5
L3BC 125mH
1
2
R3BC 1.25
X1BC
SCR ARR-1IB
VX+ VX-
A+K-
A-K+
k2BSBC
k2BSAB
k1iLB
k1iLA
k2BSCA
k1iLC
U2
Computation cct
K1ILA
K1ILB
K1ILC
K3VA
K3VB
K3VC
K2BSAB
K2BSBC
K2BSCA
k3VA
k3VB
k3VC
Three-phase controlling circuit Three-phase combined driving and power circuit
R4
0.0001
R5
0.0001
R6
0.0001
VC
Load currents detection circuit
RA
8.5
LA
10mH
1 2
RB
4.25
LB
8.5mH
1 2
RC
3.535
LC
11.25mH
1 2
R1
0.001
VA
R2
0.001
Power system voltage
VB
DAMPING = 0
DELAY = 0
FREQ_HZ = 50Hz
PP_AMPLITUDE = 17963V
OFFSET = 0
VB
PHASE = -120
0
DAMPING = 0
DELAY = 0
FREQ_HZ = 50Hz
OFFSET = 0
VC
PHASE = -240
DAMPING = 0
DELAY = 0
FREQ_HZ = 50Hz
OFFSET = 0
VA
PHASE = 0
Three-phase load
k1iLA
R3
0.001
U9
CURRENT TRANSFORMER HV
IN OUT
K1I
k1iLB
U10
IN OUT
K1I
k1iLC
U11
IN OUT
K1I
LC4CA 10uH
1
2
LC3CA 10uH
1
2
LC2CA 10uH
1
2
LC1CA 10uH
1
2
LC4AB 10uH
1
2
LC3AB 10uH
1
2
LC2AB 10uH
1
2
LC1AB 10uH
1
2
VS1AB
VX1AB
VS1AB
VX4AB
VX3AB
VX2AB
X2CA
SCR ARR-2IB
VX+ VX-
A+K-
A-K+
VX7AB
VX6AB
VX5AB
X3CA
SCR ARR-4IB
VX+ VX-
A+K-
A-K+
VX1AB-
VX1AB+
X4CA
SCR ARR-8IB
VX+ VX-
A+K-
A-K+
VX3AB+
VX2AB-
VX2AB+
VX1CA+
VX4AB-
VX4AB+
VX3AB-
X5CA
SCR ARR-2IB
VX+ VX-
A+K-
A-K+
VX5AB-
VX5AB+
X6CA
SCR ARR-4IB
VX+ VX-
A+K-
A-K+
VX7AB+
VX6AB-
VX6AB+
X7CA
SCR ARR-8IB
VX+ VX-
A+K-
A-K+
VX7AB-
VX3CA+
VX2CA+ VX6CA+
VX5CA+
VX4CA+
U4
TRIGGERING CCT
VS1
VX1
VX2
VX3
VX4
VX5
VX6
VX7
VX1+
VX1-
VX2+
VX2-
VX3+
VX3-
VX4+
VX4-
VX5+
VX5-
VX6+
VX6-
VX7+
VX7-
VX7CA-
VX7CA+
VX4CA- VX5CA- VX6CA-
VX1CA- VX2CA- VX3CA-
C1CA 10uF C2CA 20uF C3CA 40uF C4CA 80uF
L1CA 500mH
1
2
R1CA 5
L2CA 250mH
1
2
k3VAB
R2CA 2.5
U3
BINARY SVC CONTROLLING CCT
K2BS
K3V
VS1
VX1
VX2
VX3
VX4
VX5
VX6
VX7
L3CA 125mH
1
2
R3CA 1.25
X2AB
SCR ARR-2IB
VX+ VX-
A+K-
A-K+
X3AB
SCR ARR-4IB
VX+ VX-
A+K-
A-K+
X4AB
SCR ARR-8IB
VX+ VX-
A+K-
A-K+
VX1AB+ X5AB
SCR ARR-2IB
VX+ VX-
A+K-
A-K+
X6AB
SCR ARR-4IB
VX+ VX-
A+K-
A-K+
X7AB
SCR ARR-8IB
VX+ VX-
A+K-
A-K+
VX4AB+
VX3AB+
VX2AB+
X1CA
SCR ARR-1IB
VX+ VX-
A+K-
A-K+
VX7AB+
VX6AB+
VX5AB+ VX6AB- VX7AB-
VX3AB- VX4AB- VX5AB-
VX1AB- VX2AB-
C1AB 10uF C2AB 20uF C3AB 40uF C4AB 80uF
L1AB 500mH
1
2
R1AB 5
L2AB 250mH
1
2
R2AB 2.5
L3AB 125mH
1
2
R3AB 1.25
X1AB
SCR ARR-1IB
VX+ VX-
A+K-
A-K+
VX3AB
VX2AB
VX1AB
VX5AB
VX4AB
VX7AB
VX6AB
VA
VB
VC
k2BSAB
k3VAB
k3VBC
k3VCA
U1
AC v oltages detection cct
VA
VB
VC
K3VA
K3VAB
K3VB
K3VBC
K3VC
K3VCA
VS1BC
VX2BC
VX1BC
VS1BC
VX4BC
VX3BC
VX7BC
VX6BC
VX5BC
VX2BC+
VX1BC-
VX1BC+
VX3BC+
VX2BC-
VX4BC-
VX4BC+
VX3BC-
VX6BC+
VX5BC-
VX5BC+
VX7BC+
VX6BC-
VX7BC-
U6
TRIGGERING CCT
VS1
VX1
VX2
VX3
VX4
VX5
VX6
VX7
VX1+
VX1-
VX2+
VX2-
VX3+
VX3-
VX4+
VX4-
VX5+
VX5-
VX6+
VX6-
VX7+
VX7-
k3VBC
U5
K2BS
K3V
VS1
VX1
VX2
VX3
VX4
VX5
VX6
VX7
VX2BC
VX1BC
VX5BC
VX4BC
VX3BC
k2BSBC
VX7BC
VX6BC
k3VA
k3VB
k3VC
VS1CA
VS1CA
VX2CA
VX1CA
VX5CA
VX4CA
VX3CA
VX1CA+
VX7CA
VX6CA
VX2CA+
VX1CA-
VX3CA-
VX3CA+
VX2CA-
VX5CA+
VX4CA-
VX4CA+
VX6CA+
VX5CA-
VX7CA-
VX7CA+
VX6CA-
U8
TRIGGERING CCT
VS1
VX1
VX2
VX3
VX4
VX5
VX6
VX7
VX1+
VX1-
VX2+
VX2-
VX3+
VX3-
VX4+
VX4-
VX5+
VX5-
VX6+
VX6-
VX7+
VX7-
k3VCA
U7
K2BS
K3V
VS1
VX1
VX2
VX3
VX4
VX5
VX6
VX7
VX3CA
VX2CA
VX1CA
VX6CA
VX5CA
VX4CA
k2BSCA
VX7CA
LC4BC 10uH
1
2
LC3BC 10uH
1
2
LC2BC 10uH
1
2
LC1BC 10uH
1
2
X2BC
SCR ARR-2IB
VX+ VX-
A+K-
A-K+
X3BC
SCR ARR-4IB
VX+ VX-
A+K-
A-K+
X4BC
SCR ARR-8IB
VX+ VX-
A+K-
A-K+
VX1BC+ X5BC
SCR ARR-2IB
VX+ VX-
A+K-
A-K+
X6BC
SCR ARR-4IB
VX+ VX-
A+K-
A-K+
X7BC
SCR ARR-8IB
VX+ VX-
A+K-
A-K+
VX3BC+
LB
i
LC
i
LA
i
B
i
C
i
A
i
SB
i
SC
i SA
i

 ISSN: 2088-8708
3868
Figure 10. AC voltages detection circuit of 11 kV 50 Hz load currents balancing system
Figure 11. Computation circuit of 11 kV 50 Hz load currents balancing system

3869
3. RESULTS AND DISCUSSION
Many tests were carried out to demonstrate the linearity and the control continuity of the
compensator. Figure 12 shows the variations of the compensator reactive current as the reactive current
demand varies from maximum inductive to maximum capacitive. The minus sign indicates the reactive
current is inductive. The deviations of the actual response from the linear continuous response are negligible
compared to the compensator reactive current rating, thus it can be said that the compensator current to some
extent is linearly and continuously controlled.
The 11 kV 50 Hz BWSCB and BWSRB based SVC is characterized by fast response to the abrupt
changes in reactive demand. This property is demonstrated in Figure 13. The figure shows the SVC treatment
to a sudden change in reactive current demand from maximum capacitive to maximum inductive.
Figure 12. The reactive current of the 11 kV 50 Hz BWSCB and BWSRB based SVC against reactive current
demand
Figure 13. Treatment of the 11 kV 50 Hz BWSCB and BWSRB based SVC to sudden change in reactive
current demand from maximum capacitive to maximum inductive. The change was at t=60 msec and the
transition time was 5 msec

 ISSN: 2088-8708
3870
The load currents balancing systems shown in Figure 9 was tested on PSpice at different loading
conditions to investigate its effectiveness and reliability during its treatment to unbalance cases and
somewhat poor power factor loads. The system is designed for load currents balancing for an 11 kV 50 Hz
distribution station in Iraq. The station involves five feeders. The average line current drawn from this station
varies in the range of 1,200 to 1,300 A (rms values) depending on the daily loading conditions. Figure 14
shows the unity power factor correction of a balanced ungrounded load of 1,796 A (peak value) at 0.707
lagging power factor handled by the 11 kV 50 Hz load balancing system using BWSCB and BWSRB based
SVCs.
Figure 14. Unity power factor correction of a balanced ungrounded load of 1796 A (peak value) at 0.707
lagging power factor handled by the proposed balancing system
Figure 15 shows the treatment of a certain moderate unbalance. This unbalance case is within the
distribution station rated current. The compensation process had resulted in balanced pure active currents iA,
iB, and iC drawn from the balanced three-phase AC source.
Time
40ms 50ms 60ms 70ms 80ms 90ms 100ms 110ms 120ms
V(VC:PVS) V(VA:PVS) V(VB:PVS)
-10KV
0V
10KV
Time
I(LA) I(LB) I(LC)
-2.0KA
0A
2.0KA
Time
-I(R4) -I(R5) -I(R6)
-2.0KA
0A
2.0KA
Time
I(R1) I(R2) I(R3)
-2.0KA
0A
2.0KA
A
v B
v C
v
A
i B
i
LA
i
C
i
LB
i
SA
i SB
i SC
i
LC
i

3871
Figure 15. Balancing mechanism of a moderate load unbalance within the rated current of the distribution
station handled by the 11 kV 50 Hz load currents balancing system using BWSCB and BWSRB based SVCs
The treatment of a somewhat severe unbalance case is shown in Figure 16. The above unbalance
case can be considered severe, since there are significant phase and magnitude unbalance associating the load
currents. The balancing process of this unbalance case had yielded balanced active currents iA, iB, and iC
drawn from the balanced three-phase AC power system.
The treatment of a severe load unbalance is shown in Figure 17. In this load unbalance, two of the
load line currents were exceeding the current capability of the distribution station. It is obvious that the
compensation requirements of the above load unbalance were greater than the compensator capability, thus
the unbalance was not settled completely. But the compensation process had resulted in large mitigation of
phase and magnitude unbalances associating the currents drawn from the AC source What is more, the AC
source currents are all brought into the rating capability of the distribution station. This treatment has a
Time
I(R1) I(R2) I(R3)
-2.0KA
0A
2.0KA
Time
I(LA) I(LB) I(LC)
-2.0KA
0A
2.0KA
Time
V(VC:PVS) V(VA:PVS) V(VB:PVS)
-10KV
0V
10KV
Time
-I(R4) -I(R5) -I(R6)
-2.0KA
0A
2.0KA
A
v B
v C
v
A
i B
i
LA
i
C
i
LB
i LC
i
SA
i
SB
i SC
i

 ISSN: 2088-8708
3872
significant impact in the distribution system in Iraq, since the power consumption is somewhat uncontrollable
due to the great lack in the available electrical energy there.
The compensating susceptance constructed of 11 kV 50 Hz BWSCB and BWSRB showed during
PSpice investigations fast response to slow and abrupt variations in reactive current demand without any sort
of harmonic association. In addition, its transient response time was short. This compensating susceptance
has zero no load operating losses. The transformerless load currents balancing system constructed by
connecting three identical 11 kV 50 Hz compensating susceptances in delta form has a reactive power rating
of about 17.1 MVARs (capacitive or inductive). The system is capable to correct to unity the power factor of
an Iraqi 11 kV 50 Hz distribution station delivering a balanced three-phase rms current of 1270 A at a 0.707
lagging power factor.
Figure 16. The balancing mechanism of a somewhat severe unbalance case within the distribution station
rating handled by the 11 kV 50 Hz load currents balancing system using BWSCB and BWSRB based SVCs
Time
V(VA:PVS) V(VB:PVS) V(VC:PVS)
-10KV
0V
10KV
Time
I(LA) I(LB) I(LC)
-2.0KA
0A
2.0KA
Time
-I(R4) -I(R5) -I(R6)
-2.0KA
0A
2.0KA
Time
I(R1) I(R2) I(R3)
-2.0KA
0A
2.0KA
A
v B
v C
v
A
i B
i
LA
i
C
i
LB
i
SA
i
SB
i SC
i
LC
i

3873
Figure 17. Balancing mechanism of a severe load unbalance beyond the distribution station rating handled by
the 11 kV 50 Hz load currents balancing system using BWSCB and BWSRB based SVCs
4. CONCLUSION
The compensating susceptance constructed of 11 kV 50 Hz BWSCB and BWSRB showed during
PSpice investigations fast response to slow and abrupt variations in reactive current demand without any sort
of harmonic association. In addition, its transient response time was short. This compensating susceptance
has zero no load operating losses. The transformerless load currents balancing system constructed by
connecting three identical 11 kV 50 Hz compensating susceptances in delta form has a reactive power rating
of about 17.1 MVARs (capacitive or inductive). The system is capable to correct to unity the power factor of
Time
V(VA:PVS) V(VB:PVS) V(VC:PVS)
-10KV
0V
10KV
Time
I(LA) I(LB) I(LC)
-2.5KA
0A
2.5KA
Time
-I(R4) -I(R5) -I(R6)
-2.5KA
0A
2.5KA
Time
I(R1) I(R2) I(R3)
-2.5KA
0A
2.5KA
A
v B
v C
v
A
i
B
i
LA
i
C
i
LB
i
SA
i
SB
i
SC
i
LC
i

 ISSN: 2088-8708
3874
an Iraqi 11 kV 50 Hz distribution station delivering a balanced three-phase rms current of 1,270 A at a
0.707 lagging power factor. The system had showed excellent results in performing the task, which was
designed for. In addition, the system had treated efficiently different load unbalances; some of them were
exceeding the distribution station current rating and the permissible tolerance of load unbalance determined
by the protection system installed in the station. The load unbalances which were within the load currents
balancing capability had been recovered with balanced active line currents associated with significant
reduction in their magnitudes. The system had greatly mitigated the severe load unbalances which were
beyond its compensation capability.
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BIOGRAPHIES OF AUTHORS
Abdulkareem Mokif Obais was born in Iraq in 1960. He received his B.Sc. and
M.Sc. degrees in Electrical Engineering from the University of Baghdad, Baghdad, Iraq, in
1982 and 1987, respectively. He received his Ph.D. degree in Electrical Engineering from
Universiti Tenaga Nasional, Kajang, Malaysia in 2013. He is interested in electronic circuit’s
design and power electronics. He had supervised and examined a number of postgraduate
students. He had published many papers in Iraqi academic and international journals. Dr.
Obais was promoted to Professor at University of Babylon in April 2008. He can be contacted
at email: eng.abdul.kareem@uobabylon.edu.iq.
Ali Abdulkareem Mukheef was born in Iraq in 1995. He received his B.Sc. and
M.Sc. degrees from University of Babylon, Iraq in 2016 and 2020, respectively. He is one of
the Academic Staff of Almustaqbal University College, Babylon, Iraq. Presently, he is a Ph.D
student at University of Babylon, Babylon, Iraq. He can be contacted at email:
ali.abdulkreem@mustaqbal-college.edu.iq.

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