Exception handling on the x86
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When an interrupt or exception occurs in the x86 architecture, it is assigned a number called a vector. The vector determines which interrupt handler code is invoked to handle the interrupt. Common software and hardware sources of interrupts include exceptions from invalid operations, device interrupts mapped through the Programmable Interrupt Controller (PIC), and software-generated interrupts using the INT instruction. The Interrupt Descriptor Table (IDT) contains interrupt handler entries that are invoked by vector number, and the IDTR register stores the location of the active IDT. The IF flag and STI/CLI instructions control whether maskable hardware interrupts are allowed to occur.
Exception handling on the x86
- 1. X86 Interrupts Notes By: Shehrevar Davierwala Exception Handling on the x86 x86 Interrupt Vectors:: - Every Exception/Interrupt type is assigned a number: - its vector - When an interrupt occurs, the vector determines what code is invoked to handle the interrupt. - JOS example: vector 14 → page fault handler vector 32 → clock handler → scheduler 0 -Divide Error 2 -Non-Maskable Interrupt 3 -Breakpoint Exception 6 -Invalid Opcode 11- Segment Not Present 12 -Stack-Segment Fault 13 -General Protection Fault 14 -Page Fault 18 -Machine Check 32-255 -User Defined Interrupts Sources: Hardware Interrupts: Hardware Interrupt Types: Non-Maskable Interrupt - Never ignored INTR Maskable - Ignored when IF is 0 PIC: Programmable Interrupt Controller (8259A) - Has 16 wires to devices (IRQ0 – IRQ15) - Can be programmed to map IRQ0-15 → vector number - Vector number is signaled over INTR line. - In JOS/lab4: vector ← (IRQ# + OFFSET) Sources: Software-generated Interrupts: Programmed Interrupts - x86 provides INT instruction. - Invokes the interrupt handler for vector N (0-255) - JOS: we use 'INT 0x30' for system calls Software Exceptions - Processor detects an error condition while executing an instruction.
- 2. X86 Interrupts Notes By: Shehrevar Davierwala - Ex: divl %eax, %eax - Divide by zero if EAX = 0 - Ex: movl %ebx, (%eax) - Page fault or seg violation if EAX is un-mapped virtual address. - Ex: jmp $BAD_JMP - General Protection Fault (jmp'd out of CS) Enabling / Disabling Interupts: Maskable Hardware Interrupts - Clearing the IF flag inhibits processing hardware interrupts delivered on the INTR line. - Use the STI (set interrupt enable flag) and CLI (clear interrupt enable flag) instructions. - IF affected by: interrupt/task gates, POPF, and IRET. Non-Maskable Interrupt - Invoked by NMI line from PIC. - Always Handled immediately. - Handler for interrupt vector 2 invoked. - No other interrupts can execute until NMI is done. IDT: Interrupt Descriptor Table: IDT: - Table of 256 8-byte entries (similar to the GDT). - In JOS: Each specifies a protected entry-point into the kernel. - Located anywhere in memory. IDTR register: - Stores current IDT. lidt instruction: - Loads IDTR with address and size of the IDT. - Takes in a linear address.