Fpga 12-event-control

ENGR. RASHID FARID CHISHTI
LECTURER, DEE, FET, IIUI
CHISHTI@IIU.EDU.PK
WEEK 12
REGULAR EVENT CONTROL
NAMED EVENT CONTROL
EVENT OR CONTROL,
LEVEL-SENSITIVE TIMING CONTROL.
FPGA Based System Design
Sunday, May 17, 2015
1
www.iiu.edu.pk

 An event is the change in the value on a register or a net. Events can be utilized
to trigger execution of a statement or a block of statements.
 There are four types of event-based timing control:
1. Regular event control, 2. Named event control,
3. Event OR control, 4. Level-sensitive timing control.
1. Regular event control: The @ symbol is used to specify an event control.
Statements can be executed on changes in signal value or at a positive or
negative transition of the signal value.
Example: Regular Event Control
@(clock) q = d; // q = d is executed whenever signal clock changes value
@(posedge clock) q = d; // q = d is executed whenever signal clock does
//a positive transition ( 0 to 1,x or z, x to 1, z to 1 )
@(negedge clock) q = d; //q = d is executed whenever signal clock does
// a negative transition ( 1 to 0,x or z,x to 0, z to 0)
q = @(posedge clock) d; // d is evaluated immediately and assigned
// to q at the positive edge of clock
www.iiu.edu.pk Sunday, May 17, 2015
Event-Based Timing Control
2

2. Named event control: Verilog provides the capability to declare an event and
then trigger and recognize the occurrence of that event.
The event does not hold any data. A named event is declared by the keyword
event. An event is triggered by the symbol ->. The triggering of the event is
recognized by the symbol @.
Example: Named Event Control
// using data buffer for storing data after the last packet of data has arrived.
event received_data; // Define an event called received_data
always @(posedge clock) // check at each positive clock edge
begin if (last_data_packet) // If this is the last data packet
-> received_data; // trigger the event received_data
end
always @(received_data) // Await triggering of event received_data
// When event is triggered, store all four packets of received data in data buffer
// use concatenation operator { }
data_buf = {data_pkt[0], data_pkt[1], data_pkt[2], data_pkt[3]};
3

3. Event OR Control: A transition on any one of multiple signals or events can
trigger the execution of a statement or a block of statements. This is expressed
as an OR of events or signals. The list of events or signals expressed as an OR
is also known as a sensitivity list. The keyword or is used to specify multiple
triggers,
Example: Event OR Control (Sensitivity List)
// A level-sensitive latch with asynchronous reset
always @( reset or clock or d) // Wait for reset or clock or d to change
begin if (reset) // if reset signal is high, set q to 0.
q = 1'b0;
else if(clock) // if clock is high, latch input
q = d;
end
Sensitivity lists can also be specified using the "," (comma) operator instead of
the or operator. Comma operators can also be applied to sensitivity lists that
have edge-sensitive triggers.
4

Example: Sensitivity List with Comma Operator
// A level-sensitive latch with asynchronous reset
always @( reset, clock, d) // Wait for reset or clock or d to change
begin if (reset) // if reset signal is high, set q to 0.
q = 1'b0;
else if (clock) // if clock is high, latch input
q = d; end
// A positive edge triggered D flipflop with asynchronous falling reset can be
// modeled as shown below
always @(posedge clk, negedge reset) // Note use of comma operator
if (!reset) q <=0;
else q <=d;
When the number of input variables to a combination logic block are very large,
sensitivity lists can become very cumbersome to write. Moreover, if an input
variable is missed from the sensitivity list, the block will not behave like a
combinational logic block.
5

To solve this problem, Verilog HDL contains two special symbols: @* and @(*).
Both symbols exhibit identical behavior. These special symbols are sensitive to a
change on any signal that may be read by the statement group that follows this
symbol.
Example: Use of @* Operator
// Combination logic block using the or operator Cumbersome to write and it is
// easy to miss one input to the block
always @(a or b or c or d or e or f or g or h or p or m) begin
out1 = a ? b+c : d+e;
out2 = f ? g+h : p+m; end
// Instead of the above method, use @(*) symbol. Alternately, the @* symbol can
// be used. All input variables are automatically included in the sensitivity list.
always @(*) begin
out1 = a ? b+c : d+e;
out2 = f ? g+h : p+m;
end
6

4. Level-Sensitive Timing Control: Event control discussed earlier waited for the
change of a signal value or the triggering of an event.
 The symbol @ provided edge-sensitive control.
 Verilog also allows level-sensitive timing control, that is, the ability to wait for a
certain condition to be true before a statement or a block of statements is
executed.
 The keyword wait is used for level-sensitive constructs.
always wait (count_enable)
count = count + 1;
 In the above example, the value of count_enable is monitored continuously.
 If count_enable is 0, the statement is not entered.
 If it is logical 1, the statement count = count + 1 is executed.
 If count_enable stays at 1, count will be incremented continuously.
7

Fpga 12-event-control

More Related Content

What's hot (20)

Similar to Fpga 12-event-control (20)

More from Malik Tauqir Hasan (12)

Recently uploaded (20)

Fpga 12-event-control