FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGIC

FULL ADDER/ SUBTRACTOR
USING REVERSIBLE LOGIC
Dr. B. Balaji1
, M.Aditya2
,Dr.Erigela Radhamma3
,
Dr.Venkatrami Reddy4
,Dr.Y Naresh5
Associate Professor1
,Assistant Professor2
, Assistant Professor3
,
Assistant Professor4
, Assistant Professor5
Koneru Lakshmaiah Educational Foundation1,2
(KLEF)Green Fields, Vaddeswaram,
Guntur -Dist 522502. Brilliant Inst of Engg &Tech3
,
HYD.GATE Engg College4,5
,kodad
April 6, 2018
Abstract
Reversible logic is now-a-days emerging as an im-portant
research area over conventional logic. It is having variety
of applications in ﬁelds of Digital Signal Processing, Quan-
tum Computing and Low Power CMOS Design. Irreversible
logic circuits dissipate heat for every bit of information that
is lost. It is not possible to think of quantum computing
without implementation of reversible logic. The main pur-
poses of designing reversible logic are to decrease quantum
cost, depth of the circuits and the number of garbage out-
puts. This paper provides the Full adder/subtractor that
uses Half adder/ subtractor with minimum constant inputs
and minimum garbage outputs. Thus the proposed archi-
tecture Full Adder/ Subtractor is having minimum number
of Constant Inputs and Garbage Outputs than the Existing
architecture.
Key Words:Quantum Computing, Reversible Logic,
Garbage outputs, Constant Inputs.
1
International Journal of Pure and Applied Mathematics
Volume 120 No. 6 2018, 437-446
ISSN: 1314-3395 (on-line version)
url: http://www.acadpubl.eu/hub/
Special Issue
http://www.acadpubl.eu/hub/
437

1 Introduction
According to Landaurer [1], KTln2 Joules of heat energy is pro-
duced for every bit of information lost during irreversible computa-
tion, where K is Boltzmann constant and T is absolute temperature.
For room temperature T the amount of dissipating heat is small (i.e.
2.9X10-21 J ), but not negligible. This amount may not seem to be
significant, but it will become relevant in the future. This energy
dissipation would not occur during reversible computation as there
is no loss of information
[2]. Reversible circuits always maintain one-to-one mapping be-
tween the inputs and the outputs, and is performed by reversible
logic gates. There are outputs in reversible circuits which are nei-
ther used in the further stages of computation nor restore any orig-
inal inputs. These redundant outputs are called garbage outputs.
There are constant inputs (0 or 1) which are used in reversible
quantum circuits for storing intermediate values during computa-
tion. Reversible circuits are designed using reversible logic gates
such as Fredkin, Toffoli, Feynman, Peres etc. Reversible logic has
wide variety of applications in the field of emerging technologies
such as quantum computers, optical computing, Cellular automata,
ultra- low power VLSI
[3].
This paper is organized as follows. In Section II, the physi-
cal model of Reversible Logic is described. The concept of Parity
Preserving Reversible Gates is discussed in Section III in order to
validate our model. In Section IV, the design of Half Adder/ Sub-
tractor and Full Adder/ Subtractor is shown. Finally, in Section V,
the conclusion of this paper is given.
Fig. 1. n*n Reversible Logic Gate
2
International Journal of Pure and Applied Mathematics Special Issue
438

2 REVERSIBLE LOGIC
A Reversible Logic Gate should produce one-to-one map-ping be-
tween Inputs and Outputs, so that reversibility is maintained. That
is Reversible Gate is Bijective between Inputs and Outputs. It not
only helps us to determine the outputs from the inputs but also
helps us to uniquely recover the inputs from the outputs [4].
Additional inputs or outputs can be added so as to make the
number of inputs and outputs equal whenever necessary. This also
refers to the number of outputs which are not used in the synthesis
of a given function. In certain cases these become mandatory to
achieve reversibility.
Inputs + Constant Inputs = Outputs + garbage
Fig. 1 shows a n-input and n-output Reversible Logic Gate and
is called as n*n Reversible logic gate, where nth
input of logic gate
is given by In and nth
output is given by On.
There exist many reversible gates in the literature. Among them
2*2 Feynman gate (shown in Fig. 2), 3*3 Feynman Double Gate
(shown in Fig. 3), 3*3 Fredkin gate [5] (shown in Fig. 4) are the
most preferred.
The Feynman Gate shown consists of two inputs A and B, two
outputs P(= A) and Q(= A B).
Fig. 2. Feynman Gate
The Feynman Double Gate shown consists of 3 inputs A,B and
C, 3 outputs P(= A),Q(= A xor B) and R(= A xor C).
Fig. 3. Feynman Double Gate
The Fredkin Gate shown consists of 3 inputs A,B and C, 3
outputs P(=A),Q(= AB xor AC) and R(= AC xor AB).
3
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Fig. 4. Fredkin Gate
3 PARITY PRESERVING REVERSIBLE
GATES
A Reversible Gate is said to be Parity Preserving if it maintain
constant Parity between Input and output. Let us consider Fredkin
Gate Truth Table with inputs A,B,C and outputs P,Q,R.
Fig. 5. Fredkin Gate
From the truth table we observe that parity between inputs and
outputs is same
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4 PROPOSED WORK
4.1 DESIGN OF HALF ADDER/ SUBTRAC-
TOR
As we know that for a Half adder, there are two inputs and two
outputs. This itself looks like a Reversible Gate satisfying basic
property of Reversibility. But in order to maintain reversibility we
have introduced some constant inputs and Garbage Outputs. The
Logical Equations governing Half Adder are
SUM = A xor B
CARRY = A B
and that for Half Subtractor are
DIFFERENCE = AB
BORROW = AB
Thus a single circuit can work as a Half Adder and Half Subtrac-
tor using a Control (Ctrl) Input. Now for Half Adder/ Subtractor,
SU M=DIFFERENCE = A xor B
CARRY =BORROW = Ctrl AB+ Ctrl A B
1) Proposed Half Adder/Subtractor: The proposed Half Adder/Subtractor
uses two Feynaman Double Gates and two Fredkin Gates. The In-
puts are A, B, Ctrl. The constant inputs that are needed to main-
tain reversibility are O1 and O2. The outputs obtained are SD and
CB. There are also Garbage Outputs g1, g2 and g3.
The following is the proposed architecture for Half Adder/ Sub-
tractor
Fig. 6. Fault Tolerant Half Adder/ Subtractor
5
441

The symbol showing Fault Tolerant Half Adder/ Subtractor
with 5 inputs (3 Inputs and 2 constant inputs) and 5 outputs (2
outputs and 3 garbage outputs) is given in Fig.7
Fig. 7. Symbol for Fault Tolerant Half Adder/ Subtractor
4.2 DESIGN OF FULL ADDER/ SUBTRAC-
TOR
In the design of Full Adder/ Subtractor circuit, the conven-tional
method of using Two Half Adder circuits is followed. Here it makes
use of two Fault tolerant Half Adder/ Subtractor with a control
input. The equations governing Full Adder with A, B and C inputs
is
SUM = A xor B xor C
CARRY = AB + BC + CA = (A xor B)C xor AB
and that for Full Subtractor are,
DIFFERENCE = A xor B xor C
BORROW = (AxorB)C + AB
1) Proposed Full Adder/ Subtractor: The Proposed Full Adder/
Subtractor uses Two Fault tolerant Half Adder/ Sub-tractors and
a Feynman Double Gate.
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Fig. 8. Fault Tolerant Full Adder/ Subtractor
The Symbol showing Fault Tolerant Full Adder/ Subtractor
with 9 Inputs (4 inputs and 5 Constant Inputs) and 9 Outputs
(2 Outputs and 7 Garbage Outputs) is shown in Fig. 9
4.3 COMPARISON OF PROPOSED ARCHI-
TECTURE WITH EXISTING ARCHITEC-
TURE
Table II shows comparison of Half adder/Subtractor for existing [6]
and proposed architectures and Table III shows comparison of Full
Adder/Subtractor.
Fig.8. Hardware circuit Load connected
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5 CONCLUSION
As Constant Inputs and Garbage Outputs are required to maintain
Reversibility, their number needs to be minimized. The Proposed
architecture has minimized both the Constant Inputs and Garbage
Outputs in comparison with existing architecture.
References
[1] R. Landauer, Irreversibility and heat generation in the com-
puting pro-cess, IBM Journal of Research and Development,
vol. 5, no. 3, pp. 183 191, July 1961.
[2] C. Bennett, Logical reversibility of computation, IBM Journal
of Research and Development, vol. 17, no. 6, pp. 525532, Nov
1973.
[3] S. K. S. Hari, S. Shroff, S. Mahammad, and V. Kamakoti, Effi-
cient building blocks for reversible sequential circuit design, in
Circuits and Systems, 2006. MWSCAS 06. 49th IEEE Interna-
tional Midwest Symposium on, vol. 1, Aug 2006, pp. 437441.
[4] J. Bruce, M. Thornton, L. Shivakumaraiah, P. Kokate, and X.
Li, Efficient adder circuits based on a conservative reversible
logic gate, in VLSI, 2002. Proceedings. IEEE Computer Society
Annual Symposium on, 2002, pp. 7479.
[5] D. Maslov, G. Dueck, and D. Miller, Synthesis of fredkin-toffoli
re-versible networks, Very Large Scale Integration (VLSI) Sys-
tems, IEEE Transactions on, vol. 13, no. 6, pp. 765769, June
2005.
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[6] P. Kaur and B. Dhaliwal, Design of fault tolearnt full
adder/subtarctor using reversible gates, in Computer Commu-
nication and Informatics (ICCCI), 2012 International Confer-
ence on, Jan 2012, pp. 15.
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FULL ADDER/ SUBTRACTOR USING REVERSIBLE LOGIC

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