Hard IP Core design | Convolution Encoder
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The document outlines the development of a hard intellectual property core for a convolution encoder, detailing steps like IP-core selection, VHDL and Verilog coding, implementation on FPGA, and comparison with existing cores. It includes information on applications in wireless communication, design specifications, layouts, and simulation results. The conclusion highlights valuable learnings from the VLSI industry and references for further reading.
Hard IP Core design | Convolution Encoder
- 1. Development of Hard Intellectual Property core for Convolution Encoder Guide: Prof. Usha Mehta Prepared By:- Archit (09bec101) Aalay (09bec025)
- 2. Steps Selection of IP-Core and its theory and study of IP-core VHDL and Verilog coding Implementing code on FPGA kit Layout MICROWIND software tool Comparison and readings
- 3. Review 1 Selection of IP-Core and its theory and study of IP-core VHDL and verilog code for state machine apprach
- 4. About convolution codes Error Correcting Code Sequential Codes Constraint length (k) (trade-off) Rate of Coder (r) (trade-off) Why so named ? Applications (wireless communication) Popular Codes (k=7; r=1/2)
- 5. Applications Wireless Standards : W-LAN, Wi-Max etc. Satellite communication Cellular Standards : GSM, CDMA, 3G etc.
- 7. Example
- 12. Review 2 Both VHDL and Verilog codes are ready with block diagram approach Constraint Length 7; Rate ½ Results showing comparison with Coregen(Core Generation) Each component is made in microwind Dimension of Each Component made Also a C code for convolution coder is made to easy testing
- 14. Proposed code
- 15. Proposed Code
- 16. Proposed Code
- 17. Coregen
- 18. Coregen
- 20. Components required No of components No of Transistors DFF 6 16 XOR2 4 4 XOR_regular 1 6
- 21. Layouts of each component
- 22. Layouts of DFF
- 23. Layouts of 2 input Xor XOR_2 Complements Available
- 24. Layouts of 2 input Xor XOR Regular Complements Not Available
- 25. Design schematic
- 26. Comparison with Verilog Compilation Using Verilog coding 63 NMOS 51 PMOS 114 Total Buffers not provided Metalization 3 levels Area = 575.28 µm Highly rectangular Proposed Hard IP 60 NMOS 60 PMOS 120 total Bufferes provided Metalization 2 layers Area 186.3 square µm Almost square
- 27. Review 3 Floor Planning Complete Layout SPICE simulation
- 28. Floor Planning
- 29. Floor Planning
- 30. Floor Planning
- 31. Pinout
- 32. Final Layout
- 33. Simulation
- 34. Spice Netlist Exported from Microwind Got introduced to Tanner, Mentor Graphics and SPICE syntax Readings are taken from Mentor Graphics
- 35. Readings Maximum Average Power dissipation 0.622 mW 0.130 mW Idd 0.519 mA 0.109 mA X to Z1 48.706 ps 38.347 ps X to Z2 66.721 ps 40.2042 ps Clk to Z1 49.974 ps 36.343 ps Clk to Z2 57.999 ps 38.493 ps Core Size : 186.3 sq. um Supply : 1.2 V
- 36. Summary Xilinx ISE: – Verilog, RTL, Spartan 3 kit DSCH: – Gate level, Transistor level Microwind: – Floor planning, Layout Mentor Graphics: – SPICE Simulation
- 37. Conclusion Great learnings – VLSI Industry – Coregen Implementation – Verilog Coding Better than Xilinx Coregen Better than direct Verilog Implementation
- 38. References Basics Of CMOS Cell Design – Etienne Sicard, Sonia Delmas Bendhia CMOS VLSI DESIGN : A Circuit and System Perspective – Neil H. E. Weste, David Harris, Ayan Banerjee CMOS Digital Integrated Circuit,3/E – Sung-Mo-Kang, Yusuf Leblebici
- 39. References Spice User Manual Draft 10 T-Spice 12 user guide – Tanner EDA tools Open Source Semiconductor Core Licesing – Harvard Journal of Law and Technology Digital Design 4th Edition – Morris Mano
- 40. Questions ??
- 41. Thank you ! Prof. Usha Mehta Mr. Dharmesh Patel Mr. Prasann Shukla Nirma University and All Professors – 4 years of great learning