Analog vs digital integrated circuit design

Editor's Notes

• #3: The individual circuit components are generally microscopic in size.
• #4: Semiconductors have been the driving force of technology for many years now. The remarkable growth in the semiconductor industry is primarily due to the advances in large-scale integration technologies. <clcik> In the era of gigascale integration, Millions to billions of transistors are integrated in a single chip. This paves way to the increasing capabilities of microprocessors in consumer electronics such as <click> smartphones, tablets, gaming devices, wireless appliances and car electronics, even more so in the emerging technologies like 5G and AI.
• #6: According to Moore’s law, The number of transistors in a computer chip doubles roughly every two years. As the number of transistors increases, so does processing power. As the number of transistors increases, the cost per transistor falls. In the era of gigascale integration, millions to billions of transistors are integrated in a single chip.
• #7: <click>Performance, <click> Power, <click> Area. These three are the most cited criteria for a successful design. However.. At advanced process nodes, IC designers are facing three major challenges. First, the strong correlation between chip performance <click> and frequency poses a challenge to support higher clock frequencies. The second challenge <click> is lowering the power consumption to support longer battery life of portable devices. Third, <click> technology scaling allows denser integration leading to higher net/signal loading that may degrade performance if not addressed accordingly .
• #18: A digital IC design flow is a sequence of operations that transform RTL code into layout for fabrication. Shown here are just basic steps in digital design flow. <click>The design starts with design specifications of the IC. During this step, the overall goals of the design is specified. These goals and requirements span functionality, performance, physical dimensions and production technology. <click> The design is implemented at the register-transfer level (RTL) using a hardware description language (HDL) such as VHDL and Verilog. This is done by means of programs that define the functional and timing behavior of a chip. The HDL modules must then be thoroughly simulated and verified to ensure its functionality. <click> Once the functionality of the RTL Code has been verified, logic synthesis converts HDL into low-level circuit elements such as standard cells , gates and transistors. . The logic synthesis maps the described functionality to a list of signal nets called netlist. <click> Logic Verification ensures that the gate-level netlist meets the design constraints. <click> During physical design, all design components in the netlist are instantiated with their geometric representations. In other words, all cells, gates, transistors with fixed shapes and sizes per fabrication layer are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers. In short, physical design creates the layout based on the netlist provided by the logic synthesis. <click> Physical verification ensures that Physical design is performed with respect to design rules that represent the physical limitations of the fabrication medium. For instance, all wires must be a prescribed minimum distance apart and have prescribed minimum width. <click> The final result of physical design will then be handed for fabrication.
• #20: A manual process in the past, still mostly manual for Analog Logic Synthesis (1989): automate the process Many discrete optimization techniques used here: boolean minimization, static timing analysis, state equivalence, etc, etc. End point is a “netlist”, meaning a set of logic gates and their connections. A large netlist is in the 10s of millions of gates Can be simulated or “formally verified” versus the RTL.
• #21: Click first! This step is very important before moving on to the next step. To make sure that your gate-level netlist is logically equivalent with the RTL code
• #22: Floorplanning Where do we place the large blocks? Where do we place the “random” logic and “structured blocks”? A combination of manual and automated approaches is used Need to keep connections short to meet timing, but also cannot “congest” the design too much or we cannot complete the connections Note that connections do have R and C (to substrate and coupling between wires) so they introduce delay! Meeting timing can be very difficult! The Power and Ground lines usually get decided here Placement: Now we need to complete the exact details of where each block and gate will be Automation has been a key for many years (1980). A block may contain hundreds of thousands of cells, so it is very hard problem: minimize area, be routable and meet timing Note may have to add logic: repeaters to restore signals a key example Routing Complete all the connections! But, need to meet timing and keep signal integrity. This also involve separating some wires, for example, to avoid bad couplings Automation is the norm here (1980)
• #23: Spacing and sizing rules are checked for all polygons (1980) Parasitics are extracted, netlists back annotated and time analyzed using static techniques (1990) Manufacturing requires complicated rules, such as wire density been “uniform”
• #24: Finally
• #25: Thank you po for listening.
• #27: Thank you po for listening.