High speed board design considerations
- 1. 1 AN22 02/09/00 –4 –2 –1 2cm 1 Distance (cm) 100 MHz 10 GHz 1 GHz 2 4 Introduction Today’s board design is not as simple as it was in the past. Current high-speed designs demand a board designer’s extensive knowl- edge of these issues: transmission line effect, EMI, and crosstalk. The designer also needs to be an expert concerning board material, signal and power stacking, connectors, cables, vias, and trace dimensions. Pericom offers an extensive line of clock products for desktop, notebook, set-top boxes, information devices, servers, and work- stations. This application note will help a designer ensure proper termination,placement,routing,andstackingof theboardtoensure proper data transfers between the microprocessor, cache, main memory, and expansion busses. Q. Is this a transmission line or a two wire interconnect? This is a very important question that we need to answer before starting a PCB design. It is crucial because transmission lines act differently than a simple wire. Ifwehavea100Hzcircuitthatisdrivinga1MegOhmloadthrough a one meter wire, then the resistivity of the line is negligible compared to the load. The equation V = V0 (1-e ) is used to determine the characteristic of the signal. The step voltage input will be delayed by the RC constant. If, however, this circuit is running at 100 MHz, then the analysis shown above does not work and we need to treat this as a transmission line. We have to use Transmission Line Theory to determinetheresponseofthiscircuit.Ifthistransmissionlineisnot terminated properly, you will have the following to contend with: ringing delays, overshoot, and undershoot. Other conditions that couldaffectyourcircuitarecrosstalk,driveroverload,andreduced noise margins. Any of which will ensure that your board is not workingproperly. Q. How do we determine if this is a transmission line? The length of the interconnection and the frequency of the circuit is the answer. If the length of the interconnection is larger than a tenthofthesignal’ssinusoidalwavelength,youwillhavetorelyon Solutions to Current High-Speed Board Design By Mohamad Tisani 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Application Note 22 transmission line theory. For example, if you have a 32-inch long interconnect when the frequency is higher then 25 MHz, you can treat the interconnect as a transmission line. If it is 24 MHz and lower, it is a lumped circuit. The analysis below will explain it further: λ = CT or λ = C/F λ = 320 inches = 8.2 m C = C0/ ( ) , for cable = 2.3 F = C/λ = 300x10 / 8.2 2.3 = 24 MHz Following are the wavelengths for various frequencies: λ=300x10 /100Hz=3000Km λ= 300 x 10 /100 MHz = 3m λ=300x10 /1GHz=30cm If you have a signal that is 10 GHz, 1 GHz, and 100 MHz, the waveforms are shown in Figure 1 through a 2-cm-long resistor. Notice that at 1 GHz the current differs slightly at each end. At 10 GHz you cannot define the current at one end or the other. Figure 1. Rε Rε 6 6 6 6 I t RC
- 2. 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Application Note 22 2 AN22 02/09/00 H BT W When discussing digital design, to determine the interconnection type, using the signal’s rise time is easier then relying on the wavelength. Transmission line theory should be used when the signal’s rise time is less then twice the propagation time Tp, or time of flight for the signal’s electromagnetic wave to reach the end of the interconnect. Consider the 32-inch and the 24 MHz in the previous example Tp = distance/velocity Tp=81cmx/ (2.3)/300x106 =4.15ns This is the time it takes the magnetic wave to make a one-way trip. 2Tp = 8.3ns time it takes to make 2-way trip. If the rise time is less then 8.3ns, it is a transmission line. If the rise is20percentoftheperiod,thentr=0.2x8.3ns.ThenT=41.5nsand F=24MHz. To save time in determining when to use transmission line theory, refer to the figure shown below. 0.25 16 14 12 6 IN. 3 IN. 1 IN. 10 8 6 4 2 0 0.5 0.75 TRANSMISSION LINE MAXIMUM UNTERMINATED WIRE 1 SIGNAL RISE TIME (ns) LINE LENGTH (cm) 1.25 1.5 1.75 2 CharacteristicImpedance The permitivity and permeability of the medium in which it travels determines the electromagnetic wave’s velocity of propagation. Velocity in free space is V0= 1/ (ε0µ0) = 300x106 m/s Permitivity ε, is the ability of a dielectric to store electric potential energy. Permitivity of free space is ε0= Permeability, µ, is the property of a magnetic substance that determines the degree to which the substance modifies the mag- netic flux in the region of a magnetic field that the substance occupies. Permeability of free space is µ0 = 4π*10 In free space the electromagnetic wave moves at the speed of light. Electrical signals in conducting wires propagate at a speed depen- dent on the surrounding medium. Propagation delay is the inverse of propagation velocity On a PC board the wave moves at the speed of light divided by the square root of the relative dielectric constant. The following table provides some examples. muideM yaleD ).ni/sp( cirtceleiD tnatsnoC )sevawoidar(riA 58 0.1 )yticolev%66(elbacxaoC 311 8.1 )yticolev%57(elbacxaoC 921 3.2 ecartretuo,BCP4RF 081-041 5.4-8.2 ecartrenni,BCPanimulA 072-042 01-8 PropagationDelayofElectromagnicFieldsinVariousMedia The most important parameter of the transmission line is the characteristicimpedance,Z0,theeffectivetransmissionlineimped- ance that the source signal driver sees during the signal’s high- speed transition. During that transition the driver sees only Z0 and does not see the load impedance, which is at the end of the transmission line. Z0= PCBTransmissionLine Today’s PCB are made of either Microstrip lines or Striplines. Microstrip H T W This line consists of two conductors separated by dielectric. The characteristic impedance can be calculated by this formula: Z0=(87/ εR+1.41)1n(5.98H/(0.8W+T)). This is an n approximation formula that is good enough for most situations. For more precise formulas, please check the references at the end of this note. Stripline This line consists of a strip of conductor in the middle of two conducting planes. The equation: Z0= (60/ εR)1n (4B/0.67πW(0.8+(TW))). Figure2. BoundaryBetweenWirePairs andTransmissionLine Figure3. Microstrip Figure 4. Stripline L/C -7H/m. 1 36π *10 –9 F/m.
- 3. 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Application Note 22 3 AN22 02/09/00 H H 8 The following are some trace geometry examples: Microstrip,75ΩΩΩΩΩ H H H 2H Microstrip,50ΩΩΩΩΩ Stripline, 75ΩΩΩΩΩ Stripline, 50ΩΩΩΩΩ H H 3 All Substrates FR–4; εεεεεR = 4.5 Z0 accuracy ±30% Figure5. CrossSectionsofApproximateTraceGeometries NeedtoProduce50-and75-OhmTransmissionLines MultipleLoadsonaTransmissionLine The above formulas apply if the trace have a single load . But with two or more loads use the following formulas: Z0 = Z0 + 1+ Cl is the added load capacitance per unit length. Transmission Line Analysis When using transmission line analysis it is important to remember that if the line is not matched, then there will be reflections that will introduce ringing. Ringing will take away from the system margin. if the load impedance Zl does not match Z0, then the signal energy thattheloaddoesnotabsorbreflectsbacktowardthesource.When the reflection reaches the source, if the source impedance does not match Z0, there is a reflection from the source back to the load. The reflections continue until the load, the source, and losses along the transmission line fully absorb the source energy. The reflection formula can be derived by the following: Vl = Vincident + Vreflected Il = I incident + I reflected . Reflection factor ρ = Zl-Z0/ Zl+ Z0 Note: If Zl = Z0 then the reflection is zero , the optimum operating situation. If Zl = Infiniti, then ρ = 1- z0/zl/ (1 + z0/zl) = 1 ρ = 1 or the whole incident wave will be reflected back if your input is 5 volts. You will then see 9 to 8 volts at the receiver, (see Fig.6) 10 Driver Output Receiver Input Time (ns) Voltage (V) 8 6 6 50 100 150 200 4 2 0 TerminationTechniques It is very important to properly terminate the transmission line. In this section we will discuss the termination techniques available to ensurethatthehigh-speedsystemboardwillworkaccordingtoplan and with considerable noise margin. The following are several termination techniques: series, parallel, Thevenin, AC, and diode- based. Advantages and disadvantages for each will be discussed. Figure6. ReflectionsDuetoMismatched TransmissionLine Cl/CO T’PD = tPD 1+ Cl/CO ‘
- 4. 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Application Note 22 4 AN22 02/09/00 Driver Load Z0 VCC RD R2 R1 R Driver Load Z0 RD SeriesTermination Series termination is source-end matching. Easy to apply, it is a series resistor that is inserted as close to the source as possible, see followingfigure: R Driver Load Z0 RD Thesumoftheoutputimpedanceofthedriverandtheseriesresistor should be equal to Z0 which is the characteristic impedance of the board trace. With this termination we still have a mismatch at the receiver’s end. The receiver typically has very high input imped- ance. A mismatch will cause a reflection of the same voltage magnitude as the incident wave. The receiving device sees the sum of the incident and reflected voltages (full voltage) and the added signalpropagatestothedrivingend.Sincethelineismatchedatthe driving end, no further reflections occur. The series termination has the following disadvantages: 1. Difficult to tune the value of the series resistor so that you have a precisely matched line. The output impedance of the driver changes depending on the output and the load. 2. The driving end of the transmission line does not see the full voltage until the round trip. This may cause problems in multi- drop systems. Z0 CBA 0 T 1 1 1 ½ ½ 1 2T +5V TIME R1=Z0 Propagation Delay = T Seconds Each trace shows the voltage versus time observed at that position D The series termination has the following advantages: 1. Series termination adds only one resistor to the circuit. 2. This type of termination does not add any DC load. 3. Power comsuption is the lowest. No extra impedance is added to ground. ParallelTermination Thisisalsocalledendtermination.Forthisterminationthedesigner must insert a resistor equal to the Z0 of the trace. This resistor is located close to the receiver and it is connected to ground or VCC. Figure9.ExampleofParallelTermination The driving waveform propagates fully all the way down the transmissionline.Sincethetransmissionlineismatched,therewill be no reflections back and forth Advantages 1. It is an easy and simple single resistor termination. 2. The signal’s rise time is delayed by the Z0C/2 time constant as compared with a Z0C time constant of a series termination. Disadvantages 1. More power is dissipated through the termination resistor. 2. The driver needs to supply additional DC current to the termi- nationresistor.IfZ0 =50ohms,theDCcurrentcanbevery high. I=5/50=100mA;largeforCMOScircuitry. 3. Thisterminationtogroundwillcausethefallingedgetobefaster then the rising edge. This might change the duty cycle. TheveninTermination This is also called dual termination. Two resistors R1 and R2 are connected to the receiver as shown in the following figure: R= Z0 Figure10.Exampleof TheveninTermination 3. To cut down the noise margin, the designer must accommodate for the delay in the setup time. 4. The rise time of the circuit will be slowed by the receiver’s capacitive load. Therefore you have to add a delay of the Z0C time constant. Z0= We must not exceed IOH and IOL max. This circuit is not recom- mended in TTL or CMOS circuits owing to the large currents required in the HI state. Figure 7. Series Terminator R1R2 R1+R2. Figure 8.
- 5. 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Application Note 22 5 AN22 02/09/00 Driver Load Z0 RD D2 D1 VCC Otherterminationsthatarenotrecommended ACTermination R C Driver Load Z0 RD Figure11.ExampleofACTermination DiodeTermination Figure12.ExampleofSchottkyDiodeTermination DecouplingCapacitors Every printed circuit board needs large bypass capacitors to balancetheinductanceofthepowersupplywiring.Everycapacitor has some lead inductance that increases as the frequency goes higher. That is why it is very important to place the capacitors as close to the VCC pin on the chip as possible. To reduce the series lead inductance effect, avoid the following: 1. long traces larger then 0.01 inch between the capacitor pad and the via. 2. use of capacitors other than surface mount. 3. skinny via holes less than an 0.035-inch diameter. Pericom’s clock product lines uses high-precision integrated ana- log PLLs that are sensitive to noise on the supply and ground pins which can dramatically increase the skew and output jitter. For maximum protection connect a 0.1µF and a 2.2 nF capacitor to everydigitalsupplypin.Alsousethree4.7µFs,one220nF,andone 2.2µF capacitor on the analog supply pin. Connect the other side to theanaloggroundpin.Ifyouarelimitedonspacea0.1µFcapacitor on every supply line will work. Place a 10µF cap from the main Power Island to the power plane supplied to the clock chip. Use high quality, low ESR, ceramic surface-mount capacitors. Stacking At low speeds currents follow the least resistant path, but at high speeds the current follows the least inductance path. The lowest inductance return path lies directly under the signal conductor, thereby minimizing the total loops between the outgoing and returning paths. That is why, if possible, it is important to separate the signal layers by ground planes. Also, do not cut part of the groundplanetobeusedforasignal’spath.Thatistotallyunaccept- able, because it will increase crosstalk considerably. Besides, it does not provide a clean return to those signals. Also use lower traceimpedancesinceitwilllowerundershootandovershoot.Best to use FR-4 material for board fabrication. Use 4- layer stack-up arrangement. Make sure you have a signal layerfollowedbythegroundlayer,thenthepowerlayer,andfinally the second signal layer. See Figure 13. shown below: Primary Signal Layer (½ oz. cu.) Ground Plane (1 oz. cu.) 5 mils 47 mils 5 mils PREPREG CORE Z = 60 Ohms Z = 60 Ohms Total Board Thickness = 62.6 PREPREG Power Plane (1 oz. cu.) Secondary Signal Layer (½ oz. cu.) Figure13.Four-LayerBoardStack-up Clockroutingandspacing Tominimizecrosstalkontheclocksignals,wemustuseaminimum of 0.014-inch spacing between the clock traces and others. If you havetouseserpentinetomatchtracelengthsonsimilarchips,make surethatyouhaveatleast0.018-inchspacingforthoseserpentines. Serpentines are not recommended for clock signals. Clock0.014" 0.018" Figure 14. Clock Trace Spacing Guidelines
- 6. 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Application Note 22 6 AN22 02/09/00 As we discussed in an earlier section, you need to terminate the transmission line. Use a series resistor closest to the source to drive thetransmissionline.MostofPericomclockproductshave approxi- mately an 25-ohm output impedance, so, if the impedance or the transmissionlineis65ohms,useaseriesresistorof40ohms.Clock traces should be between 1- and 10-inches long. To verify that the clock delay, undershoot, overshoot, and skew are within the system’s AC parameters, it is important that the designer perform prelayout and post layout signal integrity simulation on the clock lines.PericomProvidesIBISmodelsfortheentireclockproductline. If you are forced to make a tee perform the following: RS RS Figure15.SeriesTermination,MultipleLoads GeneralGuidelines 1. Limit your trace lengths. Longer traces display more resistance and induction and introduce more delays. It also limits the bandwidth which varies inversely with the square of trace length. 2. Use higher impedance traces. Raising the impedance will also increase the bandwidth. Use 65-ohm impedance. 3. Do not use any clock signal loops. Keep clock lines straight when possible. 4. For related clock signals that have skew specifications, match the clock trace lengths. For example, PCI expansion slots. 5. Do not route any signals in the ground and VCC planes. 6. Do not route signals close to the edge of the PCB board. 7. Make sure there is a solid ground plane beneath the clock chip. 8. The power plane should face the return ground plane. No signals should be routed between. 9. Route clock signals on the top layer and make sure that there are no vias. Vias change the impedance and introduce more skew and reflections. 10. Do not use any connectors on clock traces. 11. Use wide traces for power and ground. 12. Keep high-speed switching busses and logic away from the clock chip. 13. Place the clock chip in the center of all chips, so that clock signal traces are kept to a minimum. References 1. Johnson, H.W., and Graham, M., "High-Speed Digital Design" PrenticeHall,1993. 2. "Pentium Pro Processor GTL + Guidelines", IntelAP-524,March1996 3. C. Pace "Terminate Bus lines to Avoid Overshoot and Ringing",EDN, pp227-234Sept -1987 4. J.Sutherland "As Edge Speeds Increase, Wires Become Transmission Lines", EDN, pp75-85 Oct - 1999 5. K. Ethirajan “Termination Techniques for High Speed Busses”, EDNpp60-78 Feb1998.
- 7. 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Application Note 22 7 AN22 02/09/00 Figure16.SchematicDrawing REF1 REF0 VSS XTAL_IN XTAL_OUT S1 VDDQ_3 PCICLK_F PCICLK0 VSS PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDQ_3 PCICLK5 VSS S0 SDATA SCLK VDDQ_3 48/24 MHzA 48/24 MHzB VSS VDDQ_3 N/C VDDQ_3 REFCLK_OUT PWR_DWN# VSS CPUCLK0 CPUCLK1 VDDQ_2 SDRAM_IN SDRAM_FB VSS SDRAM0 SDRAM1 VDDQ_3 SDRAM2 SDRAM3 VSS SDRAM4 SDRAM5 VDDQ_3 CPU_STOP# PCI_STOP# VDDQ_3 Decoupling Capacitors Series Terminating Resistors PI6C673 Vcc3 Board Decoupling Cap From Chipset To Chipset
- 8. 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Application Note 22 8 AN22 02/09/00 VSS VDDQ-3 Island for Clock Bypass CAP = 10µF P P P C REFCLK_OUT CPUCLK0 CPUCLK1 SDRAM0 SDRAM1 SDRAM5 SDRAM4 SDRAM3 SDRAM2 C R R R R R R R R CP2 P P C C P C R R VSS VSS VSS VSS VSS VSS 48/24 MHzB 48/24 MHzA PCI_CLK5 PCI_CLK4 PCI_CLK3 PCI_CLK2 PCI_CLKF PCI_CLK0 PCI_CLK1 REF1 REF0 R P P S S S S S S S R R R R R R R C C R VSS VSS VSS VSS VSS VSS VSS VSS VSS XTAL_IN XTAL_OUT R R PC VSS Use Wider Traces for Crystal, Ground, and Power (.034 inch width, .1 inch pitch) V SS = Via to ground plane P = Via to VDDQ-3 Plane R = Termination Resistor 12-50Ω C = Decoupling Capacitor S = Signal Connection P2 = Via to VDDQ - 2 Plane (2.5V Plane) From Chipset To Chipset Figure 17. PI6C673 Layout Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com