Hpc 4 5
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1) Early parallel architectures included the mainframe approach using a crossbar interconnect and the minicomputer approach using a shared bus. (2) Modern architectures have converged on a distributed memory model connected by a general-purpose network. (3) Programming models have also converged but hardware organizations remain flexible to support different approaches like message passing, shared memory, data parallel and systolic.
Hpc 4 5
- 1. HIGH PERFORMANCE COMPUTING LECT_04&5 Convergence of Parallel Architectures-II BATCH: 11BS(IT) PREPARED BY: MUKHTIAR AHMED Asst. Prof. I.T Department
- 2. 2 History P P C C I/O I/O M MM M PP C I/O M MC I/O $ $ “Mainframe” approach • Motivated by multiprogramming • Extends crossbar used for mem bw and I/O • Originally processor cost limited to small – later, cost of crossbar • Bandwidth scales with p • High incremental cost; use multistage instead “Minicomputer” approach • Almost all microprocessor systems have bus • Motivated by multiprogramming, TP • Used heavily for parallel computing • Called symmetric multiprocessor (SMP) • Latency larger than for uniprocessor • Bus is bandwidth bottleneck – caching is key: coherence problem • Low incremental cost
- 3. 3 Example: Intel Pentium Pro Quad • All coherence and multiprocessing glue in processor module • Highly integrated, targeted at high volume • Low latency and bandwidth P-Pro bus (64-bit data, 36-bit address, 66 MHz) CPU Bus interface MIU P-Pro module P-Pro module P-Pro module256-KB L2 $ Interrupt controller PCI bridge PCI bridge Memory controller 1-, 2-, or 4-way interleav ed DRAM PCIbus PCIbus PCI I/O cards
- 4. 4 Example: SUN Enterprise • 16 cards of either type: processors + memory, or I/O • All memory accessed over bus, so symmetric • Higher bandwidth, higher latency bus Gigaplane bus (256 data, 41 address, 83 MHz) SBUS SBUS SBUS 2FiberChannel 100bT,SCSI Bus interf ace CPU/mem cardsP $2 $ P $2 $ Mem ctrl Bus interf ace/switch I/O cards
- 5. 5 Scaling Up • Problem is interconnect: cost (crossbar) or bandwidth (bus) • Dance-hall: bandwidth still scalable, but lower cost than crossbar – latencies to memory uniform, but uniformly large • Distributed memory or non-uniform memory access (NUMA) – Construct shared address space out of simple message transactions across a general-purpose network (e.g. read-request, read-response) • Caching shared (particularly nonlocal) data? M M M M M M NetworkNetwork P $ P $ P $ P $ P $ P $ “Dance hall” Distributed memory
- 6. 6 Example: Cray T3E • Scale up to 1024 processors, 480MB/s links • Memory controller generates comm. request for nonlocal references • No hardware mechanism for coherence (SGI Origin etc. provide this) Switch P $ XY Z External I/O Mem ctrl and NI Mem
- 7. 7 Message Passing Architectures Complete computer as building block, including I/O • Communication via explicit I/O operations Programming model: directly access only private address space (local memory), comm. via explicit messages (send/receive) High-level block diagram similar to distributed-memory SAS • But comm. integrated at IO level, needn’t be into memory system • Like networks of workstations (clusters), but tighter integration • Easier to build than scalable SAS Programming model more removed from basic hardware operations • Library or OS intervention
- 8. 8 Message-Passing Abstraction • Send specifies buffer to be transmitted and receiving process • Recv specifies sending process and application storage to receive into • Memory to memory copy, but need to name processes • Optional tag on send and matching rule on receive • User process names local data and entities in process/tag space too • In simplest form, the send/recv match achieves pairwise synch event – Other variants too • Many overheads: copying, buffer management, protection ProcessP ProcessQ AddressY AddressX SendX, Q, t ReceiveY, P, tMatch Local process address space Local process address space
- 9. 9 Evolution of Message-Passing Machines Early machines: FIFO on each link • Hw close to prog. Model; synchronous ops • Replaced by DMA, enabling non-blocking ops – Buffered by system at destination until recv Diminishing role of topology • Store&forward routing: topology important • Introduction of pipelined routing made it less so • Cost is in node-network interface • Simplifies programming 000001 010011 100 110 101 111
- 10. 10 Example: IBM SP-2 • Made out of essentially complete RS6000 workstations • Network interface integrated in I/O bus (bw limited by I/O bus) Memory bus MicroChannel bus I/O i860 NI DMA DRAM IBM SP-2 node L2 $ Power 2 CPU Memory controller 4-way interleav ed DRAM General interconnection network f ormed f rom 8-port switches NIC
- 11. 11 Example Intel Paragon Memory bus (64-bit, 50 MHz) i860 L1 $ NI DMA i860 L1 $ Driv er Mem ctrl 4-way interleav ed DRAM Intel Paragon node 8 bits, 175 MHz, bidirectional2D grid network with processing node attached to ev ery switch Sandia’ s Intel Paragon XP/S-based Super computer
- 12. 12 Toward Architectural Convergence Evolution and role of software have blurred boundary • Send/recv supported on SAS machines via buffers • Can construct global address space on MP using hashing • Page-based (or finer-grained) shared virtual memory Hardware organization converging too • Tighter NI integration even for MP (low-latency, high-bandwidth) • At lower level, even hardware SAS passes hardware messages Even clusters of workstations/SMPs are parallel systems • Emergence of fast system area networks (SAN) Programming models distinct, but organizations converging • Nodes connected by general network and communication assists • Implementations also converging, at least in high-end machines
- 13. 13 Data Parallel Systems Programming model • Operations performed in parallel on each element of data structure • Logically single thread of control, performs sequential or parallel steps • Conceptually, a processor associated with each data element Architectural model • Array of many simple, cheap processors with little memory each – Processors don’t sequence through instructions • Attached to a control processor that issues instructions • Specialized and general communication, cheap global synchronization PE PE PE PE PE PE PE PE PE Control processor Original motivations •Matches simple differential equation solvers •Centralize high cost of instruction fetch/sequencing
- 14. 14 Application of Data Parallelism • Each PE contains an employee record with his/her salary If salary > 100K then salary = salary *1.05 else salary = salary *1.10 • Logically, the whole operation is a single step • Some processors enabled for arithmetic operation, others disabled Other examples: • Finite differences, linear algebra, ... • Document searching, graphics, image processing, ... Some recent machines: • Thinking Machines CM-1, CM-2 (and CM-5) • Maspar MP-1 and MP-2,
- 15. 15 Evolution and Convergence Rigid control structure (SIMD in Flynn taxonomy) • SISD = uniprocessor, MIMD = multiprocessor Popular when cost savings of centralized sequencer high • 60s when CPU was a cabinet • Replaced by vectors in mid-70s – More flexible w.r.t. memory layout and easier to manage • Revived in mid-80s when 32-bit datapath slices just fit on chip • No longer true with modern microprocessors Other reasons for demise • Simple, regular applications have good locality, can do well anyway • Loss of applicability due to hardwiring data parallelism – MIMD machines as effective for data parallelism and more general Prog. model converges with SPMD (single program multiple data) • Contributes need for fast global synchronization • Structured global address space, implemented with either SAS or MP
- 16. 16 Dataflow Architectures Represent computation as a graph of essential dependences • Logical processor at each node, activated by availability of operands • Message (tokens) carrying tag of next instruction sent to next processor • Tag compared with others in matching store; match fires execution 1 b a + c e d f Dataf low graph f = a d Network Token store Waiting Matching Instruction f etch Execute Token queue Form token Network Network Program store a = (b +1) (b c) d = c e
- 17. 17 Evolution and Convergence Key characteristics • Ability to name operations, synchronization, dynamic scheduling Problems • Operations have locality across them, useful to group together • Handling complex data structures like arrays • Complexity of matching store and memory units • Expose too much parallelism (?) Converged to use conventional processors and memory • Support for large, dynamic set of threads to map to processors • Typically shared address space as well • But separation of progr. model from hardware (like data-parallel) Lasting contributions: • Integration of communication with thread (handler) generation • Tightly integrated communication and fine-grained synchronization • Remained useful concept for software (compilers etc.)
- 18. 18 Systolic Architectures • Replace single processor with array of regular processing elements • Orchestrate data flow for high throughput with less memory access Different from pipelining • Nonlinear array structure, multidirection data flow, each PE may have (small) local instruction and data memory Different from SIMD: each PE may do something different Initial motivation: VLSI enables inexpensive special-purpose chips Represent algorithms directly by chips connected in regular pattern M PE M PE PE PE
- 19. 19 Systolic Arrays (contd.) • Practical realizations (e.g. iWARP) use quite general processors – Enable variety of algorithms on same hardware • But dedicated interconnect channels – Data transfer directly from register to register across channel • Specialized, and same problems as SIMD – General purpose systems work well for same algorithms (locality etc.) y(i) = w1 x(i) + w2 x(i + 1) + w3 x(i + 2) + w4 x(i + 3) x8 y3 y2 y1 x7 x6 x5 x4 x3 w4 x2 x w x1 w3 w2 w1 xin yin xout yout xout = x yout = yin + w xin x = xin Example: Systolic array for 1-D convolution
- 20. 20 Convergence: Generic Parallel Architecture A generic modern multiprocessor Node: processor(s), memory system, plus communication assist • Network interface and communication controller • Scalable network • Convergence allows lots of innovation, now within framework • Integration of assist with node, what operations, how efficiently... Mem Network P $ Communication assist (CA)