SlideShare a Scribd company logo
4
Most read
5
Most read
7
Most read
IEEe 754 number SYSTEM
Paper Name : COMPUTER ARCHITECHTURE
Paper code : EC502
Student Name : Debjyoti Musib
Univ. Roll : 13000320104
Department : ECE
MAKAUT CA1 EC502 1
27-07-2022
27-07-2022 MAKAUT CA1 EC502 2
CONTENTS :
 INTRODUCTION
 COMPONENTS
 EXPLANATIONS
 EXAMPLES
27-07-2022 MAKAUT CA1 EC502 3
 What is IEEE 754 number system?
The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical
standard for floating-point computation which was established in 1985 by
the Institute of Electrical and Electronics Engineers (IEEE).
IEEE in 1985 and augmented in 2008 provided a standard to
represent floating-point numbers and process them.
 IEEE Standard 754 floating point is the most common representation today for
real numbers on computers, including Intel-based PC’s, Macs, and most Unix
platforms.
 There are several ways to represent floating point number but IEEE 754 is the
most efficient in most cases.
27-07-2022 MAKAUT CA1 EC502 4
 IEEE 754 has 3 basic components:
 The Sign of Mantissa –
This is as simple as the name. 0 represents a positive number while 1 represents a
negative number.
 The Biased exponent –
The exponent field needs to represent both positive and negative exponents. A bias is
added to the actual exponent in order to get the stored exponent.
 The Normalised Mantissa –
The mantissa is part of a number in scientific notation or a floating-point
number, consisting of its significant digits. Here we have only 2 digits, i.e. O & 1. So a
normalised mantissa is one with only one 1 to the left of the decimal.
27-07-2022 MAKAUT CA1 EC502 5
 IEEE 754 numbers are divided into two based on the above three components:
 Single precision. (32 bit)
 Double precision. (64 bit)
 Single-Precision -
1. Sign- In single precision, 1 bit is assigned for the sign (positive or negative).
2. Exponent- 8 bit is assigned for the range named exponent.
3. Mantissa- 23 bit is assigned for the precision ( it's for the fractional part)
27-07-2022 MAKAUT CA1 EC502 6
 Double-precision-
1. Sign- In single precision, 1 bit is assigned for the sign(positive or negative).
2. Exponent- 8 bit is assigned for the range named as an exponent.
3. Mantissa- 23 bit is assigned for the precision ( it's for the fractional part).
 Excess = 2n-1- 1
In single precision In double precision
N= E = 8 N= E = 11
So, Excess = 28-1- 1 = 127 So, Excess = 211-1- 1 = 1023
27-07-2022 MAKAUT CA1 EC502 7
 Example:
 85.125
85 = 1010101
0.125 = 001
85.125 = 1010101.001
=1.010101001 x 2^6
sign = 0
1. Single precision:
biased exponent 127+6=133
133 = 10000101
Normalised mantisa = 010101001
we will add 0's to complete the 23 bits
The IEEE 754 Single precision is:
= 0 10000101 01010100100000000000000
This can be written in hexadecimal form 42AA4000
27-07-2022 MAKAUT CA1 EC502 8
2. Double precision:
biased exponent 1023+6=1029
1029 = 10000000101
Normalised mantisa = 010101001
we will add 0's to complete the 52 bits
The IEEE 754 Double precision is:
= 0 10000000101 0101010010000000000000000000000000000000000000000000
This can be written in hexadecimal form 4055480000000000
27-07-2022 MAKAUT CA1 EC502 9

More Related Content

PPT
encoder and decoder in digital electronics
PDF
Floating point presentation
PPTX
1. Arithmetic Operations - Addition and subtraction of signed numbers.pptx
PPTX
Design of control unit.pptx
PPTX
Parallel processing
PPT
Booth Multiplier
PPTX
Lecture Notes: EEEC6440315 Communication Systems - Inter Symbol Interference...
PPT
8086 microprocessor assembler directives.ppt
encoder and decoder in digital electronics
Floating point presentation
1. Arithmetic Operations - Addition and subtraction of signed numbers.pptx
Design of control unit.pptx
Parallel processing
Booth Multiplier
Lecture Notes: EEEC6440315 Communication Systems - Inter Symbol Interference...
8086 microprocessor assembler directives.ppt

What's hot (20)

PPT
adder and subtractor
PDF
Control Unit Design
PPT
EPROM, PROM & ROM
PPTX
Quick tutorial on IEEE 754 FLOATING POINT representation
PDF
3 jump, loop and call instructions
PDF
8155 PPI
PDF
Intel x86 Architecture
PPTX
8086 Micro-processor and MDA 8086 Trainer Kit
PPTX
8237 dma controller
PPTX
Architecture of the Intel 8051 Microcontroller
PPTX
Microprocessor architecture-I
PPTX
80486 and pentium
PPTX
Instruction Set Architecture: MIPS
PDF
8051,chapter1,architecture and peripherals
PDF
Error detection & correction codes
PDF
Quine mccluskey method
PPTX
Register transfer and microoperations part 2
PDF
BCD to Decimal - Digital Electronics
PPTX
INTEL 80386 MICROPROCESSOR
PPTX
Parity check(Error Detecting Codes)
adder and subtractor
Control Unit Design
EPROM, PROM & ROM
Quick tutorial on IEEE 754 FLOATING POINT representation
3 jump, loop and call instructions
8155 PPI
Intel x86 Architecture
8086 Micro-processor and MDA 8086 Trainer Kit
8237 dma controller
Architecture of the Intel 8051 Microcontroller
Microprocessor architecture-I
80486 and pentium
Instruction Set Architecture: MIPS
8051,chapter1,architecture and peripherals
Error detection & correction codes
Quine mccluskey method
Register transfer and microoperations part 2
BCD to Decimal - Digital Electronics
INTEL 80386 MICROPROCESSOR
Parity check(Error Detecting Codes)
Ad

Similar to IEEE 754 NUMBER SYSTEM (20)

PPTX
IEEE Floating Point Number with Single and Double Precision(Analog and Digita...
PDF
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
PDF
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
PPTX
Final modified ppts
DOCX
Mini Project 1 - 2-to-4 Decoder with Enable Input E and 4-to-2 Line Priority...
PDF
At36276280
PPTX
Floating point ALU using VHDL implemented on FPGA
PPTX
Bidirect visitor counter
PDF
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
PPTX
Ch1+Intr for the distributed system and clock
PDF
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...
PDF
IRJET- A Review on Single Precision Floating Point Arithmetic Unit of 32 Bit ...
PDF
Design, Construction and Operation of a 4-Bit Counting Circuit
PDF
K010137378
PDF
Design of 32-bit Floating Point Unit for Advanced Processors
DOCX
Ecet 105 Education Specialist -snaptutorial.com
PDF
PDF
IRJET- Analysis of Electroencephalogram (EEG) Signals
PDF
Jz2517611766
PDF
Jz2517611766
IEEE Floating Point Number with Single and Double Precision(Analog and Digita...
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
Final modified ppts
Mini Project 1 - 2-to-4 Decoder with Enable Input E and 4-to-2 Line Priority...
At36276280
Floating point ALU using VHDL implemented on FPGA
Bidirect visitor counter
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
Ch1+Intr for the distributed system and clock
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...
IRJET- A Review on Single Precision Floating Point Arithmetic Unit of 32 Bit ...
Design, Construction and Operation of a 4-Bit Counting Circuit
K010137378
Design of 32-bit Floating Point Unit for Advanced Processors
Ecet 105 Education Specialist -snaptutorial.com
IRJET- Analysis of Electroencephalogram (EEG) Signals
Jz2517611766
Jz2517611766
Ad

Recently uploaded (20)

PDF
The Rise and Fall of 3GPP – Time for a Sabbatical?
PPTX
Understanding_Digital_Forensics_Presentation.pptx
PDF
Building Integrated photovoltaic BIPV_UPV.pdf
PDF
Reach Out and Touch Someone: Haptics and Empathic Computing
PDF
Machine learning based COVID-19 study performance prediction
PDF
Encapsulation theory and applications.pdf
PDF
Profit Center Accounting in SAP S/4HANA, S4F28 Col11
PDF
Agricultural_Statistics_at_a_Glance_2022_0.pdf
PPTX
sap open course for s4hana steps from ECC to s4
PPTX
Cloud computing and distributed systems.
PDF
Spectral efficient network and resource selection model in 5G networks
PDF
Optimiser vos workloads AI/ML sur Amazon EC2 et AWS Graviton
PPTX
Spectroscopy.pptx food analysis technology
PDF
Build a system with the filesystem maintained by OSTree @ COSCUP 2025
PDF
Approach and Philosophy of On baking technology
PDF
Advanced methodologies resolving dimensionality complications for autism neur...
PDF
7 ChatGPT Prompts to Help You Define Your Ideal Customer Profile.pdf
PDF
Mobile App Security Testing_ A Comprehensive Guide.pdf
PPTX
Detection-First SIEM: Rule Types, Dashboards, and Threat-Informed Strategy
PDF
NewMind AI Weekly Chronicles - August'25 Week I
The Rise and Fall of 3GPP – Time for a Sabbatical?
Understanding_Digital_Forensics_Presentation.pptx
Building Integrated photovoltaic BIPV_UPV.pdf
Reach Out and Touch Someone: Haptics and Empathic Computing
Machine learning based COVID-19 study performance prediction
Encapsulation theory and applications.pdf
Profit Center Accounting in SAP S/4HANA, S4F28 Col11
Agricultural_Statistics_at_a_Glance_2022_0.pdf
sap open course for s4hana steps from ECC to s4
Cloud computing and distributed systems.
Spectral efficient network and resource selection model in 5G networks
Optimiser vos workloads AI/ML sur Amazon EC2 et AWS Graviton
Spectroscopy.pptx food analysis technology
Build a system with the filesystem maintained by OSTree @ COSCUP 2025
Approach and Philosophy of On baking technology
Advanced methodologies resolving dimensionality complications for autism neur...
7 ChatGPT Prompts to Help You Define Your Ideal Customer Profile.pdf
Mobile App Security Testing_ A Comprehensive Guide.pdf
Detection-First SIEM: Rule Types, Dashboards, and Threat-Informed Strategy
NewMind AI Weekly Chronicles - August'25 Week I

IEEE 754 NUMBER SYSTEM

  • 1. IEEe 754 number SYSTEM Paper Name : COMPUTER ARCHITECHTURE Paper code : EC502 Student Name : Debjyoti Musib Univ. Roll : 13000320104 Department : ECE MAKAUT CA1 EC502 1 27-07-2022
  • 2. 27-07-2022 MAKAUT CA1 EC502 2 CONTENTS :  INTRODUCTION  COMPONENTS  EXPLANATIONS  EXAMPLES
  • 3. 27-07-2022 MAKAUT CA1 EC502 3  What is IEEE 754 number system? The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point computation which was established in 1985 by the Institute of Electrical and Electronics Engineers (IEEE). IEEE in 1985 and augmented in 2008 provided a standard to represent floating-point numbers and process them.  IEEE Standard 754 floating point is the most common representation today for real numbers on computers, including Intel-based PC’s, Macs, and most Unix platforms.  There are several ways to represent floating point number but IEEE 754 is the most efficient in most cases.
  • 4. 27-07-2022 MAKAUT CA1 EC502 4  IEEE 754 has 3 basic components:  The Sign of Mantissa – This is as simple as the name. 0 represents a positive number while 1 represents a negative number.  The Biased exponent – The exponent field needs to represent both positive and negative exponents. A bias is added to the actual exponent in order to get the stored exponent.  The Normalised Mantissa – The mantissa is part of a number in scientific notation or a floating-point number, consisting of its significant digits. Here we have only 2 digits, i.e. O & 1. So a normalised mantissa is one with only one 1 to the left of the decimal.
  • 5. 27-07-2022 MAKAUT CA1 EC502 5  IEEE 754 numbers are divided into two based on the above three components:  Single precision. (32 bit)  Double precision. (64 bit)  Single-Precision - 1. Sign- In single precision, 1 bit is assigned for the sign (positive or negative). 2. Exponent- 8 bit is assigned for the range named exponent. 3. Mantissa- 23 bit is assigned for the precision ( it's for the fractional part)
  • 6. 27-07-2022 MAKAUT CA1 EC502 6  Double-precision- 1. Sign- In single precision, 1 bit is assigned for the sign(positive or negative). 2. Exponent- 8 bit is assigned for the range named as an exponent. 3. Mantissa- 23 bit is assigned for the precision ( it's for the fractional part).  Excess = 2n-1- 1 In single precision In double precision N= E = 8 N= E = 11 So, Excess = 28-1- 1 = 127 So, Excess = 211-1- 1 = 1023
  • 7. 27-07-2022 MAKAUT CA1 EC502 7  Example:  85.125 85 = 1010101 0.125 = 001 85.125 = 1010101.001 =1.010101001 x 2^6 sign = 0 1. Single precision: biased exponent 127+6=133 133 = 10000101 Normalised mantisa = 010101001 we will add 0's to complete the 23 bits The IEEE 754 Single precision is: = 0 10000101 01010100100000000000000 This can be written in hexadecimal form 42AA4000
  • 8. 27-07-2022 MAKAUT CA1 EC502 8 2. Double precision: biased exponent 1023+6=1029 1029 = 10000000101 Normalised mantisa = 010101001 we will add 0's to complete the 52 bits The IEEE 754 Double precision is: = 0 10000000101 0101010010000000000000000000000000000000000000000000 This can be written in hexadecimal form 4055480000000000