implementation of BIST

11621A0401 IMPLEMENTATION OF BUILT IN SELF TEST FOR TESTING
11621A0407 COMBINATIONAL CIRCUITS USING FPGA
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B.TECH ECE (2014-2015) AURORA’S ENGG COLLEGE,BHONGIR
1
CHAPTER - 1
INTRODUCTION
BIST (Built-In Self-Test) for random logic is becoming an eye-catching
substitute in IC testing, although logic BIST is a recent subject which is under research
over more than 3 decades. This paper provides the use of a deterministic logic BIST
structure up on state-of-the-art industrial circuits. Nevertheless, new innovations
throughout deep - submicron IC process engineering as well as core-based IC design and
design engineering will surely lead to more popular using logical BIST due to the fact
outer assessment actually becoming a lot more difficult as well as high- priced.
Logic built-in self-test (BIST) depend on the fundamental design for test methodology.
For any testing methodology, the following factor should be considered- high and
easily verifiable fault coverage, minimum test pattern generation, minimum performance
degradation, at-speed testing, short testing time, and reasonable hardware overhead [1].
Logic Built-In Self Test (BIST) provides a feasible solution to the above demands. First,
BIST significantly reduces off-chip communication to overcome the bottleneck caused by
the limited input/output access. Further, it eliminates much of the test pattern generation
and simulation process [1]. Testing time can be shortened by testing multiple units
simultaneously through test scheduling. Hardware overhead can be minimized by careful
design and through the sharing of test hardware. In the modern System - on –a- Chip
(SOC) design, many cores are integrated into a single chip. Some of them are embedded,
and cannot be accessed directly from the outside of the chip. Such SoC designs make the
test of these embedded cores a great challenge [2]. BIST is one of the most popular test
solutions to test the embedded cores. Since more And more transistors are integrated on
a single IC , the amount of test vectors to test such large ICs is increasing. This
requires large memories in external test --equipment. In addition, a significant increase
is predicted.
Originally, the predominant compelling purpose for the adopting of BIST Was
the need to execute in-field examining. Just lately , there have been developing desires

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for BIST as it may lower the price of manufacturing test together with strengthen
the standard of the particular test by providing at-speed testing ability. In BIST ,
pseudorandom styles tend to be generated on chip; the actual replies tend to be
compacted about chip, as well as the handle impulses tend to be pushed simply by an
on – chip controller. The amount of examination files exchange with the tester is
consequently considerably lowered . I addition, the scan cells are configured into a
large number of relatively short scan chains , thus reducing the time required to apply a
single test pattern. The low memory an performance requirements on the tester allow the
usage of very low cost testers for manufacturing test of designs with logic BIST.
1.1 Faults in Integrated Circuits
Failures in electronic components are generally the effects of chemical and
physical processes. Failures caused by chemical effects lead to continuous production of
defective components over whole production lines. Failures caused by physical effects,
however, result in defects in individual components, involving component shorts and
breaks, and packaging. Consequently, faults in integrated circuits are typically modeled
based on physical failures, and generally classified into two categories, i.e. parametric and
catastrophic faults. The catastrophic faults are caused by random defects, for
example dust particles, resulting in short and open circuits or large-scale deviation of
design parameters.2 The parametric faults are representing the parameter variations of
the nominal value, which exceeds the attributed tolerance band. Such parametric faults
are caused by fluctuation in the manufacturing process. Comparing catastrophic and
parametric faults, most electrical failures are catastrophic faults at a percentage of
83.5% (Rajsuman, 2000).
1.1.1 Catastrophic Faults
Catastrophic faults are commonly referred to as potential shorts and opens. In
the case of shorts, two possible short circuits are bridging defects and Gate-Oxide
Short GOS). The bridging defects appear when two or more metal lines are
electrically Connected in an integrated circuit. Fig. 1.1 shows examples of bridging

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and GOS defects in CMOS technology presented by Ohletz (1996). As shown in Fig.1.1
(a), six examples of short circuits include the shorting of metal lines caused by
unexposed photo resist, a solid – state particle on the metal mask , a scratch in the
photo resist, metallization defects , and inter-layer shorts. Bridging resistance is
important in defect detection since the majority of bridging defects show low resistance
while many high resistance-bridging defects do not result in failure. Therefore, a
resistance connecting the two bridges nodes can simply be modeled in simulation process.
Fig. 1.1 (b) shows GOS defects in CMOS technology. These GOS defects are short
circuits between the Gate electrode and the active zone through the SiO2 oxide of the
device. In the majority Of cases, gate-oxide defects cause reliability degradation such as
changes in transistor threshold voltage and the increase in switching delay. Fig. 1.2
shows examples of open circuits presented by Ohletz (1996), involving a foreign particle
causing a line open and a line thinning, and a contaminating particle causing 7-line opens.
These open circuits are unconnected or floating inputs that usually high impedance or
floating.
1.1.2 Parametric Faults
Parametric faults are generally referred to as the variation in components
and interconnect dimensions. The physical component dimension is relatively susceptible
to process variation, such as a Gate-length (L) and a threshold voltage (VT) in CMOS
transistors. The critical variations in interconnect dimensions of line-spacing and metal
thickness result in different metal properties of the interconnect wires, such as their
parasitic resistance, capacitance, and inductance values. As parametric faults typically
depend on parameter tolerance band acceptability, modeling of parametric faults is
relatively complicated at the physical design level. In order to overcome such impasses of
parametric fault modeling, analysis method realizes an acceptable circuit instances based
3 Metal short Line scratch Small solid particle Inter layer short Metal Gate-Oxide short.

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Line scratch inter layer scratch
(a) Examples of bridging defects in CMOS Technology
(b) Examples of Gate-Oxide Shorts
Metal Gate-Oxide short Gate-Oxide short
Figure: 1.1 Examples of bridging defects and Gate-Oxide Shorts.

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Foreign Particle Contaminating Particles
Figure: 1.2 Examples of opens caused by foreign and contaminating particles.
on tolerance specifications (Chang and Lee, 2002). In other words, the variation of
parameters is initially injected randomly from ±5% to ±15% deviations from the
nominal values, and the distribution of output variable values is subsequently analyzed for
region of acceptability. The distribution of output variable is generally a normal
distribution. In order to distinguish between acceptable and unacceptable instances, the
region of acceptability is on the order of ±5% for the 99% confidential interval (Spink and
et al., 2004). Large variations in circuit parameters such as ±10% variations

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in resistor and capacitor values have been considered as unacceptable, and therefore the
Circuit-Under-Test (CUT) is classified as defective component instantly. However, some
large variations in circuit parameters may not result in specification violation while some
small variation may not cause tremendous specification violation. Fig. 1.3 shows the
probability of faulty and fault-free distributions. In order to ensure that all acceptable
devices are distinguished with high yield coverage, the decision for acceptable components
is based on specification violation, i.e. within the acceptability region of ±3σ, rather than
the variation percentage of injected parametric faults.
1.2 Perspectives Reviews on On-Chip Testing Techniques
1.2.1 Reasons for On-Chip Testing Compared with Off-chip Testing
Two major reasons for on-chip testing of catastrophic and parametric faults are
(1)the need of fully analog-digital test instruments and (2) high cost of off-chip testing
through ATE. First, the advancement of deep sub-micron technology drives test
equipments towards a single platform solution that can test both digital and analog
structures on a single chip (Stound, 2006). Whereas test equipments for digital circuits are
similar to purely digital chips, preferable analog mixed-signal test equipment is expected to
be feasible. Consequently, test equipments are transversely changing from digital-only to
the full integration of high performance instruments. Second, the ATE cost is the one of
the most expensive cost in overall manufacturing process cost even though the

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combinations of equipment cost and reduction in equipment capability requirements have
been suggested. Expensive analog test instruments and long testing time remain a
difficulty. Moreover, test cost does not directly scale with transistor count, die size, device
pin count and process technology.5
1.2.2 Comparisons between Digital and Analog On-Chip Testing
Several early on-chip testing techniques have been applied successfully in digital
circuits in which each level of abstractions is verified against the immediate preceding
levels (Stound, 2006). Digital testing on-chip is supported by rigorous mathematical
expression such as Boolean expressions, high-level programming language constructs, and
single stuck-fault models. Therefore, test pattern algorithms and output response analysis
in digital domains have been developed broadly with acceptable fault coverage. As
opposed to testing in digital integrated circuits, testing in analog mixed-signal circuits is
relatively complicated owing to not only instantaneous continuous-time analog response of
signal values, but also non-linear characteristics and broad variations in circuit parameters
(Milor, 1998). Test accuracy of analog mixed-signal systems also depends upon the test
equipment resolution as well as the accuracy of input testing stimuli. Besides, both analog
and digital circuits are recently developed on the same substrate and disturbances, i.e.
noises from digital sections may produce influences on the function of the analog parts
.These characteristics lead to difficulties in testing analog circuits, including vulnerability
to performance degradation and indecipherable standard fault models (Garcia et al., 2001).
1.2.3 Comparisons between DFT and BIST Techniques
Two commonly known on-chip testing techniques are Design-for-Test (DFT) and
Built-In Self Test. The DFT is a technique to reduce difficulty of testing by adding or
modifying some hardware on chip. The scan DFT methodology (Wei et al, 1997), in which
the sequential storage elements allow normal operation and test modes, has been a standard
DFT practice followed by industry. In normal mode, the storage elements take their
stimulus from a combinational logic and the response feeds into a combinational logic. In
test mode, the storage elements are reconfigured as one or more shift registers, and each

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such configuration is known as a scan chain. The stimulus vector can be shifted serially
into this scan chain. The chip is consequently allowed to function in normal mode and the
responses for a test vector are captured in the storage elements. The response can be shifted
out and compared with reference responses in order to test the chip for functional
correctness. The use of DFT scan design has two major penalties, i.e. an area overhead due
to the additional scan flip-flops and the performance overhead caused by on-path
multiplexors in the scan flip-flops. Besides, this scan also has the disadvantage of greater
power dissipation as there is generally more switching operation during scan mode than
normal operation. Thus, a slow clock is commonly used for scan operation in order to
reduce average power dissipation.
Figure:1.4 A generalized block diagram of BIST architecture.
The BIST refers to as techniques and circuit configurations that enable a chip to test
internally and automatically (Cluskey, 1985; Yamani and McCluskey , 2003). In this BIST
technique, test patterns are generated and test responses are analyzed completely on chip.
Pattern generator logic reduces test data volume through shifting process of the easily
detectable faults. The BIST technique offers various advantages over DFT testing
techniques and ATE. First, test circuitry is incorporated on chip and no external tester is
required. Second, test operations can be performed at normal clock rate. Third, the test
operation can be performed after the chip has been incorporated in the system. However,
two difficulties encountered in BIST techniques are area overhead and performance

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degradation. Incorporation of the self-testing capability requires addition of hardware on-
chip, which may increase the silicon area and manufacturing costs. Applying BIST
techniques for analog mixed-signal circuits can be primarily considered in two approaches,
i.e. functional and structural tests. Functional BIST evaluates circuit functionality and
compares to a set of functional specifications. This functional BIST requires analog
stimulus and measurement of analog outputs. Therefore, the quality of applied input and
the precision of measured outputs are relatively important factors, highly depending on the
test setup and equipment. On the other hand, structural BIST is based on physical
information of the manufactured device. Therefore, the applied test patterns can be
optimally chosen and fault coverage can be evaluated based on fault models.
1.3 Existing BIST Techniques for Analog Mixed-Signal LSI
Fig.1.4 shows the generalized block diagram of BIST architecture. This BIST
architecture includes two essential functions, i.e. test stimulus generator and output
response analysis, and two additional functions that are necessary to facilitate execution of
7.
Figure: 1.5 Classification diagrams of BIST techniques.

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Self-testing feature, i.e. test controller and input isolation. Based on this generalized block
diagram, several BIST techniques have recently been proposed to address the need for
analog mixed-signal testing. Fig.1.5 therefore shows the classification diagram of BIST
techniques. The BIST techniques can be classified into three main categories based on the
use of input vectors, test operation modes, and test response analysis domain. Existing
BIST techniques based on Figs.1.4 and 1.5 are reviewed in this section.
1.3.1 BIST Techniques Based on Input Vectors
As depicted in Fig. 1.5 (a), the BIST techniques based on input vectors are
considered regarding the input stimulus generator in Fig.1.4 (a), and can be classified as
vector-based and vector less techniques. The vector-based BIST techniques are referred to
as the testing techniques that require the output signals for fault information processing by
means of applying test input stimuli such as DC input stimulus, sinusoidal input stimulus,
and other non-sinusoidal signal. For DC input stimuli, the measurement of DC input signal
through the use of a comparator (Venuto, 1995) yields low cost and low area overhead. A
multiple DC measurement (Sasho, 1998) was also suggested in order to increase the fault
coverage. Although these DC testing schemes are relatively simple and sufficient for some
cases in the pre-screening process, the percentage of fault coverage is not high since some
of hard-to-detect faults do not produce fault signatures through DC characteristics. The
sinusoidal signals have also been used as an input vector (Current and Chu, 2001; Marcia,
2005), in which AC characteristics can be verified for the circuit functionality. The use of
sinusoidal input vector offers a high fault coverage and multiple-frequency test can be
achieved for a functional analysis in high-precision testing. However, the implementation 8
of high-precision sinusoidal signal generation on-chip is relative complex, requiring a large
chip area. In addition, long test time for AC analysis is need in order to correctly
characterize the circuit. Non-sinusoidal input stimuli such as pulse stimulus (Singh at
al.,2004) and pseudo-random input stimulus (Marzocca and Corsi, 2002) have also been
presented for some analog LTI circuits in LSI systems. On the other hand, the vector less
BIST techniques are referred to as the testing that reconfigures CUT in order to generate
output signals automatically with no input stimuli applied. Oscillation-Based Test (OBT)
has proposed for testing different classes of analog and mixed-signal circuits (Arabi and

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Kaminska, 1996; Zarnik, 2000; Harzon and Sun, 2006). During test mode, the circuit is
transformed into an oscillator and the frequency of oscillation is measured. Fault detection
is based on the comparison of the measured oscillation frequency of the CUT with a
reference value obtained from a fault-free circuit, operating under the same test conditions.
This OBT test method is suitable for switching circuits such as the switched-capacitor
technique that can easily be transformed through switching mechanisms. Another vector
less BIST techniques is the current testing approach which employs the current sensors to
detect the magnitude of the DC quiescent current (IDDQ) through a resistor, connecting
between the CUT and the supply voltage (Rajsuman, 2000). The detected IDDQ will
subsequently be compared with reference currents. Although this current testing approach
has successfully been applied to digital circuits and can potentially enhance fault coverage,
IDDQ testing suffers from power supply variation and ground shift.
1.3.2 BIST Techniques Based on Test Operation Modes
As depicted in Fig.1.5 (b), the BIST techniques based on test operation modes are
considered regarding the input isolation circuitry in Fig.1.4 (b), and can be classified as
off-line and on-line test methods. In off-line BIST test methods, the CUT suspends normal
operations, and enters a test mode when the appropriate test method is applied. The off-line
test operation can generally be executed either through ATE or through the use of BIST
circuitry. This off-line test has been realized widely in most analog mixed-signal testing.
For instance, all of those BIST techniques summarized in Section 1.3.1 obey off-line test
methods. In on-line BIST test methods, the outputs from CUT are tested during normal
operation. This on-line test operation can be achieved by coding scheme that has been
embedded in the circuit design. For linear analog filters, continuous checksums have been
proposed by (Chatterjee, 1993) through a cascade of analog integrators, which generate a
non-zero signal in the case of an error in the transfer function of the circuit. An analog
checker employs the on-line test method, which verifies an operational amplifier by means
9 of normal input and output signals (Velasco, 1998). An on-line BIST test method for
analog bi quad filter based on system identification (Cota and et al., 1999) was studied by

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comparing the observed and expected outputs concurrently through adaptive filter in
digital domain. Nonetheless, most BIST techniques are not suitable for on-line test since
the circuit has its topology modified during the test or its input signal is being controlled by
test mechanism. Therefore, the on-line test method requires the development of test
strategies that continuously evaluate the operation of the circuit during normal operation.
This problem of on-line monitoring becomes more important due to the use of sub-micron
technologies, which are more sensitive to noise and radiation effects.
1.3.3 BIST Techniques Based on Domains of Fault Analysis
As depicted in Fig.1.5 (c), the BIST techniques based on domains of fault analysis
are considered regarding the output response analyzer in Fig.1.4 (c), and can be classified
as either in digital or analog domains. In digital domain, the output characterization
process initially converts analog fault signatures into digital signals using a sigma-delta
A/D converter (Dufaza and His, 1996) or a voltage comparator (Czaja, 2006). Such digital
signals will subsequently be employed for fault detection by means of a digital comparator
(Roh and Abraham, 2000) or a digital counter (Cassol et al., 2003), incorporating stored
fault-free bit streams. Despite the fact that the characterization in digital domain offers
expedience in comparison and storage of digital fault signatures, the implementation of
A/D converters and digital counters is relatively complicated, resulting in hardware
overhead and ultimately necessitating fault testing. On the other hand, the output
characterization process in analog domain generally captures fault signatures by means of
sampling process, and detects faults through voltage comparison in allowable tolerance
margins (Yu et al., 2004; Stround, 2006). Characterizing output response in analog domain
has been realized extensively in most cost-effective BIST systems, as both catastrophic and
parametric faults can be detected instantaneously with low area overhead.

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1.4 Dissertation Developments
1.4.1 Motivations
With references to previously developed BIST techniques described in Sections 1.2
and 1.3, there are three major motivations that have led to the research and development of
this dissertation. Firstly, there is a constant demand for new BIST techniques, especially
for recent advanced analog mixed-signal LTI systems with low-cost, 10 low testing time,
and low performance degradation. This demand for new BIST techniques has continuously
been attractive for research activities since BIST is newly introduced to real chip
manufacturing industry, and only a few number of BIST techniques have been
implemented. Unlike scan DFT that has been integrated in digital circuits, not many BIST
techniques have been integrated in the manufacturing industry yet. Secondly, there is the
need for simple and compact BIST techniques for particular analog mixed-signal systems.
Although a number of existing BIST techniques have demonstrated high fault coverage,
the extra BIST circuitry is even more complicated than the exiting CUT itself, i.e. difficult
operations and the requirement for extra external hardware. Those exiting complex BIST
system may not suitable for on-chip integration and therefore simple BIST circuits and
operations are still preferable, especially for the case of compact analog mixed-signal
CUTs such as small amplifiers or filters. Lastly, there is a lack of studies in BIST circuits
with calibration for some sensitive and complicated analog mixed-signal circuits such as
oscillators and phase-locked loops. Since extra BIST circuits may introduce some penalties
to the CUTs, applying BIST techniques to these circuit types remains a difficulty due to
awareness of performance degradation. In addition to the three motivations, the
improvement of previously proposed BIST techniques is also important in order to extend
better BIST performances and functionalities.
1.4.2 Research Objectives
The objective of this dissertation is to develop new BIST techniques and
implementations for catastrophic fault detection and parametric fault calibration. The BIST
techniques are expected to be versatile for each specific type of analog and mixed-signal
circuits, and capable of yielding high fault coverage. In addition, this dissertation also aims

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to design and implement corresponding BIST systems in CMOS technology, which yield
low area overhead, low power consumption, and low performance degradation.
1.4.3 A Strategy for BIST Architecture
Generally, BIST strategy for analog mixed-signal can be considered in two
architectures. Fig. 1.6 shows the block diagram of classical and recent BIST test strategies.
As shown in Fig.1.6 (a), the classical test strategy exploits a common BIST for all analog
sections, which can be considered as functional testing. The input signal stimuli are applied
for all analog section and the expected single output is solely employed for fault signature
analysis. The BIST circuit uses its own control system and those digital sections are
scanned independently from analog sections. Although this classical strategy can simply be
implemented, the fault coverage and testability is relatively low since different analog 11.
Figure:1.6 Architectures of classical and recent BIST test strategies.
blocks exhibit different characteristics and functionalities. In addition, accessibility for
fault localization cannot be achieved since test operation has to be done throughout analog
sections. This dissertation therefore realizes a recent BIST test strategy as shown in Fig.1.6
(b) in which each analog mixed-signal functional block is tested independently through

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different test techniques. These independent tests yield not only higher fault coverage as
each specific circuit is tested based on its functions, but also offer accessibility capability
to each individual circuit. As new mixed-signal system has been advanced, test control
operation can be achieved from the digital section. In addition, the compliance between
analog and digital boundary scan modules has been researched intensely and therefore
corporation test between digital and analog sections is possible.
1.4.4 Scopes of Research and Contributions
In order to discover new BIST techniques based on the motivations and objectives
in the previous section, the scope of developed BIST techniques in this dissertation
emphasizes on common CUT types encountered in LSI systems. Such CUTs are ranged
from a simple analog building block, which comprises only CMOS transistors, to more
complicated mixed-signal circuits composed by various analog and digital building blocks.
For a better understanding in overall figure, Fig. 1.7 summarizes scopes and contributions
of this dissertation through a flow diagram. This diagram describes two clusters of BIST
circuit and system designs, ranging from low to high circuit complexity and conducting
through five research phases. As shown in Fig.1.7 (a), the early three research phases in
cluster 1 focus on BIST techniques for small and medium analog integrated circuits.
Reasons for investigating only BIST without calibration are due to the need for BIST for
analog circuit with performance degradation awareness and also the reasonable cost for
12extra chip area, especially in small circuit size. Details of the three research phases are
described as follows. Phase 1 particularly investigates a compact CMOS-only analog
circuit as a simple building block in most LSI systems. A two-stage differential amplifier is
chosen as a CUT and the contribution to a new BIST technique is a two-step DC and AC
testing mechanism. Phase 2 focuses on a medium size Linear-Time-Invariant (LTI) analog
circuit composed by CMOS transistors, resistors and capacitors. The Sallen-Key 2nd-order
low-pass filter, which is commonly used for test demonstrations, is selected as a CUT, and
the contribution is new pulse stimulation and response capturing. Phase 3 alternatively
considers both a complicated analog circuit and a system implementation compliant to
analog and digital boundary scan. The Gm-C low-pass filter is chosen as a CUT. The 13
contributions include a new fault signature characterization technique and the extension of

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IEEE1149.4 standard analog boundary scans. As shown in Fig.1.7 (b), the latter two
research phases in cluster 2 focuses on BIST and calibration techniques for frequency-
based complicated analog mixed-signal circuits. Both test and calibration circuits are
suggested to this cluster due to the possibility of frequency calibration. Since these circuit
types are relatively complicated, comprising vast number of transistors, and calibrations
foster a cost reduction in the case where parametric faults exist. Details of two research
phases are described as follows. Phase 4 considers a self-oscillating circuit, and the
voltage-controlled oscillator is selected as a CUT. The contribution is a new BIST
technique based on a current and voltage sensor in power supply regulation system. Phase
5 particularly studies the most complex analog mixed-signal circuit, which is a Phase-
Locked Loop, comprising both analog and digital mixed-signal circuits. The contribution is
a new voltage control sensing and PLL with frequency calibration.

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Figure:1.7 block diagram of dissertation
1.5 Thesis Organizations
This thesis is organized into seven chapters. The following chapter 2 presents the
first proposed BIST technique based on two-step AC and DC testing mechanisms, which
detect faults by monitoring and analyzing the fault signatures through amplitude and offset
of sinusoidal voltage signals. This technique simplifies the design of fault-sensing circuits,
and provides a single test outputs in digital form, which is applicable in test systems.

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Details of BIST circuit design and implementation through the use of 0.18-μm CMOS
technology are included. Demonstrations of a two-stage CMOS differential amplifier show
the percentage of fault coverage and area overhead of 95.45% and 15%, respectively.
Chapter 3 presents the BIST technique that employs a new simultaneous pulse generator
and a single effective voltage on a transient pulse response for fault detection.
Demonstrations of BIST system for Sallen-Key low-pass filter with a cut-off frequency of
500kHz, containing the total number of 67 faults, show high percentage of fault coverage
at 95.5%. Experimental results show an area overhead of approximately 12% and low
degradation on existing CUT performances. On-chip BIST of four CUT examples and
comparisons of other related techniques are also included. Chapter 4 presents the BIST
technique that is a fault signature characterization for embedded analog circuits in mixed-
signal LSI compliant with IEEE1149.4 boundary scan standard. Demonstrations have been
performed for a 4th-order Gm-C low-pass filter. Both catastrophic and parametric faults
are potentially detectable at the minimum parameter variation of 0.5%. The fault coverage
associated with CMOS trans conductance operational amplifiers and capacitors is at
94.16% and 100%, respectively. Low performance.

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CHAPTER-2
Linear Feedback Shift Registers
Let F = Fq denote a nite eld having q elements. A general feedback shift register is
a map f : Fd → Fd of the form
f(x0, ..., xn−1) = (x1, x2, ..., xn), xn = C(x0, ..., xn−1),
where C : Fd → F is a given function. When C is of the form
C(x0, ..., xn−1) = a0x0 + ... + an−1xn−1,
for some given constants ai ∈ F, the map is called a linear feedback shift register (LFSR). It
turns out such sequences are periodic. The main focus of this paper will be to discuss
Massey's algorithm [4] for deciphering a stream cipher given by a linear feedback shift
register. This algorithm has been implemented (by the author) in the computer algebra
system SAGE [9] using Python (www.python.org) Here, we shall work over any nite eld,
instead of only dealing with the binary case. However, this paper will begin by discussing
some of the history of LFSRs in applications.
2.1 Background on Linear Feedback Shift Registers
A (non-)linear feedback shift register can be easily implemented in hardware or
software and is used to create a pseudo-random sequence of numbers for many die rent
applications. These applications include uses in consumer electronics, such as cell phones
and digital cable [7]; multiple access and polling techniques; secure and privacy

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communications; error detecting and correcting codes; and 1SAGE is a free and open-
source computer algebra system written primarily in Python. Please see section 4 below for
more details. cryptographic systems [1]. The fascinating notes of Körner [2] also mention
cable TV scrambling and the use of periodic sequences for modeling the behavior of the
British and German WWII codes. (We refer to Sherman [8] for a rigorous mathematical
interpretation of the Enigma cipher machine.).
Figure: 2.1 Examples of LFSRs

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In consumer electronics, a Linear Feedback Shift Register can be used as a counter
When used in this manner, LFSRs are desirable because they perform the function with
less resources and usually much faster than the conventional counters, such as binary
counters or Gray Code counters. Though it goes against intuition, LFSRs can also be
used to generate pseudo-noise which is used by such consumer electronics as cell
phones and digital cable to increase the reliability of the signal. LFSRs can also be used
in spread spectrum systems . A spread spectrum system utilizes the entire bandwidth a
signal may use to send information by spreading the data frequency over many
frequencies in the bandwidth. The next frequency to be utilized is determined by the
LFSR sequence. Other more common applications of a LFSR is the use in white noise
machines (such as the one shown below) and music synthesizers, where they are used to
make the electrically-produced music sound more natural.
Figure: 2.2 White noise machine
Another application of LFSRs is the creation of pseudo-random sequences that
can be used in cryptography. The LFSR sequence is a pseudo-random number sequence
that can be applied to a message as a cipher, as explained in Example 3 below.
Throughout this paper, the cipher will be a sequence of binary terms that is added to the
binary message to provide the encoded message, also known as the cipher text. The

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cipher encodes the message so that only someone with the key knows the proper way to
decode the message and is then able to read the message, anyone without the key
receives the cipher text and reads only nonsense. The key is a piece of information that
allows a user to determine the specie cipher used in encrypting the message. In digital
communication, the enciphering of a message with a LFSR sequence is the same as
adding in pseudo-random noise. The proper recipient with a key removes the noise from
the message, but a third party without the key interprets the message only as noise.
2.2 How to Create a LFSR Sequence
A linear feedback shift register sequence is a pseudo-random sequence of
numbers that is often created in a hardware implementation of a linear feedback shift
register. When a LFSR is implemented in hardware, a LFSR sequence is recursively
generated by taking the output from the last stage of a given LFSR to compute the next
stage. An example of a LFSR implemented in hardware is included in Figure 1 (from
Massey . This LFSR is of length L, and each state cell's current state is used as the input
to the mod 2 adder. This adder is implemented in hardware with an exclusive-or
function. Since this is a shift register, each iteration of the register causes the state of
each state cell to shift to the next cell (in this case, to the right). We use the output of the
last state cell to provide the next term of the sequence after each iteration.

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Figure: 2.3 figures 4&5 are the models of LFSRs
Figure: 2.4 1-Bit LFSR diagram

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This hardware LFSR can be modeled mathematically to generate a LFSR
sequence. In order to build this sequence, three pieces of information are needed. They
are the (1) key, the (2) initial ll, and (3) an algorithm to obtain the next term of the
sequence. In the hardware implementation, the connections between the state cells and
the mod 2 adder determines how the outputs of the cells are used as inputs to the mod 2
adder. In the same way, the key determines how the previous terms of the LFSR
sequence are used to compute the next term in the sequence. The key may be
represented as a vector c = [c1, c 2, ..., cL ], but is more often de ned by a polynomial,
known as the connection polynomial
C(x) = 1 + c1 · x + c2 · x2 + ... + cL · xL. (1)
`The coefficients ci's can also be considered the key. In Figure 1, the coefficients
describe which cells were used as inputs to the modulo 2 adder. The degree of the
polynomial also describes how many cells (or bits) are needed to create the minimal
linear feedback shift register that will generate the given LFSR sequence.
According to Massey , the initial ll is the list of initial values of the state cells, s0,
s1, s2 , ..., sL−1 the initial contents of the L stages of Figure 1 above. In the binary case,
the LFSR sequence is de need by the following recursion relation.
L
sj = ci · sj−i mod 2, (2)
=1
Xi
for j ≥ l

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Example 1 If we are given the key as a vector c = [1, 0, 0, 1] and the initial ll as a vector
s = [1, 1, 0, 1] in the nite eld GF (2), we can create the sequence 1, 1, 0, 1, 0, 1, 1, 0, 0,
1, 0, 0, 0, 1, 1, 1, 1, ... Note that the rst four terms of the sequence are the same as the
terms given to us by the vector s (namely s0 = 1, s1 = 1, s2 = 0, s3 = 1). The next term (s4)
is found by using the recursion function to
give
s = 4 c
i ·
s4 i = c s3 + c2 s2 + c3 s1 + c4 s0
4
Pi=1 − = 11··1 + 0 · 0·+ 0 · 1 +·1 · 1 = 0·.
We know that L = 4 since the length of vectors c and s is 4. This sequence satisfies
Golomb's three randomness conditions given in Ÿ2.2. Fortunately, this process can be
easily automated and a function has been written for the computer algebra system SAGE
which will quickly generate terms of a LFSR sequence of any length de need by the
user. The inputs for this function are two vectors representing the key and the initial ll
and an integer n > L representing thedesired number of terms in the output. Example 2
More generally, let
f(x) = a0 + a1x + ... + anxn + ..., g(x) = b0 + b1x +
... + bnxn + ...,
be given polynomials in F3[x] and let
h(x) = f(x) = c0 + c1x + ... + cnxn + ... .
g(x)
We can compute a recursion formula which allows us to rapidly compute the
coefficients of h(x) (take f(x) = 1):

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cn =
Xn −bi cn−i. i=1 b0
The coefficients of h(x) can, under certain conditions on f(x) and g(x), be
considered random from certain statistical points of view. For instance,
if we consider a case other than binary and if
f(x) = 1, g(x) = 2 · x4 + x + 1,
then
h(x) = 1 + 2 · x + x2 + 2 · x3 + 2 · x4 + x6 + x7 + x8 +
... .
The coefficients of h are
2, 1, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 0, 2, 0,
2, 1, 1, 2, 0, 1, 0, 2, 1, 0, 0, 2, 2, 1, 2, ... .
The sequence of 0, 1, 2's is periodic with period P = 34 − 1 = 80. However, this
sequence of period 80 can be cracked (i.e., a procedure to reproduce g(x)) by knowing
only 8 terms! This is the result of Massey's algorithm [4], which is implemented in
SAGE by the author, and described in detail below.

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2.2.1 Linear Feedback Shift Registers in Cryptography
A stream cipher is a sequence of binary digits called a cryptographic bit-stream .
The stream cipher is then added to the message to create a cipher text (encryption) and
can be added to the cipher text to obtain the original message (decryption).2.1 Four
Tenets of Security Imagine that Alice and Bob are sending messages back and forth to
one another. If the content of these messages was not very secret and Alice and Bob did
not care if anyone else read the message, they would not bother with any kind of
encryption. Then, if an evil eavesdropper, say Eve, intercepts the message she can read it
without any difficulty. If, on the other hand, Alice and Bob were exchanging
information they wanted to keep secret, they would need to employ some kind of
encryption system to encode their messages. Depending upon the type of encryption
they employ, Alice and Bob would receive a certain level of security against the actions
of third parties. No matter what type of encryption Alice and Bob use, there will be
several objectives that Alice and Bob want the encryption method to achieve. Out of a
long list of objectives, there are four that form a framework upon which all the others
are built . The four security objectives that would apply to this message include:
Secrecy: This objective ensures that the information is available only to those people
who are authorized to have it. Integrity: This ensures that no third party can make
unauthorized alterations to the data. Non-repudiation: This prevents the sender of
information from denying that they sent that information. This also allows the receiver
to prove to a third party that the information was sent by the sender. Authentication:
Authentication is related to identification. Two parties that are communicating with each
other need to be able to identify one an-other and the receiver can be sure that the person
sending the information is who the receiver thinks it is. Does the LFSR sequence, as an
encryption method, meet the above four security objectives? First, a binary LFSR
sequence stream cipher achieves secrecy by adding the sequence to the binary
representation of the message. The LFSR sequence appears as noise added to the
message, thus frustrating any-one who intercepts the message. The problem with relying
on LSFR sequences for secrecy is that the minimal connection polynomial of the
sequence is easily determined using the Berlekamp-Massey Algorithm, which is
discussed in Ÿ3.2. The minimal connection polynomial is the key necessary to generate
the LFSR sequence used as the stream cipher. With this key, the eavesdropper Eve can
easily add the sequence to the cipher text to retrieve the original message. One method

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Alice and Bob can use to have more secrecy in the stream cipher is by picking LFSR
sequences with extremely long periods (i.e. period length p ≈ 1050). With long period
lengths, Eve needs a longer amount of cipher text to and the minimal connection
polynomial and she needs more terms of the sequence to determine the correct
polynomial. LFSR sequences combined with some error-correcting codes can provide a
limited amount of integrity. However, on its own, a LFSR sequence provides very little
integrity. Likewise, on its own, a LFSR sequence provides very little in terms of non-
repudiation. In order to provide for authentication, Alice and Bob could each create their
own stream cipher using a different LFSR sequence. Alice would then send her key and
initially to Bob and Bob would send his key and initial ll to Alice. Alice would then add
together her sequence and Bob's sequence to obtain a new sequence. She would use this
sequence as the stream cipher and encode her message to send to Bob. Bob would also
add together the two sequences to obtain the same stream cipher. This would allow
Alice and Bob to verify that they are talking with each other since they created their
stream cipher by adding their own individual sequences.2.2 Pseudo-random Binary
Sequences Any binary sequence that has Golumb's three properties stated below is
considered to be pseudo-random. One type of stream cipher that is used to create cipher
texts is pseudo-random binary sequences. Linear feedback shift register sequences are
one type of pseudo-random binary sequence that are easily generated by linear feedback
shift registers. Ideally, a cryptographic bit-stream sequence would have in nite length
and complete randomness. The reality of practical application and construction
techniques necessitates the use of only nite sequences. Since nite sequences can never be
truly random, there are certain properties singled out that are associated with
randomness. Golomb's properties are
Balance: The number of 1's is approximately equal to the number of 0's. (More
generally, each symbol occurs with approximately equal frequency.)
Proportional runs: The runs of consecutive 1's or 0's frequently occur with short runs

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more frequent than long runs. (More generally, runs of a given symbol of a shorter
length occur more frequently than those of a given longer length.).
Low autocorrelation: The sequence possesses an auto-correlation function , which is
peaked in the middle and tapering o rapidly at the ends.
The auto-correlation function is a way to quantize how random a sequence is and is
denied by
1 Xp
AC(k) = p i=1 xi · xi+k
where p is the period of the sequence {xi} and the sum is taken as a real number not as
an element of the nite eld with 2 elements. When 0 < k < p, AC(k)is close to zero
(meaning there is very little correlation of the sequence with itself) and AC(0) = 12 ,
since by the Balance property, 1/2 the elements of the sequence are 0.In order to
generate a stream cipher that only Alice and Bob know, each person will generate a
pseudo-random sequence of sufficient length. Alice will send her sequence to Bob and
Bob will send his sequence to Alice. The two people will then add their sequences
together bit-wise to produce a common stream cipher. For our purposes, suppose the
resultant sequence from the two individual sequences is Alice now has a message in
binary format and a cipher to encode the message. Adding the cipher to the message,
Alice gets the encrypted message or cipher text,
E.

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00100011000101100000000101010100011110
00 M
+
1101011001000111101011001000111101011001 = + C
11110101010100011010110111011011001000 E
If a third party, Eve, were to intercept the cipher text and tried to read it, knowing that
the computers used the above table to talk to one another, he would decrypt the cipher
text as LRRA?..;BA . Notice that both À's in the original message where changed to
two different letters (`R' the rst time and `.' the second time) and that È' and À' both are
changed to `R' and `T' and `!' are both changed to À'. This helps prevent a cryptanalyst
from breaking the code by mapping each character to something different every time.
The mapping appears random since the stream cipher used was a pseudo-random
sequence. When Bob receives the cipher text, however, he is able to decrypt it since he
has the stream cipher that he and Alice created earlier. By adding the stream cipher to
the cipher text, he will uncover the original message.
11110101010100011010110111011011001000
01 E
+
1101011001000111101011001000111101011001 = + C
00100011000101100000000101010100011110
00 M
Now Bob can use the table to decode the message from binary into English and receives
BEAT ARMY! from Alice.

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2.3 How to Find the Connection Polynomial
2.3.1 Recovering the Connection Polynomial from a LFSR Sequence
In some cases, it is necessary to recover the connection polynomial of a LFSR
sequence from the sequence itself. This is true when attempting to do crypt-analysis on a
piece of intercepted code. When a part of the stream cipher is intercepted, the connection
polynomial can be recovered even if the number of bits of the cipher is less than the
period of the sequence. Once this polynomial is known, the entire cipher can be
generated and any messages that are encrypted using that particular sequence as a stream
cipher can be decrypted and read by the third party.
2.3.2 Massey’s Algorithm
An algorithm exists that provides a connection polynomial given only a few
terms of a LFSR sequence. This algorithm is known as the Berlekamp-Massey
algorithm. One is able to determine the connection polynomial of a LFSR sequence of
period 15 with only 8 terms of the sequence. This can be generalized since if we know
that a sequence has a minimal connection polynomial with degree ≤ L, then only 2 · L
terms of the sequence need to be known in order to determine the correct connection
polynomial. We can determine L if we know the period length of the sequence, since the
period p = 2L − 1 [3]. This is an extremely powerful tool for cryptanalysts trying to
break stream ciphers generated from LFSRs, since only a relatively small sample of a
long period sequence is needed to break the cipher. The algorithm as it is described by
James Massey is presented below [4]:Input: a LFSR sequence of length n.Output: a
connection polynomial C(x) of the minimal LFSR.
Initialize the algorithm by setting C(x) = 1, B(x) = 1, m = 1, b = 1, L = 0, and, N = 0.
If N = n, then terminate, otherwise calculate the discrepancy
XL
d = sN + ci · sN−i
i=1

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If d = 0, then m = m + 1, go to step 6.
If d 6= 0 and 2 · L > N, then calculate C(x) = C(x) − d · b−1 · xm · B(x),
m = m + 1, go to step 6.
d 6= 0 and 2 · L ≤ N, then set T (x) = C(x), calculate C(x) = C(x) −
d · b−1 · xm · B(x), L = N + 1 − L, B(x) = T (x),and set m = 1 and b
= d,
go to step 6.
6. Calculate N = N + 1 and repeat steps 2 through 6.
This algorithm determines whether or not the current connection polynomial C(x) can
correctly produce the next term of the given sequence. If it can, the
discrepancy d = 0 and the algorithm leaves C(x) unchanged and iterates to the next
step. If C(x) does not provide the next term of the sequence, the
discrepancy d =6 0 and a new C(x) is calculated as in steps 4 and 5 above. The
algorithm is complicated and mysterious enough to warrant a complete example,
showing all steps.
Example 4 The LFSR sequence used in this example: 110101100100011. We take the

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algorithm all the way out to the termination when N = n. Though this sequence is of
length n = 15, we arrive at the correct connection polynomial C(x).
after only 8 iterations of the algorithm. Iterations 9 through 15 return a dis-crepancy d
= 0 which causes the algorithm to return the connection polynomial
calculated in the previous iteration.
Step 1: C(x) = 1,B(x) = 1, m = 1, b = 1, L = 0, N = 0 6= 15 = n.
Step 2: Find the discrepancy
X0
d = s0 + ci · s0−i = s0 = 1
i=1
since d =6 0, we compare 2 · L to N
2 · L = 2 · 0 = 0 ≤ 0 = N

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go to step 5.
Step 5: Calculate
T (x) = C(x) = 1
C(x) = C(x) − d · b−1 · xm · B(x) = 1 − x L = N + 1 − L = 0 + 1 − 0 = 1
B(x) = T (x) = 1 b = d = 1
m = 1
go to step 6.
Step 6: Increase N
N = N + 1 = 0 + 1 = 1
Step 1: C(x) = 1 − x, B(x) = 1, m = 1, b = 1, L = 1, N = 1 6= 15 = n.
X1
d = s1 + ci · s1−i = s1 + c1 · s0 = 0
i=1
Step 3: Since d = 0, m = m + 1 = 1 + 1 = 2, and we skip to step 6.

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Step 6: Increase N
N = N + 1 = 1 + 1 = 2
Step 1: C(x) = 1 − x, B(x) = 1, m = 2, b = 1, L = 1, N = 2 6= 15 = n.
1
d = s2 + ci · s2−i = s2 + c1 · s1 = 1
=1
Xi
since d 6= 0, we compare 2 · L and N
2 · L = 2 · 1 = 2 ≤ 2 = N
go to step 5.
Step 5: Calculate C(x)
T (x) = C(x) = 1 – x
C(x) = C(x) − d · b−1 · xm · B(x) = −x − x2
L = N + 1 − L = 2 + 1 − 1 = 2
B(x) = T (x) = 1 – x
b = d = 1
m = 1
go to step 6.
Step 6: Increase N

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N = N + 1 = 2 + 1 = 3
4. Step 1: C(x) = 1 − x − x2, B(x) = 1 − x, m = 1, b = 1, L = 2,
N = 3 6= 15 = n.
2
d = s3 + ci · s3−i = s3 + c1 · s2 + c2 · s1 = 1 + 1 · 0 + 1 · 1 = 0
=1
Xi
since d = 0, m = m + 1 = 1 + 1 = 2, and we skip to step 6.
Step 6: Increase N
N = N + 1 = 3 + 1 = 4
5. Step 1: C(x) = 1 − x − x2, B(x) = 1 − x, m = 2, b = 1, L = 2,
N = 4 6= 15 = n.

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d = s6 + ci ·s6−i = s6 + c1 ·s5 + c2 ·s4 + c3 ·s3 = 1+0 ·1+1 ·0+0 ·1 = 1
i=1
since d =6 0 we compare 2 · L and N
2 · L = 2 · 3 = 6 ≤ 6 = N
go to step 5.
Step 5: Calculate C(x)
T (x) = C(x) = 1 + x2
C(x) = C(x) − d · b−1 · xm · B(x) = 1 + x3 + x4
L = N + 1 − L = 6 + 1 − 3 = 4 B(x) = T (x) = 1 +
x2
b = d = 1 m = 1
go to step 6.
Step 6: Increase N N + 1 = 6 + 1 = 7

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At this point the algorithm outputs the last value of L and C(x) which are L = 4 and C(x)
= 1 − x + x4 . The algorithm terminates since N = n. Figure2 (from Massey [4]) depicts
the minimal LFSR found in this example. Since the coefficients (c1, c2 , c3, c4) of the
connection polynomial C(x) = 1 − x + x4are
(1, 0, 0, 1) we know that the inputs for the mod 2 adder are taken o the rst
and forth registers. Since L = 4, we know that the LFSR must have a minimum
of four registers. It should be noted that, since this example uses the binary case of
GF(2), −1 and +1 are the same modulo 2.
Figure:2.5 minimal LFSR with C(X)=1+X+X4 and L=4

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CHAPTER-3
COMBINATIONAL CIRCUITS
Combinational circuit is circuit in which we combine the different gates
the circuit for example encoder, decoder, multiplexer and de-multiplexer. Some
of the characteristics of combinational circuits are following .
The output of combinational circuit at any instant of time, depends only
on the levels present at input terminals.
The combinational circuit do not use any memory. The previous state of input
does not have any effect on the present state of the circuit.
A combinational circuit can have a n number of inputs and m number of outputs.
Block diagram
Figure:3.1 block diagram
We're going to elaborate few important combinational circuits as follows.

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3.1 DIFFERENT TYPES OF MODULES
Half Adder
Half adder is a combinational log ic circuit with two input and two output. The half
adder circuit is designed to add two sing le bit binary number A and B. It is the basic
building block for addition of two single bit numbers. This circuit has two outputs
carry and sum.
Block diagram
Figure:3.2 block diagram of half adder
Truth Table
Table:3.1 truth table of half adder
Circuit Diagram
Figure:3.3 circuit diagram of half adder

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Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two
one-bit numbers A and B, and carry c. The full adder is a three input and two output
combinational circuit.
Block diagram
Figure:3.4 block diagram of full adder
Truth Table
Table:3.2 truth table of full adder

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Circuit Diagram
Figure:3.5 circuit diagram of full adder
N-Bit Parallel Adder
The Full Adder is capable of adding only two sing le dig it binary number along with a
carry input. But in practical we need to add binary numbers which are much long er
than just one bit. To add two n-bit binary numbers we need to use the n-bit parallel
adder. It uses a number of full adders in cascade. The carry output of the previous full
adder is connected to carry input of the next full adder.
4 Bit Parallel Adder
In the block diag ram, A0 and B0 represent the LSB of the four bit words A and B.
Hence Full Adder-0 is the lowest stag e. Hence its Cin has been permanently made
0. The rest of the connections are exactly same as those of n-bit parallel adder is
shown in fig . The four bit parallel adder is a very common log ic circuit.

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Block diagram
Figure:3.6 block diagram of 4 bit parallel adder
N-Bit Parallel Subtractor
The subtraction can be carried out by taking the 1's or 2's complement of the number
to be subtracted. For example we can perform the subtraction (A-B) by adding either
1's or 2's complement of B to A. That means we can use a binary adder to perform the
binary subtraction.
4 Bit Parallel Subtractor
The number to be subtracted (B) is first passed through inverters to obtain its 1's
complement. The 4-bit adder then adds A and 2's complement of B to produce the
subtraction. S3 S2 S1 S0 represent the result of binary
subtraction (A-B) and carry output Cout represents the polarity of the result. If A > B
then Cout =0 and the result of binary form (A-B) then Cout = 1 and the result is in the
2's complement form.

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Block diagram
Figure:3.7 block diagram 4 bit parallel subtractor
Half Subtractors
Half subtractor is a combination circuit with two inputs and two outputs (difference and
borrow). It produces the difference between the two binary bits at the input and also produces
a output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as
Minuend bit and B is called as Subtrahend bit.

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Truth Table
Table:3.3 truth table of half subtractor
circuit Diagram
Figure:3.8 circuit diagram of half subtractor
Full Subtractors
The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a
combinational circuit with three inputs A,B,C and two output D and C'. A is the minuend, B is
subtrahend, C is the borrow produced by the previous stag e, D is the difference output and C'
is the borrow output.

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Truth Table
Table:3.4 truth table of full subtractor
Circuit Diagram
Figure:3.9 circuit diagram of full subtractor

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Multiplexers
Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and
m select inputs with 2m = n. It is a dig ital circuit which selects one of the n data inputs and
routes it to the output. The selection of one of the n inputs is done by the selected inputs.
Depending on the dig ital code applied at the selected inputs, one out of n data sources is
selected and transmitted to the sing le output Y. E is called the strobe or enable input which is
useful for the cascading . It is g enerally an active low terminal, that means it will perform the
required operation when it is low.
Block diagram
Figure :3.10 block diagram of multiplexer
Multiplexers come in multiple variations
2 : 1 multiplexer

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4 : 1 multiplexer
16 : 1 multiplexer
32 : 1 multiplexer
Block Diagram
Truth Table
Table ;3.5 truth table of mux
De-multiplexers
A de-multiplexer performs the reverse operation of a multiplexer i.e. it receives one input and
distributes it over several outputs. It has only one input, n outputs, m select input. At a time
only one output line is selected by the select lines and the input is transmitted to the selected
output line. A de-multiplexer is equivalent to a sing le pole multiple way switch as shown in
fig .

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De-multiplexers come in multiple variations
1: 2 de-multiplexers
1: 4 de-multiplexers
1: 16 de-multiplexer
1: 32 de-multiplexer
Block diagram
Figure:3.11 block diagram of de-mux
Decoder
A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs.
Decoder is identical to a de-multiplexer without any data input. It performs operations
which are exactly opposite to those of an encoder.
Block diagram
Figure:3.12 block diagram of decoder

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Examples of Decoders are following .
Code converters
BCD to seven segment decoders
Nixie tube decoders
Relay actuator
2 to 4 Line Decoder
The block diagram of 2 to 4 line decoder is shown in the fig . A and B are the two inputs
where D through D are the four outputs. Truth table explains the operations of a decoder. It
shows that each output is 1 for only a specific combination of inputs.
Block diagram
Figure:3.13 block diagram of 2to4 line decoder

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Truth Table
Table: 3.6 truth table of 2to4 line decoder
Logic Circuit
Figure:3.14 circuit diagram of 2 t0 4 line decoder

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Encoder
Encoder is a combinational circuit which is desig ned to perform the inverse operation of the
decoder. An encoder has n number of input lines and m number of output lines. An encoder
produces an m bit binary code corresponding to the dig ital input number. The encoder
accepts an n input dig ital word and converts it into an m bit another dig ital word
Block diagram
Figure:3.15 block diagram of encoder
Examples of Encoders are following .
Priority encoders
Decimal to BCD encoder
Octal to binary encoder
Hexadecimal to binary encoder
Priority Encoder
This is a special type of encoder. Priority is g iven to the input lines. If two or more input
line are 1 at the same time, then the input line with hig hest priority will be considered.
There are four input D0, D1, D2, D3 and two output Y0, Y1. Out of the four input D3 has
the hig hest priority and D0 has the lowest priority. That means if D3 = 1 then Y1 Y1 = 11

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irrespective of the other inputs. Similarly if D3 = 0 and D2 = 1 then Y1 Y0 = 10
irrespective of the other inputs.
Block diagram
Figure: 3.16 block diagram priority encoder
Truth Table
Table: 3.7 truth table of priority encoder

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Logic circuit
Figure :3.17 circuit diagram of priority encoder
Truth table
Table:3.8 truth table of encoder

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B.TECH ECE (2014-2015) AURORA’S ENGG COLLEGE, BHONGIR
CHAPTER -4
OUTPUT RESPONSE ANALYZERS
When test patterns are applied to a CUT, its fault free response(s) should be pre-
determined. For a given set of test vectors, applied in a particular order, we can obtain the
expected responses and their order by simulating the CUT. These responses may be stored
on the chip using ROM, but such a scheme would require a lot of silicon area to be of
practical use. Alternatively, the test patterns and their corresponding responses can be
compressed and re-generated, but this is of limited value too, for general VLSI circuits due
to the inadequate reduction of the huge volume of data.
The solution is compaction of responses into a relatively short binary sequence
called a signature. The main difference between compression and compaction is that
compression is loss less in the sense that the original sequence can be regenerated from the
compressed sequence. In compaction though, the original sequence cannot be regenerated
from the compacted response. In other words, compression is an invertible function while
compaction is not.
4.1Principle behind ORAs
The response sequence R for a given order of test vectors is obtained from a
simulator and a compaction function C(R) is defined. The number of bits in C(R) is much
lesser than the number in R. These compressed vectors are then stored on or off chip and
used during BIST. The same compaction function C is used on the CUTs response R* to
provide C(R*). If C(R) and C(R*) are equal, the CUT is declared to be fault-free. For
compaction to be practically used, the compaction function C has to be simple enough to
implement on a chip, the compressed responses should be small enough and above all, the
function C should be able to distinguish between the faulty and fault-free compression
responses. Masking [3.3] or aliasing occurs if a faulty circuit gives the same response as
the fault-free circuit. Due to the linearity of the LFSRs used, this occurs if and only if the
‘error sequence’ obtained by the XOR operation from the correct and incorrect sequence
leads to a zero signature.

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Compression can be performed either serially, or in parallel, or in any mixed
manner. A purely parallel compression yields a 'global' value C describing the complete
behaviour of the CUT. On the other hand, if additional information is needed for fault
localization then a serial compression technique has to be used. Using such a method, a
special compacted value C(R*) is generated for any output response sequence R* where
R* depends on the number of output lines of the CUT.
4.2 Different Compression Methods
We now take a look at a few of the serial compression methods that are used in the
implementation of BIST. Let X=(x1...xt) be a binary sequence. Then, the sequence X can
be compressed in the following ways:
4.2.1 Transition counting
In this method, the signature is the number of 0-to-1 and 1-to-0 transitions in the
output data stream. Thus the transition count is given by
t -1
T(X) = Σ(xi ⊕ xi+1)
i=1
Here the symbol '_' is used to denote the addition modulo 2, but the sum sign must be
interpreted by the usual addition.
4.2.2 Syndrome testing (or ones counting)
In this method, a single output is considered and the signature is the number of 1’s
appearing in the response R. It is mathematically expressed as:
t
Sy(X) = Σ xi (Savir, 1980);
i=1.
4.2.3 Accumulator compression testing
t k

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A(X) = Σ Σ xi (Saxena, Robinson1986);
k=1 i=1
In each one of these cases, the compaction rate n is of the order of O(log n). The following
well-known methods also lead to a constant length of the compressed value.
4.2.4 Parity check compression
In this method, the compression is performed with the use of a simple LFSR whose
primitive polynomial is G(x) = x + 1. The signature S is the parity of the circuit
response – it is zero if the parity is even, else it is one. This scheme detects all single
and multiple bit errors consisting of an odd number of error bits in the response
sequence but fails for a circuit with even number of error bits.
t
P(X) = ⊕ xi
i=1
where the bigger symbol '⊕' is used to denote the repeated addition modulo 2.
4.2.5 Cyclic redundancy check (CRC)
A linear feedback shift register of some fixed length n >=1 performs CRC. Here it
should be mentioned that the parity test is a special case of the CRC for n = 1.
4.3 Response Analysis
The basic idea behind response analysis is to divide the data polynomial (the input
to the LFSR which is essentially the compressed response of the CUT) by the characteristic
polynomial of the LFSR. The remainder of this division is the signature used to determine
the faulty/fault-free status of the CUT at the end of the BIST sequence. This is illustrated
in Figure 3.1 for a 4-bit signature analysis register (SAR) constructed from an internal
feedback LFSR with characteristic polynomial from Table 2.1. Since the last bit in the
output response of the CUT to enter the SAR denotes the co-efficient x
0
, the data
polynomial of the output response of the CUT can be determined by counting backward
from the last bit to the first. Thus the data polynomial for this example is given by K(x), as
shown in the Figure 3.3(a). The contents for each clock cycle of the output response from

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the CUT are shown in Figure 3.3(b) along with the input data K(x), shifting into the SAR
on the left hand side and the data shifting out the end of the SAR, Q(x), on the right-hand
side. The signature contained in the SAR at the end of the BIST sequence is shown at the
bottom of Figure 3.3(b) and is denoted R(x). The polynomial division process is illustrated
in Figure 3.3(c) where the division of the CUT output data polynomial, K(x), by the LFSR
characteristic polynomial, P(x) results in a quotient, Q(x), which is shifted out of the right
end of the SAR, and a remainder R(x), which is contained in the SAR at the end of the
BIST sequence.
Figure: 4.1 Example of fault detection and signature aliasing
The polynomial division process of the SAR is given by:
K(x) = Q(x)P(x) + R(x)
Or equivalently,
R(x) = K(x) mod P(x)
Once the fault free signature has been established, fault detection occurs when the
signature of the faulty circuit is different from that of the fault-free circuit. Given a faulty
CUT response, K’(x) the signature resulting from signature analysis, R’(x) is given by:
R’(x) = K’(x) mod P(x)
K’(x) is related to the fault-free output response K(x) as

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K’(x) = K(X) + E(x)
Where E(x) is the error polynomial since it indicates the erroneous bits in the output
response. The difference between the signatures of the faulty and fault-free circuits R’(x)
and R(x) respectively, is given by:
Re(x) = R(x) + R’(x) = E(x) mod P(x)
Where Re(x) is the signature of the error polynomial E(x). Thus, a faulty CUT is always
identified as long as Re(x) is not equal to zero. Otherwise it results in masking or aliasing.
4.4 Multiple Input Signature Registers (MISRs)
A serial-input signature register can only be used to test logic with a single output.
We can extend the idea of a serial-input signature register to the multiple-input signature
register (MISR) shown in figure4.2. There are several ways to connect the inputs to both
types (type 1 and type 2) of LFSRs to form an MISR. Since the XOR operation is linear
and associative, so that (A ⊕B) ⊕C = A ⊕(B ⊕C), as long as the result of the additions
are the same then the different representations are equivalent. If we have an n -bit long
MISR we can accommodate up to n inputs to form the signature. If we use m < n inputs
we do not need the extra XOR gates in the last n – m positions of the MISR.
Figure:4.2 3bit misr circuit diagram
There are several types of BIST architecture based on the MISR. By including extra
logic we can reconfigure an MISR to be an LFSR or a signature register; this is called
a built-in logic block observer (BILBO). By including the logic that we wish to test in the
feedback path of an MISR, we can construct circular BIST structures. One of these is
known as the circular self-test path (CSTP).

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We can test compiled blocks including RAM, ROM, and data path elements using an
LFSR generator and a MISR. To generate all 2 n address values for a RAM or ROM we
can modify the LFSR feedback path to force entrance and exit from the all-zeros state.
This is known as a complete LFSR . The pattern generator does not have to be an LFSR
or exhaustive.
For example, if we were to apply an exhaustive test to a 4-bit by 4-bit multiplier this
would require 2 8 or 256 vectors. An 8-bit by 8-bit multiplier requires 65,536 vectors and,
if it were possible to test a 32-bit by 32-bit multiplier exhaustively, it would require
1.8 10 19 vectors. Table4.1 shows two sets of no exhaustive test patterns, {SA} and
{SAE}, if A and B are both 4 bits wide. The test sequences {SA} and {SAE} consist of
nested sequences of walking 1’s and walking 0’s (S1 and S1B), walking pairs (S2 and
S2B), and triplets (S3, S3B). The sequences are extended for larger inputs, so that, for
example, {S2} is a sequence of seven vectors for an 8-bit input and so on. Intermediate
sequences {SX} and {SXB} are concatenated from S1, S2, and S3; and from S1B, S2B,
and S3B respectively. These sequences are chosen to exercise as many of the add-and-
carry functions within the multiplier as possible.

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Table:4.1 multiplier test pattern
The sequence length of {SA} is 3A (B – 1), and 3(2A – 1)(3B – 2) for {SAE}, where
A and B are the sizes of the multiplier inputs. For example, {SA} is 168 vectors for A = B
= 8 and 2976 vectors for A = B = 32; {SAE} is 990 vectors (A = B = 8) and 17,766 vectors
(A = B = 32). From fault simulation, the stuck-at fault coverage is 93 percent for sequence
{SA} and 97 percent for sequence {SAE}.
Figure4.3 shows an MISR with a scan chain. We can now include the BIST logic as
part of a boundary-scan chain, this approach is called scan BIST.
Figure: 4.3 MISR with scan generator
Sequence
{SX}
Sequence
{SXB}
Sequence
{SA}
Sequence
{SAE}
S1= {1000 0100 0010
0001}
S2 = {1100 0110
0011}
S3 = {1110 0111}
SX = { {S1} {S2}
{S3}}
S1B = {0111 1011 1101
0111}
S2B = {0011 1001
1100}
S3B = {0001 1000}
SXB = { {S1B} {S2B}
{S3B} }
{
A B= {S1,
SX}
}
{ { AB = {S1, SX} }
{ AB = {S1B, SXB}
}
{ AB = {S2, SX} }
{ AB = {S2B, SXB}
}
{ A B= {S3, SX} }
{ AB = {S3B, SXB}
}
}
Total = 3(X – 1) = 9,
X = 4
Total = 3(X – 1) = 9, X
= 4
Total = 4 9
= 3A(B – 1) =
36
Total = 3(2A –
1)(3B – 2)
= 3 7 10 = 210

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4 bit misr is shown below
dfl
Figure: 4.4 4-bit misr block diagram
In 4-bit misr i used 4 d flip-flops and 7 xor gates and the input to the misr is given from
the circuit under test and the misr will generate the signature which is a combination of
repeated random sequence we can also use the misr as a shift register and lfsr and the
generated sequence is given to rom for further analysis.
The problem with ordinary LFSR response compacter is too much hardware
overhead if one of these is put on each primary output (PO). ƒMultiple-input signature
register (MISR) is the solution that compacts all outputs into one LFSR. It works because
LFSR is linear and obeys superposition principle. All responses are superimposed in one
Q3
33
Q2 Q1 Q0d d dd
clk
rst
P0 P1
P2 P3

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LFSR. The final remainder is XOR sum of remainders of polynomial divisions of each PO
by the characteristic polynomial.
m
Test patterns Response Ri(X) Si(X)
Figure:4.5 misr function diagram.
Figure 40.15 illustrates a m-stage MISR. After test cycle i, the test responses are
stable on CUT outputs, but the shifting clock has not yet been applied.
Ri(x)= (m-1)th polynomial representing the test responses after test cycle i.
Si(x)=polynomial representing the state of the MISR after test cycle i.
Ri(x) = ri, m-1xm-1+ri, m-2xm-2+.......................................................+ri,1x+ri,0
Si(x) = Si, m-1xm-1+Si, m-2xm-2+......................................................+Si,1+Si,0
Si+1(x) = [Ri(x)+xSi(x)]modG(x)
G(x) is the characteristic polynomial
Assume initial state of MISR is 0. So,
S0(x) =0
S1(x) =[R0(x)+xS0(x)]modG(x)
S2(x) =[R2(x)+xS2(x)]modG(x)
LFSR CUT MISR
Signature
Analysis
Golden
signatu
re

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.
.
.
.
.
Sn(x) =[xn-1R0(x)+xn-2 R1(x)+...................................+xRn-2(x)+Rn-1(x)]modG(x)
This is the signature left in MISR after n patterns are applied. Let us consider a n-bit
response compactor with m-bit error polynomial. Then the error polynomial is of (m+n-2)
degree that gives (2m+n-1-1) non-zero values. G(x) has 2n-1-1 nonzero multiples that
result m polynomials of degree <=m+n-2.
2n-1-1
Probability of masking P(M)=
2m+n-1-1
~=1/2m.
4.5 Masking / Aliasing
The data compressions considered in this field have the disadvantage of some loss
of information. In particular, the following situation may occur. Let us suppose that during
the diagnosis of some CUT, any expected sequence Xo is changed into a sequence X due
to any fault F such that Xo ≠ X. In this case, the fault would be detected by monitoring the
complete sequence X. On the other hand, after applying some data compaction C, it may
be that the compressed values of the sequences are the same, i.e. C(Xo) = C(X).
Consequently, the fault F that is the cause for the change of the sequence Xo into X cannot
be detected if we only observe the compression results instead of the whole sequences.
This situation is said to be masking or aliasing of the fault F by the data compression C.
Obviously, the background of masking by some data compression must be intensively

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studied before it can be applied in compact testing. In general, the masking probability
must be computed or at least estimated, and it should be sufficiently low.
The masking properties of signature analyzers depend widely on their structure,
which can be expressed algebraically by properties of their characteristic polynomials.
There are three main ways of measuring the masking properties of ORAs:
(i) General masking results either expressed by the characteristic polynomial or in
terms of other LFSR properties;
(ii) Quantitative results, mostly expressed by computations or estimations of error
probabilities;
(iii) Qualitative results, e.g. concerning the general possibility or impossibility of LFSR to
mask special types of error sequences.
The first one includes more general masking results, which are based either on the
characteristic polynomial or on other ORA properties. The simulation of the circuit and the
compression technique to determine which faults are detected can achieve this. This
method is computationally expensive because it involves exhaustive simulation. Smith’s
theorem states the same point as:
Any error sequence E=(e1,...,et) is masked by an ORA S if and only if its “error
polynomial” pE(x) = e1xt-1+...+et-1x+et is divisible by the characteristic polynomial pS(x)
[4].
The second direction in masking studies, which is represented in most of the papers
[7],[8] concerning masking problems, can be characterized by “quantitative” results mostly
expressed by some computations or estimations of masking probabilities. This is usually
not possible and all possible outputs are assumed to be equally probable. But this
assumption does not allow one to correlate the probability of obtaining an erroneous
signature with fault coverage and hence leads to a rather low estimation of faults. This can
be expressed as an extension of Smith’s theorem as:
If we suppose that all error sequences having any fixed length are equally likely the
masking probability of any n-stage ORA is not greater than 2
-n
.

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The third direction in studies on masking contains “qualitative” results concerning
the general possibility or impossibility of ORAs to mask error sequences of some special
type. Examples of such a type are burst errors, or sequences with fixed error-sensitive
positions. Traditionally, error sequences having some fixed weight are also regarded as
such a special type, where the weight w(E) of some binary sequence E is simply its number
of ones. Masking properties for such sequences are studied without restriction of their
length. In other words,
If the ORA S is non-trivial then masking of error sequences having the weight 1 by S is
impossible.

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CHAPTER-5
READ-ONLY MEMORY
5.1 INTRODUCTION
Read-only memory (ROM) is a class of storage medium used in computers and
other electronic devices. Data stored in ROM can only be modified slowly, with difficulty,
or not at all, so it is mainly used to distribute firmware that is very closely tied to
specific hardware and unlikely to need frequent updates).Strictly, read-only memory refers
to memory that is hard-wired, such as diode matrix and the later mask ROM. Although
discrete circuits can be altered (in principle), Integrated Circuits (ICs) cannot and are
useless if the data is bad. The fact that such memory can never be changed is a large
drawback; more recently, ROM commonly refers to memory that is read-only in normal
operation, while reserving the fact of some possible way to change it.
Other types of non-volatile memory such as erasable programmable read-only
memory (EPROM) and electrically erasable programmable read-only memory (EEPROM
or Flash ROM) are sometimes referred to, in an abbreviated way, as "read-only memory"
(ROM); although these types of memory can be erased and re-programmed multiple times,
writing to this memory takes longer and may require different procedures than reading the
memory. When used in this less precise way, "ROM" indicates a non-volatile memory
which serves functions typically provided by mask ROM, such as storage of program code
and non-volatile data.
5.2 HOW THE DEVICE WORKS
The read only memory cell usually consists of a single transistor (ROM and
EPROM cells consist of one transistor, EEPROM cells consist of one, one-and-a-half, or
two transistors).The threshold voltage of the transistor determines whether it is a“1” or

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“0.” During the read cycle, voltage is placed on the gate of the cell. Depending on the
programmed threshold voltage, the transistor will or will not drive a current. The
sense amplifier will transform this current, or lack of current, into a “1”or “0.” Figure 5.1
shows the basic principle of how a Read Only Memory works.
Column
Row
Cell
Selected
Sense Amplifier
Current Detector
To Output Buffer
Figure: 5.1. Read Only Memory Schematic
5.3 MASK PROGRAMMABLE ROMS
Mask programmable read-only memories (ROMs) are the least expensive type of
solid state memory. They are primarily used for storing video game software and fixed
data for electronic equipment, such as fonts for laser printers, dictionary data in word
processors, and sound data in electronic musical instruments.

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ROM programming is performed during IC fabrication. Several process methods
can be used to program a ROM. These include
• Metal contact to connect a transistor to the bit line.
• Channel implant to create either an enhancement-mode transistor or a depletion-
mode transistor.
• Thin or thick gate oxide, which creates either a standard transistor or a high
threshold transistor, respectively.
The choice of these is a trade-off between process complexity, chip size, and
manufacturing cycle time. A ROM programmed at the metal contact level will have the
shortest manufacturing cycle time, as metallization is one of the last process steps.
However, the size of the cell will be larger.
Figure 5.2 shows a ROM array programmed by channel implant. The transistor cell
will have either a normal threshold (enhancement-mode device) or a very high threshold
(higher than VCC to assure the transistor will always be off). The cell array architecture is
NOR. The different types of ROM architectures (NOR, NAND, etc.) are detailed in the
flash memory section (Section 10) as they use the same principle.
Figure 5.3 shows an array of storage cells (NAND architecture). This array consists
of single transistors noted as devices 1 through 8 and 11 through 18 that is programmed
with either a normal threshold (enhancement-mode device) or a negative threshold
(depletion-mode device).

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Figure:5.2 ROM Programmed by Channel Implant

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1
Word 1/11 11
2
Word 2/12 12
3
Word3/133 13
4
word 4/14 14
5
Word 5/15 15
6
WORD 6/16 16
7
Word7/17 17
8
WORD 8/18 18
9CONTROL
LINE 19
10SELECT
LINE 20
BIT
LINE
Figure: 5.3. Memory Cell Schematic

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5.4 MULTIMEDIA CARD
In 1996, Siemens announced the introduction of a new solid-state memory chip
technology that enables the creation of a multimedia card that is sized 37mm x 45mm x
1.4mm, or roughly 40 per-cents the size of a credit card. It is offered with either 16Mbit
or 64Mbit of ROM.
5.4.1 EPROM
EPROM (UV Erasable Programmable Read Only Memory) is a special type of
ROM that is programmed electrically and yet is erasable under UV light.
The EPROM device is programmed by forcing an electrical charge on a small piece of
polysilicon material (called the floating gate) located in the memory cell. When this charge
is present on this gate, the cell is “programmed,” usually a logic “0,” and when this charge
is not present, it is a logic “1.” Figure 5.4 shows the cell used in a typical EPROM. The
floating gate is where the electrical charge is stored.
First-Level
+VG Second-LevelPolysilicon
(Floating) Polysilicon
Gate Oxide
Field Oxide
– – –
N+
P- Substrate
Figure: 5.4 Double-Poly Structures (EPROM/Flash Memory Cell

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Prior to being programmed, an EPROM has to be erased. To erase the EPROM, it
is exposed to an ultraviolet light for approximately 20 minutes through a quartz window in
its ceramic package. After erasure, new information can be programmed to the EPROM.
After writing the data to the EPROM, an opaque label has to be placed over the quartz
window to prevent accidental erasure.
Programming is accomplished through a phenomenon called hot electron
injection. High voltages are applied to the select gate and drain connections of the cell
transistor. The select gate of the transistor is pulsed “on” causing a large drain current to
flow. The large bias voltage on the gate connection attracts electrons that penetrate the thin
gate oxide and are stored on the floating gate.
5.4.1.1 EPROM Floating Gate Transistor Characteristic Theory
The following explanation of EPROM floating gate transistor characteristic theory
also applies to EEPROM and flash devices. Figures 5.5 (a) and (b) show the cross section
of a conventional MOS transistor and a floating gate transistor, respectively. The upper
gate in Figure 5.5 (b) is the control gate and the lower gate, completely isolated within the
gate oxide, is the floating gate.

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Figure: 5.5 Cross Section of a Conventional MOS Transistor and a Floating-Gate MOS
Transistor.
CFG and CFS are the capacitances between the floating gate and the control gate and
substrate, respectively. VG and VF are the voltages of the control gate and the floating gate,
respectively. -QF is the charge in the floating gate. (As electrons have a negative charge, a
negative sign was added). In an equilibrium state, the sum of the charges equals zero.
VG  VF  CFG  0  VF  CFS  QF  0

C
FG


Q
F
V
F   V
G
C
FG
C
FS CFG  CFS 
VTC is the threshold voltage of the conventional transistor, and VTCG is the threshold
voltage of the floating gate transistor.
Gate Floating
Control
Gate
Gate
G
S D S D
C
FG
C
FS
N+ N+ N+ N+
(a) Conventional MOS (b) Floating-Gate MOS

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VTCG
CFG QF
VTC
CFG FSCFG
FS
VTCG VTO
QF
CG
CFG
Where
VT
O VTC and CG
FG
CFS
FG FS
The threshold voltage of the floating gate transistor (VTCG) will be VTO (around 1V)
plus a term depending on the charge trapped in the floating gate. If no electrons are in the
floating gate, then VTCG = VTO (around 1V). If electrons have been trapped in the floating
gate, then VTCG = VTO -QF/CG (around 8V for a 5V part). This voltage is process and
design dependent. Figure 5.6 shows the threshold voltage shift of an EPROM cell before
and after programming.

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Figure: 5.6 Electrical Characteristics of an EPROM
The programming (write cycle) of an EPROM takes several hundred milliseconds.
Usually a byte—eight bits—is addressed with each write cycle. The read time is
comparable to that of fast ROMs and DRAMs (i.e., several tens of nanoseconds). In those
applications where programs are stored in EPROMs, the CPU can run at normal speeds.
Field programmability is the EPROM’s main advantage over the ROM. It allows
the user to buy mass-produced devices and program each device for a specific need. This
characteristic also makes the EPROM ideal for small-volume applications, as the devices
are usually programmed in very small quantities. Also, the systems supplier can program
any last minute upgrades to the program just before shipment. EPROM cells may be
configured in the NAND structure shown previously, or, more commonly, in the NOR
configuration shown in Figure 5.7

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WORD 1 WORD 2 WORD3 WORD n
BIT 1
Figure: 5.7 NOR EPROM Configuration
BIT 2
22
Selected
Gate
Floating
Gate

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EPROMs were created in the 1970s and have long been the cornerstone of the
non-volatile memory market. But the development of flash memory devices (see Section
10) will lead to a loss of EPROM market share. EPROM uses a mature technology and
design and is on the decline part of its lifecycle. For this reason there is not a lot of R&D
expenditure made for EPROM devices. Figure 9-8 shows a cross section of a 1Mbit
EPROM cell from two different manufacturers. The main difference between the
processes is the polysilicon gate. One manufacturer uses a polycide to improve the speed.
5.4.1.2 EPROM Cell Size and Die Size
The cell size of the EPROM is also relatively small. The EPROM requires one
additional polysilicon layer, and will usually have slightly lower yields due to the
requirement for nearly perfect (and thin) gate oxides.
Figure: 5.8 Typical 1Mbit EPROM Cells

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These factors, plus the fact that an EPROM is encased in a ceramic package with
a quartz window, make the EPROM average selling price three to five times the price of
the mask ROM. Table 5.1 shows the main feature sizes of 1Mbit EPROM analyzed by
ICE’s laboratory.
Table: 5.1 EPROM Feature Sizes
5.4.2 EEPROM
EEPROM (Electrically Erasable Programmable ROM) offer users excellent
capabilities and performance. Only one external power supply is required since the high
voltage for program/erase is internally generated. Write and erase operations are
performed on a byte per byte basis.
The EEPROM uses the same principle as the UV-EPROM. Electrons trapped in a
floating gate will modify the characteristics of the cell, and so a logic “0” or a logic “1”
will be stored.
The EEPROM is the memory device that implements the fewest standards in cell
design. The more common cell is composed of two transistors. The storage transistor has
a floating gate (similar to the EPROM storage transistor) that will trap electrons. In
Manufacturer Density Date Code
Cell Size Die Size Min. Gate
( m2) (mm2) Length ( m)
Atmel 1Mbit 9428 4.40 14.6 0.6
AMD 1Mbit 9634 5.52 15.9 0.7
ST 1Mbit 9514 3.60 11.5 0.5
ISSI 1Mbit 94/95 6.80 18.0 0.7

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addition, there is an access transistor, which is required for operations. Figure 9-10
shows the voltages applied on the memory cell to program/erase a cell. Note that an
EPROM cell is erased when electrons are removed from the floating gate and that the
EEPROM cell is erased when the electrons are trapped in the float-ing cell. To have
products electrically compatible, the logic path of both types of product will give a “1”
for erase state and a “0” for a programmed state. Figure 9-11 shows the electrical
differences between EPROM and EEPROM cells
5.4.2.1 Parallel EEPROM
There are two distinct EEPROM families: serial and parallel access. The serial
access represents 90 percent of the overall EEPROM market, and parallel EEPROMs
about 10 percent. Parallel devices are available in higher densities (≥256Kbit), are
generally faster, offer high endurance and reliability, and are found mostly in the military
market. They are pin compatible with EPROMs and flash memory devices. Figure 9-12
shows feature sizes of three 1Mbit parallel EEPROM from different manufacturers,
analyzed by ICE’s laboratory. Figures 5.9 to 5.10 show photographs and schematics of
the respective cells. It is interesting to see the wide differences in these cells.
5.4.2.2 Serial EEPROM
Serial EEPROMs are less dense (typically from 256 bit to 256Kbit) and are
slower than parallel devices. They are much cheaper and used in more “commodity”
applications.

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Table: 5.2 1Mbit Parallel EEPROM Feature Sizes
Serial access EEPROMs feature low pin count. Typically they are packaged in an
8-pin package. As illustrated in Figure 9-16, Xicor’s 128Kbit serial EEPROM uses the 8
pins in the following manner:
• VCC and VSS for supply voltage
• SCL (Serial Clock) to clock the data
• SDA (Serial Data) is a bi-directional pin used to transfer data into and out of the
device
• S0, S1, S2 are select inputs used to set the first three bits of the 8-bit slave address
• WP (Write Protection) controls Write Protection features.
Serial EEPROMs use data transfer interface protocols for embedded control
applications. These protocols include the Microwave bus, the I2C bus, the XI2C
(Extended I2C) or the SPI (Serial Peripheral Interface) bus interfaces.
There continues to be an ongoing effort to reduce the size of serial EEPROMs.
Microchip Technology, for example, introduced a 128bit serial EEPROM in a five-lead
Cell Size Die Size Min Gate
(cm2) (mm2) Length (cm)
Winbond 1Mbit 9432 7.8 22.6 0.9
Xicor 1Mbit 9443 21.0 51.0 1.3
Hitachi 1Mbit 94/95 22.5 51.0 0.6

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SOT-23 package.
144424443
FLOATING GATE
PROGRAM LINE
POLY 2
WORD
LINE
BIT Q2
Q1
144424443
FLOATING GATE
PASSIVATION
METAL2
INTERLEVELGLASS
METAL1 BITLINE
FLOATING GATES
PROGRAM LINE
SELECTGATE N+ S/D
Figure :5.9 Xircom 1Mbit EEPROM Cell

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PASSIVATION
METAL2
INTERLEVELGLASS
METAL1 BITLINE
FLOATING GATES
PROGRAM LINE
SELECTGATE N+ S/D
Figure:5.10 Hitachi 1Mbit EEPROM Cell
METAL POLYCIDE
POLY
Figure 5.11 shows feature sizes of three serial EEPROMs from different
manufacturers that were analyzed by ICE’s laboratory. Note that larger cell sizes
accompany low-density EEPROM devices. When building an EEPROM chip that contains
sense amplifiers, controllers, and other peripheral circuitry, cell size is not as great a factor
at low (1Kbit, 2Kbit) densities. At larger densities, the size of the cell array is more critical.
It becomes a larger portion of the chip. Therefore, greater consideration must be given to
the size of the cell.

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Figure: 5.11 Xicor 128Kbit Serial EEPROM Functional Diagram
Cell Size Die Size Min Gate
( m2) (mm2) Length ( m)
Microchip 16K 9540 60.5 6.0 2.0
Xicor 2K 9432 100.0 4.0 2.0
ST 1K 9618 286.0 2.6 1.2
Table: 5.3 EEPROM Serial Configuration Feature Sizes

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This size impact is illustrated in Figure 9-18 using a 1Kbit serial EEPROM
example from SGS-Thomson. The cell array represents only 11 percent of the total surface
of the chip.
Figures 5.12 and 5.13 show additional EEPROM cells. As noted, there is no design
standard for this type of cell. In laying out the EEPROM cell, the designer must take into
consideration the elements of size, performance, and process complexity.
CELL ARRAY
wL
D
2
PIN 1
1
D
2 BITB
3
C
1 BITA
TUNNEL
OXI DEDEVICE
Figure: 5.12 SGS-Thomson 1Kbit Serial EEPROM

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PASSIVATION
BITLINE
REFLOW GLASS
POLY 2 PGM LINE
POLY 2 WORD LINE
N+ S/D
POL Y 1 FLO A T I N G GATE
Figure: 5.13 Microchip 16Kbit Serial EEPROM Cell
5.4.2.3 Multi-Level Analog Storage EEPROM
The goal of multi-level cell (MLC) is to store more than one bit of information in a
single cell. Much work has already been done regarding MLC as applied to flash memory
devices. The typical development for digital flash memories is to store four different levels
in the same cell, and thus divide the number of cells by two (four data are given by two bits
: 00, 01, 10, and 11).
However, for several years now, Information Storage Devices (ISD), a San Jose
based company, has proposed multi-level analog storage EEPROMs for analog storage.
ISD presented a 480Kbit EEPROM at the 1996 ISSCC conference. The multi-level storage
cell is able to store 256 different levels of charge between 0V and 2V. This means the cell
needs to have a 7.5mV resolution. The 256 different levels in one cell correspond to eight
bits of information. A comparable digital implementation requires 3.84Mbit memory
elements to store the same amount of information. The information stored will not be 100
percent accurate but is good enough for audio applications, which allows some errors.

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CHAPTER _6
SIMULATION RESULTS AND RTL SCHEMATIC DIAGRAMS
6.1 LINEAR FEEDBACK SHIFT REGISTER
6.1.1 Rtl Schematic Diagram
LFSR is having a schematic diagram and it is different from our theoretical block
diagram the tool will take its own design in behaviour model.
Figure:6.1 RTL schematic of LFSR.
6.1.2 Simulation Results of Lfsr
The LFSR will generate sequence by taking the previous out of LFSR that at the last D-
flip-flop and is xor with the first D-flip-flop and is feed as a input to it and also it will
generate sequence by right or left shifting the previous output and generate a random
sequence.

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Figure:6.2 lfsr simulation results
Here we cannot be able to keep the full sequence in a single image so i managed to
take two screenshots.

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6.2 CIRCUIT UNDER TEST
6.2.1 Circuit under Test Rtl Schematic
Figure: 6.3 rtl schematic of circuit under test
The circuit here we used is a combinational circuit contain xor, and, decoder at the we used
one 2 to 1 mux and one 4to1 mux but we faced problem that so we decided to remove them
for the better results.
6.2.2 Simulation Results of Circuit Under Test
The circuit under test or cut will take it inputs from lfsr for each clk cycle and give
a output according to the produced sequence of lfsr here we can also assign a port with a
permanent value to change the results. Due to this the circuit under test will assign that
particular value to that port and it will not take lfsr sequence value so we will get a faulty
results.

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Figure: 6.4 simulation result of circuit under test
6.3 MULTIPLE INPUT SIGNATURE REGISTER
6.3.1 Rtl Schematic Of Misr
The MISR circuit is designed by taking 4 d-flip-flops and 7 xor gates by writing A
verilog code for it. But the tool will take its own combination by changing some modules
for reducing power dissipation and time take to design it

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Figure: 6.5 rtl schematic of MISR
6.3.2 Simulation Results Of MISR
The misr block will take input from circuit under test for each clk cycle and
produce a signature result. A signature is nothing but a sequence with repeated bits and
randomly generated bits. The simulations are shown below

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Figure: 6.6 simulation results of MISR block
6.4 READ ONLY MEMORY(ROM)
6.4.1 Rtl Schematic Of Rom
The rom is used to store the values of lfsr sequence and to compare the results
Figure: 6.7 rtl schematic of rom

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6.4.2 Simulation Results Of Rom
The rom will take the misr sequence as a input and compare it with the address of
lfsr and gives the output of lfsr with random and repeated sequence. The rom will take misr
output sequence as a address.
Figure: 6.8 simulation result of rom
6.5 TOP MODULE (BIST)
The bist is a top module which is our goal. It is obtained by instating the entire
above module properly without any mistake and with proper mapping.
6.5.1 Rtl Schematic Of Top Module
The rtl schematic of bist contains lfsr, cut, misr and rom modules and all are
instated properly with proper mapping if we do any mistake we will get the output but it
will be the faulty circuit. The rtl schematic is given below

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Figure: 6.9 rtl schematic of bist
By expanding the above one we will get
Figure: 6.10 expanded rtl schematic of bist

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6.5.2 Simulation Results Of Bist
The simulation of bist obtained by proper functioning and proper instantiation of all
the modules and proper mapping of all the wire and registers. The rom will compare its
address with the misr sequence for each clk cycle and gives a random and repeated
sequence of lfsr. If we get this we can say that the circuit is working and it is good.
We can also generate the faulty circuit by making giving values to one port in the
code for circuit under test and it will permanently take that value only by skipping lfsr
sequence value so in this case we can say that the circuit is faulty.

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Figure: 6.11 simulation results of top module or bist

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CHAPTER – 7
CONCLUSION & FURUTE SCOPE
6.1 CONCLUSION
The BIST architecture proposed is implemented using Verilog language and tested
on various faulty circuits. Then design has been synthesized on Xilinx and fault has been
created and simulated on Modelsim.
In this paper we have illustrated an implementation of BIST logic using Verilog.
LFSR is used as a pseudorandom sequence generator. Signature analysis is used to make
verification of the circuit. Signature mismatch with the reference signature means that the
circuit is faulty. However, there is a small probability that the signature of a bad circuit will
be the same as a good circuit. When longer sequences are used , signature analysis gives
high fault coverage.
6.2 FUTURE SCOPE
There are some the following disadvantages regarding this technique and the work
is still going on these.
 Area Overheads: Larger chip area results in fewer chips for wafer and hence, high
cost for chip.
 Performance penalty: Large signal routing paths, as the system function spread out
to room for BIST circuitry.
 Increased power dissipation: Due to high data activity, during BIST sequence , can
present problems in some system applications, such as, those with power
consumption or temperature restrictions.
 Additional design time and effort.

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 Additional risk to the project: Since we are now faced with the task of designing
and verifying proper operation of the BIST system, in addition.

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BIBLIOGRAPHY
1. http://en.wikipedia.org/wiki/built-in_self-test
2. http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=4167 999
3. http://ieeexplore.ieee.org/xpl/articleDetails.js p? tp=&arnumber=1402 683
4.Implementation of BIST structure using VHDL for VLSI circuits
Mrs.Jamuna.SProfessor, department of ECE, Bangalore Dr. V.K. Agrawal Group director,
ISRO, Bangalore
5. Built-inselftest, AbdelRashid Linkoping University, Sweden
6. www.wikipedia.org/wiki/linear feedback shift register.
7. www.wikipedia.org/wiki/multiple input signature register.
8. www.xilinx.com.
9. www.slideshare.com
10. www.scribd.com.

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APPENDIX A
ABOUT SOFTWARE TOOL
XILINX
Xilinx is American Technology Company, primarily supplied programmable logic
devices. It is known for field programmable logic array(FPGA).
Ross Freeman, Bernard Vonderschmitt, and James V Barnett II, who all had
worked for integrated circuit and solid-state device manufacturer Zilog Corp, founded
Xilinx in 1984.
While working for Zilog, Freeman wanted to create chips that acted like a blank
tape, allowing users to program the technology themselves. At the time, the concept
was paradigm changing. "The concept required lots of transistors and, at that time,
transistors were considered extremely precious – "people thought that Ross's idea was
pretty far out", said Xilinx Fellow Bill Carter, who when hired in 1984 as the first IC
designer was Xilinx's eighth employee.
ISE DESIGN SUITE 14.5
Xilinx ISE (Integrated Synthesis Environment) is a software tool produced
by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize
("compile") their designs, perform timing analysis, examine RTL, diagrams, simulate a
design's reaction to different stimuli, and configure the target device with the programmer.
The Xilinx ISE is a design environment for FPGA products from Xilinx, and is
tightly-coupled to the architecture of such chips, and cannot be used with FPGA products
from other vendors. The Xilinx ISE is primarily used for circuit synthesis and design,
while the ModelSim logic simulator is used for system-level testing. Other components
shipped with the Xilinx ISE include the Embedded Development Kit (EDK), a Software
Development Kit (SDK) and Chip Scope Pro.

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User interface
The primary user interface of the ISE is the Project Navigator, which includes the
design hierarchy (Sources), a source code editor (Workplace), an output console
(Transcript), and a processes tree (Processes).
The Design hierarchy consists of design files (modules), whose dependencies are
interpreted by the ISE and displayed as a tree structure. For single-chip designs there may
be one main module, with other modules included by the main module, similar to the main
() subroutine in C++ programs. Design constraints are specified in modules, which include
pin configuration and mapping.
The Processes hierarchy describes the operations that the ISE will perform on the currently
active module. The hierarchy includes compilation functions, their dependency functions,
and other utilities.] The window also denotes issues or errors that arise with each function.
The Transcript window provides status of currently running operations, and informs
engineers on design issues. Such issues may be filtered to show Warnings, Errors, or both.
Simulation
System-level testing may be performed with the Modelsim logic simulator, and such test
programs must also be written in HDL languages. Test bench programs may include
simulated input signal waveforms, or monitors which observe and verify the outputs of
the device under test.
Modelsim may be used to perform the following types of simulations:
 Logical verification, to ensure the module produces expected results
 Behavioural verification, to verify logical and timing issues
 Post-place & route simulation, to verify behaviour after placement of the module
within the reconfigurable logic of the FPGA.
]

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Synthesis
Xilinx's patented algorithms for synthesis allow designs to run upto 30% faster than
competing programs, and allow greater logic density which reduces project costs.
Also, due to the increasing complexity of FPGA fabric, including memory blocks
and I/O blocks, more complex synthesis algorithms were developed that separate unrelated
modules into slices, reducing post-placement errors.
IP Cores are offered by Xilinx and other third-party vendors, to implement system-
level functions such as digital signal processing (DSP), bus interfaces, networking
protocols, image, embedded processors, and peripherals. Xilinx has been instrumental in
shifting designs from ASIC-based implementation to FPGA-based implementation.
Editions
The Subscription Edition is the licensed version of Xilinx ISE, and a free trial
version is available for download.
The Web Edition is the free version of Xilinx ISE that can be downloaded and used for no
charge. It provides synthesis and programming for a limited number of Xilinx devices. In
particular, devices with a large number of I/O pins and large gate matrices are disabled.
The low-cost Spartan family of FPGAs is fully supported by this edition, as well as the
family of CPLDs, meaning small developers and educational institutions have no
overheads from the cost of development software.
License registration is required to use the Web Edition of Xilinx ISE, which is free and can
be renewed an unlimited number of times.

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Device Support
ISE
Web pack(free)
ISE Design Suite
(commercial)
Virtex FPGA
Virtex-4
LX: XC4VLX15,
XC4VLX25
SX: XC4VSX25
FX: XC4VFX12
Virtex-5
LX: XC5VLX30,
XC5VLX50
LXT: XC5VLX20T -
XC5VLX50T
FXT: XC5VFX30T
Virtex-6
XC6VLX75T
Virtex-4
LX: All
SX: All
FX: All
Virtex-5
LX: All
LXT: All
SXT: All
FXT: All
Virtex-6
All
Spartan FPGA Spartan-3
XC3S50 - XC3S1500
Spartan-3A
All
Spartan-3AN
All
Spartan-3A DSP
XC3SD1800A
Spartan-3E
All
Spartan-6
XC6SLX4 - XC6SLX75T
XA (Xilinx Automotive)
Spartan-6
All
Spartan-3
All
Spartan-3A
All
Spartan-3AN
All
Spartan-3 DSP
All
Spartan-3E
All
Spartan-6
All
XA (Xilinx Automotive
Coolrunner PLA
Coolrunner-II CPLD
Cool runner-IIA CPLD
ALL ALL
XC9500 Series CPLD
All (Except 9500XV family) All (Except 9500XV family)

implementation of BIST

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implementation of BIST