Intel 80386 Architecture and Programming
- 2. MODULE OUTLINE At the end of this module, the student should be able to: • Understand the difference between 8086 and 80386 • Perform basic instruction set on 80386 • Explain the 80386 registers • Differentiate the different instruction set of 80386 2
- 3. MICROPROCESSOR • A microprocessor, sometimes called a logic chip, is a computer processor on a microchip. • It is also called as “Heart of Computer”. • The microprocessor contains all, or most of, the central processing unit (CPU) functions. • A microprocessor is designed to perform arithmetic and logic operations that make use of small number-holding areas called registers. • Typical microprocessor operations include adding, subtracting, comparing two numbers, and fetching numbers from one area to another. • These operations are the result of a set of instructions that are part of the microprocessor design. 3
- 4. MICROPROCESSOR FAMILY Chip Introduction Data Bus Address Bus Memory 4004 1971 4 8 256 byte 8008 1972 8 8 256 byte 8080 1974 8 16 64 kB 8086/88 1978 16/8 20 1 MB 80186/88 1982 16/8 20 1 MB 80286 1983 16 24 16 MB: High Clock speed 80386 DX: 1986 SX: 1988 32 + 132 pin 16 + 100 pin 32 24 4 GB 16 GB 4
- 6. LOGICAL TO PHYSICAL ADDRESS TRANSLATION IN 8086 • The 20-bit address of a byte is called its Physical Address. But it is specified as a Logical Address. • Logical address is in the form of: Base Address:Offset • Offset is the displacement of the memory location from the starting location of the segment 6
- 7. EXAMPLE The value of Data Segment Register (DS) is 2222 H • To convert this 16-bit address into 20-bit, the Bus Interface Unit (BIU) appends 0H to the LSBs of the address. • After appending, the starting address of the Data Segment becomes 22220 H • If the data at any location has a logical address specified as: 2222 H : 0016 H • Then, the number 0016 H is the offset. 2222H is the value of DS. 7
- 8. To calculate the physical address of the memory, BIU uses the following formula: Physical Address = Starting Address of Segment + Offset To find the starting address of the segment, BIU appends the contents of Segment Register with 0H. Then, it adds offset to it. Therefore: EA = 22220 H + 0016 H --------------------- 22236 H 8
- 9. 9
- 10. 80386 • Data bus = 32bit, all registers of 32 bit and Eflags is also of 32 bit. • Address Bus = 32 bit with 4 GB Memory • Enhanced Memory Management Unit. • Supports Virtual addressing. • Faster execution of arithmetic operations. 10
- 11. 80386 FEATURES • Manufactured using Intel’s complementary High performance Metal-oxide-semiconductor 3 process. • 8 general purpose registers of 32-bit . • 32-bit Address and Data Bus. • Supports 8-bit, 16-bit and 32-bit data. • Prefetch queue of 16B. • Very Large address space i.e VM of 64 TB and PM of 4GB. • Supports Segmentation and Paging. 11
- 12. 80386 FEATURES • 4 levels of protection. • Uses 3-stage pipelines. • Supports multitasking with protection. • On chip cache memory forTLB. • Pipelined instruction Execution. • Memory Management unit. • High speed numeric support via 80287 and 80387 coprocessor. • It can operate in real , protected and virtual mode. 12
- 13. 80386SX AND 80386DX DIFFERENCE • Both have the same architecture • SX is introduced later which featured a 16-bit external data bus, making it suitable for lower-cost PCs and simplifying circuit board design. • The original 80386, later renamed 80386DX, retained the full 32-bit external data bus, making it more suitable for workstations and demanding tasks. 13
- 14. 80386 INTERNAL ARCHITECTURE The Internal Architecture of 80386 is divided into 3 sections: 1.Central processing unit (CPU) • Execution unit (EU) and • Instruction unit (IU) 2.Memory management unit (MMU) • Segmentation unit • Paging unit. 3.Bus interface unit( BIU) 14
- 16. CENTRAL PROCESSING UNIT • Central processing unit is further divided into Execution unit and Instruction unit. • Execution unit has 8 General purpose and 8 Special purpose registers which are either used for handling data or calculating offset addresses. • The Instruction unit decodes the opcode bytes received from the 16-byte instruction code queue and arranges them in a 3- instruction decoded instruction queue. 16
- 17. CENTRAL PROCESSING UNIT • After decoding them, the data is pass to the control section for deriving the necessary control signals. • The barrel shifter increases the speed of all shift and rotate operations. • The multiply / divide logic implements the bit-shift- rotate algorithms to complete the operations in minimum time. • Even 32- bit multiplications can be executed within one microsecond by the multiply / divide logic. 17
- 18. MEMORY MANAGEMENT UNIT • The Memory management unit consists of a Segmentation unit and a Paging unit. • Segmentation unit allows the use of two address components: the segment and offset, for relocability and sharing of code and data. • Segmentation unit allows segments of size 4Gbytes at max. • Paging unit organizes the physical memory in terms of pages of 4 kbytes size each. 18
- 19. MEMORY ORGANIZATION AND SEGMENTATION • The physical memory of an 80386 system is organized as a sequence of 8-bit bytes. • Each byte is assigned a unique address that ranges from 0 to a maximum of 232-1 (4 Gigabytes). • The model of memory organization determined by systems-software designers. 19
- 20. DATA TYPES AND EXECUTION UNITS Bytes, words, and doublewords are the fundamental data types Integer: A signed binary numeric value contained in a 32-bit doubleword, 16-bit word, or 8-bit byte. All operations assume a 2's complement representation. • range of an 8-bit integer is -128 through +127 • 16-bit integers may range from -32,768 through +32,767 • 32-bit integers may range from -231 through +231 20
- 21. 21
- 22. DATA TYPES AND EXECUTION UNITS Ordinal: An unsigned binary numeric value contained in a 32-bit doubleword, 16-bit word, or 8-bit byte. All bits are considered in determining magnitude of the number. • - range of an 8-bit ordinal number is 0-255; • - 16 bits can represent values from 0 through 65,535; • - 32 bits can represent values from 0 through 232-1. Near Pointer: A 32-bit logical address. A near pointer is an offset within a segment. Far Pointer: A 48-bit logical address of two components: a 16-bit segment selector component and a 32-bit offset component. String: A contiguous sequence of bytes, words, or doublewords. A string may contain from zero bytes to 232-1 bytes (4 gigabytes). 22
- 23. DATA TYPES AND EXECUTION UNITS Bit field: A contiguous sequence of bits. A bit field may begin at any bit position of any byte and may contain up to 32 bits. Bit string: A contiguous sequence of bits. A bit string may begin at any bit position of any byte and may contain up to 232-1 bits. BCD: A byte (unpacked) representation of a decimal digit in the range 0 through 9. Unpacked decimal numbers are stored as unsigned byte quantities. One digit is stored in each byte. Packed BCD: A byte (packed) representation of two decimal digits, each in the range 0 through 9. One digit is stored in each half-byte. 23
- 24. 80386 REGISTERS The 80386 contain total 16 registers. These registers grouped as: 1. General 2. Segment 3. Status and Instruction 4. Control Registers 5. System Address Registers 6. Debug Registers 7. Test Registers 24
- 25. 80386 REGISTERS • The 80386 has eight 32-bit general purpose registers which may be used as either 8 bit, 16 bit or 32 bit registers. • A 32-bit register known as an extended register, is represented by the register name with prefix E. Example : A 32 bit register corresponding to AX is EAX • The general-purpose registers of 386 are EAX, EBX, ECX, EDX, EBP, ESP, ESI and EDI • BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can be used as independent 16 bit registers. • The 16-bit flag register is available along with 32 bit counterpart EFLAGS. 25
- 26. 26
- 27. 80386 REGISTERS •EAX, EBX, ECX, EDX: These 32-bit registers are used for general data storage and arithmetic/logical operations. •EBP (Base Pointer): Used to point to the current stack frame. •ESP (Stack Pointer): Points to the top of the stack. •ESI (Source Index): Used as an index register for string operations. •EDI (Destination Index): Used as an index register for string operations. 27
- 28. SEGMENT REGISTERS 28 • CS: The segment containing the currently executing sequence of instructions is known as the current code segment. • The 80386 fetches all instructions from this code segment, using as an offset the contents of the instruction pointer. • SS: Subroutine calls, parameters, and procedure activation records usually require to allocate memory as a stack. • All stack operations use the SS register to locate the stack. • DataRegisters: The DS, ES, FS, and GS registers allow the specification of four data segments.
- 29. FLAG REGISTER • The Flag register of 80386 is a 32 bit register. • Out of the 32 bits,Intel has reserved bits D18 to D31,D5 and D3 and set to 0 • While D1 is always set at 1. • Two extra new flags are added to the 80286 flag to derive the flag register of 80386. • They are VM and RF flags. • The 32-bit EFLAGS contains bits indicating the status of various activities. • The rightmost 16 bits of EFLAGS is the FLAGS register, nine of its 16 bits indicate the status and results of processing. • Many instructions change the status of these flags, other instructions test the flags to determine later action. 29
- 30. 30
- 31. FLAG BITS • SF (sign) Contains the resulting sign of an arithmetic operation (1=negative) • ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes) • AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized arithmetic. • PF (parity) indicates the number of 1 bits that result from an operation. 31 3/29/2025
- 32. FLAG BITS • CF (carry) Contains carry from leftmost bit following arithmetic, also contains last bit from a shift or rotate operation. 32 3/29/2025 Flag O D I T S Z A P C Bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- 33. VM BIT - VIRTUALMODE FLAG • If this flag is set to VM=1, the 80386 enters the virtual 8086 mode within the protection mode. • When VM bit is 0, 386 operates in protected mode • This is to be set only when the 80386 is in protected mode. • This bit can be set using IRET instruction or any task switch operation only in the protected mode. 33
- 34. RF-BIT RESUME FLAG • If RF=1, 386 ignores debug faults and does not take another exception so that an instruction can be restarted after a normal debug exception. • If RF=0, 386 takes another debug exception to service debug faults • This flag is used with the debug register breakpoints. • It is checked at the starting of every instruction cycle and if it is set=1, any debug fault is ignored during the instruction cycle. • The RF is automatically reset after successful execution of every instruction, except for IRET and POPF instructions • Also, it is not automatically cleared after the successful execution of JMP, CALL and INT instruction causing a task switch. 34
- 35. IF (INTR Enable Flag): The IF flag, when set, allows recognition of external interrupts signaled on the INTR pin. TF (Trap Enable Flag): When TF is set, the Intel386 DX generates an exception 1 trap after the next instruction is executed. When TF is reset, exception 1 traps occur only as a function of the breakpoint addresses loaded into debug registers DR0-DR3. OF (Overflow Flag): It is set if the operation resulted in a signed overflow. Signed overflow occurs when the operation resulted in carry/borrow into the sign bit (high-order bit) of the result. DF (Direction Flag): DF defines whether ESI and/or EDI registers post-decrement or post-increment during the string instructions. Post-decrement occurs if DF is set 35
- 36. INSTRUCTION The information encoded in an 80386 instruction includes a specification of: • Operation to be performed (Opcode). • Type of the operands to be manipulated, • Location of these operands. 36
- 37. INSTRUCTION FORMAT • Two-operand instructions of the 80386 permit operations of the following kinds: • Register-to-register • Register-to-memory • Memory-to-register • Immediate-to-register • Immediate-to-memory • Certain string instructions and stack manipulation instructions transfer data from memory to memory. • Push and pop stack operations allow transfer between memory operands and the memory-based stack. 37
- 38. LOGICAL INSTRUCTIONS The group of logical instructions includes: • The Boolean operation instructions • Bit test and modify instructions • Bit scan instructions • Rotate and shift instructions • Byte set on condition 38
- 39. BOOLEAN INSTRUCTIONS NOT (Not): Inverts the bits in the specified operand to form a one’s complement of the operand. Has no effect on flags. AND, OR, and XOR AND- is useful instruction for turning a particular bit off. (Turn to 0) OR- is useful instruction for setting a particular bit on.(Turn to 1) XOR- is useful instruction for clearing a register for toggling particular bit without changing other bits. 39
- 40. BIT TEST AND MODIFY INSTRUCTIONS This group of instructions operates on a single bit which can be in memory or in a general register. These instructions first assign the value of the selected bit to CF, the carry flag. 40
- 41. BIT SCAN INSTRUCTIONS • These instructions scan a word or doubleword for a one-bit and store the index of the first set bit into a register. • The bit string being scanned may be either in a register or in memory. • Affects ZF=1 if word is zero, otherwise clear ZF • BSF (Bit Scan Forward) scans from low-order to high- order (starting from bit index zero). • BSR (Bit Scan Reverse) scans from high-order to low- order (starting from bit index 15 of a word or index 31 of a doubleword). 41
- 42. SHIFT INSTRUCTIONS The bits in bytes, words, and double words may be shifted arithmetically or logically. CF always contains the value of the last bit shifted out of the destination operand. OF is set if the value of the high-order (sign) bit was changed by the operation. • SAL (Shift Arithmetic Left) • SHL (Shift Logical Left) • SHR (Shift Logical Right) • SAR (Shift Arithmetic Right) • ROL (Rotate Left) • ROR (Rotate Right) • RCL (Rotate Through Carry Left) 42
- 43. SHIFT ARITHMETIC LEFT SAL (Shift Arithmetic Left) shifts the destination byte, word, or double word operand left by one or by the number of bits specified in the count operand The processor shifts zeros in from the right (low-order) side of the operand as bits exit from the left (high-order) side. 43
- 45. SHIFT ARITHMETIC RIGHT The processor preserves the sign of the operand by shifting in 0 on the left (high-order) side if the value is positive or by shifting by 1 if the value is negative. 45
- 46. DOUBLE-SHIFT INSTRUCTION These instructions provide the basic operations needed to implement operations on long unaligned bit strings. The double shifts operate either on word or double word operands, as follows: SHLD (Shift Left Double):shifts bits of the R/M field to the left, while shifting high-order bits from the Reg field into the R/M field on the right. The result is stored back into the R/M operand. The Reg field is not modified. 46
- 47. SHIFT RIGHT DOUBLE SHRD (Shift Right Double) shifts bits of the R/M field to the right, while shifting low-order bits from the Reg field into the R/M field on the left. 47
- 48. ROTATE Rotate instructions allow bits in bytes, words, and double words to be rotated. • Bits rotated out of an operand are not lost as in a shift, but are "circled" back into the other "end" of the operand. • Rotates affect only the carry and overflow flags. • CF may act as an extension of the operand. • CF always contains the value of the last bit rotated out. • ROL (Rotate Left) rotates the byte, word, or double word destination operand left by one or by the number of bits specified in the count operand. 48
- 49. RCL AND RCR It treats CF as a high-order one-bit extension of the destination operand. 49
- 50. CONTROL TRANSFER INSTRUCTIONS • Unconditional Transfer Instructions: • JMP- JMP is a one-way transfer of execution; it does not save a return address on the stack. • CALL- activates an out-of-line procedure, saving on the stack, the address of the instruction following the CALL for later use by a RET (Return) instruction. • RET- terminates the execution of a procedure and transfers control through a back-link on the stack to the program that originally invoked the procedure. • IRET- returns control to an interrupted procedure. IRET differs from RET in that it also pops the flags from the stack into the flags register. 50
- 51. STRING AND CHARACTER TRANSLATION INSTRUCTIONS 1. A set of primitive string operations MOVS — Move String CMPS — Compare string SCAS — Scan string LODS — Load string STOS — Store string 2. Indirect, indexed addressing, with automatic incrementing or decrementing of the indexes. • Indexes: • ESI —Source index register EDI — Destination index register • Control flag: • DF — Direction flag • Control flag instructions: • CLD Clear direction flag instruction STD — Set direction flag instruction 3. Repeat prefixes • REP Repeat while ECX not zero • REPE/REPZ Repeat while equal or zero • REPNE/REPNZ Repeat while not equal or not zero 51
- 52. STRING INSTRUCTIONS • MOVS (Move String) moves the string element pointed to by ESI to the location pointed to by EDI. The MOVS instruction, when accompanied by the REP prefix, operates as a memory-to-memory block transfer. • CMPS (Compare Strings) subtracts the destination string element (at ES:EDI) from the source string element (at ESI) and updates the flags AF, SF, PF, CF and OF. If the string elements are equal, ZF=1; otherwise, ZF=0. CMPSB compares bytes, CMPSW compares words, and CMPSD compares doublewords. • SCAS (Scan String) subtracts the destination string element at ES:EDI from EAX, AX, or AL and updates the flags AF, SF, ZF,PF,CF and OF. If values are equal, ZF=1;otherwise,ZF=0. • LODS (Load String) places the source string element at ESI into EAX for doubleword strings, into AX for word strings, or into AL for byte strings. LODS increments or decrements ESI according to DF. • STOS (Store String) places the source string element from EAX, AX, or AL into the string at ES:DSI. STOS increments or decrements EDI according to DF. 52