Labsheet1 ec303 student
- 1. 1 PRACTICAL WORK ASSESSMENT EC303 COMPUTER ARCHITECTURE & ORGANIZATION PROGRAMME : PRACTICAL WORK NUMBER : 1 DATE : LECTURER’S NAME : M rizal TITLE : Introduction to Altera Quartus II and Digital Circuit 1. PRACTICAL WORK ASSESSMENT - 100% i. Practical Skill Assessment - 70% ii. Lab Report Assessment - 30% 2. GENERIC SKILL ASSESSMENT - None 1. PRACTICAL WORK ASSESSMENT NO. A. PRACTICAL SKILL ASSESSMENT (CLO1,PLO1,LD1) ATTAINMENT B. LAB REPORT ASSESSMENT ATTAINMENT 1. Student able to identify, choose and use apparatus/equipment’s correctly Report Format and Organization Results Analysis Question/ Discussion Conclusion 2. Student able to set and calibrate apparatus/equipment correctly 3. Student able to construct circuit correctly 4. Student able to measure equipments correctly 5. Student able to take the reading measurement accurately 6. Student able to follow instruction and procedure correctly 7. Student able to complete task given within time frame PERCENTAGE = (70%) PERCENTAGE = (30%) 2. GENERIC SKILL ASSESSMENT (GSA) (PLO9, LD9) ATTAINMENT TOTAL (100%) NONE Remark: LD1 Knowledge, LD2 Practical Skill, LD3 Communication Skill, LD4 Critical Thinking and Problem Solving Skills LD5 Sosial Skills and Responsibilities, LD6 Continuous Learning and Information Management Skills, LD7 Management and Entrepreneurial Skills, LD8 Professionalism, Ethics and Moral, LD9 Leadership and Teamwork Skills NO. REG. NO. NAME PRACTICAL WORK ASSESSMENT TOTAL (A+B=100%) GSA (100%) A. PRACTICAL SKILL ASSESSMENT (70%) B. LAB REPORT ASSESSMENT (30%)
- 2. 2 PRACTICAL/LAB SHEET EC303 COMPUTER ARCHITECTURE & ORGANIZATION. PRACTICAL LABORATORY NUMBER : 1 TITLE : INTRODUCTION TO ALTERA QUARTUS II AND DIGITAL CIRCUIT LEARNING OUTCOME : 1. Construct arithmetic logic operation and interfacing circuit into the digital circuit using logic gates and flip-flop (P4). APPARATUS / EQUIPMENT : 1. Personal computer (Pentium III (866 MHz or faster)) 2. Altera Quartus II,Version 8 INTRODUCTION / THEORY : The Altera Quartus II design software provides a complete, multiplatform design environment that easily adapts to your specific design needs. It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes solutions for all phases of FPGA and CPLD design (Figure 1). In addition, the Quartus II software allows user to use the Quartus II graphical user interface and command-line interface for each phase of the design flow. User can use one of these interfaces for the entire flow, or different options at different phases. ACTION NAME & DESIGNATION SIGNATURE DATE Prepared by: Approved by:
- 3. 3 Figure 1: Quartus II design flow. WORKING PROCEDURES : Experiment 1.1 : Draw a 2 input AND gate , and show the simulation 1. Run the Altera Quartus II program and create a new project. 2. Create a directory and name of the project as test1. 3. Choose the right device. 4. Make a new schematic file by clicking File > New > Block diagram/Schematic file 5. Draw the AND gate by insert the symbol. Select the symbol tool. 6. Add a symbol by type the name of component. (and2 = 2 input for AND gate; input = input ; output=output) Figure 2: And gate. VCC pin_name INPUT VCC pin_name2 INPUT pin_name3OUTPUT AND2 inst
- 4. 4 7. Rename the input of the AND gate with A and B, and the output as C. Save all the project.(step 1 until 7 is for drawing a circuit) 8. Compile the project by clicking a compilation button. 9. Click on the test1.bdf window and click Processing > Analyze Current File 10. Click Start Analysis & Synthesis button. (step 8 until 10 is for compilation,analysis and synthesis the circuit) 11. Insert a title and get a RTL viewer by click Tool>Netlist Viewers >RTL Viewer 12. Create a new file of waveform file. Click File> New > Vector Waveform File 13. Right click on the waveform1.vwf window and click insert > insert node or bus > Insert node or bus. 14. Click Node Finder > List. Select all the nodes found. Figure 3: Node finder 15. Setup the value of clock for input A and B by clicking the overwrite clock icon. Click the waveform, then click on the overwrite clock icon. For A, the time period is set to 10ns with 50% duty cycle. For B, time period is change to 20ns.
- 5. 5 Figure 4 : Clock setting. 16. Save all the project. 17. Click processing > simulator tool. Select simulation mode to functional. Click Generate Functional Simulation Netlist. Click start. 18. Click open on the simulator tool window to see the simulation input file. 19. Click report on the simulator too; window to see simulation report. 20. Discuss all the result. Experiment 1.2 : Combinational Logic Circuit With the same steps, draw the combinational logic circuit by using Altera Quartus II, and show the simulation waveform with the period value of A =10ns, B=20ns and C=40 ns with 50% duty cycle. Figure 5: Combinational logic circuit.
- 6. 6 RESULTS : Experiment 1.1 Result Schematic circuit (print screen) RTL Viewer (Print screen) Output Waveform (Sketch) and truth table A B C 0 0 0 1 1 0 1 1 Output Waveform (print screen)
- 7. 7 RESULTS : Experiment 1.2 Result Schematic circuit (print screen) RTL Viewer (Print screen) Output Waveform (Sketch) and truth table A B C J 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
- 8. 8 Result Output Waveform (print screen) ANALYSIS : 1. Altera Quartus ii application and logic circuit. 2. Boolean equation 3. Related output data and theory
- 9. 9 QUESTION / DISCUSSIONS : 1. What the effect to the output waveform if the duty cycle below 50 percent, 50 percent and over 50 percent? CONCLUSION :