Static and Dynamic Read/Write memories
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This document summarizes different types of random access memory (RAM), including static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and double data rate SDRAM (DDR SDRAM). It describes the basic operation and characteristics of each type of RAM, such as the use of transistors and capacitors, refresh requirements, packaging, and timing. Key details covered include the differences between SRAM and DRAM, DRAM refresh requirements, DRAM and SDRAM timing diagrams, and how DDR SDRAM transfers data on both clock edges.
Static and Dynamic Read/Write memories
- 1. EET 3350 Digital Systems Design Textbook: John Wakerly Chapter 9: 9.2-9.4 Static read/write memories Dynamic read/write memories 1
- 2. Random Access Memory (RAM) • For most applications, main memory is a collection of RAM chips – These are volatile, switch the machine off and the contents in this form of memory are lost • There are three basic types of RAM – Dynamic RAM (DRAM) – Static RAM (SRAM) – Non-volatile RAM (NVRAM = RAM + battery) 2
- 3. Random Access Memory (RAM) • Read/Write Memory – Access time is independent of bit’s location – Volatile: lose their content when power is removed • Static RAM (SRAM) – Memory behaves like Latches or Flip-Flops – Data remains stored as long as power applied • Dynamic RAM (DRAM) – Charged or discharged capacitor – Memory lasts only for a few milliseconds – Data must be refreshed periodically by reading and rewriting 3
- 4. Static RAM (SRAM) • Each bit (or the cell that stores the bit) is represented by a Flip-Flop (or, more accurately, a Latch) • The cell's output is maintained until either altered to a new value or the power is turned off • When compared to Dynamic RAM (DRAM) – More complex – More expensive 4
- 5. Static RAM (SRAM) • Since storage cells in SRAM are made of Latches they do not require refreshing in order to keep their data • The problem is that each cell requires at least six transistors to build and the cell holds only one bit data • The capacity of SRAM is far below DRAM • SRAM is widely used for cache memory 5
- 6. SRAM • Basic structure and logic symbol for a 2n x b SRAM 6
- 7. SRAM Operation • Individual bits are D latches, not edge-triggered D flip-flops – Fewer transistors per cell • Implications for write operations: – Address must be stable before writing cell – Data must be stable before ending a write ≡ 7
- 8. SRAM Operation • SEL and WR asserted → IN data stored in D-latch (Write) • SEL only asserted → D-latch output enabled (Read) • SEL not asserted → No operation ≡ 8
- 9. SRAM Array • Internal structure of an 8 x 4 static RAM • As with ROM, the decoder selects a particular row • Outputs are tri-state buffered and controlled by an enable input 9
- 10. 10
- 11. SRAM Read Timing • Similar to ROM read timing – tAA access time from address – tACS access time from chip select – tOE/tOZ output-enable/disable time – tOH output-hold time 11
- 12. SRAM Write Timing – tAS (address setup time before write): all address inputs must be stable at this time before both CS and WE are asserted – tAH (address hold time after write): all address inputs must be stable until this time after CS or WE are negated – tCSW (chip-select setup before end of write): CS must be asserted at least this long before the end of the write cycle in order to select a cell – tWP (write-pulse width): WE must be asserted at least this long to reliably latch data into the selected cell – tDS (data setup time before end of write): all data inputs must be stable at this time before the write cycle ends – tDH (data hold time after end of write) : all data inputs must be stable until this time after the write cycle ends 12
- 13. SRAM Write Timing – tAS/tAH address setup/hold time before/after write – tCSW chip-select setup before end of write – tWP write-pulse width – tDS/tDH data setup/hold time before/after write 13
- 14. SRAM Write Timing • Address must be stable before and after write-enable is asserted • Data is latched on trailing edge of (WE & CS) 14
- 15. Bidirectional Data In and Out Pins • Use the same data pins for reads and writes – Especially common on wide devices – Makes sense when used with microprocessor buses (also bidirectional) • Output buffer is disabled whenever WE_L is asserted, even if OE_L is asserted 15
- 16. SRAM Devices • Similar to ROM packages 28-pin DIPs 32-pin DIPs 16
- 17. Synchronous SRAMs • Use latch-type SRAM cells internally but has a clocked interface for control, address & data • Put registers in front of address (AREG) and control (CREG) and data input (INREG). • Depending on whether the device has “pipelined” or “flow-through” outputs register OUTREG is either provided or not provided • e.g., Pentium cache RAMs 17
- 18. Dynamic RAM (DRAM) • Commonly used in main memory. – A logical '1' is used to charge a capacitor, and this holds the device in its switched on (or positive state). – The capacitor will lose it's charge with time so the capacitor has to constantly refreshed to keep the switched on state. • If a logical '0' is to be stored the capacitor is discharged. 18
- 19. Dynamic RAM (DRAM) • The use of a capacitor as a means to store data • Cuts down the number of transistors needed to build cell • However, it requires constant refreshing due to leakage • Advantage: – High density (capacity) – Cheaper cost per bit – Lower power consumption per bit • Disadvantage: – Must be refreshed periodically – While it is being refreshed, the data can not be accessed 19
- 20. DRAM • DRAM: Dynamic RAM – Uses MOS transistor and capacitor to store bit – More compact than SRAM – “Refresh” required due to capacitor leak – Typical refresh rate 15.625 microsecond – Slower to access than SRAM bit line word line 1-bit DRAM cell 20
- 21. DRAM Charge Leakage • Typical devices require each cell to be refreshed once every 4 to 64 mS • During “suspended” operation, notebook computers use power mainly for DRAM refresh 21
- 22. DRAM Packaging • Packaging in DRAM – To reduce the number of pins needed for address, multiplex / demultiplexing is used – Method is to split the address into half and send in each half of the address through the same pins requires fewer pins – Internally, DRAM is divided into a square of rows and columns, the first half of the address is called the row and the second half is called the column • Organization of DRAM – Most DRAM are x 1 and x 4 22
- 23. DRAM-Chip Internal Organization 64K x 1 DRAM multiplex 16-bit address as 8-bit row selector and 8-bit column selector 23
- 24. DRAM Timing • No clock • DRAM operations are initiated and completed on both the rising and falling edges of RAS_L and CAS_L • The timing for RAS-only refresh cycle is shown on next slide • This cycle is used to refresh a row of memory without actually reading or writing any data at the external pins of the DRAM chip • The cycle begins when a row address is applied to the multiplexed address inputs & RAS_L is asserted 24
- 25. DRAM refresh timing • The DRAM stores the row-address in an internal row-address register on the falling edge of RAS_L and reads the selected row of memory array into an on-chip row latch • When RAS_L is negated the contents of the row are written back from the row latch • To refresh the entire 64k × 1 DRAM, one must ensure 256 such cycles 25
- 26. DRAM read timing • Begins like a refresh cycle, selected row is read into the row latch • Next a column address is applied to the multiplexed address inputs & is stored in an on-chip column address register on the falling edge of CAS_L • It selects one bit of the just read row which is made available on the DRAM’s DOUT pin which is enabled as long as CAS_L is asserted 26
- 27. DRAM write timing • Begins like a refresh or read cycle, WE_L must be asserted before CAS_L is asserted, this disables DOUT for the rest of the cycle, even though CAS_L will be asserted subsequently • Once the selected row is read into the row latch, WE_L forces the input bit on DIN to be merged into the row latch in the bit position selected by the column address 27
- 28. RAS/CAS Operation • Row Address Strobe, Column Address Strobe – n address bits are provided in two steps using n/2 pins, referenced to the falling edges of RAS_L and CAS_L – Traditional method of DRAM operation for 20 years – Now being supplemented by synchronous, clocked interfaces in SDRAM (synchronous DRAM) 28
- 29. SDRAM Timing (Read) • PRE precharge (bit line) • ACTV row-address strobe and activate bank • READ column address and read command 29
- 30. SDRAM Timing (Write) • PRE precharge (bit line) • ACTV row-address strobe and activate bank • WRITE column address and write command 30
- 31. Types of RAM • Synchronous DRAM (SDRAM) – SDRAM has a synchronous interface – SDRAM replaced DRAM, FPM, and EDO – SDRAM is an improvement because it synchronizes data transfer between the CPU and memory. – It waits for a clock pulse before transferring data and is therefore synchronous with the computer system bus and processor. – This greatly improves performance over asynchronous DRAM. 31
- 32. Types of RAM • Double Data Rate SDRAM (DDR SDRAM) – DDR SDRAM is a newer form of SDRAM that can theoretically improve memory clock speed to 200 megahertz (MHz) or more. – Sends and receives data twice as often as common SDRAM. – This is achieved by transferring data on both the rising edge and the falling edge of a clock cycle. – DDR memory is being phased out and replaced by DDR2 memory. – DDR memory modules usually take the form of 184-pin DIMMs. 32