1
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 1
ELEC 5200-001/6200-001
Computer Architecture and Design
Fall 2014
History of Computers (Chapter 1)
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
vagrawal@eng.auburn.edu
2
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 2
Historic Events
1623, 1642: Wilhelm Schickard (1592-1635) and Blaise
Pascal (1623-1662) built mechanical counters with carry.
1823-34: Charles Babbage designed a difference engine.
http://www.youtube.com/watch?v=0anIyVGeWOI&feature=
related
1941: Conrad Zuse (1910-1995) built Z3, the first working
programmable computer, built in Germany.
Z3
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 3
Conrad Zuse
Z1 (1938)
Z2 (1939)
Z3 (1941)
∙
∙
∙
4
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 4
Historic Events
1942: Vincent Atanasoff (professor) and Clifford Barry
(graduate assistant) built the first electronic computer (ABC)
at Iowa State College.
1943-44: John Mauchly (professor) and J. Presper Eckert
(graduate student) built ENIAC at U. Pennsylvania, 1623.
1944: Howard Aiken used “separate data and program
memories” in MARK I – IV computers – Harvard
Architecture.
1945-52: John von Neumann proposed a “stored program
computer” EDVAC (Electronic Discrete Variable Automatic
Computer) – Von Neumann Architecture – use the same
memory for program and data.
5
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 5
The Atanasoff Story
The First Electronic Computer, the
Atanasoff Story, by Alice R. Burks and
Arthur W. Burks, Ann Arbor, Michigan:
The University of Michigan Press, 1991.
The Man Who Invented the Computer:
The Biography of John Atanasoff, Digital
Pioneer, by Jane Smiley, 256 pages,
Doubleday, $25.95.
National Medal of Technology
1990
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 6
John Vincent Atanasoff (1903–1995)
7
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 7
Most Influential Document
“Preliminary Discussion of the Logical
Design of an Electronic Computing
Instrument,” 1946 report by A. W. Burks,
H. H. Holdstine and J. von Neumann.
Appears in Papers of John von Neumann,
W. Aspray and A. Burks (editors), MIT
Press, Cambridge, Mass., 1987, pp. 97-
146.
8
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 8
History Continues
1946-52: Von Neumann built the IAS computer
at the Institute of Advanced Studies, Princeton –
A prototype for most future computers.
1947-50: Eckert-Mauchly Computer Corp. built
UNIVAC I (Universal Automatic Computer), used
in the 1950 census.
1949: Maurice Wilkes built EDSAC (Electronic
Delay Storage Automatic Calculator), the first
stored-program computer.
9
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 9
First General-Purpose Computer
Electronic Numerical
Integrator and Calculator
(ENIAC) built in World War II
was the first general
purpose computer
– Used for computing artillery
firing tables
– 80 feet long, 8.5 feet high and
several feet wide
– Twenty 10 digit registers, each
2 feet long
– Used 18,000 vacuum tubes
– 5,000 additions/second
– Weight: 30 tons
– Power consumption: 140kW
© 2004 Morgan Kaufman Publishers
10
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 10
Univac: Election, Nov. 4, 1952
Harold Sweeney, operator
J. Presper Eckert, co-inventor
Walter Cronkite, CBS
USA TODAY, Oct 27, 2004, p. B.3
Candidate
Electoral votes
Univac prediction Actual count
Eisenhower 438 442
Stevenson 93 89
11
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 11
First-Generation Computers
Late 1940s and 1950s
Stored-program computers
Programmed in assembly language
Used magnetic devices and earlier forms
of memories
Examples: IAS, ENIAC, EDVAC, UNIVAC,
Mark I, IBM 701
12
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 12
The Organization of IAS Computer
Accumulator (AC) Multiplier/Quotient (MQ)
Arithmetic Logic Circuits
Memory Buffer Register (MBR)
Instr. Buffer (IBR) Program Counter (PC)
Instruction Register (IR) Memory Address Reg. (MAR)
Main
Memory
(M)
212 x 40 bit
words
Input/
Output
Equipment
Control
Circuit
Control
Signals
DATAPATH
CONTROL UNIT
13
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 13
IAS Computer Machine Language
40-bit word, two machine instructions per word.
Left instruction Right instruction
bit 0 7 8 19 20 27 28 39
8-bit opcode 12-bit memory address
(operand)
Ref: J. P. Hayes, Computer Architecture and Organization, New York:
McGraw-Hill, 1978.
14
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 14
IAS Data Transfer Instructions (7)
Instruction Opcode Description
LOAD MQ 00001010 AC ← MQ
LOAD MQ, M(X) 00001001 MQ ← M(X)
STOR M(X) 00100001 M(X) ← AC
LOAD M(X) 00000001 AC ← M(X)
LOAD – M(X) 00000010 AC ← – M(X)
LOAD |M(X)| 00000011 AC ← |M(X)|
LOAD – |M(X)| 00000100 AC ← – |M(X)|
Ref. W. Stallings, Computer Organization & Architecture, Sixth Edition,
Prentice-Hall, 2003, page 23.
15
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 15
IAS Unconditional Branch
Instructions (2)
Instruction Opcode Description
JUMP M(X,0:19) 00001101 next instruction
M(X,0:19)
JUMP M(X,20:39) 00001110 next instruction
M(X,20:39)
16
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 16
IAS Conditional Branch
Instructions (2)
Instruction Opcode Description
JUMP +M(X,0:19) 00001111 IF AC ≥ 0,
then next
instruction
M(X,0:19)
JUMP +M(X,20:39) 00010000 IF AC ≥ 0,
then next
instruction
M(X,20:39)
17
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 17
IAS Arithmetic Instructions (8)
Instruction Opcode Description
ADD M(X) 00000101 AC ← AC + M(X)
ADD |M(X)| 00000111 AC ← AC + |M(X)|
SUB M(X) 00000110 AC ← AC ─ M(X)
SUB |M(X)| 00001000 AC ← AC ─ |M(X)|
MUL M(X) 00001011 AC, MQ ← MQ×M(X)
DIV M(X) 00001100 MQ, AC ← MQ/M(X)
LSH 00010100 AC ← AC x 2
RSH 00010101 AC ← AC / 2
18
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 18
IAS Address Modify Instructions (2)
Instruction Opcode Description
STOR M(X,8:19) 00010010 M(X,8:19) ←
AC(28:39)
STOR M(X,28:39) 00010011 M(X,28:39) ←
AC(28:39)
19
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 19
How IAS Computer Adds Two
Numbers
Suppose the numbers are stored in
memory locations 100 and 101, and
The sum is to be saved in memory
location 102
Instruction Opcode Description
LOAD M(100) 00000001 AC ← M(100)
ADD M(101) 00000101 AC ← AC + M(101)
STOR M(102) 00100001 M(102) ← AC
20
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 20
IAS Computer Machine Code
00000001 000001100100 00000101 000001100101
00100001 000001100110 00000000 000000000000
Load 100 Add 101
Stor 102 Stop
21
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 21
Save Program in Memory
First program word
Second program word
Word 100
Word 101
Word 102
Address
Memory
Load program
Counter, PC
Address 0
Address max
22
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 22
Executing the Program
Accumulator (AC) Multiplier/Quotient (MQ)
Arithmetic Logic Circuits
Memory Buffer Register (MBR)
Program Counter (PC) Main
Memory
(M)
212 x 40 bit
words
Input/
Output
Equipment
Control
Circuit
Control
Signals
DATAPATH
CONTROL UNIT
Instr. Buffer (IBR)
Instruction Register (IR) Memory Address Reg. (MAR)
23
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 23
IAS Instruction Cycles
Store machine code in contiguous words of memory.
Place starting address in program counter (PC).
Start program: MAR ← PC
Read memory: IBR ← MBR ← M(MAR), fetch
Place left instruction (Load) in IR and operand (address)
100 in MAR, decode
Read memory: AC ← M(100), execute
Place right instruction (Add) in IR and operand (address)
101 in MAR, decode
Read memory and add: AC ← AC + M(101), execute
PC ← PC + 1
24
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 24
IAS Instruction Cycles (Cont.)
MAR ← PC
Read memory: IBR ← MBR ← M(MAR), fetch
Place left instruction (Stor) in IR and operand
(address) 102 in MAR, decode
MBR ← AC, execute
Write memory
Place right instruction (Stop) in IR and operand
000 in MAR, decode
Stop, execute
25
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 25
Hardware Contains
Data storage devices
Memory
Registers
Instruction decoding and execution
devices
Execution unit (arithmetic logic unit, ALU)
Data transfer buses
Control unit
26
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 26
Registers in IAS
Register
Size
(bits)
Function
Program counter (PC) 12 Holds mem. address of next instruction
Accumulator (AC) 40 Temporary data storage
Multiplier quotient (MQ) 40 Temporary data storage
Memory buffer (MBR) 40 Memory read / write data
Instruction buffer (IBR) 20 Holds right instr. (bits 20-39)
Instruction register (IR) 8 Holds opcode part of instruction
Memory address (MAR) 12 Holds mem. address part of instruction
27
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 27
Register Transfer
Transfer data synchronously with clock
Register to register
Register to register through ALU logic
Registers to register through memory (write)
Register to register through memory (read)
Data transfer through communication bus
Source register writes on bus
Destination register reads from bus
Control circuit provides read / write signals for bus
and memory
28
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 28
Communication Bus
A device writing
on bus
outputs inputs
A device neither
writing on nor
reading from bus
outputs inputs
1
0
0
0
0
1
outputs inputs
A device reading
from bus
Control signals
Bus
Control
circuit
Opcode
Control
signals
29
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 29
Control Circuit – Finite State Machine
Start
Fetch Instruction
Read
memory
Execute
Decode
left
instruction
Decode
right
instruction
Execute
MAR ← PC
PC ← PC+1
30
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 30
Von Neumann Bottleneck
Von Neumann architecture uses the same
memory for instructions (program) and
data.
The time spent in memory accesses can
limit the performance. This phenomenon is
referred to as von Neumann bottleneck.
To avoid the bottleneck, later architectures
restrict most operands to registers
(temporary storage in processor).
Ref.: D. E. Comer, Essentials of Computer Architecture, Upper Saddle
River, NJ: Pearson Prentice-Hall, 2005, p. 87.
31
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 31
John von Neumann (1903-1957)
32
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 32
Second Generation Computers
1955 to 1964
Transistor replaced vacuum tubes
Magnetic core memories
Floating-point arithmetic
High-level languages used: ALGOL,
COBOL and FORTRAN
System software: compilers, subroutine
libraries, batch processing
Example: IBM 7094
33
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 33
Third Generation Computers
Beyond 1965
Integrated circuit (IC) technology
Semiconductor memories
Memory hierarchy, virtual memories and caches
Time-sharing
Parallel processing and pipelining
Microprogramming
Examples: IBM 360 and 370, CYBER, ILLIAC IV,
DEC PDP and VAX, Amdahl 470
34
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 34
C Programming Language and
UNIX Operating System
1972 Now
35
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 35
Theory of Computing
Alan Turing (1912-1954) gave a model of
computing in 1936 – Turing Machine.
Original paper: A. M. Turing, “On
Computable Numbers with an Application
to the Entscheidungsproblem*,” Proc.
Royal Math. Soc., ser. 2, vol. 42, pp. 230-
265, 1936.
Recent book: David Leavitt, The Man
Who Knew Too Much: Alan Turing and
the Invention of the Computer (Great
Discoveries), W. W. Norton & Co., 2005.
* The question of decidability, posed by
mathematician Hilbert.
36
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 36
Turing Machine
Processor
P
Read-write head
Infinite memory tape (data)
ti
Machine instruction: sh ti oj sk
Present state of processor
Symbol on tape
Operation
Next state of processor
37
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 37
Turing Machine
Four operations:
– oj = tj, replace present symbol ti by tj
– oj = R, move head one position to right
– oj = L, move head one position to left
– oj = H, halt the computation
Universal Turing Machine: small instruction set,
#symbols × #states < 30; can perform any
possible (computable) computation.
Computable means that Turing machine halts in
finite number of steps.
Real computers have finite memory – they find
certain problems intractable.
Ref: J. P. Hayes, Computer Architecture and Organization, New York:
McGraw-Hill, 1978.
Example
Start with a blank tape and create a
pattern 0b1b0b1b . . .
Define symbols: b (blank), 0, 1
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 38
Present state Symbol on tape Operation Next state
S0 (begin) blank Write 0 and move right S1
S1 blank Move right S2
S2 blank Write 1 and move right S3
S3 blank Move right S0
http://en.wikipedia.org/wiki/Turing_machine_examples
Turing Test
Can a computer think? (Turing, 1950).
http://en.wikipedia.org/wiki/Computing_Machinery_and_Intelligence
#cite_note-1
A. P. Saygin, I. Cicekli and V. Akman, “Turing Test: 50 Years Later,”
Minds and Machines, vol. 10, no. 4, pp. 463-518, 2000.
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 39
Watson vs. humans:
http://www.engadget.com/
2011/01/13/ibms-watson-
supercomputer-destroys-
all-humans-in-jeopardy-
pract/
Turing Test in 2014
June 8, 2014, The 65 year-old Turing Test was passed
for the very first time by computer program Eugene
Goostman during Turing Test 2014 held at the renowned
Royal Society in London on Saturday.
'Eugene' simulates a 13 year old boy and was developed
in Saint Petersburg, Russia. The development team
includes Vladimir Veselov and Eugene Demchenko.
A program wins the Turing Test if it is mistaken for a
human more than 30% of the time.
http://www.reading.ac.uk/news-and-events/releases/PR583836.aspx
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 40
Movie: The Imitation Game
About English mathematician and logician, Alan
Turing, helps crack the Enigma code during World
War II.
Screenplay: Graham Moore
Cast: Benedict Cumberbatch, Keira Knightley,
Matthew Goode
Trailer:
http://www.imdb.com/title/tt2084970/?ref_=nv_sr_1
Release date: November 2014
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 41
42
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 42
Incompleteness Theorem
In 1931, the Czech-born mathematician
Kurt Gödel (1906-1978) demonstrated
that within any given branch of
mathematics, there would always be
some propositions that couldn't be
proven either true or false using the rules
and axioms.
Gödel's Theorem has been used to
argue that a computer can never be as
smart as a human being because the
extent of its knowledge is limited by a
fixed set of axioms, whereas people can
discover unexpected truths.
See http://www.miskatonic.org/godel.html
and other websites.
43
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 43
The Barber Paradox
By Linda Shaver
(An Example of Undecidability)
In a particular town, there’s a particular barbershop
with a peculiar sign in the window that reads:
“This barber shaves all and only those men of
the town who do not shave themselves.”
Question: According to the sign in the window, does
the barber shave himself?
44
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 44
The Now Generation
Personal computers
Laptops and Palmtops
Networking and wireless
SOC and MEMS technology
And the future!
Biological computing
Molecular computing
Nanotechnology
Optical computing
Quantum computing
See articles listed on the next slide and available at E7700:
Advanced VLSI Design course site,
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12/
course.html
45
Useful Reading
R. I. Bahar, D. Hammerstrom, J. Harlow, W. H. Joyner Jr., C. Lau, D. Marculescu, A. Orailoglu and M.
Pedram, “Architectures for Silicon Nanoelectronics and Beyond,” Computer, vol. 40, no. 1, pp. 25-33,
January 2007.
T. Munakata, “Beyond Silicon: New Computing Paradigms, “Comm. ACM, vol. 50, no. 9, pp. 30-34, Sept.
2007.
W. Robinett, G. S. Snider, P. J. Kuekes and S. Williams, “Computing with a Trillion Crummy Components,”
Comm. ACM, vol. 50, no. 9, pp. 35-39, Sept. 2007.
J. Kong, “Computation with Carbon Nanotube Devices,” Comm. ACM, vol. 50, no. 9, pp. 40-42, Sept. 2007.
R. Stadler, “Molecular, Chemical and Organic Computing,” Comm. ACM, vol. 50, no. 9, pp. 43-45, Sept.
2007.
M. T. Bohr, R. S. Chau, T. Ghani and K. Mistry, "The High-k Solution," IEEE Spectrum, vol. 44, no. 10, pp.
29-35, October 2007.
J. H. Reif and T. H. Labean, “Autonomous Programmable Biomolecular Devices using Self-Assembled DNA
Nanostructures,” Comm. ACM, vol. 50, no. 9, pp. 46-53, Sept. 2007.
D. Bacon and D. Leung, “Toward a World with Quantum Computers,” Comm. ACM, vol. 50, no. 9, pp. 55-
59, Sept. 2007.
H. Abdeldayem and D. A. Frazier, “Optical Computing: Need and Challenge,” Comm. ACM, vol. 50, no. 9,
pp. 60-62, Sept. 2007.
D. W. M. Marr and T. Munakata, “Micro/Nanofluidic Computing,” Comm. ACM, vol. 50, no. 9, pp. 64-68,
Sept. 2007.
M. Aono, M. Hara and K. Aihara, “Amoeba-Based Neurocomputing with Chaotic Dynamics,” Comm. ACM,
vol. 50, no. 9, pp. 69-72, Sept. 2007.
C. C. Lo and J. J. L. Morton, “Silicon’s Second Act, Can this semiconductor workhorse take computing tnto
the quantum era?” IEEE Spectrum, vol. 51, no. 8, pp. 36-43, Aug. 2014.
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 45
A Question
Which is the most popular programming
language today?
A:
http://spectrum.ieee.org/static/interactive-
the-top-programming-languages
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 46
Top 10 Prog. Languages
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 47
W: Web
M: Mobile
D: Desktop/Enterprise
E: Embedded
Scores are normalized
so that the top-ranked
language’s score is
set to 100.
Source:
IEEE Spectrum
July 2014
48
Next: The MIPS ISA
MIPS (Microprocessor without Interlocked
Pipeline Stages) is a reduced instruction
set architecture.
Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2

More Related Content

PPTX
PPT
Week1 HARDWARE
PPT
computer system organization basics
PPTX
Computer_Architecture&O_ECEG_3163_02_computer_evolution_performance.pptx
PDF
Energy Efficient Computing - 26mar13
DOCX
PPT
Computer basic and cpu
PDF
Pipe line
Week1 HARDWARE
computer system organization basics
Computer_Architecture&O_ECEG_3163_02_computer_evolution_performance.pptx
Energy Efficient Computing - 26mar13
Computer basic and cpu
Pipe line

Similar to lec2_history about von Neumann architecture (20)

PDF
Computer Organization & Architecture
PPTX
Introduction to computers
PPT
Computers Ch1
PDF
Software Based calculations of Electrical Machine Design
PDF
Introduction to information technology
PPT
History Of Computers
PDF
Computing for Engineering - Lecture 01
PPTX
Introduction to computer by karan shah
PPTX
History of Computers
PDF
PPTX
Computer basics Intro
PDF
Technology In Action Introductory 14th Edition Evans Test Bank
PDF
Technology In Action Introductory 14th Edition Evans Test Bank
PDF
DRDO CEPTAM Technician A COPA Computer MCQ Book
PDF
DRDO CEPTAM Technician A COPA Computer MCQ Book
PPT
History of Computer (Evolution in Computern).ppt
PPT
8086 cpu 1
PPT
Lecture 1
PDF
Energy Efficiant Computing in the 21c
Computer Organization & Architecture
Introduction to computers
Computers Ch1
Software Based calculations of Electrical Machine Design
Introduction to information technology
History Of Computers
Computing for Engineering - Lecture 01
Introduction to computer by karan shah
History of Computers
Computer basics Intro
Technology In Action Introductory 14th Edition Evans Test Bank
Technology In Action Introductory 14th Edition Evans Test Bank
DRDO CEPTAM Technician A COPA Computer MCQ Book
DRDO CEPTAM Technician A COPA Computer MCQ Book
History of Computer (Evolution in Computern).ppt
8086 cpu 1
Lecture 1
Energy Efficiant Computing in the 21c
Ad

Recently uploaded (20)

DOCX
internal and external hardware in Orthopedic Center
PDF
Melt Flow Index Tester from Perfect Group India
PDF
script scriptscriptscriptscriptscriptscript
PPTX
Presentation (1).pptx gjkbhhjk hjjgtihkk
PPTX
SAI-CAO-24CSEN2021-PPT-UNIT-------1.pptx
PPTX
Chapter no 8 output devices dpart 2.pptx
PPTX
Presentation societal project DEEPIKA T.pptx
DOCX
Copy-OT LIST 12.8.25.docxjdjfufufufufuuffuf
PPTX
RTS MASTER DECK_Household Convergence Scorecards. Use this file copy.pptx
PPTX
ELETRONIC-PRODUCTS-ASSEMBLY-AND-SERVICING-NC-II-WEEK-1-Copy.pptx
PDF
20A LG INR18650HJ2 3.6V 2900mAh Battery cells for Power Tools Vacuum Cleaner
PPTX
Unit-1.pptxgeyeuueueu7r7r7r77r7r7r7uriruru
PDF
Printing Presentation to show beginners.
PPTX
Computer Hardware - Technology and Livelihood Education
PPT
The process of making an electrical connection by melting low-temperature met...
PDF
SAHIL PROdhdjejss yo yo pdf TOCOL PPT.pdf
PPT
COA______________₹₹_₹₹33₹₹₹33₹₹₹3UNIT1V8.ppt
PPTX
Clauses_Part1.hshshpjzjxnznxnxnndndndndndndndnndptx
PDF
PakistanCoinageAct-906.pdfdbnsshsjjsbsbb
PDF
GENERATOR AND IMPROVED COIL THEREFOR HAVINGELECTRODYNAMIC PROPERTIES
internal and external hardware in Orthopedic Center
Melt Flow Index Tester from Perfect Group India
script scriptscriptscriptscriptscriptscript
Presentation (1).pptx gjkbhhjk hjjgtihkk
SAI-CAO-24CSEN2021-PPT-UNIT-------1.pptx
Chapter no 8 output devices dpart 2.pptx
Presentation societal project DEEPIKA T.pptx
Copy-OT LIST 12.8.25.docxjdjfufufufufuuffuf
RTS MASTER DECK_Household Convergence Scorecards. Use this file copy.pptx
ELETRONIC-PRODUCTS-ASSEMBLY-AND-SERVICING-NC-II-WEEK-1-Copy.pptx
20A LG INR18650HJ2 3.6V 2900mAh Battery cells for Power Tools Vacuum Cleaner
Unit-1.pptxgeyeuueueu7r7r7r77r7r7r7uriruru
Printing Presentation to show beginners.
Computer Hardware - Technology and Livelihood Education
The process of making an electrical connection by melting low-temperature met...
SAHIL PROdhdjejss yo yo pdf TOCOL PPT.pdf
COA______________₹₹_₹₹33₹₹₹33₹₹₹3UNIT1V8.ppt
Clauses_Part1.hshshpjzjxnznxnxnndndndndndndndnndptx
PakistanCoinageAct-906.pdfdbnsshsjjsbsbb
GENERATOR AND IMPROVED COIL THEREFOR HAVINGELECTRODYNAMIC PROPERTIES
Ad

lec2_history about von Neumann architecture

  • 1. 1 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 1 ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2014 History of Computers (Chapter 1) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu
  • 2. 2 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 2 Historic Events 1623, 1642: Wilhelm Schickard (1592-1635) and Blaise Pascal (1623-1662) built mechanical counters with carry. 1823-34: Charles Babbage designed a difference engine. http://www.youtube.com/watch?v=0anIyVGeWOI&feature= related 1941: Conrad Zuse (1910-1995) built Z3, the first working programmable computer, built in Germany.
  • 3. Z3 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 3 Conrad Zuse Z1 (1938) Z2 (1939) Z3 (1941) ∙ ∙ ∙
  • 4. 4 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 4 Historic Events 1942: Vincent Atanasoff (professor) and Clifford Barry (graduate assistant) built the first electronic computer (ABC) at Iowa State College. 1943-44: John Mauchly (professor) and J. Presper Eckert (graduate student) built ENIAC at U. Pennsylvania, 1623. 1944: Howard Aiken used “separate data and program memories” in MARK I – IV computers – Harvard Architecture. 1945-52: John von Neumann proposed a “stored program computer” EDVAC (Electronic Discrete Variable Automatic Computer) – Von Neumann Architecture – use the same memory for program and data.
  • 5. 5 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 5 The Atanasoff Story The First Electronic Computer, the Atanasoff Story, by Alice R. Burks and Arthur W. Burks, Ann Arbor, Michigan: The University of Michigan Press, 1991. The Man Who Invented the Computer: The Biography of John Atanasoff, Digital Pioneer, by Jane Smiley, 256 pages, Doubleday, $25.95.
  • 6. National Medal of Technology 1990 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 6 John Vincent Atanasoff (1903–1995)
  • 7. 7 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 7 Most Influential Document “Preliminary Discussion of the Logical Design of an Electronic Computing Instrument,” 1946 report by A. W. Burks, H. H. Holdstine and J. von Neumann. Appears in Papers of John von Neumann, W. Aspray and A. Burks (editors), MIT Press, Cambridge, Mass., 1987, pp. 97- 146.
  • 8. 8 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 8 History Continues 1946-52: Von Neumann built the IAS computer at the Institute of Advanced Studies, Princeton – A prototype for most future computers. 1947-50: Eckert-Mauchly Computer Corp. built UNIVAC I (Universal Automatic Computer), used in the 1950 census. 1949: Maurice Wilkes built EDSAC (Electronic Delay Storage Automatic Calculator), the first stored-program computer.
  • 9. 9 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 9 First General-Purpose Computer Electronic Numerical Integrator and Calculator (ENIAC) built in World War II was the first general purpose computer – Used for computing artillery firing tables – 80 feet long, 8.5 feet high and several feet wide – Twenty 10 digit registers, each 2 feet long – Used 18,000 vacuum tubes – 5,000 additions/second – Weight: 30 tons – Power consumption: 140kW © 2004 Morgan Kaufman Publishers
  • 10. 10 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 10 Univac: Election, Nov. 4, 1952 Harold Sweeney, operator J. Presper Eckert, co-inventor Walter Cronkite, CBS USA TODAY, Oct 27, 2004, p. B.3 Candidate Electoral votes Univac prediction Actual count Eisenhower 438 442 Stevenson 93 89
  • 11. 11 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 11 First-Generation Computers Late 1940s and 1950s Stored-program computers Programmed in assembly language Used magnetic devices and earlier forms of memories Examples: IAS, ENIAC, EDVAC, UNIVAC, Mark I, IBM 701
  • 12. 12 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 12 The Organization of IAS Computer Accumulator (AC) Multiplier/Quotient (MQ) Arithmetic Logic Circuits Memory Buffer Register (MBR) Instr. Buffer (IBR) Program Counter (PC) Instruction Register (IR) Memory Address Reg. (MAR) Main Memory (M) 212 x 40 bit words Input/ Output Equipment Control Circuit Control Signals DATAPATH CONTROL UNIT
  • 13. 13 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 13 IAS Computer Machine Language 40-bit word, two machine instructions per word. Left instruction Right instruction bit 0 7 8 19 20 27 28 39 8-bit opcode 12-bit memory address (operand) Ref: J. P. Hayes, Computer Architecture and Organization, New York: McGraw-Hill, 1978.
  • 14. 14 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 14 IAS Data Transfer Instructions (7) Instruction Opcode Description LOAD MQ 00001010 AC ← MQ LOAD MQ, M(X) 00001001 MQ ← M(X) STOR M(X) 00100001 M(X) ← AC LOAD M(X) 00000001 AC ← M(X) LOAD – M(X) 00000010 AC ← – M(X) LOAD |M(X)| 00000011 AC ← |M(X)| LOAD – |M(X)| 00000100 AC ← – |M(X)| Ref. W. Stallings, Computer Organization & Architecture, Sixth Edition, Prentice-Hall, 2003, page 23.
  • 15. 15 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 15 IAS Unconditional Branch Instructions (2) Instruction Opcode Description JUMP M(X,0:19) 00001101 next instruction M(X,0:19) JUMP M(X,20:39) 00001110 next instruction M(X,20:39)
  • 16. 16 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 16 IAS Conditional Branch Instructions (2) Instruction Opcode Description JUMP +M(X,0:19) 00001111 IF AC ≥ 0, then next instruction M(X,0:19) JUMP +M(X,20:39) 00010000 IF AC ≥ 0, then next instruction M(X,20:39)
  • 17. 17 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 17 IAS Arithmetic Instructions (8) Instruction Opcode Description ADD M(X) 00000101 AC ← AC + M(X) ADD |M(X)| 00000111 AC ← AC + |M(X)| SUB M(X) 00000110 AC ← AC ─ M(X) SUB |M(X)| 00001000 AC ← AC ─ |M(X)| MUL M(X) 00001011 AC, MQ ← MQ×M(X) DIV M(X) 00001100 MQ, AC ← MQ/M(X) LSH 00010100 AC ← AC x 2 RSH 00010101 AC ← AC / 2
  • 18. 18 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 18 IAS Address Modify Instructions (2) Instruction Opcode Description STOR M(X,8:19) 00010010 M(X,8:19) ← AC(28:39) STOR M(X,28:39) 00010011 M(X,28:39) ← AC(28:39)
  • 19. 19 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 19 How IAS Computer Adds Two Numbers Suppose the numbers are stored in memory locations 100 and 101, and The sum is to be saved in memory location 102 Instruction Opcode Description LOAD M(100) 00000001 AC ← M(100) ADD M(101) 00000101 AC ← AC + M(101) STOR M(102) 00100001 M(102) ← AC
  • 20. 20 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 20 IAS Computer Machine Code 00000001 000001100100 00000101 000001100101 00100001 000001100110 00000000 000000000000 Load 100 Add 101 Stor 102 Stop
  • 21. 21 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 21 Save Program in Memory First program word Second program word Word 100 Word 101 Word 102 Address Memory Load program Counter, PC Address 0 Address max
  • 22. 22 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 22 Executing the Program Accumulator (AC) Multiplier/Quotient (MQ) Arithmetic Logic Circuits Memory Buffer Register (MBR) Program Counter (PC) Main Memory (M) 212 x 40 bit words Input/ Output Equipment Control Circuit Control Signals DATAPATH CONTROL UNIT Instr. Buffer (IBR) Instruction Register (IR) Memory Address Reg. (MAR)
  • 23. 23 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 23 IAS Instruction Cycles Store machine code in contiguous words of memory. Place starting address in program counter (PC). Start program: MAR ← PC Read memory: IBR ← MBR ← M(MAR), fetch Place left instruction (Load) in IR and operand (address) 100 in MAR, decode Read memory: AC ← M(100), execute Place right instruction (Add) in IR and operand (address) 101 in MAR, decode Read memory and add: AC ← AC + M(101), execute PC ← PC + 1
  • 24. 24 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 24 IAS Instruction Cycles (Cont.) MAR ← PC Read memory: IBR ← MBR ← M(MAR), fetch Place left instruction (Stor) in IR and operand (address) 102 in MAR, decode MBR ← AC, execute Write memory Place right instruction (Stop) in IR and operand 000 in MAR, decode Stop, execute
  • 25. 25 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 25 Hardware Contains Data storage devices Memory Registers Instruction decoding and execution devices Execution unit (arithmetic logic unit, ALU) Data transfer buses Control unit
  • 26. 26 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 26 Registers in IAS Register Size (bits) Function Program counter (PC) 12 Holds mem. address of next instruction Accumulator (AC) 40 Temporary data storage Multiplier quotient (MQ) 40 Temporary data storage Memory buffer (MBR) 40 Memory read / write data Instruction buffer (IBR) 20 Holds right instr. (bits 20-39) Instruction register (IR) 8 Holds opcode part of instruction Memory address (MAR) 12 Holds mem. address part of instruction
  • 27. 27 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 27 Register Transfer Transfer data synchronously with clock Register to register Register to register through ALU logic Registers to register through memory (write) Register to register through memory (read) Data transfer through communication bus Source register writes on bus Destination register reads from bus Control circuit provides read / write signals for bus and memory
  • 28. 28 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 28 Communication Bus A device writing on bus outputs inputs A device neither writing on nor reading from bus outputs inputs 1 0 0 0 0 1 outputs inputs A device reading from bus Control signals Bus Control circuit Opcode Control signals
  • 29. 29 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 29 Control Circuit – Finite State Machine Start Fetch Instruction Read memory Execute Decode left instruction Decode right instruction Execute MAR ← PC PC ← PC+1
  • 30. 30 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 30 Von Neumann Bottleneck Von Neumann architecture uses the same memory for instructions (program) and data. The time spent in memory accesses can limit the performance. This phenomenon is referred to as von Neumann bottleneck. To avoid the bottleneck, later architectures restrict most operands to registers (temporary storage in processor). Ref.: D. E. Comer, Essentials of Computer Architecture, Upper Saddle River, NJ: Pearson Prentice-Hall, 2005, p. 87.
  • 31. 31 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 31 John von Neumann (1903-1957)
  • 32. 32 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 32 Second Generation Computers 1955 to 1964 Transistor replaced vacuum tubes Magnetic core memories Floating-point arithmetic High-level languages used: ALGOL, COBOL and FORTRAN System software: compilers, subroutine libraries, batch processing Example: IBM 7094
  • 33. 33 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 33 Third Generation Computers Beyond 1965 Integrated circuit (IC) technology Semiconductor memories Memory hierarchy, virtual memories and caches Time-sharing Parallel processing and pipelining Microprogramming Examples: IBM 360 and 370, CYBER, ILLIAC IV, DEC PDP and VAX, Amdahl 470
  • 34. 34 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 34 C Programming Language and UNIX Operating System 1972 Now
  • 35. 35 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 35 Theory of Computing Alan Turing (1912-1954) gave a model of computing in 1936 – Turing Machine. Original paper: A. M. Turing, “On Computable Numbers with an Application to the Entscheidungsproblem*,” Proc. Royal Math. Soc., ser. 2, vol. 42, pp. 230- 265, 1936. Recent book: David Leavitt, The Man Who Knew Too Much: Alan Turing and the Invention of the Computer (Great Discoveries), W. W. Norton & Co., 2005. * The question of decidability, posed by mathematician Hilbert.
  • 36. 36 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 36 Turing Machine Processor P Read-write head Infinite memory tape (data) ti Machine instruction: sh ti oj sk Present state of processor Symbol on tape Operation Next state of processor
  • 37. 37 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 37 Turing Machine Four operations: – oj = tj, replace present symbol ti by tj – oj = R, move head one position to right – oj = L, move head one position to left – oj = H, halt the computation Universal Turing Machine: small instruction set, #symbols × #states < 30; can perform any possible (computable) computation. Computable means that Turing machine halts in finite number of steps. Real computers have finite memory – they find certain problems intractable. Ref: J. P. Hayes, Computer Architecture and Organization, New York: McGraw-Hill, 1978.
  • 38. Example Start with a blank tape and create a pattern 0b1b0b1b . . . Define symbols: b (blank), 0, 1 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 38 Present state Symbol on tape Operation Next state S0 (begin) blank Write 0 and move right S1 S1 blank Move right S2 S2 blank Write 1 and move right S3 S3 blank Move right S0 http://en.wikipedia.org/wiki/Turing_machine_examples
  • 39. Turing Test Can a computer think? (Turing, 1950). http://en.wikipedia.org/wiki/Computing_Machinery_and_Intelligence #cite_note-1 A. P. Saygin, I. Cicekli and V. Akman, “Turing Test: 50 Years Later,” Minds and Machines, vol. 10, no. 4, pp. 463-518, 2000. Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 39 Watson vs. humans: http://www.engadget.com/ 2011/01/13/ibms-watson- supercomputer-destroys- all-humans-in-jeopardy- pract/
  • 40. Turing Test in 2014 June 8, 2014, The 65 year-old Turing Test was passed for the very first time by computer program Eugene Goostman during Turing Test 2014 held at the renowned Royal Society in London on Saturday. 'Eugene' simulates a 13 year old boy and was developed in Saint Petersburg, Russia. The development team includes Vladimir Veselov and Eugene Demchenko. A program wins the Turing Test if it is mistaken for a human more than 30% of the time. http://www.reading.ac.uk/news-and-events/releases/PR583836.aspx Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 40
  • 41. Movie: The Imitation Game About English mathematician and logician, Alan Turing, helps crack the Enigma code during World War II. Screenplay: Graham Moore Cast: Benedict Cumberbatch, Keira Knightley, Matthew Goode Trailer: http://www.imdb.com/title/tt2084970/?ref_=nv_sr_1 Release date: November 2014 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 41
  • 42. 42 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 42 Incompleteness Theorem In 1931, the Czech-born mathematician Kurt Gödel (1906-1978) demonstrated that within any given branch of mathematics, there would always be some propositions that couldn't be proven either true or false using the rules and axioms. Gödel's Theorem has been used to argue that a computer can never be as smart as a human being because the extent of its knowledge is limited by a fixed set of axioms, whereas people can discover unexpected truths. See http://www.miskatonic.org/godel.html and other websites.
  • 43. 43 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 43 The Barber Paradox By Linda Shaver (An Example of Undecidability) In a particular town, there’s a particular barbershop with a peculiar sign in the window that reads: “This barber shaves all and only those men of the town who do not shave themselves.” Question: According to the sign in the window, does the barber shave himself?
  • 44. 44 Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 44 The Now Generation Personal computers Laptops and Palmtops Networking and wireless SOC and MEMS technology And the future! Biological computing Molecular computing Nanotechnology Optical computing Quantum computing See articles listed on the next slide and available at E7700: Advanced VLSI Design course site, http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12/ course.html
  • 45. 45 Useful Reading R. I. Bahar, D. Hammerstrom, J. Harlow, W. H. Joyner Jr., C. Lau, D. Marculescu, A. Orailoglu and M. Pedram, “Architectures for Silicon Nanoelectronics and Beyond,” Computer, vol. 40, no. 1, pp. 25-33, January 2007. T. Munakata, “Beyond Silicon: New Computing Paradigms, “Comm. ACM, vol. 50, no. 9, pp. 30-34, Sept. 2007. W. Robinett, G. S. Snider, P. J. Kuekes and S. Williams, “Computing with a Trillion Crummy Components,” Comm. ACM, vol. 50, no. 9, pp. 35-39, Sept. 2007. J. Kong, “Computation with Carbon Nanotube Devices,” Comm. ACM, vol. 50, no. 9, pp. 40-42, Sept. 2007. R. Stadler, “Molecular, Chemical and Organic Computing,” Comm. ACM, vol. 50, no. 9, pp. 43-45, Sept. 2007. M. T. Bohr, R. S. Chau, T. Ghani and K. Mistry, "The High-k Solution," IEEE Spectrum, vol. 44, no. 10, pp. 29-35, October 2007. J. H. Reif and T. H. Labean, “Autonomous Programmable Biomolecular Devices using Self-Assembled DNA Nanostructures,” Comm. ACM, vol. 50, no. 9, pp. 46-53, Sept. 2007. D. Bacon and D. Leung, “Toward a World with Quantum Computers,” Comm. ACM, vol. 50, no. 9, pp. 55- 59, Sept. 2007. H. Abdeldayem and D. A. Frazier, “Optical Computing: Need and Challenge,” Comm. ACM, vol. 50, no. 9, pp. 60-62, Sept. 2007. D. W. M. Marr and T. Munakata, “Micro/Nanofluidic Computing,” Comm. ACM, vol. 50, no. 9, pp. 64-68, Sept. 2007. M. Aono, M. Hara and K. Aihara, “Amoeba-Based Neurocomputing with Chaotic Dynamics,” Comm. ACM, vol. 50, no. 9, pp. 69-72, Sept. 2007. C. C. Lo and J. J. L. Morton, “Silicon’s Second Act, Can this semiconductor workhorse take computing tnto the quantum era?” IEEE Spectrum, vol. 51, no. 8, pp. 36-43, Aug. 2014. Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 45
  • 46. A Question Which is the most popular programming language today? A: http://spectrum.ieee.org/static/interactive- the-top-programming-languages Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 46
  • 47. Top 10 Prog. Languages Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2 47 W: Web M: Mobile D: Desktop/Enterprise E: Embedded Scores are normalized so that the top-ranked language’s score is set to 100. Source: IEEE Spectrum July 2014
  • 48. 48 Next: The MIPS ISA MIPS (Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set architecture. Fall 2014, Aug 20 . . . ELEC 5200-001/6200-001 Lecture 2