SlideShare a Scribd company logo

Lect09 adv-branch-prediction

Download as PPT, PDF
Gour Rakesh, profile picture
Gour Rakesh

The document discusses advanced techniques for branch prediction in computer processors. It covers topics like branch speculation, branch direction prediction using static, dynamic, and hybrid approaches, branch target prediction, and reducing branch mispredictions through techniques like two-level adaptive prediction, bi-mode prediction, and path history prediction. The goal is to better predict conditional branch instructions to improve instruction pipeline utilization and overall processor performance.

1 of 49
Downloaded 42 times
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Advanced Branch Prediction Prof. Mikko H. Lipasti University of Wisconsin-Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti
Advanced Branch Prediction • Control Flow Speculation – Branch Speculation – Mis-speculation Recovery • Branch Direction Prediction – Static Prediction – Dynamic Prediction – Hybrid Prediction • Branch Target Prediction • High-bandwidth Fetch • High-Frequency Fetch
Branch Speculation • Leading Speculation – Typically done during the Fetch stage – Based on potential branch instruction(s) in the current fetch group • Trailing Confirmation – Typically done during the Branch Execute stage – Based on the next Branch instruction to finish execution NT T NT T NT TNT T NT T NT T NT T (TAG 1) (TAG 2) (TAG 3)
Branch Speculation • Leading Speculation 1. Tag speculative instructions 2. Advance branch and following instructions 3. Buffer addresses of speculated branch instructions • Trailing Confirmation 1. When branch resolves, remove/deallocate speculation tag 2. Permit completion of branch and following instructions
Branch Speculation • Start new correct path – Must remember the alternate (non-predicted) path • Eliminate incorrect path – Must ensure that the mis-speculated instructions produce no side effects NT T NT T NT TNT T NT T NT T NT T (TAG 2) (TAG 3) (TAG 1)
Mis-speculation Recovery • Start new correct path 1. Update PC with computed branch target (if predicted NT) 2. Update PC with sequential instruction address (if predicted T) 3. Can begin speculation again at next branch • Eliminate incorrect path 1. Use tag(s) to deallocate ROB entries occupied by speculative instructions 2. Invalidate all instructions in the decode and dispatch buffers, as well as those in reservation stations
Tracking Instructions • Assign branch tags – Allocated in circular order – Instruction carries this tag throughout processor • Track instruction groups – Instructions managed in groups, max. one branch per group – ROB structured as groups • Leads to some inefficiency • Simpler tracking of speculative instructions
Program Control Flow Decode Buffer Fetch Dispatch Buffer Decode Reservation Dispatch Stations Issue Execute Finish Completion Branch to I-cache FA (fetch address) FABranch Predictor Spec. target Prediction FA-mux SFX SFX CFX FPU LSBRN Buffer Branch Predictor Update
Static Branch Prediction • Single-direction – Always not-taken: Intel i486 • Backwards Taken/Forward Not Taken – Loop-closing branches – Used as backup in Pentium Pro, II, III, 4 • Heuristic-based: void * p = malloc (numBytes); if (p == NULL) errorHandlingFunction( );
Static Branch Prediction • Heuristic-based: Ball/Larus – Thomas Ball and James R. Larus. Branch Prediction for Free. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pages 300-313, May 1993. Heuristic Name Description Loop Branch If the branch target is back to the head of a loop, predict taken. Pointer If a branch compares a pointer with NULL, or if two pointers are compared, predict in the direction that corresponds to the pointer being not NULL, or the two pointers not being equal. Opcode If a branch is testing that an integer is less than zero, less than or equal to zero, or equal to a constant, predict in the direction that corresponds to the test evaluating to false. Guard If the operand of the branch instruction is a register that gets used before being redefined in the successor block, predict that the branch goes to the successor block. Loop Exit If a branch occurs inside a loop, and neither of the targets is the loop head, then predict that the branch does not go to the successor that is the loop exit. Loop Header Predict that the successor block of a branch that is a loop header or a loop pre-header is taken. Call If a successor block contains a subroutine call, predict that the branch goes to that successor block. Store If a successor block contains a store instruction, predict that the branch does not go to that successor block. Return If a successor block contains a return from subroutine instruction, predict that the branch does not go to that successor block.
Static Branch Prediction • Profile-based 1. Instrument program binary 2. Run with representative (?) input set 3. Recompile program a. Annotate branches with hint bits, or b. Restructure code to match predict not-taken • Best performance: 75-80% accuracy
Dynamic Branch Prediction • Main advantages: – Learn branch behavior autonomously • No compiler analysis, heuristics, or profiling – Adapt to changing branch behavior • Program phase changes branch behavior • First proposed in 1979-1980 – US Patent #4,370,711, Branch predictor using random access memory, James. E. Smith • Continually refined since then
Smith Predictor Hardware • Jim E. Smith. A Study of Branch Prediction Strategies. International Symposium on Computer Architecture, pages 135-148, May 1981 • Widely employed: Intel Pentium, PowerPC 604, PowerPC 620, etc. Branch Address Branch Prediction m 2m k-bit counters most significantbit Saturating Counter Increment/Decrement Branch Outcome Updated Counter Value
Two-level Branch Prediction • BHR adds global branch history – Provides more context – Can differentiate multiple instances of the same static branch – Can correlate behavior across multiple static branches BHR 0110 PC = 01011010010101 010110 000000 000001 000010 000011 010100 010101 010110 010111 111110 111111 PHT 1 0 1 Branch Prediction
Two-level Prediction: Local History • Detailed local history can be useful 110 PC = 01011010010101 0101110 0000000 0000001 0000010 0000011 0101100 0101101 0101110 0101111 0111110 0111111 PHT 0 1 0 Branch Prediction 000 001 010 011 100 101 110 111 BHT
Local History Predictor Example • Loop closing branches – Must identify last instance • Local history dedicates PHT entry to each instance – ‘0111’ entry predicts not taken 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11 11 11 00 11101110111011101110 PHT Loop closing branch’s history
Two-level Taxonomy • Based on indices for branch history and pattern history – BHR: {G,P,S}: {Global, Per-address, Set} – PHT: {g,p,s}: {Global, Per-address, Set} – 9 combinations: GAg, GAp, GAs, PAg, PAp, PAs, SAg, SAp and SAs • Tse-Yu Yeh and Yale N. Patt. Two-Level Adaptive Branch Prediction. International Symposium on Microarchitecture, pages 51- 61, November 1991.
Index Sharing in Two-level Predictors • Use XOR function to achieve better utilization of PHT • Scott McFarling. Combining Branch Predictors. TN-36, Digital Equipment Corporation Western Research Laboratory, June 1993. • Used in e.g. IBM Power 4, Alpha 21264 1101 0110 GAp BHR PC 1001 1001 1010 BHR PC 1001 gshare BHR PC 1101 0110 1011XOR BHR PC 1001 1010 0011XOR 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Sources of Mispredictions • Lack of history (training time) • Randomized behavior – Usually due to randomized input data – Surprisingly few branches depend on input data values • BHR capacity – Correlate to branch that already shifted out – E.g. loop count > BHR width • PHT capacity – Aliasing/interference • Positive • Negative
Reducing Interference • Compulsory aliasing (cold miss) – Not important (less than 1%) – Only remedy is to set appropriate initial value – Also: beware indexing schemes with high training cost (e.g. very long branch history) • Capacity aliasing (capacity miss) – Increase PHT size • Conflict aliasing (conflict miss) – Change indexing scheme or partition PHT in a clever fashion
Bi-Mode Predictor • PHT partitioned into T/NT halves – Selector chooses source • Reduces negative interference, since most entries in PHT0 tend towards NT, and most entries in PHT1 tend towards T Branch Address Global BHR XOR PHT0 PHT1 Final Prediction choice predictor
gskewed Predictor • Multiple PHT banks indexed by different hash functions – Conflicting branch pair unlikely to conflict in more than one PHT • Majority vote determines prediction • Used in Alpha EV8 (ultimately cancelled) • P. Michaud, A. Seznec, and R. Uhlig. Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. ISCA-24, June 1997 Branch Address Global BHR f0 f1 f2 Majority Final Prediction PHT0 PHT1 PHT2
Agree Predictor • Same principle as bi-mode • PHT records whether branch bias matches outcome – Exploits 70-80% static predictability • Used in in HP PA-8700 • E. Sprangle, R. S. Chappell, M. Alsup, and Y. N. Patt. The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. ISCA-24, June 1997. Branch Address Global BHR XOR Prediction PHT biasing bits 1 0 1 = agree with bias bit 0 = disagree
YAGS Predictor • Based on bi-mode – T/NT PHTs cache only the exceptions • A. N. Eden and T. N. Mudge. The YAGS Branch Prediction Scheme. MICRO, Dec 1998. Branch Address Global BHR XOR Partial Tag 2bC Partial Tag 2bC = = 0 1 0 1 0 1 F i n a l P re d i c ti o n choice PHT T-cache NT-cache T/NT-cache hit?
Branch Filtering • Highly-biased branches – e.g. ‘11111’ history – Eliminated from PHT • P-Y Chang, M. Evers, and Y Patt. Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference. PACT, October 1996. Branch Address Global BHR XOR AND Branch Prediction gshare ... counter direction Branch Counting Table
Alloyed-History Predictors • Local history vs. global history • Kevin Skadron, Margaret Martonosi, and Douglas W. Clark. Alloyed Global and Local Branch History: A Robust Solution to Wrong-History Mispredictions. International Journal of Parallel Programming, 31(2), April 2003. Branch Address Global BHR Local BHT Alloyed History PHT Branch Prediction
Path History • Sometimes T/NT history is not enough • Path history (PC values) can help if (y == 0) goto C; if (y == 5) goto C; if (y < 12) goto D; if (y % 2) goto E; History = T History = T H is to r y = T T A B C DPath ACD: Branch Address = X Branch History = TT Branch Outcome = Not Taken Path BCD: Branch Address = X Branch History = TT Branch Outcome = Taken
Path-Based Branch Predictor • Ravi Nair. Dynamic Path-Based Branch Correlation. International Symposium on Microarchitecture, pages 15-23, December 1995. Branch Address Shift in address atupdate PHT Path History Shift Registers Branch Prediction
Dynamic History Length • Branch history length: – Some prefer short history (less training time) – Some require longer history (complex behavior) • Vary history length – Choose through profile/compile-time hints – Or learn dynamically • References – Maria-Dana Tarlescu, Kevin B. Theobald, and Guang R. Gao. Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy. ICCD, October 1996. – Toni Juan, Sanji Sanjeevan, and Juan J. Navarro. Dynamic History-Length Fitting: A Third Level of Adaptivity for Branch Prediction. ISCA, June 1998. – Jared Stark, Marius Evers, and Yale N. Patt. Variable Path Branch Prediction. ACM SIGPLAN Notices, 33(11):170-179, 1998
Loop Count Predictors • To predict last loop iteration’s NT branch: – Must have length(BHR) > loop count – Not feasible for large loop counts • Instead, BHR has mode bit – Once history == ‘111…11’ or ‘000…00’ switch to count mode – Now nth entry in PHT trains to NT and predicts nth iteration as last one – Now length(BHR) > log2(loop count) is sufficient • Used in Intel Pentium M/Core Duo/ Core 2 Duo History/CountH/C BHR entry: Mode bit: H – history C – count “1”
Understanding Advanced Predictors • Four types of history – Local (bimodal) history (Smith predictor) • Table of counters summarizes local history • Simple, but only effective for biased branches – Local outcome history (correlate with self) • Shift register of individual branch outcomes • Separate counter for each outcome history (M-F vs Sat/Sun) – Global outcome history (correlate with others) • Shift register of recent branch outcomes • Separate counter for each outcome history – Path history (overcomes CFG convergence aliasing) • Shift register of recent (partial) block addresses • Can differentiate similar global outcome histories • Can combine or “alloy” histories in many ways
Understanding Advanced Predictors • History length – Short history—lower training cost – Long history—captures macro-level behavior – Variable history length predictors • Really long history (long loops) – Loop count predictors – Fourier transform into frequency domain • Limited capacity & interference – Constructive vs. destructive – Bi-mode, gskewed, agree, YAGS – Read sec. 9.3.2 carefully
Perceptron Branch Prediction [Jimenez, Lin HPCA 2001] • Perceptron – Basis in AI concept [1962] – Computes boolean result based on multiple weighted inputs • Adapted for branch prediction – xi from branch history (1 T, -1 NT) – wi incremented whenever branch outcome matches xi – Finds correlation between current branch and any subset of prior branches n y = w0 + ∑ xi wi i=1
Perceptrons - Implementation • Complex dot product must be computed for every prediction – Too slow • Arithmetic tricks, pipelining: – Daniel A. Jimenez and Calvin Lin. Neural methods for dynamic branch prediction. ACM Transactions on Computer Systems, 20(4):369– 397, November 2002. – Analog circuit implementation also possible • Key insight: – Not all branches in history are important (correlate) – Perceptron weights learn this
Combining or Hybrid Predictors • Select “best” history • Reduce interference w/partial updates • Scott McFarling. Combining Branch Predictors. TN-36, Digital Equipment Corporation Western Research Laboratory, June 1993. Branch Address P0 P1 Branch Prediction Meta-Prediction Branch Address M PApgshare M Branch Prediction
Branch Classification • Static (profile-based) branch hints select which prediction to use – Static T/Static NT/Dynamic – PowerPC y-bit overrides static BTFN • P-Y Chang, E Hao, TY Yeh, and Y Patt. Branch Classification: a New Mechanism for Improving Branch Predictor Performance. MICRO, Nov. 1994. • D Grunwald, D Lindsay, and B Zorn. Static Methods in Hybrid Branch Prediction. PACT, October 1998 Branch Address P0 P1 Dynamic Branch Prediction Meta-Prediction M 0 1 Final Branch Prediction Instruction Register Static Branch Hint
Multi-Hybrid Predictor • Generalizes selector to choose from > 2 predictors • Marius Evers, Po-Yung Chang, and Yale N. Patt. Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. International Symposium on Computer Architecture, pages 3-11, May 1996. Branch Address = 3 ? = 3 ? = 3 ? Table of Counters Priority Encoder P1 P2 Pn Final Prediction ...
Overriding Predictors • Different types of history – E.g. Bimodal, Local, Global (BLG) • Different history lengths (up to hundreds of branches) • How to choose? – Metapredictor/selector? Expensive, slow to train • Tag match with most sophisticated predictor entry – Parallel tag check with B, L, G, long-history G – Choose most sophisticated prediction – Fancy predictors only updated when simple ones fail © Shen, Lipasti 38
Multiple History Lengths • Championship Branch Prediction (CBP) – 2 contests, standardized methods and traces • Insight from perceptron BP: – Some branches need short history – Others need very long history • Geometric history length (O-GEHL) [Seznec] – Geometric series of history lengths • Tagged Geometric History Length (TAGE) – Choose longest matching history © Shen, Lipasti 39
Branch Target Prediction • Partial tags sufficient in BTB Branch Address Branch ...target tag target tag target tag = = = OR Branch Target Buffer + Size of Instruction Branch Target BTB Hit? Direction Predictor not-taken target taken-target 0 1
Return Address Stack • Speculative update causes headaches – On each predicted branch, checkpoint head/tail – Further, checkpoint stack contents since speculative pop/push sequence is destructive – Conditional call/return causes more headaches Branch Address Size of Instruction BTB Target Prediction Return Address BTB Target Predictionis this a return? Branch Address (a) (b)
Branch Confidence Estimation • Limit speculation (energy), reverse predictions, guide fetch for multithreaded processors • Q Jacobson, E Rotenberg, and JE Smith. Assigning Confidence to Conditional Branch Predictions. MICRO, December 1996. Branch Address Global BHR XOR Table of CIRs Reduction Function Confidence Prediction
High-Bandwidth Fetch: Collapsing Buffer • Fetch from two cache blocks, rotate, collapse past taken branches • Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills and Burzin A. Patel. Optimization of Instruction Fetch Mechanisms for High Issue Rates. International Symposium on Computer Architecture, June 1995. Branch Address Interleaved BTB Cache Bank 1 Cache Bank 2 Two cache line addresses E F G HA B C D E F G H A B C D Interchange Switch Collapsing Circuit Valid Instruction Bits GA B C E To Decode Stage
High-Bandwidth Fetch: Trace Cache • Fold out taken branches by tracing instructions as they commit into a fill buffer • Eric Rotenberg, S. Bennett, and James E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. MICRO, December 1996. A B C D E F G H I J A B C D E F G H I J Instruction Cache Trace Cache (a) (b)
Intel Pentium 4 Trace Cache • No first-level instruction cache: trace cache only • Trace cache BTB identifies next trace • Miss leads to fetch from level two cache • Trace cache instructions are decoded (uops) • Cache capacity 12k uops – Overwhelmed for database applications – Serial decoder becomes performance bottleneck Trace CacheTrace Cache BTB Instruction Decode Instruction TLB and Prefetcher Front-End BTB Level-Two Unified Data and Instruction Cache Instruction Fetch Queue To renamer, execute, etc.
High-Bandwidth Fetch: Loop Buffers • History: AMD29K Branch Target Cache – Don’t cache the target address; cache 4 instructions from the target itself – Avoid accessing I$ for first fetch group following a taken branch – If loop body is <= 4 instructions, effectively a loop cache – Room for 32/64 branch targets • Also common in DSP designs, under s/w control (e.g. Lucent) • Introduced in Intel Merom (Core 2 Duo) – Fetch buffer detects short backward branches, inhibits refetch from I$ • Intel Nehalem (Core i7) – Moved loop buffer after decoders: contains uops • Intel Sandybridge – General-purpose uop cache (not just loops) – 1.5K capacity bc Loop Body Fetch/Decode/ Dispatch Buffer
High Frequency: Next-line Prediction • Embed next fetch address in instruction cache – Enables high-frequency back-to-back fetch • Brad Calder and Dirk Grunwald. Next Cache Line and Set Prediction. International Symposium on Computer Architecture, pages 287-296, June 1995. 2A B C D 6E F G H tag tag Target Prediction Target Prediction = Next line misprediction Tag check for cycle 1’s lookup Cycle 1 Cycle 2 next line prediction I J K L Cycle 3 = T a g c h e c k f o r cycle 2’s lookup Target Pred
High Frequency: Overriding Predictors • Simple, fast predictor turns around every cycle • Smarter, slower predictor can override • Widely used: PowerPC 604, 620, Alpha 21264 Small, Fast Predictor Instruction Cache Slow Overriding Predictor Stage 1 Stage 2 Stage 3 Predict A PredictA Fetch A Predict A Fetch Queue Predict B Predict B Fetch B PredictB Predict C Predict C Queue A PredictA If slow predict agrees with fastpredict, do nothing If predictions do not match, flush A, B, and C, and restart fetch at newpredicted target Cycle 1 Cycle 2 Cycle 3
Advanced Branch Prediction Summary • Control Flow Speculation – Branch Speculation – Mis-speculation Recovery • Branch Direction Prediction – Static Prediction – Dynamic Prediction – Hybrid Prediction • Branch Target Prediction • High-bandwidth Fetch • High-Frequency Fetch

More Related Content

ODP
Introduction to Optee (26 may 2016)
Yannick Gicquel
 
PPTX
Deadlock- Operating System
Rajan Shah
 
PPT
Branch prediction
Aneesh Raveendran
 
PPT
Process management in os
Sumant Diwakar
 
PPT
CCNA Router Startup and Configuration
Dsunte Wilson
 
PPT
Lustre And Nfs V4
awesomesos
 
PPTX
Operating system architecture
Sabin dumre
 
PDF
WN Memory Tiering WP Mar2023.pdf
RochanSankar1
 
Introduction to Optee (26 may 2016)
Yannick Gicquel
 
Deadlock- Operating System
Rajan Shah
 
Branch prediction
Aneesh Raveendran
 
Process management in os
Sumant Diwakar
 
CCNA Router Startup and Configuration
Dsunte Wilson
 
Lustre And Nfs V4
awesomesos
 
Operating system architecture
Sabin dumre
 
WN Memory Tiering WP Mar2023.pdf
RochanSankar1
 

What's hot (20)

DOCX
operating system question bank
rajatdeep kaur
 
PPT
Unit 3-pipelining &amp; vector processing
vishal choudhary
 
PPTX
High availability deep dive high-end srx series
Muhammad Denis Iqbal
 
PPTX
Warmhole routing ppt
Meenakshi Tripathi
 
PPT
OpenVPN
francisdinha
 
PPTX
Hệ điều hành linux (1)
khung196
 
PPTX
Conditional branches
Dilip Mathuria
 
PDF
Signal Handling in Linux
Tushar B Kute
 
PPTX
Multiprocessor architecture
Arpan Baishya
 
PDF
Computer organisation -morris mano
vishnu murthy
 
PPTX
Pipelining and vector processing
Kamal Acharya
 
PPTX
Introduction of Memory Management
Maitree Patel
 
PPTX
Modes of transfer - Computer Organization & Architecture - Nithiyapriya Pasav...
priya Nithya
 
PPTX
Producer consumer
Mohd Tousif
 
PPTX
Ch1-Operating System Concept
Muhammad Bilal Tariq
 
PDF
Operating Systems Part II-Process Scheduling, Synchronisation & Deadlock
Ajit Nayak
 
PDF
Video Drivers
Anil Kumar Pugalia
 
PPTX
Von Neumann Architecture
Lor Ham
 
PPTX
Multiprogramming&timesharing
Tanuj Tyagi
 
PDF
8085 microprocessor ramesh gaonkar
SAQUIB AHMAD
 
operating system question bank
rajatdeep kaur
 
Unit 3-pipelining &amp; vector processing
vishal choudhary
 
High availability deep dive high-end srx series
Muhammad Denis Iqbal
 
Warmhole routing ppt
Meenakshi Tripathi
 
OpenVPN
francisdinha
 
Hệ điều hành linux (1)
khung196
 
Conditional branches
Dilip Mathuria
 
Signal Handling in Linux
Tushar B Kute
 
Multiprocessor architecture
Arpan Baishya
 
Computer organisation -morris mano
vishnu murthy
 
Pipelining and vector processing
Kamal Acharya
 
Introduction of Memory Management
Maitree Patel
 
Modes of transfer - Computer Organization & Architecture - Nithiyapriya Pasav...
priya Nithya
 
Producer consumer
Mohd Tousif
 
Ch1-Operating System Concept
Muhammad Bilal Tariq
 
Operating Systems Part II-Process Scheduling, Synchronisation & Deadlock
Ajit Nayak
 
Video Drivers
Anil Kumar Pugalia
 
Von Neumann Architecture
Lor Ham
 
Multiprogramming&timesharing
Tanuj Tyagi
 
8085 microprocessor ramesh gaonkar
SAQUIB AHMAD
 
Ad

Viewers also liked (9)

PPT
Like 2014214
Jingwen Leng
 
PPT
[2009 11-09] branch prediction
mobilevc
 
PDF
Comp architecture : branch prediction
rinnocente
 
PDF
Instruction Level Parallelism (ILP) Limitations
Jose Pinilla
 
PDF
Intel CPU Manufacturing Process
Dr. A. B. Shinde
 
PDF
Pipelining and ILP (Instruction Level Parallelism)
Dr. A. B. Shinde
 
PPT
Lec12 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- P6, Netbur...
Hsien-Hsin Sean Lee, Ph.D.
 
PDF
Study: The Future of VR, AR and Self-Driving Cars
LinkedIn
 
PDF
Hype vs. Reality: The AI Explainer
Luminary Labs
 
Like 2014214
Jingwen Leng
 
[2009 11-09] branch prediction
mobilevc
 
Comp architecture : branch prediction
rinnocente
 
Instruction Level Parallelism (ILP) Limitations
Jose Pinilla
 
Intel CPU Manufacturing Process
Dr. A. B. Shinde
 
Pipelining and ILP (Instruction Level Parallelism)
Dr. A. B. Shinde
 
Lec12 Computer Architecture by Hsien-Hsin Sean Lee Georgia Tech -- P6, Netbur...
Hsien-Hsin Sean Lee, Ph.D.
 
Study: The Future of VR, AR and Self-Driving Cars
LinkedIn
 
Hype vs. Reality: The AI Explainer
Luminary Labs
 
Ad

Similar to Lect09 adv-branch-prediction (20)

PPT
KSpeculative aspects of high-speed processor design
ssuser7dcef0
 
PPTX
Instruction pipelining
Tech_MX
 
PDF
rnaseq2015-02-18-170327193409.pdf
Pushpendra83
 
PDF
RNA-Seq
Bioinformatics and Computational Biosciences Branch
 
PDF
ChIP-seq - Data processing
Sebastian Schmeier
 
PPT
Mayank
Mayank Miky
 
PDF
Raft After ScyllaDB 5.2: Safe Topology Changes
ScyllaDB
 
PPT
Inside LoLA - Experiences from building a state space tool for place transiti...
Universität Rostock
 
PPT
instruction parallelism .ppt
shottofidelis1
 
PPT
SOC-CH3.pptSOC ProcessorsSOC Processors Used in SOC Used in SOC
SnehaLatha68
 
PPTX
Pentinum 2
Prateek Pandey
 
PPTX
Ion Torrent Sequencer, Mappers, Variant Callers
Venu Thatikonda
 
PDF
Training Distributed Deep Recurrent Neural Networks with Mixed Precision on G...
Databricks
 
PDF
High Speed Design Closure Techniques-Balachander Krishnamurthy
ICTperspectives
 
PDF
BITS - Comparative genomics: the Contra tool
BITS
 
PDF
An open source framework for processing daily satellite images (AVHRR) over l...
Sajid Pareeth
 
PPTX
Control hazards MIPS pipeline.pptx
Irfan Anjum
 
PDF
SC08_talk_final_handouts
Mitesh Meswani
 
PPT
PPC 750
Raviraj Kaur
 
PDF
ThesisPresentation_Upd
Ashraf ElSharif
 
KSpeculative aspects of high-speed processor design
ssuser7dcef0
 
Instruction pipelining
Tech_MX
 
rnaseq2015-02-18-170327193409.pdf
Pushpendra83
 
RNA-Seq
Bioinformatics and Computational Biosciences Branch
 
ChIP-seq - Data processing
Sebastian Schmeier
 
Mayank
Mayank Miky
 
Raft After ScyllaDB 5.2: Safe Topology Changes
ScyllaDB
 
Inside LoLA - Experiences from building a state space tool for place transiti...
Universität Rostock
 
instruction parallelism .ppt
shottofidelis1
 
SOC-CH3.pptSOC ProcessorsSOC Processors Used in SOC Used in SOC
SnehaLatha68
 
Pentinum 2
Prateek Pandey
 
Ion Torrent Sequencer, Mappers, Variant Callers
Venu Thatikonda
 
Training Distributed Deep Recurrent Neural Networks with Mixed Precision on G...
Databricks
 
High Speed Design Closure Techniques-Balachander Krishnamurthy
ICTperspectives
 
BITS - Comparative genomics: the Contra tool
BITS
 
An open source framework for processing daily satellite images (AVHRR) over l...
Sajid Pareeth
 
Control hazards MIPS pipeline.pptx
Irfan Anjum
 
SC08_talk_final_handouts
Mitesh Meswani
 
PPC 750
Raviraj Kaur
 
ThesisPresentation_Upd
Ashraf ElSharif
 

Lect09 adv-branch-prediction

  • 1. Advanced Branch Prediction Prof. Mikko H. Lipasti University of Wisconsin-Madison Lecture notes based on notes by John P. Shen Updated by Mikko Lipasti
  • 2. Advanced Branch Prediction • Control Flow Speculation – Branch Speculation – Mis-speculation Recovery • Branch Direction Prediction – Static Prediction – Dynamic Prediction – Hybrid Prediction • Branch Target Prediction • High-bandwidth Fetch • High-Frequency Fetch
  • 3. Branch Speculation • Leading Speculation – Typically done during the Fetch stage – Based on potential branch instruction(s) in the current fetch group • Trailing Confirmation – Typically done during the Branch Execute stage – Based on the next Branch instruction to finish execution NT T NT T NT TNT T NT T NT T NT T (TAG 1) (TAG 2) (TAG 3)
  • 4. Branch Speculation • Leading Speculation 1. Tag speculative instructions 2. Advance branch and following instructions 3. Buffer addresses of speculated branch instructions • Trailing Confirmation 1. When branch resolves, remove/deallocate speculation tag 2. Permit completion of branch and following instructions
  • 5. Branch Speculation • Start new correct path – Must remember the alternate (non-predicted) path • Eliminate incorrect path – Must ensure that the mis-speculated instructions produce no side effects NT T NT T NT TNT T NT T NT T NT T (TAG 2) (TAG 3) (TAG 1)
  • 6. Mis-speculation Recovery • Start new correct path 1. Update PC with computed branch target (if predicted NT) 2. Update PC with sequential instruction address (if predicted T) 3. Can begin speculation again at next branch • Eliminate incorrect path 1. Use tag(s) to deallocate ROB entries occupied by speculative instructions 2. Invalidate all instructions in the decode and dispatch buffers, as well as those in reservation stations
  • 7. Tracking Instructions • Assign branch tags – Allocated in circular order – Instruction carries this tag throughout processor • Track instruction groups – Instructions managed in groups, max. one branch per group – ROB structured as groups • Leads to some inefficiency • Simpler tracking of speculative instructions
  • 8. Program Control Flow Decode Buffer Fetch Dispatch Buffer Decode Reservation Dispatch Stations Issue Execute Finish Completion Branch to I-cache FA (fetch address) FABranch Predictor Spec. target Prediction FA-mux SFX SFX CFX FPU LSBRN Buffer Branch Predictor Update
  • 9. Static Branch Prediction • Single-direction – Always not-taken: Intel i486 • Backwards Taken/Forward Not Taken – Loop-closing branches – Used as backup in Pentium Pro, II, III, 4 • Heuristic-based: void * p = malloc (numBytes); if (p == NULL) errorHandlingFunction( );
  • 10. Static Branch Prediction • Heuristic-based: Ball/Larus – Thomas Ball and James R. Larus. Branch Prediction for Free. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pages 300-313, May 1993. Heuristic Name Description Loop Branch If the branch target is back to the head of a loop, predict taken. Pointer If a branch compares a pointer with NULL, or if two pointers are compared, predict in the direction that corresponds to the pointer being not NULL, or the two pointers not being equal. Opcode If a branch is testing that an integer is less than zero, less than or equal to zero, or equal to a constant, predict in the direction that corresponds to the test evaluating to false. Guard If the operand of the branch instruction is a register that gets used before being redefined in the successor block, predict that the branch goes to the successor block. Loop Exit If a branch occurs inside a loop, and neither of the targets is the loop head, then predict that the branch does not go to the successor that is the loop exit. Loop Header Predict that the successor block of a branch that is a loop header or a loop pre-header is taken. Call If a successor block contains a subroutine call, predict that the branch goes to that successor block. Store If a successor block contains a store instruction, predict that the branch does not go to that successor block. Return If a successor block contains a return from subroutine instruction, predict that the branch does not go to that successor block.
  • 11. Static Branch Prediction • Profile-based 1. Instrument program binary 2. Run with representative (?) input set 3. Recompile program a. Annotate branches with hint bits, or b. Restructure code to match predict not-taken • Best performance: 75-80% accuracy
  • 12. Dynamic Branch Prediction • Main advantages: – Learn branch behavior autonomously • No compiler analysis, heuristics, or profiling – Adapt to changing branch behavior • Program phase changes branch behavior • First proposed in 1979-1980 – US Patent #4,370,711, Branch predictor using random access memory, James. E. Smith • Continually refined since then
  • 13. Smith Predictor Hardware • Jim E. Smith. A Study of Branch Prediction Strategies. International Symposium on Computer Architecture, pages 135-148, May 1981 • Widely employed: Intel Pentium, PowerPC 604, PowerPC 620, etc. Branch Address Branch Prediction m 2m k-bit counters most significantbit Saturating Counter Increment/Decrement Branch Outcome Updated Counter Value
  • 14. Two-level Branch Prediction • BHR adds global branch history – Provides more context – Can differentiate multiple instances of the same static branch – Can correlate behavior across multiple static branches BHR 0110 PC = 01011010010101 010110 000000 000001 000010 000011 010100 010101 010110 010111 111110 111111 PHT 1 0 1 Branch Prediction
  • 15. Two-level Prediction: Local History • Detailed local history can be useful 110 PC = 01011010010101 0101110 0000000 0000001 0000010 0000011 0101100 0101101 0101110 0101111 0111110 0111111 PHT 0 1 0 Branch Prediction 000 001 010 011 100 101 110 111 BHT
  • 16. Local History Predictor Example • Loop closing branches – Must identify last instance • Local history dedicates PHT entry to each instance – ‘0111’ entry predicts not taken 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11 11 11 00 11101110111011101110 PHT Loop closing branch’s history
  • 17. Two-level Taxonomy • Based on indices for branch history and pattern history – BHR: {G,P,S}: {Global, Per-address, Set} – PHT: {g,p,s}: {Global, Per-address, Set} – 9 combinations: GAg, GAp, GAs, PAg, PAp, PAs, SAg, SAp and SAs • Tse-Yu Yeh and Yale N. Patt. Two-Level Adaptive Branch Prediction. International Symposium on Microarchitecture, pages 51- 61, November 1991.
  • 18. Index Sharing in Two-level Predictors • Use XOR function to achieve better utilization of PHT • Scott McFarling. Combining Branch Predictors. TN-36, Digital Equipment Corporation Western Research Laboratory, June 1993. • Used in e.g. IBM Power 4, Alpha 21264 1101 0110 GAp BHR PC 1001 1001 1010 BHR PC 1001 gshare BHR PC 1101 0110 1011XOR BHR PC 1001 1010 0011XOR 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
  • 19. Sources of Mispredictions • Lack of history (training time) • Randomized behavior – Usually due to randomized input data – Surprisingly few branches depend on input data values • BHR capacity – Correlate to branch that already shifted out – E.g. loop count > BHR width • PHT capacity – Aliasing/interference • Positive • Negative
  • 20. Reducing Interference • Compulsory aliasing (cold miss) – Not important (less than 1%) – Only remedy is to set appropriate initial value – Also: beware indexing schemes with high training cost (e.g. very long branch history) • Capacity aliasing (capacity miss) – Increase PHT size • Conflict aliasing (conflict miss) – Change indexing scheme or partition PHT in a clever fashion
  • 21. Bi-Mode Predictor • PHT partitioned into T/NT halves – Selector chooses source • Reduces negative interference, since most entries in PHT0 tend towards NT, and most entries in PHT1 tend towards T Branch Address Global BHR XOR PHT0 PHT1 Final Prediction choice predictor
  • 22. gskewed Predictor • Multiple PHT banks indexed by different hash functions – Conflicting branch pair unlikely to conflict in more than one PHT • Majority vote determines prediction • Used in Alpha EV8 (ultimately cancelled) • P. Michaud, A. Seznec, and R. Uhlig. Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. ISCA-24, June 1997 Branch Address Global BHR f0 f1 f2 Majority Final Prediction PHT0 PHT1 PHT2
  • 23. Agree Predictor • Same principle as bi-mode • PHT records whether branch bias matches outcome – Exploits 70-80% static predictability • Used in in HP PA-8700 • E. Sprangle, R. S. Chappell, M. Alsup, and Y. N. Patt. The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference. ISCA-24, June 1997. Branch Address Global BHR XOR Prediction PHT biasing bits 1 0 1 = agree with bias bit 0 = disagree
  • 24. YAGS Predictor • Based on bi-mode – T/NT PHTs cache only the exceptions • A. N. Eden and T. N. Mudge. The YAGS Branch Prediction Scheme. MICRO, Dec 1998. Branch Address Global BHR XOR Partial Tag 2bC Partial Tag 2bC = = 0 1 0 1 0 1 F i n a l P re d i c ti o n choice PHT T-cache NT-cache T/NT-cache hit?
  • 25. Branch Filtering • Highly-biased branches – e.g. ‘11111’ history – Eliminated from PHT • P-Y Chang, M. Evers, and Y Patt. Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference. PACT, October 1996. Branch Address Global BHR XOR AND Branch Prediction gshare ... counter direction Branch Counting Table
  • 26. Alloyed-History Predictors • Local history vs. global history • Kevin Skadron, Margaret Martonosi, and Douglas W. Clark. Alloyed Global and Local Branch History: A Robust Solution to Wrong-History Mispredictions. International Journal of Parallel Programming, 31(2), April 2003. Branch Address Global BHR Local BHT Alloyed History PHT Branch Prediction
  • 27. Path History • Sometimes T/NT history is not enough • Path history (PC values) can help if (y == 0) goto C; if (y == 5) goto C; if (y < 12) goto D; if (y % 2) goto E; History = T History = T H is to r y = T T A B C DPath ACD: Branch Address = X Branch History = TT Branch Outcome = Not Taken Path BCD: Branch Address = X Branch History = TT Branch Outcome = Taken
  • 28. Path-Based Branch Predictor • Ravi Nair. Dynamic Path-Based Branch Correlation. International Symposium on Microarchitecture, pages 15-23, December 1995. Branch Address Shift in address atupdate PHT Path History Shift Registers Branch Prediction
  • 29. Dynamic History Length • Branch history length: – Some prefer short history (less training time) – Some require longer history (complex behavior) • Vary history length – Choose through profile/compile-time hints – Or learn dynamically • References – Maria-Dana Tarlescu, Kevin B. Theobald, and Guang R. Gao. Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy. ICCD, October 1996. – Toni Juan, Sanji Sanjeevan, and Juan J. Navarro. Dynamic History-Length Fitting: A Third Level of Adaptivity for Branch Prediction. ISCA, June 1998. – Jared Stark, Marius Evers, and Yale N. Patt. Variable Path Branch Prediction. ACM SIGPLAN Notices, 33(11):170-179, 1998
  • 30. Loop Count Predictors • To predict last loop iteration’s NT branch: – Must have length(BHR) > loop count – Not feasible for large loop counts • Instead, BHR has mode bit – Once history == ‘111…11’ or ‘000…00’ switch to count mode – Now nth entry in PHT trains to NT and predicts nth iteration as last one – Now length(BHR) > log2(loop count) is sufficient • Used in Intel Pentium M/Core Duo/ Core 2 Duo History/CountH/C BHR entry: Mode bit: H – history C – count “1”
  • 31. Understanding Advanced Predictors • Four types of history – Local (bimodal) history (Smith predictor) • Table of counters summarizes local history • Simple, but only effective for biased branches – Local outcome history (correlate with self) • Shift register of individual branch outcomes • Separate counter for each outcome history (M-F vs Sat/Sun) – Global outcome history (correlate with others) • Shift register of recent branch outcomes • Separate counter for each outcome history – Path history (overcomes CFG convergence aliasing) • Shift register of recent (partial) block addresses • Can differentiate similar global outcome histories • Can combine or “alloy” histories in many ways
  • 32. Understanding Advanced Predictors • History length – Short history—lower training cost – Long history—captures macro-level behavior – Variable history length predictors • Really long history (long loops) – Loop count predictors – Fourier transform into frequency domain • Limited capacity & interference – Constructive vs. destructive – Bi-mode, gskewed, agree, YAGS – Read sec. 9.3.2 carefully
  • 33. Perceptron Branch Prediction [Jimenez, Lin HPCA 2001] • Perceptron – Basis in AI concept [1962] – Computes boolean result based on multiple weighted inputs • Adapted for branch prediction – xi from branch history (1 T, -1 NT) – wi incremented whenever branch outcome matches xi – Finds correlation between current branch and any subset of prior branches n y = w0 + ∑ xi wi i=1
  • 34. Perceptrons - Implementation • Complex dot product must be computed for every prediction – Too slow • Arithmetic tricks, pipelining: – Daniel A. Jimenez and Calvin Lin. Neural methods for dynamic branch prediction. ACM Transactions on Computer Systems, 20(4):369– 397, November 2002. – Analog circuit implementation also possible • Key insight: – Not all branches in history are important (correlate) – Perceptron weights learn this
  • 35. Combining or Hybrid Predictors • Select “best” history • Reduce interference w/partial updates • Scott McFarling. Combining Branch Predictors. TN-36, Digital Equipment Corporation Western Research Laboratory, June 1993. Branch Address P0 P1 Branch Prediction Meta-Prediction Branch Address M PApgshare M Branch Prediction
  • 36. Branch Classification • Static (profile-based) branch hints select which prediction to use – Static T/Static NT/Dynamic – PowerPC y-bit overrides static BTFN • P-Y Chang, E Hao, TY Yeh, and Y Patt. Branch Classification: a New Mechanism for Improving Branch Predictor Performance. MICRO, Nov. 1994. • D Grunwald, D Lindsay, and B Zorn. Static Methods in Hybrid Branch Prediction. PACT, October 1998 Branch Address P0 P1 Dynamic Branch Prediction Meta-Prediction M 0 1 Final Branch Prediction Instruction Register Static Branch Hint
  • 37. Multi-Hybrid Predictor • Generalizes selector to choose from > 2 predictors • Marius Evers, Po-Yung Chang, and Yale N. Patt. Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. International Symposium on Computer Architecture, pages 3-11, May 1996. Branch Address = 3 ? = 3 ? = 3 ? Table of Counters Priority Encoder P1 P2 Pn Final Prediction ...
  • 38. Overriding Predictors • Different types of history – E.g. Bimodal, Local, Global (BLG) • Different history lengths (up to hundreds of branches) • How to choose? – Metapredictor/selector? Expensive, slow to train • Tag match with most sophisticated predictor entry – Parallel tag check with B, L, G, long-history G – Choose most sophisticated prediction – Fancy predictors only updated when simple ones fail © Shen, Lipasti 38
  • 39. Multiple History Lengths • Championship Branch Prediction (CBP) – 2 contests, standardized methods and traces • Insight from perceptron BP: – Some branches need short history – Others need very long history • Geometric history length (O-GEHL) [Seznec] – Geometric series of history lengths • Tagged Geometric History Length (TAGE) – Choose longest matching history © Shen, Lipasti 39
  • 40. Branch Target Prediction • Partial tags sufficient in BTB Branch Address Branch ...target tag target tag target tag = = = OR Branch Target Buffer + Size of Instruction Branch Target BTB Hit? Direction Predictor not-taken target taken-target 0 1
  • 41. Return Address Stack • Speculative update causes headaches – On each predicted branch, checkpoint head/tail – Further, checkpoint stack contents since speculative pop/push sequence is destructive – Conditional call/return causes more headaches Branch Address Size of Instruction BTB Target Prediction Return Address BTB Target Predictionis this a return? Branch Address (a) (b)
  • 42. Branch Confidence Estimation • Limit speculation (energy), reverse predictions, guide fetch for multithreaded processors • Q Jacobson, E Rotenberg, and JE Smith. Assigning Confidence to Conditional Branch Predictions. MICRO, December 1996. Branch Address Global BHR XOR Table of CIRs Reduction Function Confidence Prediction
  • 43. High-Bandwidth Fetch: Collapsing Buffer • Fetch from two cache blocks, rotate, collapse past taken branches • Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills and Burzin A. Patel. Optimization of Instruction Fetch Mechanisms for High Issue Rates. International Symposium on Computer Architecture, June 1995. Branch Address Interleaved BTB Cache Bank 1 Cache Bank 2 Two cache line addresses E F G HA B C D E F G H A B C D Interchange Switch Collapsing Circuit Valid Instruction Bits GA B C E To Decode Stage
  • 44. High-Bandwidth Fetch: Trace Cache • Fold out taken branches by tracing instructions as they commit into a fill buffer • Eric Rotenberg, S. Bennett, and James E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. MICRO, December 1996. A B C D E F G H I J A B C D E F G H I J Instruction Cache Trace Cache (a) (b)
  • 45. Intel Pentium 4 Trace Cache • No first-level instruction cache: trace cache only • Trace cache BTB identifies next trace • Miss leads to fetch from level two cache • Trace cache instructions are decoded (uops) • Cache capacity 12k uops – Overwhelmed for database applications – Serial decoder becomes performance bottleneck Trace CacheTrace Cache BTB Instruction Decode Instruction TLB and Prefetcher Front-End BTB Level-Two Unified Data and Instruction Cache Instruction Fetch Queue To renamer, execute, etc.
  • 46. High-Bandwidth Fetch: Loop Buffers • History: AMD29K Branch Target Cache – Don’t cache the target address; cache 4 instructions from the target itself – Avoid accessing I$ for first fetch group following a taken branch – If loop body is <= 4 instructions, effectively a loop cache – Room for 32/64 branch targets • Also common in DSP designs, under s/w control (e.g. Lucent) • Introduced in Intel Merom (Core 2 Duo) – Fetch buffer detects short backward branches, inhibits refetch from I$ • Intel Nehalem (Core i7) – Moved loop buffer after decoders: contains uops • Intel Sandybridge – General-purpose uop cache (not just loops) – 1.5K capacity bc Loop Body Fetch/Decode/ Dispatch Buffer
  • 47. High Frequency: Next-line Prediction • Embed next fetch address in instruction cache – Enables high-frequency back-to-back fetch • Brad Calder and Dirk Grunwald. Next Cache Line and Set Prediction. International Symposium on Computer Architecture, pages 287-296, June 1995. 2A B C D 6E F G H tag tag Target Prediction Target Prediction = Next line misprediction Tag check for cycle 1’s lookup Cycle 1 Cycle 2 next line prediction I J K L Cycle 3 = T a g c h e c k f o r cycle 2’s lookup Target Pred
  • 48. High Frequency: Overriding Predictors • Simple, fast predictor turns around every cycle • Smarter, slower predictor can override • Widely used: PowerPC 604, 620, Alpha 21264 Small, Fast Predictor Instruction Cache Slow Overriding Predictor Stage 1 Stage 2 Stage 3 Predict A PredictA Fetch A Predict A Fetch Queue Predict B Predict B Fetch B PredictB Predict C Predict C Queue A PredictA If slow predict agrees with fastpredict, do nothing If predictions do not match, flush A, B, and C, and restart fetch at newpredicted target Cycle 1 Cycle 2 Cycle 3
  • 49. Advanced Branch Prediction Summary • Control Flow Speculation – Branch Speculation – Mis-speculation Recovery • Branch Direction Prediction – Static Prediction – Dynamic Prediction – Hybrid Prediction • Branch Target Prediction • High-bandwidth Fetch • High-Frequency Fetch

Editor's Notes

  • #6: “squash” on instructions following NT prediction
  • #7: Draw simple CFG, map to sequential, write branch instr. Deviates from implied sequential control flow
  • #8: Alpha 21264, Power 4 (PowerPC 970) use this approach: ROB group has up to 4 instructions x 16 groups (21264) or up to 5 instructions x 20 groups (PowerPC 970)
  • #9: 4 cycles or more to compute condition/target; in Pentium 4 best case is 20 cycles (!)
  • #16: Analogy from Ch. 9: driving, turn left at this intersection 5 days a week to get to work, but Sat/Sun turn right to go the mall? Local history for that intersection will be able to differentiate these cases.
  • #17: Good for loops with low iteration counts - High iteration count: little benefit from predicting the exit (Amdahl’s law)
  • #24: Where do you get biasing bits? Compiler can provide hint, or simply use BTFN
  • #25: Simplification of bi-mode: choice PHT covers common case
  • #31: Increasing loop iteration count =&amp;gt; diminishing return in terms of performance benefit (why?)
  • #35: Large storage requirement (weights) Expensive weighted sum “Compute y”