![Addressing Architecture
• Register-memory type
– ADD R1, A R1 R1+M[A]←
– program lengths and number of memory accesses tend
to be intermediate between the previous two
architectures
• Single-accumulator architecture
– no register file
– significant additional memory accesses would be
needed for complex programs
– inefficient, is restricted to use in CPUs for simple, low-
cost applications](https://image.slidesharecdn.com/memoryaddressing-190205061531/85/Memory-Addressing-6-320.jpg)
Memory Addressing
- 1. Memory Addressing Prof. Neeraj Bhargava Kapil Chauhan Department of Computer Science School of Engineering & Systems Sciences MDS University, Ajmer
- 2. Computer Architecture Concepts • Machine language: binary language • Assembly language: symbolic language • In the past, architecture, organization and hardware are used to descript a computer. • Due to the higher and higher performance of computer, the relationships among architecture, organization and hardware become intertwined. • Instruction set architecture (ISA) is then used to encompass the whole of computer.
- 3. Computer Architecture Concepts Program Counter (PC) keeps track of the instructions in the program stored in memory.
- 4. Addressing Architecture Memory-to-memory PC is the only register 21 accesses to memory needed in the previous example (includes accesses of address, data, instruction) instruction count is low, but the execution time is potentially high
- 5. Addressing Architecture Register-to-register allow only one memory address restrict its use to load and store type needs sizable register file see the program on the top of page 522 in textbook only 18 memory accesses are needed
- 6. Addressing Architecture • Register-memory type – ADD R1, A R1 R1+M[A]← – program lengths and number of memory accesses tend to be intermediate between the previous two architectures • Single-accumulator architecture – no register file – significant additional memory accesses would be needed for complex programs – inefficient, is restricted to use in CPUs for simple, low- cost applications
- 7. PUSH A PUSH B ADD PUSH C MUL PUSH D PUSH E MUL ADD
- 8. Addressing Mode Addressing mode: The rule for interpreting or modifying the address field of an instruction. Effective address: The address of operand produced by the application of the rule for interpreting or modifying the address field of the instruction before the operand is actually referenced.
- 9. Addressing Mode Implied mode: needs no address field, the operand is specified implicitly in the definition of the opcode. For example, ADD in a stack computer. Immediate mode: an instruction has an operand field rather than an address field.
- 10. Addressing Mode Indirect addressing mode: the address field of the instruction gives the address at which the effective address is stored in memory Relative addressing mode: Effective address= address part of the instruction + contents of PC (signed number)
- 11. Addressing Mode Indexed addressing mode: the content of an indexed register is added to the address part of the instruction to obtain the effective address. The indexed register may be a special register in CPU or simply a register in register file. In the application of array, the distance between the beginning address and the address of the operand is the index value stored in the register.
- 12. Stack instructions (push/pop) Reside in memory Due to the negative effects on performance, a stack typically handles only state information related to procedure calls/returns/interrupts. A register holds the address for the stack is called stack pointer (SP).