Nand 4011 design

[CMOS DESIGN] March 8, 2013
DECEMBER 2012 SESSION Page 1
ELECTRICAL ENGINEERING DEPARTMENT
EE603-CMOS INTEGRATED CIRCUIT DESIGN
LAB REPORT 3
Designing Basic Logic Gates and IC
No Registration No. Name
1. 18DTK10F1036 CHONG WEI TING
2. 18DTK10F1034 ADLAN BIN ABDULLAH
CLASS : DTK 6B
LECTURER : EN. MUHAMAD REDUAN BIN ABU BAKAR
DATE SUBMITTED : 8th MARCH 2013
(Date submitted is one week after date lab)
TUANKU SYED
SIRAJUDDIN
POLYTECHNIC
MARKS
Lab Work :
Lab Report:
Total :

LAB 3 : DESIGNING BASIC LOGIC GATES & IC
Aim: Designing NAND gates, then make a cell of IC 4011 using L-edit software.
Objective:
After students had done this laboratory, then students should be able to:
1) Introduce schematic circuit, logic symbols and truth table of NAND gates.
2) Design individual 2-input logic gates (NAND).
3) Design IC4011 (2-input NAND gate).
Apparatus: PC-set & L-edit student V 7.12 software.
This is an AND gate with the output inverted, as shown by the 'o' on the output.
The output is true if input A AND input B are NOT both true: Q = NOT (A AND B)
A NAND gate can have two or more inputs, its output is true if NOT all inputs are true.
Figures: a) Logic Symbol; b) static schematic symbol; and c) truth table of NAND
INTRODUCTION
a) b) c)

Draw the CMOS static logic diagram and stick diagram of
the NAND gate.
NOTES
Metal 1
Metal 2
Poly
P- diffusion
n-diffusion
contact

1. DESIGN INDIVIDUAL NAND GATES
a) Procedure for create new file similar to the previous lab.
b) Combined the both of PMOS in parallel and both of NMOS in series to build a
NAND gates, and then selected the metal2 and drawn overlap to the metal1, we
had done a complete single NAND layout. And label it to identify connection. We
had to follow the properly design rule to avoid the error occurrence.
LAB WORK
ACTIVITY

c) Selected ToolDRC, to ensure that the design does not violating any design
rules.
d) Specify the size and area of NAND logic gates.
Area: 42µm X 35µm=1470

PART 2: DESIGN NAND GATES IC (4011)
a) Selected an individual NAND gates layout, and pressed ctrl+Cctrl+V, and then
drag and moved the copy of second NAND gate to the same position with the
first NAND GATES.
b) Used same method of previous step to build two more NAND gate layout copy,
and then kept the properly arrangement to their own position and made
connection to the metal 2 with each edge of gate. (Always adjust the suitable
length of metal 2, and also always refer design rule for entire layout)

c) Selected ToolDRC, to ensure that the design does not violating any design
rules.
d) Selected the cellNew, to open the new file. Typing the New Cell Name into text
box, then press OK. The new window would appear.

e) Selected CellInstance, and then press “OK” to create a cell of the previous
layout.
f) New cell had been created, and then we had to label of the pin name surround
edge of the NAND cell.

Area: 98µm X 90µm=8820
4 NAND GATE IC 4011

This lab work will consider the complete NAND gates layout that based on IC 4011
Cell that involve four NAND gates is presented, which after completing the lab phase,
we will be able to design an individual 2-input logic gates which is NAND gate based on
given specification design rule.
Before start the design of CMOS layout, we able to recognize schematic circuit,
logic symbols and truth table of NAND gates. In the design process, we will know how
to avoid the CMOS phenomenon such as parasitic for every individual gate, so one of
the typical solution is place substrate tap and well tap as body tap for pull down network
and pull up network/. After an individual NAND gate design, we had able to check their
design rule without any design error, else fix the error well. Finally, we able to instances
the combination of four NAND layout of a small IC block, which is 4011.
CONCLUSION

Nand 4011 design

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Nand 4011 design