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EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Combinational vs. Sequential Logic
Combinational Sequential
Output = f(In) Output = f(In, Previous In)
Combinational
Logic
Circuit
Out
In
Combinational
Logic
Circuit
Out
In
State
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Static Complementary CMOS
VDD
F(In1,In2,…InN)
In1
In2
InN
In1
In2
InN
PUN
PDN
PMOS only
NMOS only
PUN and PDN are dual logic networks
…
…
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
PMOS Transistors
in Series/Parallel Connection
X Y
A B
Y = X if A AND B = A + B
X
Y
A
B Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
PMOS switch closes when switch control input is low
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
X Y
A B
Y = X if A and B
X
Y
A
B Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Threshold Drops
VDD
VDD  0
PDN
0  VDD
CL
CL
PUN
VDD
0  VDD - VTn
CL
VDD
VDD
VDD  |VTp|
CL
S
D S
D
VGS
S
S
D
D
VGS
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Complementary CMOS Logic Style
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Example Gate: NAND
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Example Gate: NOR
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Complex CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Cell Design
 Standard Cells
 General purpose logic
 Can be synthesized
 Same height, varying width
 Datapath Cells
 For regular, structured designs (arithmetic)
 Includes some wiring in the cell
 Fixed height and width
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Standard Cells
In
Out
VDD
GND
In Out
VDD
GND
With silicided
diffusion
With minimal
diffusion
routing
Out
In
VDD
M2
M1
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Standard Cells
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors
In
Out
VDD
GND
Inverter
A
Out
VDD
GND
B
NAND2
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Input Pattern Effects on Delay
 Delay is dependent on
the pattern of inputs
 Low to high transition
 both inputs go low
– delay is 0.69 Rp/2 CL
 one input goes low
– delay is 0.69 Rp CL
 High to low transition
 both inputs go high
– delay is 0.69 2Rn CL
CL
B
Rn
A
Rp
B
Rp
A
Rn Cint
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Transistor Sizing
CL
B
Rn
A
Rp
B
Rp
A
Rn
Cint
B
Rp
A
Rp
A
Rn
B
Rn CL
Cint
2
2
2 2
1
1
4
4
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Transistor Sizing a Complex
CMOS Gate
OUT = D + A • (B + C)
D
A
B C
D
A
B
C
1
2
2 2
4
4
8
8
6
3
6
6
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Ratioed Logic
VDD
VSS
PDN
In1
In2
In3
F
RL
Load
VDD
VSS
In1
In2
In3
F
VDD
VSS
PDN
In1
In2
In3
F
VSS
PDN
Resistive Depletion
Load
PMOS
Load
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT < 0
Goal: to reduce the number of devices over complementary CMOS
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Ratioed Logic
VDD
VSS
PDN
In1
In2
In3
F
RL
Load
Resistive
N transistors + Load
• VOH = VDD
• VOL = RPN
RPN + RL
• Assymetrical response
• Static power consumption
•
• tpL= 0.69 RLCL
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Active Loads
VDD
VSS
In1
In2
In3
F
VDD
VSS
PDN
In1
In2
In3
F
VSS
PDN
Depletion
Load
PMOS
Load
depletion load NMOS pseudo-NMOS
VT < 0
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Pseudo-NMOS
VDD
A B C D
F
CL
VOH = VDD (similar to complementary CMOS)
k
n
V
DD
V
Tn
–
 V
OL
VOL
2
2
-------------
–
 
 
  kp
2
------ V
DD
V
Tp
–
 2
=
VOL VDD VT
–
  1 1
kp
kn
------
–
– (assuming that VT VTn VTp )
= = =
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Pseudo-NMOS VTC
0.0 0.5 1.0 1.5 2.0 2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Vin[V]
V
out
[V]
W/Lp = 4
W/Lp = 2
W/Lp = 1
W/Lp = 0.25
W/Lp = 0.5
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Improved Loads
A B C D
F
CL
M1
M2 M1 >> M2
Enable
VDD
Adaptive Load
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Improved Loads (2)
VDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
A
A
B
B
M1 M2
Differential Cascode Voltage Switch Logic (DCVSL)
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
DCVSL Example
B
A A
B B B
Out
Out
XOR-NXOR gate
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
DCVSL Transient Response
0 0.2 0.4 0.6 0.8 1.0
-0.5
0.5
1.5
2.5
Time [ns]
V
ol
ta
ge[V]
A B
A B
A,B
A,B
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Pass-Transistor Logic
Inputs Switch
Network
Out
Out
A
B
B
B
• N transistors
• No static consumption
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
Example: AND Gate
B
B
A
F = AB
0
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
NMOS-Only Logic
VDD
In
Out
x
0.5m/0.25m
0.5m/0.25m
1.5m/0.25m
0 0.5 1 1.5 2
0.0
1.0
2.0
3.0
Time [ns]
Voltage
[V]
x
Out
In
EE141
© Digital Integrated Circuits2nd
Combinational Circuits
NMOS-only Switch
A = 2.5 V
B
C = 2.5V
CL
A = 2.5 V
C = 2.5 V
B
M2
M1
Mn
Threshold voltage loss causes
static power consumption
VB does not pull up to 2.5V, but 2.5V -VTN
NMOS has higher threshold than PMOS (body effect)

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NMOS Switches in Electrical and Computer Engineering

  • 1. EE141 © Digital Integrated Circuits2nd Combinational Circuits Combinational vs. Sequential Logic Combinational Sequential Output = f(In) Output = f(In, Previous In) Combinational Logic Circuit Out In Combinational Logic Circuit Out In State
  • 2. EE141 © Digital Integrated Circuits2nd Combinational Circuits Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.
  • 3. EE141 © Digital Integrated Circuits2nd Combinational Circuits Static Complementary CMOS VDD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks … …
  • 4. EE141 © Digital Integrated Circuits2nd Combinational Circuits PMOS Transistors in Series/Parallel Connection X Y A B Y = X if A AND B = A + B X Y A B Y = X if A OR B = AB PMOS Transistors pass a “strong” 1 but a “weak” 0 PMOS switch closes when switch control input is low
  • 5. EE141 © Digital Integrated Circuits2nd Combinational Circuits NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y A B Y = X if A and B X Y A B Y = X if A OR B NMOS Transistors pass a “strong” 0 but a “weak” 1
  • 6. EE141 © Digital Integrated Circuits2nd Combinational Circuits Threshold Drops VDD VDD  0 PDN 0  VDD CL CL PUN VDD 0  VDD - VTn CL VDD VDD VDD  |VTp| CL S D S D VGS S S D D VGS
  • 7. EE141 © Digital Integrated Circuits2nd Combinational Circuits Complementary CMOS Logic Style
  • 8. EE141 © Digital Integrated Circuits2nd Combinational Circuits Example Gate: NAND
  • 9. EE141 © Digital Integrated Circuits2nd Combinational Circuits Example Gate: NOR
  • 10. EE141 © Digital Integrated Circuits2nd Combinational Circuits Complex CMOS Gate OUT = D + A • (B + C) D A B C D A B C
  • 11. EE141 © Digital Integrated Circuits2nd Combinational Circuits Cell Design  Standard Cells  General purpose logic  Can be synthesized  Same height, varying width  Datapath Cells  For regular, structured designs (arithmetic)  Includes some wiring in the cell  Fixed height and width
  • 12. EE141 © Digital Integrated Circuits2nd Combinational Circuits Standard Cells In Out VDD GND In Out VDD GND With silicided diffusion With minimal diffusion routing Out In VDD M2 M1
  • 13. EE141 © Digital Integrated Circuits2nd Combinational Circuits Standard Cells A Out VDD GND B 2-input NAND gate B VDD A
  • 14. EE141 © Digital Integrated Circuits2nd Combinational Circuits Stick Diagrams Contains no dimensions Represents relative positions of transistors In Out VDD GND Inverter A Out VDD GND B NAND2
  • 15. EE141 © Digital Integrated Circuits2nd Combinational Circuits Input Pattern Effects on Delay  Delay is dependent on the pattern of inputs  Low to high transition  both inputs go low – delay is 0.69 Rp/2 CL  one input goes low – delay is 0.69 Rp CL  High to low transition  both inputs go high – delay is 0.69 2Rn CL CL B Rn A Rp B Rp A Rn Cint
  • 16. EE141 © Digital Integrated Circuits2nd Combinational Circuits Transistor Sizing CL B Rn A Rp B Rp A Rn Cint B Rp A Rp A Rn B Rn CL Cint 2 2 2 2 1 1 4 4
  • 17. EE141 © Digital Integrated Circuits2nd Combinational Circuits Transistor Sizing a Complex CMOS Gate OUT = D + A • (B + C) D A B C D A B C 1 2 2 2 4 4 8 8 6 3 6 6
  • 18. EE141 © Digital Integrated Circuits2nd Combinational Circuits Ratioed Logic VDD VSS PDN In1 In2 In3 F RL Load VDD VSS In1 In2 In3 F VDD VSS PDN In1 In2 In3 F VSS PDN Resistive Depletion Load PMOS Load (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS VT < 0 Goal: to reduce the number of devices over complementary CMOS
  • 19. EE141 © Digital Integrated Circuits2nd Combinational Circuits Ratioed Logic VDD VSS PDN In1 In2 In3 F RL Load Resistive N transistors + Load • VOH = VDD • VOL = RPN RPN + RL • Assymetrical response • Static power consumption • • tpL= 0.69 RLCL
  • 20. EE141 © Digital Integrated Circuits2nd Combinational Circuits Active Loads VDD VSS In1 In2 In3 F VDD VSS PDN In1 In2 In3 F VSS PDN Depletion Load PMOS Load depletion load NMOS pseudo-NMOS VT < 0
  • 21. EE141 © Digital Integrated Circuits2nd Combinational Circuits Pseudo-NMOS VDD A B C D F CL VOH = VDD (similar to complementary CMOS) k n V DD V Tn –  V OL VOL 2 2 ------------- –       kp 2 ------ V DD V Tp –  2 = VOL VDD VT –   1 1 kp kn ------ – – (assuming that VT VTn VTp ) = = = SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
  • 22. EE141 © Digital Integrated Circuits2nd Combinational Circuits Pseudo-NMOS VTC 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Vin[V] V out [V] W/Lp = 4 W/Lp = 2 W/Lp = 1 W/Lp = 0.25 W/Lp = 0.5
  • 23. EE141 © Digital Integrated Circuits2nd Combinational Circuits Improved Loads A B C D F CL M1 M2 M1 >> M2 Enable VDD Adaptive Load
  • 24. EE141 © Digital Integrated Circuits2nd Combinational Circuits Improved Loads (2) VDD VSS PDN1 Out VDD VSS PDN2 Out A A B B M1 M2 Differential Cascode Voltage Switch Logic (DCVSL)
  • 25. EE141 © Digital Integrated Circuits2nd Combinational Circuits DCVSL Example B A A B B B Out Out XOR-NXOR gate
  • 26. EE141 © Digital Integrated Circuits2nd Combinational Circuits DCVSL Transient Response 0 0.2 0.4 0.6 0.8 1.0 -0.5 0.5 1.5 2.5 Time [ns] V ol ta ge[V] A B A B A,B A,B
  • 27. EE141 © Digital Integrated Circuits2nd Combinational Circuits Pass-Transistor Logic Inputs Switch Network Out Out A B B B • N transistors • No static consumption
  • 28. EE141 © Digital Integrated Circuits2nd Combinational Circuits Example: AND Gate B B A F = AB 0
  • 29. EE141 © Digital Integrated Circuits2nd Combinational Circuits NMOS-Only Logic VDD In Out x 0.5m/0.25m 0.5m/0.25m 1.5m/0.25m 0 0.5 1 1.5 2 0.0 1.0 2.0 3.0 Time [ns] Voltage [V] x Out In
  • 30. EE141 © Digital Integrated Circuits2nd Combinational Circuits NMOS-only Switch A = 2.5 V B C = 2.5V CL A = 2.5 V C = 2.5 V B M2 M1 Mn Threshold voltage loss causes static power consumption VB does not pull up to 2.5V, but 2.5V -VTN NMOS has higher threshold than PMOS (body effect)

Editor's Notes

  • #3: One and only one of the networks (PUN or PDN) is conducting in steady state
  • #6: Why PMOS in PUN and NMOS in PDN … threshold drop NMOS transistors produce strong zeros; PMOS transistors generate strong ones
  • #10: Shown synthesis of pull up from pull down structure
  • #16: Assumes Rp = Rn
  • #17: For class lecture. Red sizing assuming Rp = Rn Follow short path first; note PMOS for C and B 4 rather than 3 – average in pull-up chain of three – (4+4+2)/3 = 3 Also note structure of pull-up and pull-down to minimize diffusion cap at output (e.g., single PMOS drain connected to output) Green for symmetric response and for performance (where Rn = 3 Rp) Sizing rules of thumb PMOS = 3 * NMOS 1 in series = 1 2 in series = 2 3 in series = 3 etc.