On the Impact of Timer Resolution in the Efficiency Optimization of Synchronous Buck Converters

International Journal of Power Electronics and Drive Systems (IJPEDS)
Vol. 6, No. 4, December 2015, pp. 693 – 702
ISSN: 2088-8694 693
On the Impact of Timer Resolution in the Efficiency
Optimization of Synchronous Buck Converters
Pedro Amaral*
, Cândido Duarte**,*
, and Pedro Costa***
*
Faculty of Engineering, University of Porto, Portugal
**
INESC TEC - INESC Technology and Science, Porto, Portugal
***
Infineon Technologies AG, Neubiberg, Germany
Article Info
Article history:
Received Aug 27, 2015
Revised Oct 31, 2015
Accepted Nov 14, 2015
Keyword:
Synchronous buck converter
Dead time
Sensorless optimization
DC/DC converter
Energy efficiency
Timer resolution
Digital controller
ABSTRACT
Excessive dead time in complementary switches causes significant energy losses in DC-DC
power conversion. The optimization of dead time prevents the degradation of overall effi-
ciency by minimizing the body diode conduction of power switches and, as a consequence,
also reduces reverse recovery losses. The present work aims at analyzing the influence of
one of the most important characteristics of a digital controller, the timer resolution, in the
context of dead-time optimization for synchronous buck converters. In specific, the analysis
quantifies the efficiency dependency on the timer resolution, in a parameter set that com-
prises duty-cycle and dead-time, and also converter frequency and analog-to-digital con-
verter accuracy. Based on a sensorless optimization strategy, the relationship between all
these limiting factors is described, such as the number of bits of timer and analog-to-digital
converter. To validate our approach experimental results are provided using a 12-to-1.8V
DC-DC converter, controlled by low- and high-resolution pulse-width modulation signals
generated with an XMC4200 microcontroller from Infineon Technologies. The measured
results are consistent with our analysis, which predicts the power efficiency improvements
not only with a fixed dead time approach, but also with the increment of timer resolution.
Copyright c 2015 Institute of Advanced Engineering and Science.
All rights reserved.
Corresponding Author:
Pedro Costa
Infineon Technologies AG
Am Campeon 1-12 85579 Neubiberg Germany
Email: pedro.costa@infineon.com
1. INTRODUCTION
Digital control has been making inroads in the design of low-power dc-dc converters. Besides the benefits
brought by digital processing on nonlinear control capabilities, reconfigurability, and reduced noise susceptibility [1,
2], other useful functions become feasible with a digitally-controlled power converter. For instance, the ability to
further optimize the energy efficiency, while keeping track of it, is of great value for any power converter system. The
present work addresses specifically this issue, by implementing an algorithm for minimizing specific power losses on
a synchronous buck-converter, and investigating the influence of the main resources on the optimization performance.
In a synchronous buck-converter, a minimum dead time is often required to prevent the occurrence of shoot-
through currents. However, this short time has the side effect of forward biasing the internal body diode in the
synchronous switch, causing high conduction losses. These energy losses can be described as [3]
Ploss = VDIout
td,r + td,f
Ts
(1)
where VD is the diode voltage drop, Iout the output current, Ts the switching period, and td,r and td,f the rising and
falling edge dead times, respectively. Fig. 1 illustrates these control signals together with the schematic for the buck
topology used in this work. A single feedback loop is applied for voltage mode control, with a digital proportional-
integral (PI) controller. The proposed efficiency optimization takes place in the digital domain, following the PI
controller, without the need for significant changes in the feedback structure.

694 ISSN: 2088-8694
[]
Vin
control law
PI
ADC
ton
td,f
vH
vL
PWM
digital
Vdd
Vdd
Vref
optimization
dead-time
td,r
Vout
[]
ton
Ts
vH
vL
td,r td,f
toff
Figure 1. Synchronous buck converter (a) block diagram; and (b) PWM signals with dead time.
Numerous solutions can be adopted for dead-time optimization. The simplest approach relies on a fixed
dead time td. Most gate driving integrated circuits (ICs) and microcontrollers already have complementary PWM
modes with fixed dead time. Nevertheless, as the optimum efficiency varies according to operation conditions (e.g.
load, input voltage, temperature, aging, etc.), the worst condition is often used to define td to avoid shoot-through,
thus the efficiency is not kept maximized. Alternatives to define an optimum dead time imply detecting body-diode
conduction [4], or preventing its occurrence by emulating a diode behavior in the control [5, 6], or by zero crossing
detection of the switching-node voltage (vDS) on the synchronous switch [7]. Although such adaptive methods can
be quite fast – about one switching cycle – their main drawback is the additional hardware required to sense vDS, and
in some cases the control signal vGS as well. If some speed can be sacrificed, an interesting improvement is the so
called predictive delay [3, 4], in which information from the previous cycle is also included in deciding the present
dead time.
Most of the optimization approaches just mentioned make use of supplementary circuitry to sense the voltage
at the switching node. In contrast, sensorless approaches rely only on existent hardware [8, 9, 10]. These methods
make use of parameters being already sensed, such as the output voltage usually acquired for regulation purposes,
or the input current, which is sometimes sensed for current-mode control or circuit protection. In [10], the authors
employ input current sensing to keep track of the maximum efficiency. Optimum conditions for the dead time are
achieved at a minimum input current. Similarly, in [11, 12] the dead times are varied until the duty cycle gets its
minimum value. At this particular point, the losses at the body diode should be minimized, which as a consequence
reduce also the reverse recovery losses. This way the peak efficiency can be tracked without actually measuring it.
In this paper, the impact of the digital controller resources on the efficiency improvement is studied, namely
the timer resolution that affects the dead time and duty cycle accuracies, the resolution of the analog-to-digital con-
version (ADC), input and reference voltages, and the switching period. A dead-time optimization algorithm similar
to [11] is adopted here, for its simplicity and the relatively low computation overhead. The remainder of this paper is
organized as follows. Next section presents the dead-time optimization analysis of the proposed digitally-controlled
synchronous buck-converter, in terms of digital resource usage, operation limits, and attainable improvement. Prac-
tical implementation and prototype measurements are presented in the third section, and final remarks are following
presented, concluding this paper.
IJPEDS Vol. 6, No. 4, December 2015: 693 – 702

IJPEDS ISSN: 2088-8694 695
td ton
tk
Vout
ttk−1 tk+1
regulatedupdatedchanged
Figure 2. Dead time optimization algorithm steps.
2. ANALYSIS OF DEAD-TIME OPTIMIZATION
The proposed buck converter with dead-time optimization is depicted in Fig. 1. The voltage at the output is
sensed by an ADC channel and the feedback control loop is completely performed in the digital domain, whereas the
duty cycle is set by a digital PI controller. When the output is stable, its value is determined by a function of the dead
time and duty cycle, such as follows
Vout = Vin
ton
Ts
− VD
td,r + td,f
Ts
(2)
where Vin is the input voltage and ton/Ts the duty cycle. In fact, the dead time has an opposite effect to the duty cycle
on the output voltage. Nevertheless, if Vout is constant, changing one of these parameters automatically affects the
other. This is actually the essence of some dead-time algorithms [8, 9, 10, 11, 12]. Fig. 2 depicts the three main steps
of a generic algorithm, which can be summarized as follows1
1. At a given time instant tk-1, the dead time td is changed (for simplicity let us assume td,r +td,f = td). Prior to any
compensation in the duty cycle, ∆ton = 0, this change in td will disturb the output voltage, introducing some
variation ∆Vout given by
∆Vout = VD
∆td
Ts
, ∆ton = 0 (3)
2. At tk, the controller detects the output voltage variation and compensates this deviation by changing the duty
cycle accordingly
∆ton = Ts
∆Vout
Vin
, ∆td = 0 (4)
3. At tk+1, the output returns to its regulated value, with the converter now operating with new values both for the
duty cycle and dead time
∆td =
Vin
VD
∆ton, ∆Vout = 0 (5)
The three equations (3)–(5) have been derived derived from (2) and define the set of possible operation points
for the algorithm. This set of points is represented by
r = (∆ton, ∆td, ∆Vout) = ∆ton · (1, Vin/VD, Vin/Ts) (6)
which, geometrically, represents a straight line in IR3
. Naturally, r is limited in domain because the algorithm is
running on a microcontroller with finite resources, in specific the ADC and timer.
2.1. Operation limits
The output voltage variation is only detectable if it is larger than one least-significant bit of the ADC. The
duty cycle and dead time are defined by the PWM signals produced by the timer, which also has a limited resolution.
These constraints can be represented in terms of ADC and timer bits, respectively NADC and Ntimer, given by
∆Vout ≥
Vref
2NADC
(7)
∆td, ∆ton ≥
Ts
2Ntimer
(8)
1The time instants relative to tk are merely indicative of the algorithm states rather than true sequential sample times.
Impact of Timer Resolution in the Efficiency of Synchronous Buck Converters (Pedro Amaral)

696 ISSN: 2088-8694
-0.06-0.05 -0.05-0.04 -0.04-0.03
-0.03-0.02
-0.02-0.01
-0.01
0
0
0
0.01
0.01
0.02
0.02
0.03
0.03
0.04
0.04
0.050.05
0.060.06
Ntimer
2 4 6 8 10 12 14
NADC
2
4
6
8
10
12
14
Figure 3. Contour plot of ϕ for Vref/Vin = 0.275V in terms of number of bits for the timer (Ntimer) and ADC (NADC).
Taking such limitations into account, the minimum dead time variation, ∆td,min, can be expressed as
∆td,min = Ts
Vin
VD
· max
1
2Ntimer
,
Vref
Vin
1
2NADC
(9)
where the minimum operation point guarantees the maximum algorithm resolution. Graphically, the minimum op-
eration point can be determined by simply finding the intersection between the line containing the set of all possible
solutions with one of the three planes that impose the aforementioned constraints.
2.2. Resource utilization
The algorithm operation point is defined by one of two arguments of function max(·) given in (9). Let us now
define the parameter ϕ as the difference between the two arguments so that one can evaluate the usage of resources in
the algorithm
ϕ =
1
2Ntimer
−
Vref
Vin
1
2NADC
(10)
Fig. 3 depicts the contour plot of ϕ given by (10). When ϕ is positive, the minimum dead-time variation ∆td,min is
defined by the first argument in (9) and the optimization is limited by the timer resolution. Conversely, if ϕ is negative,
∆td,min is defined by the second argument and the optimization is limited by the ADC. Such limitation means that,
no matter how much the other resource is improved, ∆td,min will not decrease and the optimization will not improve.
Ideally, in this context, ϕ is null and there are no unused resources, which implies
NADC = Ntimer − log2
Vin
Vref
(11)
Thus, typically, NADC > Ntimer.
2.3. Power efficiency improvement
Considering the minimum algorithm operation point, which yields a dead-time variation of ∆td,min, the power
losses caused by an initial dead time td,ini, Ploss,ini, can be eliminated in power steps
∆Ploss,min = VDIout ·
∆td,min
Ts
(12)

IJPEDS ISSN: 2088-8694 697
γ
0 2 4 6 8 10 12 14 16 18 20
Ψ[inpercentage]
0
10
20
30
40
50
60
70
80
90
100
Exact, (15)
Approximation, (16)
Figure 4. Plots of Ψ(γ) using the floor function and its approximation.
The number of steps necessary to fully eliminate the initial losses can be expressed as
γ =
∆Ploss,min
Ploss,ini
=
∆td,min
td,ini
(13)
Since only an integer number of steps can be taken, i.e. γ , the ratio between eliminated and initial losses, Ψ, can be
expressed as
Ψ =
Ploss,elim
Ploss,ini
=
γ
γ
(14)
The parameter Ψ as a function of γ is depicted in Fig. 4. Note that when γ is an integer, even at small
values, theoretically the losses are completely eliminated. However, this only happens at very precise points. If γ
suffers a slightest variation, the improvement Ψ will drop significantly. An average value can be computed with an
approximation of the floor function · , i.e. x = x − 1
2 + 1
π
∞
k=1
1
k sin (2πkx) x − 1
2 . By substitution of γ, (14)
ends up as
Ψ 1 −
∆td,min
2td,ini
(15)
If (9) is replaced in (15) it is possible to predict the amount of power losses that will be eliminated by a duty
cycle minimizing algorithm, running in a controller with defined resources. Naturally, the loss elimination is closer to
100 % as the resolution of the ADC and timer increase. Fig. 5 illustrates the possible improvements attainable under a
realist scenario.
3. IMPLEMENTATION
The hardware implementation consists of a synchronous buck converter with input-to-output voltage 12-to-
1.8 V and maximum current of 5 A (9 W peak power). A fixed load of 0.5 Ω was used in the experiments. For the
control and dead-time algorithm implementation, an XMC4200 microcontroller unit was adopted, featuring both low-
and high-resolution PWM generation peripherals – the low resolution has a time step of 8.3 ns and high resolution has
a time step of 150 ps. These features allow for a comparison between two different timer resolutions, as well as their
influence in the power efficiency optimization to be performed. A duty-cycle minimizing algorithm was designed in
the microcontroller. Fig. 6 shows the prototype boards used for the experimentation purpose.
3.1. Output voltage control law
The control loop that regulates the output voltage is not only essential to keep the converter operating within
the desired set point, but also because the dead optimization algorithm depends on the minimization of the duty cycle,

698 ISSN: 2088-8694
161412
Ntimer
10864
5
10
NADC
15
100
80
60
40
20
0
Ψ[inpercentage]
Figure 5. Dependency of the efficiency improvement factor Ψ with ADC and timer resolutions for td,ini = 400 ns,
Vin = 12 V, VD = 0.8 V, Vref = 3.3 V and Ts = 1/320 kHz.
Buck
12V input
card connectors
load connectors
XMC4200
Figure 6. Buck converter and XMC prototype boards.
which is defined by this loop. Therefore, the performance of the output voltage control law, namely the settling speed
and the resolution of the duty-cycle value, is reflected directly on the dead-time optimization algorithm.
Firstly, the ADC measures the output voltage and converts it into a 12-bit value. This is fed to a PI controller
that outputs a new duty cycle, a decimal value. The duty cycle is then written to the registers, with possible loss of
precision, depending on the timer resolution. This loop is executed every 20 µs. In each iteration, the average duty
cycle D[n] is calculated using an exponential moving average filter
D[n] = D[n − 1] +
1
M
· d[n] − D[n − 1] (16)
where d[n] is the current duty-cycle value and M is a weighting factor given to the most recent samples – a large

IJPEDS ISSN: 2088-8694 699
time/500us
0 1 2 3 4 5 6 7 8 9 10
deadtime(ns)
0
50
100
150
200
← ←
→
dutycycle(%)
19.0
19.5
20.0
20.5
t d,f
t d,r
duty cycle
Figure 7. The results of the dead time optimization algorithm, running at slow speed.
M means a smoother but slower filtering, while a small value implies a noisier but faster response [13]. In the next
subsection, the usefulness of this value will become clearer.
3.2. Dead-time optimization algorithm
The dead-time optimization algorithm should only be executed when a change in duty cycle is detected,
because for a certain load there is only one optimal dead time (td,opt). This load change is indicated by a variation in
the average duty cycle. When the transient stops, the algorithm is triggered and the optimization can take place.
The algorithm is executed a total of two times, i.e. one for the rising edge dead time and one for the falling-
edge dead time. The dead time is initially set to 200 ns and is decreased with a step ∆td. In every iteration, a delay
allows the duty cycle to settle after the dead-time variation. Then, the gradient is calculated and compared to determine
in which region the current dead time is, i.e.
sign(∆D) = sign(∆td) ⇒ td < td,opt ⇒ diode conduction (17)
sign(∆D) = sign(∆td) ⇒ td > td,opt ⇒ shoot-through region (18)
When the border between regions is crossed, a finer search is initiated by inverting the direction and decreasing the
dead-time step. This is repeated until the stop condition ∆D < ε is fulfilled, where ε is related to the minimum
duty-cycle variation imposed by hardware limits early addressed. For protection purposes, despite of the existence of
current limiting circuitry, a minimum dead time constrain is included in the algorithm to avoid too high currents in the
shoot-through region.
3.3. Results
In order to obtain the data from the microcontroller and illustrate the duty-cycle minimization algorithm
running, a first version has been employed at slow-speed operation. Fig. 7 shows the evolution of the duty-cycle
optimization and respective rising and falling edge dead times. The duty cycle decreases ∼1 %, while both dead times
start from 200 ns and converge to around td,r = 26.5 ns and td,f = 32.0 ns. First td,r is processed and only then td,f is
optimized. It can be noticed that the duty-cycle peaks, which indicate the instants when the algorithm enters the short
circuit region, are small and do not pose risk to the hardware.
The algorithm was then tested at 1/Ts = 320 kHz with two different resolutions in the PWM, a low resolution
of 8 bits and 12.5 ns, and the high resolution of 14.3 bits and 150 ps. The same ADC has been used in both cases
(12 bits and Vref = 3.3 V). In terms of resources, referring to Fig. 3, the high resolution is closer to a null ϕ, i.e.
ϕ 3.84 × 10−3
and ϕ −1.76 × 10−5
, respectively for low and high resolutions. The optimum value achieved for
low-resolution dead time is 25 ns, both for td,r and td,f. An equal value for the two cases denotes the timer limitation,
because of a positive valued ϕ. On the other hand, in the high resolution optimization the dead times converge to
different values, even though superior to the low resolution case.
The initial dead time is set at 200 ns, which is about 80 and 20 times the turn-on and turn-off times of the
power switches, respectively. In these conditions the losses are 368.6 mW on the body diode. Fig. 8 depicts proto-
type measurements with and without the optimization procedure. It is possible to observe the body diode conduction

700 ISSN: 2088-8694
(a)
(b)
Figure 8. Control switch (yellow, 1), synchronous switch (cyan, 2) and switching node voltage (magenta, 3) – (a) fixed
dead time of 200 ns and (b) with the optimization algorithm.
(Fig. 8a), i.e. the negative voltage drops close to the switching node transitions, which is completely eliminated with
dead time optimization (Fig. 8b). Table 1 summarizes the results that were obtained for the two versions. The mea-
surement of the power dissipation at the body diode eliminated by the algorithm (Pelim,measure) has been predicted with
relative accuracy (Pelim,theory) with our simplistic analysis. The absolute and incremental efficiency of the converter
(ηconverter and ∆ηconverter, respectively) has been measured as well as the impact on overall efficiency of the converter
and microcontroller (∆system), denoting also significant improvements. Lastly, the temperatures were also measured
for both the synchronous and control switch. On the fixed dead time implementation, at 200 ns, the package ambient
temperatures were 43.5 ◦
C and 42.5 ◦
C, whereas at optimal dead time, when the losses are minimal, the temperatures
of the MOSFET packages were the lowest, at 40 and 41 ◦
C in low and high resolution implementations, respectively.
When entering the short circuit region, both temperatures increased about 4 ◦
C.
4. CONCLUSION
This work presents a study on the influence of timer and ADC resolutions in the dead-time optimization
of buck converters. An analysis of body diode losses and respective minimization by means of digital control has
been presented. This analysis includes the hardware limitations of a sensorless algorithm for minimizing the duty-
cycle of digital PWM signals. In spite of the low complexity and reduced computation requirements of the similar
sensorless algorithms, most solutions make use of ICs or FPGAs for the implementation of the digital control. The
present approach is completely implemented in a microcontroller unit. The designed algorithm demonstrated about
5 % efficiency improvement over a fixed dead-time solution and 1 % improvements from using low- to high-resolution
PWM signals. These results are significant and may influence the decision of choosing a controller with this kind of
resources for the design of a power supply.

IJPEDS ISSN: 2088-8694 701
Table 1. Experimental results using low- and high-resolution PWM.
Parameter
Resolution
Units
low high
NADC 12 12 bits
Ntimer 8 14.3 bits
td,r,opt 25 27.5 ns
td,f,opt 25 31.3 ns
Pelim,theory 76.5 99.6 %
Pelim,measure 72 98.6 %
∆ηsystem 2.5 3.6 %
∆ηconverter 3.6 4.9 %
ηconverter 95.1 96.1 %
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BIOGRAPHIES OF AUTHORS
Pedro Amaral obtained his Bachelor and Master Degrees in Electrical and Computer Engineering
from Faculty of Engineering, University of Porto (Portugal).
His researches are in fields of power electronics and microcontrollers.
Since 2012 he is with the Microelectronics Student Group in the Department of Electrical and
Computer Engineering. He has served also as Teaching Assistant in the same institution.
Cândido Duarte received the Licenciatura and PhD degrees in electrical and computer engineering
from the Faculty of Engineering of the University of Porto (FEUP), Portugal.
Since 2009 he has been with the Department of Electrical and Computer Engineering Department
at FEUP as a lecturer in courses of electronics, sensors and instrumentation. He is also researcher
at INESC TEC (formerly INESC Porto). His scientific interests include RF power amplifiers, wire-
less transceiver architectures, low-power mixed-signal IC design, and CMOS circuits for mobile
communication systems.
Pedro Costa received the Licenciatura in Electrical and Computer Engineering from the Faculty of
the University of Porto, Portugal.
He has worked in several semiconductor companies since 2005, in the field of integrated circuit
design and definition.
Currently he works for Infineon Technologies, in Munich, Germany, in the area of product definition
and architecture for industrial microcontrollers. His main two fields of expertise are digital power
conversion and electrical motor control.

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