OPAL-RT Distributed Multi-User Laboratories

Jean Bélanger
Typical Multi-User Real-Time
HIL/RCP Simulation Laboratory Configurations
From Nanoseconds to Seconds
From Small isolated systems To Micro Grids
To Large Interconnected Grids
From 200 nanoseconds to 10 milliseconds time step

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TYPICAL MULTI-USER SCALABLE REAL-TIME LABORATORY
OP4510- 4CPU
Lab 1
Lab 13 Lab 12 Lab 11 Lab 10 Lab 9
SFP : optical fiber Tx/Rx links with speed grad of 1 to 5 Gbits/s in each direction
OP4510- 4CPU OP4510- 4CPU OP4510- 4CPU OP4510- 4CPU
OP4510- 4CPU
OP4510- 4CPU
Lab 15
OP4510- 4CPU
Lab 14
OP4510- 4CPU
Lab 7
OP4510- 4CPU
Lab 8
SFP
SFP
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO

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CONTENTS
 Needs for Flexible Multi-User Multi-Domain Real-Time
Laboratories
 OPAL-RT Solutions
 Typical Multi-User Laboratories Configurations
 HIL and RCPArchitecture and Chassis
 Software and Hardware compatibility

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Context and Needs For Multi-User HIL/RCP Labratories
 Multi-User, Flexible, Scalable HIL Real-Time Laboratory
 Several research groups need to conduct several Master and Phd projects
simultaneously to increase productivity
 Some of these projects may need very small simulators capable to
simulate power electronic systems with time step below one
microseconds or power grids with less than 40 3-ph busses at 50
microseconds
 But some projects may require the use of very powerful simulators
capable to simulate large power grids with several hundreds 3-phs busses
 Some projects require very few IO channels while some require very
large number of IO with different signal conditioning and the possibility
to distribute IO over optical fibers
 Consequently, several simulators with different capabilities are need
to meet this needs, which may lead to a solution exceeding available
budgets

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Context and Needs (2)
 Multi-Domain and Multi-Solver Real-time HIL Laboratory
 Some researchers and students would like to work with a simulator like
eMEGAsim deeply integrated with MATLAB and SPS but capable to
simulate large power grids with SPS in real-time as offered by the
ARTEMIS-SSN state-space solver optimized for parallel real-time
simulation
 Other would like to work with specialized power grid tools like
HYPERSIM and EMTP using the classical nodal solver based on prof
Hermann Dommel work. Hypersim implements the nodal solver in
parallel to simulate very large power systems
 The EMT simulation of large distribution systems requires the use of an
advance parallel state-space nodal solvers capable to simulate large
circuits without adding artificial delays as offered by the unique
ARTEMIS SSN state-space nodal solver capable to simulate a
distribution system with up to 600 nodes (1200 states ) in 100 us.

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Context and Needs (3)
 Multi-Domain and Multi-Solver Real-time HIL Laboratory
 The use of real-time phasor-type solvers is required by other researchers
 to develop new wide area special control and protection system
 to analyze the effect of actual communication systems.
 To analyze Cyber security, to develop and test counter measures.
 Such capability is supported by ePHASORsim
 Multi-domain simulation tools such as SimScape, Modelica, CARSIM and
AMEsim are also required to analyze the interaction between electrical,
mechanical and chemical systems. Multi-domain simulation tools are
integrated with eMEGAsim and ePHASORsim
 Fast power electronic systems require the simulation of models on FPGA
with time step below 500 nanos concurrently with other EMT phenomena
expected on large power grids simulated with time step of 50 us on standard
multi core processors
 Consequently, the ideal power system simulator must be very flexible in
order to cover all the needs of a multi disciplinary research team. A single
circuit solver cannot yet be used effectively for all applications. Fast co-
simulation between different type of solvers is required to simulate
complex systems

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OPAL-RT Solution
 (1): Flexible Distributed HIL/RCP Laboratory
 (2): High-Performance CPU and FPGAs
 (3): Electro-magnetic transient (EMT) solvers :
 ARTEMIS-SSN state-space nodel solver
 and HYPERSIM classical nodal solver
 (4): Phasor mode solver: ePHASORsim (rms value)
 (5): FPGA circuit solvers, MMC HVDC models and FPGA user-made
models
 (6): SIMULINK Models and Other Multi-Domain Tools

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OPAL-RT Solution (1): Flexible Distributed HIL/RCP Laboratory
 Several OP4510 or OP5707 HIL and RCP (Rapid Control Prototyping
systems) interconnected by fast optical cable real-time links
 These system can be used independently or interconnected
 Small and affordable OP4510 HIL and RCP systems with four Intel CPU
and one KINTEX-7 XILINX FPGA can be used to make HIL/RCP
stations for each students
 All HIL/RCP station can be interconnected together to perform larger
simulation for system integration studies
 All HIL/HIL stations can be interconnect to a large 16 or 32 CPUs
simulation server capable to simulate large distribution and transmission
systems
 The optical interconnexion system is very flexible and can be modified at
will to meet special needs

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OPAL-RT Solution (2): High-Performance CPU and FPGAs
 Each RCP/HIL system can be selected among the following plateforms:
 OP4510 (2U) 4 Intel 3-GHz CPU, KINTEX-7 FPGA, 4 SFP optical
ports, 96 I/O ch. (4 modules: 16 A/D, 16 D/A, 32 DI, 32 DO)
 OP4510-325: KINTEX-7-325T capable to execute 1 eHS x64 Gen 3
core and to simulate 3000 MMC cells at 500 nanos
 OP4510-410: KINTEX-7-410T capable to execute 2 eHS x64 Gen 3
core and to simulate 3000 MMC cells at 500 nanos with its
controller
 OP5607 (4U) with external industrial PC (4U) with 12 or 16 INTEL CPU
and one VIRTEX 7 high-end FPGA with 16 optical fiber SFP connection
and up to 8 I/O module.
 One high-end Virtex 7 can execute 2 eHS x64 Gen3 cores and more
than 6000 MMC cells at 500 nanos with its controller
 OP5707 (5U) (2016Q1) integrating the computer mother motherboard
with one VITEX-7 and up to 8 I/O modules
 OP5707-4: Four-CPU computer
 OP5707-16 : 16-CPU computer

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OPAL-RT Solution (3): Electro-magnetic transient (EMT) solvers
 User can select RT-LAB-eMEGAsim software pack
 fully integrated with MATLAB, SIMULINK and SimPowerSystems
using ARTEMIS Order-5 solvers to get the maximum accuracy with
the largest time step
 ARTEMIS-SSN also allows to simulate very large circuits wit up to
600-nodes (1200 states) using 4 CPs at 100 micros without adding
parasitic capacitors and inductors.
 Without SSN, users must ad stub-lines, which leads to inaccurate
results in several applications like distribution circuits
 Users can also select HYPERSIM software pack
 using the classical nodal solver optimized for the simulation of very
large AC/DC transmission systems
 Capable to integrate Simulink/SPS sFunctions
 Capable to distribute automatically the simulation over several CPU
 Supporting Intel compatible laptop, workstation, server and SGI
 HYPERSIM software pack includes aslo eMEGAsim software

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OPAL-RT Solution (4): ePHASORsim Advanced Solvers
 User can select RT-LAB-ePHASORsim software pack
 Real-time phasor-mode solver (RMS value)
 Can simulate circuit between 10,000 and 20,000 nodes in reaal-time
with 10 millis time step with only one CPU
 Can simulate more than 30,000 nodes at 11 millis using 10 CPUs
 Positive sequence or phase-by-phase unbalanced circuits
 Interfaced with PSS/e data base for specific models
 fully integrated with MATLAB, SIMULINK to implement advanced
models and control systems
 Interface with Modelica FMU to facilitate the developpement of
models using an open source language
 Users can interface SPS EMT models with ePHASORsim models to
implement hybrid simulation
 Interface with popular comunication systems (DNP3, IEC ..104,
IEC61850, OPC …

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OPAL-RT Solution (5):FPGA circuit solvers,
MMC HVDC models and FPGA user-made model
 Since that all HIL and RCP real-time systems are equiped with powerful
FPGA, users can
 Use eHS circuit solver to implement any type of power electronic
models executed on FPGAs with time step values ranging from 200
nanos to 1 micros
 Interfaced with circuit diagram of SPS, PLEXS, PSIM and
MULTISIM
 Include several examples and tutorials
 All I/O converters are directly connected to the eHS solvers to
provide a very small latency below 2 us between the controller
IGBT firing order and the currents returned on D/A
 The eHS subsystems running on te FPGA can be interconnected
to the slower subsystems running on the main CPU cores at 10 to
50 us
 Users can execute pre-developed MMC modes and controllers
 Users can implement their own signal processing functions and
models with XILINX Syste, Generator

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OPAL-RT Solution (6): SIMULINK Models and Other Multi-Domain Tools
 Users can implement it own SIMULINK models and simulated it in real-
time with only one CPUs or several CPUs using RT-LAB frameworks
 Complex controllers algorithms can be implemented and interfaced with
hundreds of I/Os to interconnect with physical analog benches or virtual
plant models
 Several analog I/Os signal conditioning and optical fiber interfaces
are availables
 SimScape, AMEsim, Modelica, PLECS, PSIM and SPS models can be
interfaced with the Simulink controller or models

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TYPICAL MULTI-USER LABORATORY CONFIGURATIONS
USING SFP OPTICAL FIBER LINKS

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CONFIGURATION SFP-6 Six Independent/inter-connected
Multi-User HIL real-time Laboratory, 3 HIL/RCP per lab.
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO
OP4520-IO
OP4510- 4CPU
Lab 1
OP4510- 4CPU
OP4510- 4CPU
OP4520-IO
OP4510- 4CPU
OP4510- 4CPU
OP4510- 4CPU
OP4520-IO
OP4510- 4CPU
OP4510- 4CPU
OP4510- 4CPU
OP4520-IO
OP4510- 4CPU
OP4510- 4CPU
OP4510- 4CPU
OP4520-IO
OP4510- 4CPU
OP4510- 4CPU
OP4510- 4CPU

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Multi-User HIL real-time Laboratory- Use case 1
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO
OP4520-IO
OP4510- 4CPU
Lab 1
Lab 2
OP4510- 4CPU
OP4510- 4CPU
OP4510 4 Cores
KINTEX-7, 96 I/Os, 4SFP
Power Electronic Bench 1 : RCP and HIL with one OP4510
External controller
(see OP8665
TI controler interface)
See http://opal-rt.com/new-product/op4510-simulator-rt-lab-rcp-hil-system
see http://www.opal-rt.com/new-product/op8665-controller-interface-ti-controller-board
Ethernet Analog I/O

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Multi-User HIL real-time Laboratory – Use case 2
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO
OP4520-IO
OP4510- 4CPU
Lab 1
Lab 2
OP4510- 4CPU
OP4510- 4CPU
OP4510 4 Cores
KINTEX-7, 96 I/Os, 4SFP
Power Electronic Bench 1 : RCP and HIL with two OP4510
HIL Simulator
(Plant model on
CPU or FPGAs)
See http://opal-rt.com/new-product/op4510-simulator-rt-lab-rcp-hil-system
see http://www.opal-rt.com/new-product/op8665-controller-interface-ti-controller-board
Ethernet
HI and RCP
interconnected by
Analog I/O or SFP
Control Prototyping
(controller implemented
on CPU or FPGAs)

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CONFIGURATION SFP-6 15 Independent/inter-connected
(two or more OP4510 RCP/HIL can be used in each lab)
OP4510- 4CPU
Lab 1
OP4510- 4CPU
OP4510- 4CPU
Lab 15
OP4510- 4CPU
Lab 14
OP4510- 4CPU
Lab 7
OP4510- 4CPU
Lab 8
SFP
SFP
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO

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CONFIGURATION SFP-6 Six Independent/inter-connected lab
With a large number of Daisy-Chained Deported IO with OP4520
OP4520-IO -16 OP4520-IO -16
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO
OP4520-IO -16 OP4520-IO -16 OP4520-IO -16
OP4520-IO -2 OP4520-IO -2
OP4510- 4CPU OP4510- 4CPU
OP4520-IO -2
OP4510- 4CPU
OP4520-IO -2
OP4510- 4CPU
OP4520-IO -2
OP4510- 4CPU
Lab 1
1 SFP

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REMOTE I/O CONCEPT
USING SFP and LOW-COST
OPTICAL FIBER LINKS

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REMOTE I/O USING SFP and LOW-COST
OPTICAL FIBER LINKS
A. Why optical fibers
1. To install I/O systems close or inside controller cubicles
a. To decrease cabling cost (installation, testing,
maintenance)
b. To reduce noise
c. To provide galvanic isolation
2. To install I/O systems close to power converters
a. To minimize firing delays
b. To increase security
c. All other reasons as 1 above
C. Why using low-cost optical fiber links in addition to high-
speed SFP
1. To decrease the cost of adding low speed AD, DA and DIO
2. Models update between 10us and 50 us
3. Low-speed IO modules can be designed using low-cost
CPLD/FPGA with persistent memory
B. Why Using Fast SFP for I/O expansion units
1. To add I/O channels with minimum latency for models using
eHS
2. Or other models requiring communication between FPGAs

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Transfer rate required as function of number of IOs
total total
OP4520 DA DO bits 1 10 50 DA ch. D0 ch.
1 16 32 288 288 29 6 16 32
1 64 0 1,024 1,024 102 20 64 -
8 16 32 2,304 2,304 230 46 128 256
8 64 0 8,192 8,192 819 164 512 -
8 0 64 512 512 51 10 - 512
16 16 32 4,608 4,608 461 92 256 512
16 64 0 16,384 16,384 1,638 328 1,024 -
16 0 64 1,024 1,024 102 20 - 1,024
16 0 128 2,048 2,048 205 41 - 2,048
Tranfer rate required
as fuction of nbre of IO and Time step
So one SFP at 4Gbits/s can easily up to 16 OP4520
wih 64 DA (or AD) each or 1024 analog ch in 10 us
plus 2000 static IO
Mbits/s
Tstep (us)

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Use Case 1: Multi-FPGA Power Electronic Bench:
HIL with three Kintex FPGA for large eHS models
OP4510 4 Cores
KINTEX-7-410T,
96 I/Os, 4SFP
HIL Simulator OP4510
(Plant model on
CPU and FPGAs) with eHS
Ethernet
HIL OP4520 Simulator
(Plant model with eHS
HIL OP4520 Simulator
(Plant model with eHS
CONTROLLER UNDER TESTS
(ex 6 NPC INVERTERS connected to the same DC bus)
OP4520
KINTEX-7-410T,
96 I/Os, 4SFP
CPU SIMULINK &
SPS/ARTEMISMODEL
eHS
MODEL
eHS
MODEL
eHS
MODEL
PCIe
SFP SFP (optional)
SFP
Several eHS models interfaced using eHS signals
to achieve minimum latency and accuracy

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Use Case 2: Remote IO configuration with
several OP4520 (or OP4200) connected in Daisy-Chained
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO
OP4520-IO -2
OP4520-1
64DA
SFP : optical fiber Tx/Rx links with speed
grad of 1 to 5 Gbits/s in each direction
OP4520-4OP4520-3
OP4520-IO-7OP4520-8 OP4520-5OP4520-6
A configuration with 8 OP4520 with 64 DA (or AD) requires a total bandwidth of 8 x 102
Mbits/s or 816 Mbits/s if the model time step is 10 us.
The total update time will be about 8 x 200 nanos =1.6 with an SFP at 5 Gbits/s or 3.2
us with an SFP at 2.5 Gbits/s, which is sufficient for a model Tstep of 10 us
1024 bit for 64 DA
1024 Mbist/s if Tstep = 1 us
Or 102 Mbits/s if Tstep = 10 us
(200ns at 5Gbits/s)
Remote I/O and FPGA systems requiring a
2-port switch on each FPGA
Other remote I/O
and FPGA
systems
SFP

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Use Case 3: Remote IO configuration with SFP and Low speed
optical DIO modules interconnected in Daisy-Chained
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO
OP4520-IO -2
OP4520-1
64DA
OP4520-4OP4520-3
1024 bit for 64 DA
(200ns at 5Gbits/s)
Other remote I/O
and FPGA
systems
SFP
• Low cost optical fiber RxTx link (20
to 100 Mbits/s
• Capable to update 64 Static DIO in
less than 4 us (20 Mbits/s)
• Or 128 DIO in less than 10 us
• Good enough for breaker control and
status, OLTC controt and status
• Low-cost DIN-Rail IO modules
OP4xxx
64 DIO
OP4xxx
64 DIO
OP4xxx
64 DIO
OP4xxx
64 DIO
OP4xxx
64 DIO

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Use Case 4: Remote IO configuration with Low speed optical
DIO and AD/DA modules interconnected in Daisy-Chained
OP5707 V7 16 SFP
12, 16,32
or 40 cpu, 256 IO
OP4520-IO -2
OP4520-1
64DA
OP4520-4OP4520-3
1024 bit for 64 DA
(200ns at 5Gbits/s)
Other remote I/O
and FPGA
systems
SFP
• Low cost optical fiber RxTx link (20
to 100 Mbits/s)
• Capable to update 64 Static DIO in
less than 4 us (20 Mbits/s)
• Good enough for breaker control and
status, OLTC controt and status
• Or 16 AD/DA in less than 20 us
• Good enough for analog signals
updated at 20 us or more
• Low-cost DIN-Rail IO modules
OP4xxx
64 DIO
OP4xxx
16 AD
OP4xxx
16 DA
OP4xxx
64 DIO
OP4xxx
16 AD
OP4xxx
16 DA
OP4xxx
16 AD
OP4xxx
16 DA

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OTHER MULTI-USER LABORATORY CONFIGURATIONS
USING SFP OPTICAL FIBER LINKS

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CONFIGURATION SFP-2a 64 cores, 2 V7
Use of SFP optical links between main simulator and large number of remote I/Os
32 cores -1
OP7020-16 SFP-1
OP4520-IO -1
OP4520-IO -2
OP4520-IO -9
SFP
PCIe4x
SIM -1
IO modules
installed in
ABB cubicles
32 cores -1
OP7020-16 SFP-1
OP4520-IO -1
OP4520-IO -2
OP4520-IO -9
SFP
PCIe4x
SIM -2
IO modules
installed in
ABB cubicles
Target Nbre CPU
2 x 12 24
2x 16 (x10) 32
2 x 20 (x10) 40
2x 32 64
2x 40 80

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CONFIGURATION SFP-2b Witht OP4510
Utilisation des liens SFP pour communiquer entre les target et avec les IO remote
32 cores -1
OP4520-IO -1
OP4520-IO -3
SFP
PCIe4x
SIM -1
IO modules
installed in
controller cubicles
32 cores -1
OP4520-IO -6
OP4520-IO -7
SFP
PCIe4x
SIM -2
OP4520-IO -4 OP4520-IO -8
IO modules
installed in
controller cubicles
OP4520-IO -2
OP4520-IO -5
Target Nbre CPU
2 x 12 24
2x 16 (x10) 32
2 x 20 (x10) 40
2x 32 64
2x 40 80
Les grands simulateurs sont
souvent divisés en petits
simulateurs interconectable pour
faire plus de projet en même temps
• Only one PCIe slot used
• Point-to-point
• Synchro integrated witt SFP
• Can scaled up
• From 24 to 80 cpu

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CONFIGURATION SFP-4 (48 to 160 CPUs) – Four Simulators
OP4520-IO -1
OP4520-IO -2OP4520-IO 4
4SFP
OP5707 V7 16 SFP
12 cpu 256 IO
OP5707 V7 16 SFP
cpu, 256 IO
OP5707 V7 16 SFP
256 IO
OP5707 V7 16 SFP
256 IO
2SFP 2SFP
2SFP
2SFP
OP4520-IO 4
Other IO, MMC
Other IO, MMC
Other IO, MMC
Other IO, MMCOther IO, MMC
2SFP 2SFP
3SFP3SFP
10SFP10SFP
10SFP
Target Nbre CPU
4 x 12 48
4x 16 (x10) 64
4 x 20 (x10) 80
4x 32 128
4x 40 160
• No switches
• No adaptor cards
• Minimum latency
• Point-to-point
• Synchro integrated witt SFP
• Can scaled up
• to 16 target with one SFP
per target
• 16 x 40 = 640 cpu !
Le coût sera plus petit qu’avec
DOLPHIN ou INFINIBAND
surtout si les FPGA sont requis
pour les modèle et IO. En fait, le
coût est seulement le coût des
cables optique
Simulateur entre 1M$ et 4M$
selon le nbre de cores, donc
assez rare
Exemple de 4 simulateurs interconnectables
pour faire plus de projets en même temps ou
une grande simulation

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Configuration SFP-16a 16 targets 512 CPUs
4x 32-cores 4 SFP4x32-cores 4 SFP
4x 32-cores 4 SFP 4x 32-cores 4 SFP
IO System IO System
IO SystemIO System
32-cores 4 SFP32-cores 4 SFP
32-cores 4 SFP 32-cores 4 SFP
• Group of 128 CPUs
• Or 160 CPU (4 x40)
• One FPGA with 4 or 8 SFP
in each target
• Four independent lab of 128 CPUs
• 4 x 128 = 512 CPUs
• Or 4 x 160 = 640 CPUs

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HIL and RCP Chassis and Architecture

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OPAL-RT Real-Time Simulators – Main Specifications
Simulator OP4500
OP5600
OP5607
OP7000 OP7020
Size (19’’) 2U (89 mm) 4U (178 mm) 6U (267 mm) 2U (89 mm)
Type
Compact entry-level
system
High-end system with
CPUs, I/Os and
monitoring panel
High-end system with
FPGAs, I/Os and
monitoring panel
FPGA-based
simulator with 16
SFP optical fiber
Target PC 4 CPU cores
OP5600 4 to 12 CPU
OP5607: 12 to 32 CPU
External
FPGA Kintex 7
Spartan 3
Virtex 6 (OP5600)
Virtex 7 (OP5607)
Virtex 6
Virtex 7
FPGA count 1 1 Up to 4 1
Analog I/O count 32 Up to 128 Up to 128 No analog I/O
16 SFP optical fiber
intrfaces
Digital I/O count 64 Up to 256 Up to 256

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OP4500 – High-Performance Architecture
The power electronic market required the highest performance
simulators and RCP systems
but at the lowest cost

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OP4500 – 4-CPU High-Performance Architecture – Multi-
rate
≈ 2 μs
Analog Outputs Digital Inputs
FPGA
CPU
Actual Controller Hardware
Or Prototype Controller
Firing Pulses
Real-TimeSimulator
0.25 μs model step
10 μs to 100 μs model step
≈ 20-30 μs
Complex grid and mechanical
models and controllers
communication systems
Very
Low Latency
IO Interface
Small
time step
For fast
Power
Electronic
Larger
time step
For grid and
mechanical
subsystems
OP4500 – 4-CPU HIL Systems
OP4500 RCP
Prototype Controler
FPGA/Multicore CPU Architecture for HIL and RCP Systems
IO
Interface
4 Intel CPU & KINTEX-7

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OP5600– 12-CPU High-Performance Architecture – Multi-
rate
≈ 2 μs
Analog Outputs Digital Inputs
FPGA
CPU
Actual Controller Hardware
Or Prototype Controller
Firing Pulses
Real-TimeSimulator
0.25 μs model step
10 μs to 100 μs model step
≈ 20-30 μs
Complex grid and mechanical
models and controllers
communication systems
Very
Low Latency
IO Interface
Small
time step
For fast
Power
Electronic
Larger
time step
For grid and
mechanical
subsystems
OP5600 – 12-CPU HIL Systems
OP4500 RCP
Prototype Controller
FPGA/Multicore CPU Architecture for HIL and RCP Systems
IO
Interface
SPARTAN 3, VIRTEX 6, VIRTEX 7
4 Intel CPU
KINTEX 7

Home/contentSee http://www.opal-rt.com/new-product/op7020-chassis
OPAL-RT Real-Time Simulators – OP7020 V7, 16 SFP
Interfaced with an external 4 to 16 CPUs industrial computer – Available since 2014
option 1: One socket 4 CPU (as OP4500),
option 2: Two sockets 6, 12, 16, 20 CPU
(new x10 Motherboard)
Option 3: four sockets, 32 or 40 CPUs
Key Features
Industrial Computer
4, 6, 12, 16 20 or 32/40 CPUs
PCI Express x4
(2 x 20 Gbits/s
O7020 : VIRTEX 7 FPGA
with 16 SFP optical fiber sockets (1 to 5
Gbits/s)
Application:
1) MMC HVDC simulator interfaced with
external controllers using optical fibers
2) Large simulators with distributed HIL and
RCP real-time systems
2U
16 SFP Optical Fiber Interface
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OPAL-RT Real-Time Simulators – OP5607 V7, 16 SFP
Interfaced with an external 4 to 16 CPUs industrial computer – Available since 2014
Back
Connection to external devices
(controllers, plants)
16 DB37 connectors drive all I/O lines
16 channels per DB37 connector
2 wires per signal
DB37 to screw terminal boards available
option 2: Two sockets 6, 12, 16, 20 CPU
(new x10 Motherboard)
Option 3: four sockets, 32 or 40 CPUs
16 SFP
Front
Monitoring of all I/O lines (max 256)
with an oscilloscope
Each RJ45 connector drives 4 signals
These signals can be redirected to the
monitoring panel an its BNC interface
using differential amplifiers
16 SFP
Key Features
Industrial Computer
4, 6, 12, 16 20 or 32/40 CPUs
PCI Express x4 (2 x 20 Gbits/s
4U
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OPAL-RT Real-Time Simulators – OP5707 V7 (5U height)
16 SFP and integrated 4 to 16 CPUs motherboards – Available Q1 2016
MOTHERBOARD 4, 12 or 16 CPU PCI Slot 5
PCI Slot 6
PCI Slot 3
PCI Slot 4ALIM
Front
Monitoring of all I/O lines (max 256)
with an oscilloscope
Each RJ45 connector drives 4 signals
These signals can be redirected to the
monitoring panel an its BNC interface
using differential amplifiers
16 SFP
Back
Connection to external devices
(controllers, plants)
16 DB37 connectors drive all I/O lines
16 channels per DB37 connector
2 wires per signal
DB37 to screw terminal boards available
option 2: Two sockets 6, 12, 16, 20 CPU (new x10 Motherboard)
16 SFP 5U
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40
SOFTWARE A& HARDWARE COMPATIBILITY

OPAL-RT Real-Time Power Systems Simulation Suite
ePHASORsim
eFPGAsim
Wide Area Simulation
Large EMT Simulation
Power Systems & Power
Electronics
Precise Power Electronics
Simulation
Very
large
30 000+
Nodes
Smal
l
<100
Nodes
ModelSize
100 to 500 nanoseconds10 – 15 milliseconds 10 – 50 microseconds
eMEGAsim
HYPERSIM Full waveforms with fast transients (E
SLOW
(100 Hz)
FAST
(20 000 Hz)
VERY FAST
(2 000 000 Hz)
Large
12000+
Nodes
Mediu
m
1000+
Nodes

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Hypersim – EMT
25 to 100 us time step
2500 3-ph busses,
120 cpu, 50 us)Parallel Nodal solver
ePowerGRID and eDRIVEsim Simulator
Product Family
NumberofNodes
20
100
1000
10,000
100,000
20,000
500
Speed/Period of Phenomena
1s 10ms 50us 20us 100ns 20ns1us
Electromagnetic Transient (EMT) Simulation
System and equipment design, control and protection system HIL testing
eMEGAsim EMT
250 3-ph busses, 12 CPU, 50 us)SIMULINK/SPS/ARTEMIS
Parallel State-Space solver
10
Power Electronic
Simulation on FPGA
eHS Nodal Solver
100 ns to 1 us
time step
10 ns resolution
50 nodes/FPGA
I/O Management
eFPGAsim
Phasor (rms) or fundamental frequency simulation
for analysis of electromechanical oscillations and slow phenomena
ePHASORsim
10 t0 20 ms
time step
15 January 2016 42
eDRIVEsim EMT
VSC, Multi-Drive, AC Fed Drives
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Scalable FPGA – Multi-core CPU hardware platform
SGI
SUPER
COMPUTER
Number of processors
OP7000 MULTI FPGA-V6 & IO
OP5600–SP3&V6
MULTI CORE
SIMULATORS
With IO & FPGA
OP4500
eMINIsim
4- Intel CORES
FPGA I/O
4 6 16 32 64 256
cRIO (NI)
ZYNQ
2 ARM CORES
FPGA I/O
2
OP7020-V7 16 SFP
16 /32 Industrial PC
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Software Compatibility
SGI
SUPER
COMPUTER
Nbr of processors
OP7000
MULTI FPGA
IO and
SIMULATORS
OP5600 - 07
MULTI CORE
SIMULATORS
With IO & FPGA
OP4500
eMINIsim
4- Intel CORES
FPGA I/O
4 6 16 32 64 256
ePHASORsim
HYPERSIM
eMEGAsim
RT-LAB
eDRIVEsim
cRIO (NI)
ZYNQ
2 ARM CORE
FPGA I/O
2
eFPGAsim
(eHS solver)
for
undergraduate
tutorial

Connectivity
SGI
SUPER
COMPUTER
Number of processors
OP7000
MULTI FPGA
IO and
SIMULATORS
OP5600 - 07
MULTI CORE
SIMULATORS
With IO & FPGA
OP4500
eMINIsim
4- Intel CORES
FPGA I/O
4 6 16 32 64 256
5 Gbits/s Optical Fibers

46
OP4200 – ZYNQ-ARM- KINTEX 7 HIL/RCP
Dimension: 7.5’’x7’’x7’’
Product Preview (2015Q4
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OPAL-RT Distributed Multi-User Laboratories

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