OVERVIEW OF IC PACKAGING
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The document provides an overview of integrated circuit (IC) packaging, discussing its importance, types, and metrics for good packaging, including electrical and mechanical requirements. It covers various packaging methods such as chip scale packaging (CSP) and wafer level CSP (WLCSP), along with their advantages and disadvantages. Additionally, it highlights the significance of packaging materials and interconnections in relation to performance and application demands.
OVERVIEW OF IC PACKAGING
- 1. OVERVIEW OF IC PACKAGING BASAVARAJ GANGUR 22-04-2015 1
- 2. Agenda Package overview Why package required ? (Purposes) Rent’s Rule Good packaging requirements (Metrics) Packaging materials Package Interconnections Chip Scale Packaging – CSP Wafer level CSP – WLCSP CSP Vs WLCSP Packaging Advantages pf WLCSP Q & A 2
- 3. Package Overview Development of IC package is a Dynamic technology. From mobile telecommunication and satellite broadcasting to aerospace and automotive applications Each imposes its own demands on electronic package. To meet such diverse range of requirements, IC package range encompasses over 30 and more different types. An overview of this range is shown in figure in next slide 3
- 5. Why packaging required? (Purposes) Electrical connections Signals Power and ground Aids heat dissipation Increase effective surface area for increased convection Heat conduction into PC board Physical protection for IC e.g., against breakage Environmental protection Hermetic (airtight) seal e.g., against corrosion or moisture 5
- 6. Rent’s Rule Empirical formula. Rule states that, P = K Gβ P = number of input/output connections (pins) K = Rent’s constant, i.e. average number of I/Os per “gate” G = number of “gates” β = Rent’s exponent, i.e. empirically‐found parameter that varies according to application and technology, generally between 0.1 and 0.7 Rule widely used to estimate the power dissipation in interconnects and number of interconnects. β K Computer (chip) 0.63 1.4 Computer (board) 0.25 82 Static memory 0.12 6 6
- 7. Good packaging requirements (Metrics) Electrical Low capacitance Low inductance Low resistance Mechanical Reliable across temperature variations (thermal expansion matching) Thermal Low thermal resistance to get the heat out Economical (cost) Purchase of package Assembly (chip and board assembly) System (heat removal equipment included) 7
- 8. Package Materials Plastic Low cost Typically requires a custom‐designed package Ceramic Better heat transfer characteristics Generally more reliable More likely an off‐the‐shelf part can be used Good for research and prototyping Factors to be considered Thermal expansion Dielectric constant Interconnect capacitance 8
- 9. Package Interconnections Package to Board connections Through Hole Mount Surface Mount Technology (SMT) Chip to Package connections Wire Bonding Tape Automated Bonding Flip Chip Solder Bump 9
- 10. Through-Hole mount Package Classic approach Involves the use of leads on the components that are Inserted into holes (PTH - Plated Through-Hole) with copper Drilled in printed circuit boards (PCB) Soldered to pads on the opposite side. Chips placed inside the holes Compared to surface mounting techniques, Provides strong mechanical bonds Additional drilling required Makes the boards more expensive to produce. Usually these techniques reserved for bulkier components such as electrolytic capacitors, that require the additional mounting strength. 10
- 12. Surface mount Package It has largely replaced the through-hole technology. Components are smaller and mounted directly on surface of PCB. Chips on both sides of board More wiring room inside PC board Stronger PC board Reduced space between package leads. It has either smaller leads or no leads at all. It may have short pins or leads of various styles, flat contacts, a matrix of solder balls (BGAs). Soldering, Solder paste applied and Heat supplied by intense infrared light, heated air Lower resistance and inductance at the connection 12
- 14. Wire bonding die attached gold or aluminum wires one at a time not entirely repeatable Electrical characteristics: 1. R: low 2. C: low 3. L: ~1 nH/mm 14
- 15. Tape automated bonding (TAB) Die attached to metal lead frame printed on polymer film using solder bumps Tape then connected to package Fast and parallel operation Lower electrical parasitic (R, L, C) 15
- 16. Flip chip solder bump chip placed face down in package connected with solder bumps very low parasitic allows “area pads” pads can cover chip area and are not limited to chip periphery 16
- 17. Chip-Scale Package (CSP) CSP is a single-die, direct surface mountable package with an area of no more than 1.2 X the original die area.. CSP is a type of integrated circuit chip carrier. Any package that meets the surface mount ability and dimensional requirements of the definition is a CSP, regardless of structure. For this reason, CSP's come in many forms flip-chip, Wire bonded, ball grid array, leaded 17
- 18. Wire-Bonded BGA BGA is an acronym for Ball Grid array, as the name suggests its array of balls aligned to grids. Bond pads from top level layout pad ring are stitched to external pad frame with Gold Bond Wires. Further these pins are connected to balls through conductor traces on interpose substrate. 18
- 19. Flip Chip - BGA Here chip/die is flipped. Bond pads in pad ring layout are connected to external ball grid array via conductor traces on layered substrate. During packaging solder bumps are formed on bond pads which align and make contact with conductor traces when flipped. Connect die bond pads to a package substrate without using wire bonds. The bumped die is placed on the package substrate where the bumps connect to the package pins/balls Advantages ● Lower inductance power planes support high frequency designs ● Supports higher pin counts than wire bond packages ● Improved current distribution providing more ability to minimize IR drops (power is distributed through top metal layer metal bumps) 19
- 20. Flip Chip - BGA 20
- 21. Difference of WB BGA and FC BGA 21
- 22. Wafer level CSP (WLCSP) Packaging is done at the Wafer level, and then dicing is performed WLP allows direct connection, without wires, to a PCB by inverting the die and connecting by solder balls. WLP chips are manufactured by building up the package interconnect structure directly on the silicon circuit substrate. A dielectric re-passivation polymer film is applied over the active wafer surface. This film provides both mechanical stress relief for the ball attachment, and electrical isolation on the die surface. Here CSP can be expanded as Chip-SIZE Package 22
- 23. CSP VS WLCSP Packaging In this type of technology packaging is done at the Wafer level, and then dicing is performed 23
- 25. CSP VS WLCSP Wafer level package is different from FC, as FC requires the presence of Interposer substrate . 25
- 26. Advantages & Disadvantages of WLCSP Advantages: WLCSP are a small package size, a minimized IC to PCB inductance and shortened manufacture cycle time. Lighter weight and thinner package profile due to elimination of lead frame and molding compound. No under-fill required. Economical. Disadvantages: Very high I/O IC’s would require very small solder balls on a very tight pitch. Requires very high density PCB to interconnect- expensive. All the IC’s (good and bad) are packaged at the wafer level 26
- 27. References Google webpages : en.wikipedia.org/wiki/ http://www.icproto.com/capabilities-services/ic-packages Document of IC Packages 27
- 28. Q & A THANKS 28