.3mm CSP and LFCSP Reliability

Manufacturability and
Reliability of 0.3mm Pitch Chip
Scale Packages and QFNs
Greg Caswell December 6, 2011
1

Focus on Quality/Reliability/Durability of Electronics
2
Tech
Insertion
Design
Supply
Chain
Warranty
Test
All levels
of the supply chain

Reliability and Next Generation Technologies
o One of the most common drivers for failure is
inappropriate adoption of new technologies
o The path from consumer (high volume, short lifetime) to high rel is
not always clear
o Obtaining relevant information
can be difficult
o Information is often segmented
o Focus on opportunity, not risks
o Can be especially true for
component packaging
o Fine pitch CSP (Chip Scale Packages)
3 3

Solder Wearout
o Design change: More silicon, less plastic
o Increases mismatch in coefficient of thermal expansion
(CTE)
BOARD LEVEL ASSEMBLY AND RELIABILITY
CONSIDERATIONS FOR LNCSP TYPE
PACKAGES, Ahmer Syed and WonJoon Kang,
Amkor Technology.
4 4

Solder Wearout (cont.)
o Hotter devices
o Increases change in temperature (DT)
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0 50 100 150 200
Change in Temperature (oC)
Characteristic Life (Cycles to Failure)
tf = DTn
n = 2 (SnPb)
n = 2.3 (SnNiCu)
n = 2.7 (SnAgCu)
5 5

.3 mm CSP: Why Not?
o .3 mm CSP is a ‘next generation’ technology for non-consumer
electronic OEMs due to concerns with
o Manufacturability
o Compatibility with other OEM processes
o Reliability
o Acceptance of this package, especially in long-life, severe
environment, high-reliability applications, is currently
limited as a result
6 6

Chip Scale Packages
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Wafer Level CSP
Lead Frame Chip Scale Package

Design and Fab Thoughts?
o Board Fabricators
8
o A first step in adapting to .3 mm pitch(12 mil)
o 2 mil traces and spaces
o Why? Bond pad will be .15mm
o 2 mil trace is only size that will fit between
o Most likely use via in pad
o Copper Thickness
o Board fabricators introducing a reduction in copper foil thickness
to work with these smaller components
o Going down to .25 ounce copper – good for lateral etching,
trace width control, uniform trace width.
ISSUE IS REDUCED RELIABILITY DUE TO POTENTIAL FOR TRACE
CRACKING

Fine Pitch CSP Manufacturability: Bond Pads
o Non Solder Mask Defined Pads Preferred (NSMD)
o Copper etch process has tighter process control than solder mask process
o Makes for more consistent, strong solder joints since solder bonds to both tops and sides of pads
o Use solder mask defined pads (SMD) with care
o Can be used to avoid bridging between pads, especially between thermal and signal pads.
o Pads can significantly grow in size based on PCB manufacturer capabilities
NSMD
Images courtesy of Screaming Circuits
9 9

Solder Paste
o Continued reduction in apertures and bond pad dimensions are
10
driving toward Types 5 or 6 shown in the chart to facilitate
.3mm pitch components
o While changes in the solder paste is expected – this move
toward “nanosolder” - the increasing ratio of surface area to
volume in these small particle systems may start to influence
coalescence behavior and storage times as well.

Stencils
o The actual minimum area ratio tends to change for different
11
solder paste types.
o For standard Type 3, the number tends to be 0.66, while pastes
with even smaller powder have minimum area ratios closer to 0.5.
Regardless, for a 0.15 mm (6 mil) bond pad, maintaining either of
these ratios would require stencil thicknesses of less than 4 mil.
o These stencil requirements can be problematic for larger or
non-fine pitch components, which can potentially experience
solder starvation or solder bridging or solder balls (if the
stencil aperture is widened to introduce more paste on pad).
o All of these challenges are, of course, before attempting to
select the type of stencil technology (electroformed or laser cut)
or the process parameters (pressure, speed, etc.).

Manufacturability: Stencil Design
Datasheet says solder paste coverage should be 40-80%
Drawing supplied in same datasheet is for 26% coverage
12 12

Reliability
o As usual, reliability is often the last issue to be considered.
o While minimum modeling or testing has been performed,
13
the relatively small volume of solder and the non-uniformity
of the interconnect geometry (0.15 mm bond
pads on board and 0.075 mm bond pads on package)
could create unique scenarios in regards to solder joint
response to the application of stresses.
o This is in addition to the increasing introduction of mixed
mode (shear and tensile stresses) that are greatly
accelerating creep and fatigue damage accumulation.

.3mm CSP Reliability Conclusions
o While the move to 0.3 mm pitch CSPs will be challenging, there
14
is significant opportunity for leveraging the experiences of
other portions of the supply chain.
o Examples include wafer-level bumping, which has been stencil
printing 0.15mm pitch solder bumps for some time period,
o BGA substrates, which has been using 2 mil width and spacing on
advanced packages, and
o 01005s, which have bond pads only 7 mil wide.
Success will be ensured through adopting the information gained
from these other processes, being aware of the potential gaps in this
knowledge, and implementing industry best practices and physics of
failure to understand margins and interconnect robustness.

LFCSP Manufacturability: Bond Pads
o Can lose solder volume and standoff height through vias in thermal pads
o May need to tent, plug, or cap vias to keep sufficient paste volume
o Reduced standoff height reduces cleanability and pathways for flux outgassing
o Increased potential for contamination related failures
o Tenting and plugging vias is often not well controlled and can lead to placement
and chemical entrapment issues
o Exercise care with devices placed on opposing side of LFCSP
o Can create placement issues if solder “bumps” are created in vias
o Can create solder short conditions on the opposing device
o Capping is a more robust, more expensive process that eliminates these concerns
Images courtesy of Screaming Circuits
Thermal
vias capped
with solder
mask
15 15

Bond Pads
o Extend bond pad 0.2 – 0.3 mm
beyond package footprint
o May or may not solder to cut edge
o Allows for better visual inspection
o Need X-ray for best results
o Allows for verification of bridging,
adequate solder coverage and
void percentage
o Cannot detect head in pillow or
fractures
o Note: Lack of good criteria
for acceptable voiding of the thermal
pad. Depends upon thermal needs.
16 16

Manufacturability: Reflow & Moisture
o LFCSP solder joints are more susceptible to dimensional changes
o Case Study: Military supplier experienced solder separation under LFCSP
o LFCSP supplier admitted that the package was more susceptible to moisture
absorption that initially expected
o Resulted in transient swelling during reflow soldering
o Induced vertical lift, causing solder separation
o Was not popcorning
o No evidence of cracking or delamination in component package
17 17

18
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Corrective Actions: Manufacturing
• Verify good MSL (moisture sensitivity level) handling and
procedure procedures
• Reflow Profile: Specify and confirm
• Room temperature to preheat: maximum 2-3oC/sec
• Preheat to at least 150oC
• Preheat to maximum temperature: maximum 4-5oC/sec
• Cooling: maximum 2-3oC/sec
• In conflict with profile from J-STD-020C which allows
up to 6oC/sec
• Make sure assembly is less than 60oC before any
cleaning processes

Manufacturability: LFCSP Joint Inspection
Goal is 2-3 mils of post-reflow
solder thickness
19 19

Manufacturability: LFCSP Joint Inspection
Convex or absence of fillet highly likely
•Etching of leadframe can prevent
pad from reaching edge of package
•Edge of bond pad is not plated for
solderability
20 20

Manufacturability: Board Flexure
o Area array devices are known to have board flexure
limitations
o In circuit testing (ICT), board depanelization, connector insertion,
manual assembly operations, shock and vibration, etc. are
common causes.
o For SAC attachment, maximum microstrain can be as low as 500
ue
o Use IPC-JEDEC 9701 and 9704 specifications
o .3mm CSPs and LFCSPs have an even lower level of compliance
o Limited quantifiable knowledge in this area
o Must be conservative during board build
o IPC is working on a specification similar to BGAs
21 21

22
2222
Pad Cratering
o Drivers
o Finer pitch components
o More brittle laminates
o Stiffer solders (SAC vs. SnPb)
o Presence of a large heat sink
o Difficult to detect using
standard procedures
o X-ray, dye-n-pry, ball shear, and
ball pull
Intel (2006)

23
2323
Solutions to Pad Cratering
o Board Redesign
o Solder mask defined vs. non-solder mask defined
o Limitations on board flexure
o 750 to 500 microstrain, Component dependent
o More compliant solder
o SAC305 is relatively rigid, SAC105 and SNC are possible
alternatives
o New acceptance criteria for laminate materials
o Intel-led industry effort
o Attempting to characterize laminate material using high-speed
ball pull and shear testing, Results inconclusive to-date
o Alternative approach
o Require reporting of fracture toughness and elastic modulus

Reliability: Thermal Cycling
o Order of magnitude reduction in time to
failure from QFP
o 3X reduction from BGA
o Driven by die / package ratio
o 40% die; tf = 8K cycles (-40 / 125C)
o 75% die; tf = 800 cycles (-40 / 125C)
o Driven by size and I/O#
o 44 I/O; tf = 1500 cycles (-40 / 125C)
o 56 I/O; tf = 1000 cycles (-40 / 125C)
o Very dependent upon solder bond with
thermal pad
QFP: >10,000
BGA: 3,000 to 8,000
LFCSP: 1,000 to 3,000
24 24

Reliability: Bend Cycling
o Low degree of compliance
and large footprint can
also result in issues during
cyclic flexure events
o Example: IR tested a
5 x 6mm LFCSP to
JEDEC JESD22-B113
o Very low beta (~1)
o Suggests brittle fracture, possible along the interface
25 25

26
2626
Electro-Chemical Migration: Details
o Insidious failure mechanism
o Self-healing: leads to large number
of no-trouble-found (NTF)
o Can occur at nominal voltages (5 V)
and room conditions (25C, 60%RH)
o Due to the presence of contaminants
on the surface of the board
o Strongest drivers are halides (chlorides and bromides)
elapsed time
o Weak organic acids (WOAs) and polyglycols can also lead to drops in the
surface insulation resistance
o Primarily controlled through controls on cleanliness
o Minimal differentiation between existing Pb-free solders, SAC and SnCu,
and SnPb
o Other Pb-free alloys may be more susceptible (e.g., SnZn)
12 sec.

Reliability: Dendritic Growth / Electrochemical Migration
o Large area, multi-I/O and low standoff can trap flux
under the LFCSP
o Processes using no-clean flux should be requalified
o Particular configuration could result in weak organic acid
concentrations above maximum (150 – 200 ug/in2)
o Aqueous Cleaning processes will likely experience
dendritic growth without modifications like:
o Increase in water temperature
o Additions of saponifiers or solvents
o Changes to number and angle of impingement jets
27 27

Cleanliness Controls: Ion Chromatography
o Contamination tends to be controlled through industrial specifications (IPC-
28
6012, J-STD-001)
o Primarily based on original military specification
o 10 μg/in2 of NaCl ‘equivalent’
o Calculated to result in 2 megaohm surface insulation resistance (SIR)
o Not necessarily best practice
o Best practice is contamination controlled through ion chromatography (IC)
testing
o IPC-TM-650, Method 2.3.28A
*Based on R/O/I testing
Pauls
General
Electric
NDCEE DoD* IPC* ACI
Chloride (μg/in2) 2 3.5 4.5 6.1 6.1 10
Bromide (μg/in2) 20 10 15 7.8 7.8 15

Thank you!
Any Questions?
Contact me:
gcaswell@dfrsolutions.com
www.dfrsolutions.com
29

.3mm CSP and LFCSP Reliability

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.3mm CSP and LFCSP Reliability