Predicting Reliability of Zero Level Through Silicon Vias (TSV)

Predicting Reliability of Zero-Level
Through Silicon Via (TSV)
© 2004 -–2200011070
Presented by Greg Caswell – DfR Solutions
IMAPS Device Packaging Conference 2012

Through-Silicon-Vias
o Through Silicon Vias (TSV) are the next generation
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technology for system in package devices
o Similar to plated through holes in a PCB
o Promised advantages include
o Thinner packages
o Greater level of integration between active die.
o Process still being optimized and cost must be reduced
for widespread adoption.

TSVs (cont.)
o Concept mentioned in patent
by Harris in 1995 (5682062)
o First patent mentioning TSV
is with Micron in 2002 (6800930)
o Commercial launch is expected
between 2010 and 2014
o Initial focus will be memory stacks
and interposers
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3

TSV (cont.)
TSV is rarely justified by just miniaturization alone
More cost-effective to thin, stack and wire bond
Cost can be 2X-4X price of flip chip ($200/wafer is the goal)
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and 5X-10X the price of wire bonding
TSV will be justified by
performance
Increase in inter-die I/O
Increase in bandwidth
Decrease in
interconnect length
4
http://www.intel.com/technology/itj/2007/v11i3/3-
bandwidth/6-architectures.htm (August 22, 2007)

TSV Processes
o Via First, before Front End of Line (FEOL)
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o Vias etched in bare wafer prior to fab
o Not likely
o Back End of Line (BEOL)
o Via First, before BEOL
o Via Last, after BEOL
o Vias can be created at various stages of the process
o By the wafer provider, IC manufacturer, or packaging house

TSV Process (FEOL)
Ion Etch vias Oxidation Filling (polysilicon)
Polysilicon is used for conductor because it can survive high temp
wafer processing (up to 1000C).
Easily integrated into the wafer process.
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TSV Process – BEOL
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TSV – Via First, Before BEOL
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Via Formation
Two main technologies for “drilling” TSVs
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Dry etching or Bosch etching
Laser
9

Via Formation (Etching)
Developed more than a decade ago for the MEMS industry
Bosch process alternates between short isotropic SF6
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plasma etches for the removal of silicon and short C4F8
plasma deposition steps for sidewall passivation
Current etch rates are approximately 50 um/min
For next generation thinned die, this could allow via formation in
under one minute.
This technology is capable of creating very high aspect
ratio vias with no limit on minimum diameter.
10

Via Formation – Laser drill
Being maskless, the laser process eliminates PR coat,
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expose, develop and strip processing.
The laser process produces sloped sidewalls which are
more conducive to barrier and seed layer deposition
and can “drill” through oxide and nitride layers as well
as Al, Cu, Ni and Ti metallizations.
11

TSV Process (Drilling)
o Currently, laser drilling will likely dominate
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o Initial adoption technology will be memory stacks (see Micron-
IBM press release) and interposers
o Neither require large numbers (10K+) of small diameter
connections.
o Under this configuration, laser drilling is more cost effective
and easier to implement
o CPUs will likely not utilize TSV until 10K+ connections
can be made between die.
o At which point reactive etching may become the technology of
choice.

TSV Drilling Cost
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TSV Process – Insulating
o After via formation, oxide (SiO2) insulation layers are
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typically deposited by CVD using silane (SiH4) or
TEOS.
o If the TSVs are being insulated and filled after chip
fabrication, care has to be taken with the deposition
temperature.
o Typical TEOS deposition processes are in the 275-350°C
range.
o To reduce the deposition temp, one option is the use of
Parylene precursor, which can be deposited at room
temperature, as a conformal organic insulator for TSVs.
14

TSV Process – Filling
o The final step is the filling of the via
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o It is important to know what aspect ratios will be required for
various via diameters both in terms of creating the vias and
filling them.
o Most cost of ownership (CoO) models show that via
formation and via filling are the major cost barriers for
3-D, but this depends on size, pitch and aspect ratio.

How Can Through Silicon Vias (TSV) Fail?
o Three primary failure mechanisms
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o Cracking of the Copper Plating
o Cracking of the Silicon /Change in Resistance of Silicon
o Interfacial Delamination of Via Wall from Silicon
o Challenges
o The exact process and architecture (materials, design) for TSV
has yet to be finalized
o Can lead to large changes in stress state

TSV Design
o Via walls can be straight (etch) or tapered (laser)
o Vias can be filled (likely) or not filled (aka, annular)
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TSV Design
o Depending on Via First or Via Last design layout, TSV
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can have a ‘floor’ of copper
o Also known as Carpeted or Nailheading
S. Barnat et. al., EuroSIME 2010

TSV Materials
o Will the via be filled?
o If yes, with what material?
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o Copper
o Tungsten
o Conductive
polymer
Why Tungsten?
Low CTE mismatch with
Silicon

Via Fill (Tradeoffs)
o Solid Fill (copper, nickel, tungsten, aluminum, etc.)
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o Most robust (fatigue)
o High stress in silicon
o Longest process
o Enhanced thermal performance
o Greater density (think filled microvias)
o Polymer Fill
o Still robust
o Reduced stress in silicon
o Shorter process, more expensive material
o No Fill (annular)
o Least robust
o Lowest stress in silicon
o Fastest process, lowest cost

TSV Materials (cont.)
o The TSV can have a polymer liner
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o Significant reduction in radial stress
K. Lu et. al., SEMATECH 2008

TSV Process
o Is the copper deposited through electroplating or chemical
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vapor deposition (CVD)?
o CVD primarily for small holes (3um dia.), high aspect ratio
o EP for larger holes (5um dia.)
o Will there be an anneal after plating?
o Stress free temperatures can be completely different
o Electroplated copper is stress free near room temperature
(25 – 50C)
o CVD can occur at 400C
o Annealing can occur around 200C
o Lu measured 125C (Via First, before BEOL, no fill)

Cracking of Copper TSV
o Will copper in TSV experience fatigue cracking?
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o Classic circumferential fatigue cracking of copper plating is
currently unlikely for two reasons
o Reason #1: Hole Fill
o Most TSV concepts seem to be moving to a solid plug design
(fully filled)
o A partial fill or plated barrel
likely a process defect
(pinch off due to non-optimized
leveler)

Example: Filled PCB Vias
o Filled PCB vias (copper, solder,
or conductive fill) do not fail
when subjected to temperature
cycling
o KEY EXCEPTION
o Partially filled PCB vias fail faster
due to the presence of a stress
concentration
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Cracking of Copper TSV (cont.)
o Reason #2: Unfilled Via and Compressive Stress
o Unlike in PCB, the ‘matrix’ (i.e., silicon) has a lower coefficient of
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thermal expansion (CTE) than the barrel
o There is also a lower CTE mismatch
o PCB: 50ppm vs. 17ppm (33) / TSV: 2ppm vs. 17ppm (-15)
o If electroplated, stress free state should be at room
temperature
o Any increase in temperature, due to hot spots or change in ambient
conditions, will place the copper
plating under an axial compressive stress
o The tensile stress then arises circumferentially
o Could induce cracking along the length of
the via, but will not cause electrical failure

Cracking of Copper TSV – Possible Exceptions
o Lu claimed very large stresses in the copper plating for
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annular TSV
Lu, Dissertation, UTexas, 2010

Cracking of Copper TSV – Possible Exceptions
o Liu measured (XRD) similar stress levels in filled TSV
Liu, ECTC, 2009
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Note zero stress state

Cracking of Copper TSV – Possible Exceptions (cont.)
o One publication seems to show stress-driven cracking
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of TSV, but little additional information is provided
J. McDonald, Thermal and
Stress Analysis Modeling for 3D
Memory over Processor Stacks,
SEMATECH Workshop on
Manufacturing and Reliability
Challenges for 3D IC’s using
TSV’s, 2008

Cracking of Silicon – Single TSV
o Stresses within the silicon can be computed using plane-strain
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analytical solution known as Lamé stress solution
Cylindrical
Cartesian
xx and s
yy are inplane
stresses
o s
o B is modulus, T is
thermal mismatch strain, r is
TSV radius
o s
r and s
q are radial and
circumferential stresses
o E is modulus, e
T = (af-am)DT
(thermal mismatch strain), Df
is TSV diameter, u is
Poisson’s ratio
Ignores elastic
Lu, Dissertation, UTexas, 2010 mismatch
Zhang, IEEE Trans. ED, 2011

Stresses in Silicon (cont.)
o Are these stresses high enough to cracking
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semiconductor-grade silicon?
o Unlikely
o Fracture strengths of silicon wafers have been reported
between 1 – 20 GPa
Ritchie, Failure of Silicon, 2003
o Some debate about silicon and fatigue
o Dauskardt reports no fatigue behavior
o Ritchie reports fatigue behavior up to 0.5 fracture strength

Cracking of Silicon – TSV Array
o These stresses can be adjusted for a TSV array
o where D is the TSV
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diameter, H is the TSV
height, and S is the
spacing of the TSV array

Cracking of Silicon – TSV Array (cont.)
o Array does not create
a substantial rise in
stress
o Maximum stress is
theoretically 4.66
times that of a single
TSV, but requires very
close spacing
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Resistance of Silicon
o The electrical properties of silicon (piezoresistance) will
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change before it cracks
o Could require a keep out zone (or could improve
performance!)

Interfacial Failure of TSV
o This failure mechanism is the most likely failure mode of
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TSVs
o Very high stresses
o Very complex stresses
o Difficult to measure
material properties
o Key material properties
not controlled
(i.e., fracture strength)

Interfacial Delamination (cont.)
o Analysis by Dudek identified risk of micro cracking and
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delamination problems at the upper via pad in a local
model.
o R. Dudek, et. al., Thermo-Mechanical Reliability Assessment for
3D Through-Si Stacking, EuroSimE, 2009
o Liu found that Cu/SiO2 interfacial cracks and SiO2
cohesive cracks are likely to initiate and propagate at
the corners of electroplated Cu pads, where large
stress gradients and plastic deformation exist
o X. Liu, et. al., Failure Mechanisms and Optimum Design for
Electroplated Copper TSV, ECTC, 2009

Interfacial Delamination
o Interfacial delamination of TSVs was found to be
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mainly driven by a shear stress concentration at the
TSV/Si interface
o Can result in TSV extrusion, fracturing the overlaying
dielectric material
P. Garrou, “Researchers Strive for Copper TSV Reliability,” Semi Int,
03-Dec-2009.

TSV Failures (Summary)
o Ability to predict TSV reliability still in its infancy
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o Hampered by little published test data (primarily simulation)
o Any prediction must taken into account changes in
interfacial material
o Don’t simulate/test nominal; investigate realistic worst-case
o However, there is no need to reinvent the wheel
o A significant amount of relevant material, especially in
regards to interfacial reliability can be found in studies on
fiber-reinforced ceramic composites

Predicting Reliability of Zero Level Through Silicon Vias (TSV)

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