Reliability Modeling of Electronics for Co-designed Systems
- 1. 1/1/2013 1 JANUARY 28-31, 2013 SANTA CLARA CONVENTION CENTER Reliability Modeling of Electronics for Co-Designed System Applications Agenda • Introduction • High Reliability Applications • Common Issues • Lifetime Expectations • Failure Mechanisms • Virtual Qualification Approach • Automated Design Analysis Solution
- 2. 1/1/2013 2 High Reliability Systems are Prevalent in Several Market Segments Solar Power Modules Thermoelectric Modules Automotive Power Modules Switching Power Supply IGBT Street Lighting What Do they All Have in Common? • High Temperature Environments • Possible Vibration and Shock Environments • Temperature and Power Cycling Environments • Very High Current Flows and Thermal Transfer Requirements • A variety of materials forming the product – Substrate tiles bonded to copper baseplate
- 3. 1/1/2013 3 Stringent Environmental Conditions • Being used at varying temperatures or temperature extremes • Having a temperature range of -55°C to 125°C • Being used in an application having a medium to high shock, pressure, vibration, or moisture environment • Being stored for later usage (over 10 years) • Having an application life span of 10 to 25 years Example Life Expectancies • IGBT – Rail application – 30 years (Each module 100FIT) • Power Module – Automotive Application – 20 years – 10W/cm2 – DBC Substrate bonded to heatsink – Vibration, shock, humidity, salt spray – Cost • Solar Power Inverters-25 years • Street Lighting – 15-20 years
- 4. 1/1/2013 4 Failure Mechanisms • Thermo-mechanical fatigue induced failures – CTE mismatch – Temperature swings • Bond Wire Fatigue – Shear Stresses between bond pad and wire – Repeated flexure of the wire – Lift off (fast temperature cycling effect) – Heel Cracking • Die Attach Fatigue • Solder Fatigue – Voids • Device Burn Out • Automotive- degradation of power – Solder Fatigue – Bond wire failure (lift off due to fast temperature cycling) • Structural Integrity – ceramic substrate to heat sink in thermal cycling • IGBTs – solder joint fatigue, wirebond liftoff, substrate fracture, conductor delamination How Can We Resolve these Issues During the Design Phase of a Product? • Utilize an Automated Design Analysis Approach Because: – Mil-HBK-217 actuarial in nature – Physics based algorithms are too time consuming – Need to shorten NPI cycles and reduce costs – Increased computing power – Better way to communicate
- 5. 1/1/2013 5 PoF: the Complexity Roadblock exp(~ 0.063% ) ~ 0.51 exp RH kT eV Tf − × µ E 1 1 1 − = h h L L V 2 2 t ( ) × − c s − ×D × = × + + + + A G G a A G E A E A T L F c c b s s 9 1 1 2 2 2 1 n a a a 1 1 2 2 exp K T T V t B n Common Failure Modes • Wire Bonds Wire bonding has been the most common interconnect for IC packages for over 50 years. The most common materials are gold, aluminum, and more recently copper. The most common bond pad material is aluminum. Wire bonds tend to fail if exposed to elevated temperatures (intermetallic formation), exposure to elevated temperature and humidity (corrosion) and exposure to temperature cycling (low cycle fatigue).
- 6. 1/1/2013 6 Common Failure Modes: PCBs • Printed Wiring Boards have several failure modes that are detrimental to reliable operation. Failures in PCBs can be driven by: • Size (larger boards tend to experience higher temperatures) • Thickness (thicker boards experience more thermal stress) • Material (lower Tg tends to be more susceptible) • Design (higher density, higher aspect ratios) • Number of reflow exposures Common Failure Modes: PCBs Plated Through Hole Failure Mechanisms: voids (left), etch pits (center) and barrel cracking from fatigue (right) Conductive anodic filament (CAF), also referred to as metallic electromigration, is an electrochemical process which involves the transport (usually ionic) of a metal across a nonmetallic medium under the influence of an applied electric field. CAF can cause current leakage, intermittent electrical shorts and dielectric breakdown between conductors in printed wiring boards. PTH voids can cause large stress concentrations, resulting in crack initiation. Etch pits are due to either insufficient tin resist deposition or improper outer-layer etching process and rework. Overstress cracking can occur in the PTH due to a Coefficient of Thermal Expansion (CTE) mismatch which places the PTH in compression.
- 7. 1/1/2013 7 Common Failure Modes: Solder Fatigue • Thermo-Mechanical Fatigue of solder joints is one of the primary wear-out mechanisms in electronic products. This is especially true in products used outside of commercial/ consumer environments where a longer lifetime is required and more severe operating conditions exist. The analysis assesses the fatigue of the solder joints as a function of the stresses applied during its lifetime and provides insight into whether joints are susceptible to failure. Automated Design Analysis • Easy to Utilize • Easy to Locate commands • Industry Terminology – Parts List – Stack-up – Pick and Place – ODB++ – GERBER There are several high levels steps involved in performing an automated design analysis. They are: • Define Reliability Goals • Define Environments • Add Circuit Cards • Import Files • Generate Inputs • Perform Analysis • Interpret Results
- 8. 1/1/2013 8 Reliability Goals Ambient Environment Handles Very Complex Environments
- 9. 1/1/2013 9 Input Design Files Input: Parts List • Color coding of data origin • Minimizes data entry through intelligent parsing and embedded package and materials database
- 10. 1/1/2013 10 Inputs: Stack-Up • Automatically generates stackup and copper percent (%) • Embedded database with almost 400 laminate materials with 48 different properties Analyses • Eight different analyses can be performed. They are: – CAF – Conductive Anodic Filament Formation – Plated Through Hole Fatigue – Solder Joint Fatigue – Finite Element Simulations – ICT Impact – DFMEA – Vibration Fatigue - Natural Frequencies – Mechanical Shock
- 11. 1/1/2013 11 Results: Automated Mesh Generation • Identifies optimum mesh density based on board size • Expert user no longer required; model time reduced by 90% 3D Output The analysis can also establish 3D models by creating a mesh structure and the model from the data input to the analysis.
- 12. 1/1/2013 12 In-Circuit Test Evaluation • Uses embedded FEA engine to compute board deflection and strain cause by ICT fixture DFMEA • Uses ODB++ data including net list to create board level DFMEA • Includes customizable spreadsheets for export
- 13. 1/1/2013 13 Results: Five Different Outputs Unreliability Curves
- 14. 1/1/2013 14 Natural Frequencies Natural Frequencies Identified (1st-upper left), (2nd-upper right), (3rd -lower left) and 4th – lower right) Vibration Strain Levels In addition, the analysis can provide data regarding the strains applied to the circuit board as a function of the vibration stress levels. The left illustrates this data in the XX direction and YY in the right image.
- 15. 1/1/2013 15 What If? Comparison of Sn/Pb (left) and SAC305 (right) with respect to solder fatigue Product Test Plans • Product test plans, also known as design verification, product qualification, and accelerated life testing (though, these are not the same thing), are critical to the successful launch of a new product or new technology into the marketplace. • These test plans require sufficient stresses to bring out real design deficiencies or defects, but not excessive levels that induce non-representative product failure. • Tests must be rapid enough to meet tight schedules, but not so accelerated as to produce excessive stresses. • Every test must provide value and must demonstrate correlation to the eventual use environment (which includes screening, storage, transportation/shipping, installation, and operation).
- 16. 1/1/2013 16 Thank You! Greg Caswell Sr. Member of the Technical Staff DfR Solutions 301-474-0607 (office) 443-834-9284 (cell) gcaswell@dfrsolutions.com