FUNDAMENTALS OF HIGH SPEED DESIGN.pdf
- 1. FUNDAMENTALS OF HIGH SPEED DESIGN CC: Vince Balogh https://www.behance.net/gallery/75625645/Processor ▪ Raghavendra Anjanappa RAGHAVENDRAANJANAPPA FUNDAMENTALS OF HIGH SPEED DESIGN
- 2. AGENDA 1. Fundamental Concepts of High Speed Design 2. Impedance for High Speed Design 3. Stack-up for High Speed Design 4. High speed design workflow & routing guidelines 5. Do’s & Don'ts in high speed design RAGHAVENDRAANJANAPPA FUNDAMENTALS OF HIGH SPEED DESIGN
- 3. WHAT IS A HIGH SPEED DESIGN? Over 50 MHz is “High-Speed” “High-Speed” isn’t related to frequency, it’s a function of rise times A net is “High-Speed” when its round-trip delay is greater than twice its edge-speed A signal is “High-Speed” when it is faster than anything you’ve designed before “High-Speed” occurs when skin effect and dielectric loss effects become important What is a High Speed Design? PCB DESIGNER
- 4. FUNDAMENTAL CONCEPTS OF HIGH SPEED DESIGN
- 5. WHEN DOES A TRACE ACT AS TRANSMISSION LINE? ▪ PCB Trace behaves as a Transmission line when ▪ Where wavelength is in Meters is frequency in MHz ▪ We need to consider the highest frequency of the signal ▪ Signal changes from low to High and High to low in a finite time called Rise/Fall time ▪ Rise time is approximately 7% of signal period ▪ CMOS Technology has Rise time is > Fall time.
- 6. WHY HIGH SPEED PCB? BW = 0.35/Tr Tr is the rise time r r
- 7. SIGNAL PROPAGATION PATH ▪ Signal propagates from Driver to Receiver ▪ Signal Velocity depends on the medium ▪ Time for signal to reach receiver end depends on ➢ Propagation velocity of signal ➢ Length of the Interconnect
- 8. SIGNAL PROPAGATION VELOCITY Where: ▪ Vc is the velocity of light in vacuum or air ▪ Er is the dielectric constant of the PCB material ▪ Ereff is the effective dielectric constant for Microstrips; its value lies between 1 and Er, and is approximately given by: ▪ Signal Speed on Striplines: ▪ Signal Speed on Microstrips::
- 9. SPEED & PROPAGATION DELAY OF PCB MATERIALS ▪ The propagation delay (tpd) is the time delay through the transmission line per unit length tpd =Zo * Co
- 10. HIGH SPEED CURRENT PATH Return Current Path = Shortest Possible Connection High Frequency Current Paths Always Follow the Path of Least Impedance - Not Resistance.
- 11. IMPEDANCE FOR HIGH SPEED DESIGN
- 12. TRANSMISSION LINE IMPEDANCE ▪ The transmission line is modelled with a resistance (R) and inductance (L) in series with a capacitance (C) and conductance (G) in parallel. The resistance and conductance contribute to the loss in a transmission line.. ▪ For a lossless transmission line R & G is 0
- 13. REFLECTION CO EFFICIENT – LOAD ,SOURCE Image Courtesy: Signal and power Integrity – Simplified by Eric Bogatin ▪ The load at the end of some length of a transmission line (with characteristic impedance Z0 ) can be specified in terms of its impedance ZL or its reflection coefficient ρ
- 14. IMPEDANCE CHANGES IN A PCB ▪ Impedance Zo changes with discontinuity ▪ The common discontinuities are ➢ A line width change ➢ A layer change ➢ A gap in return path plane ➢ A connector ➢ A bend T or a stub ➢ The end of a net depends on the output driver
- 15. COMMON IMPEDANCES IN HIGH SPEED DESIGN Trace impedance is completely subjective to silicon chipset manufacturer guidelines and impedance requirements for each trace/interface. ➢42Ω (Single Ended): DDR/LPDDR ➢85Ω (Differential pairs): DDR/LPDDR (MIPI/UFS for Qualcomm) ➢90Ω (Differential pairs): USB, DDR ➢100Ω (Differential pairs): MIPI CSI, MIPI DSI, RJ45-LAN, HDMI ➢50Ω (Single Ended): eMMC, SDIO, SD card, RGMII, DMIC, RF(Wi-Fi-BT), NOR, all Low speed interfaces on board ➢120Ω (Differential pairs): CAN
- 16. WHEN TERMINATION IS REQUIRED? ▪ Reflections result in ringing and stair stepping ▪ False triggering in clock lines, Erroneous bits on data, address and control lines increased jitter and enhanced EM radiations ▪ As a rule of thumb no termination is required if transmission line length propagation time is <0.2XTr. Zd<Zt<Zr<50Ω Zd – Driver Impedance Zt – Transmission Line Impedance Zr – Receiver Impedance
- 17. COMMON TERMINATION SCHEME ▪ SERIES TERMINATION ▪ PARALLEL TERMINATION ▪ RC PARALLEL TERMINATION ▪ THEVININ TERMINATION
- 18. STACKUP FOR HIGH SPEED DESIGN
- 19. WHAT IS EXPECTED OF A HIGH SPEED PCB MATERIAL? ▪ Dimensional Tolerance Stability: The high-speed PCB should have materials that provide mechanical stability when experiencing different temperature ranges, vibrations, shocks, and electric surges. ▪ Superior Thermal Management: The PCB material should provide excellent heat transfer and dissipation without having the layers start to peel away, delaminate, or decompose at high rates. ▪ Enhanced Signal Performance: Signal performance should be constant across the board with little signal loss even when the frequencies increase. The materials should have a low Df to provide this advantage. ▪ Tight Impedance Control: High-speed circuits will require tight control of the impedance routing to maintain a constant dielectric constant (Dk) when there are varying frequency ranges. ▪ Moisture and Chemical Resistance: Select materials that have low absorption rates of moisture and chemicals so there will be little changes to the electrical performance of the PCB. What is expected of a PCB material?
- 20. HOW TO CHOOSE A MATERIAL FOR A HSD? ▪ IPC 4101C is the standard for PCB material selection with more then 55 materials to choose ▪ The key points to be considered when selecting a PCB material are ➢Application of the product ➢Know the operating conditions of the product ➢What cost implications will the material have? ➢Make sure that the material is available with your manufacturer ➢Ensure that the material is RoHS Compliant – Tg ➢For Gbps designs have a look at the dielectric loss – Tan δ or Df Material must expand in the Z direction. The CTE along the Z axis should be as low as possible; aim for less than 70 ppm per degree Celsius ▪ Df – Dissipation factor
- 21. HIGH SPEED DESIGN MATERIAL PROPERTIES
- 22. HIGH SPEED DESIGN WORKFLOW & ROUTING GUIDELINES
- 23. HIGH SPEED DESIGN WORKFLOW
- 24. INTER VS INTRA PAIR SKEW
- 25. SERPENTINE TRACE GEOMETRY ▪ For example the width of the trace(W) is 6 mils and the distance between the differential pair(A) is 8 mils. These mean that the width of the serpentine(B) is at least 16 mils and the length of C is at least 18 mils. + -
- 26. RETURN PATH ▪ An electrical circuit must always be a closed loop system. With DC, the return current takes the way back with the lowest resistance for DC signals. ▪ High Frequency Return Path SIGNAL PATH RETURN PATH
- 27. ROUTING ACROSS A SPLIT PLANE ▪ High-speed signals should be routed over a solid GND reference plane and not across a plane split or a void in the reference plane unless absolutely necessary SIGNAL PATH RETURN PATH
- 28. AC CAPACITOR ACROSS A SPLIT PLANE ▪ If routing over a plane-split is completely unavoidable, place stitching capacitors across the split to provide a return path for the high-frequency current. These stitching capacitors minimize the current loop area and any impedance discontinuity created by crossing the split. These capacitors should be 1 µF or lower and placed as close as possible to the plane crossing. SIGNAL PATH RETURN PATH
- 29. ROUTING ACROSS DIFFERENT REFERENCE PLANES ▪ It is best to avoid routing across different reference planes because it can cause impedance issues as well as EMI issue. Do not change the reference plane of the high speed signal trace unless completely unavoidable. SIGNAL PATH RETURN PATH ▪ If routing across different reference planes cannot be avoided use AC Capacitors to allow the return current to have a pathway.
- 30. DIFFERENTIAL PAIR VIA RETURN PATH WITHOUT GND VIAS ▪ Any high-speed signal trace should maintain the same GND reference from origination to termination. If unable to maintain the same GND reference, via-stitch both GND planes together to ensure continuous grounding and uniform impedance. Place these stitching vias symmetrically within 200 mils (center-to-center, closer is better) of the signal transition vias SIGNAL PATH RETURN PATH
- 31. DIFFERENTIAL PAIR VIA RETURN PATH WITH GND VIAS SIGNAL PATH RETURN PATH
- 32. VCC REFERENCE PLANE ▪ High-speed signal references to power planes unless it is completely unavoidable. If it is unavoidable it is best to use AC coupling capacitors and ground vias to allow the return signal to have a path back from the sink to the source. Figure below depicts the use of AC coupling capacitors and ground vias for the return path SIGNAL PATH RETURN PATH
- 34. HIGH SPEED DIFFERENTIAL SIGNAL RULES ▪ Do not place probe or test points on any high-speed differential signal. ▪ Do not route high-speed traces under or near crystals, oscillators, clock signal generators, switching power regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals. ▪ After BGA breakout, keep high-speed differential signals clear of the FPGA because high current transients produced during internal state transitions can be difficult to filter out. ▪ When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an adjacent GND layer. We do not recommend stripline routing of the high-speed differential signals. ▪ Ensure that high-speed differential signals are routed ≥ 90 mils from the edge of the reference plane. ▪ Ensure that high-speed differential signals are routed at least 1.5 W (calculated trace-width × 1.5) away from voids in the reference plane. This rule does not apply where SMD pads on high-speed differential signals are voided. ▪ Maintain constant trace width after the SoC FPGA escape to avoid impedance mismatches in the transmission lines. ▪ Maximize differential pair-to-pair spacing when possible.
- 35. SYMMETRY IN THE DIFFERENTIAL PAIRS
- 36. CONNECTORS AND RECEPTACLES ▪ High speed differential signal connections to the receptacle on the bottom layer of the PCB. Making these connections on the bottom layer of the PCB prevents the through-hole pin from acting as a stub in the transmission path ▪ For surface-mount receptacles such as USB Micro-B and Micro-AB, make high-speed differential signal connections on the top layer. Making these connections on the top layer eliminates the need for vias in the transmission path. For examples of USB through-hole receptacle connections. Signal coming from the middle of the PCB :Signal coming from the top of the PCB Signal Coming from the bottom of the PCB
- 37. VIA DISCONTINUITY MITIGATION ▪ A via presents a short section of change in geometry to a trace and can appear as a capacitive and/or an inductive discontinuity. These discontinuities result in reflections and some degradation of a signal as it travels through the via. Reduce the overall via stub length to minimize the negative impacts of vias (and associated via stubs). ▪ Because longer via stubs resonate at lower frequencies and increase insertion loss, keep these stubs as short as possible. In most cases, the stub portion of the via present significantly more signal degradation than the signal portion of the via LONG STUB SHORT STUB
- 38. BACKDRILL STUBS ▪ Back-drilling is a PCB manufacturing process in which the undesired conductive plating in the stub section of a via is removed. To back-drill, use a drill bit slightly larger in diameter than the drill bit used to create the original via hole. When via transitions result in stubs longer than 15 mils, back-drill the resulting stubs to reduce insertion losses and to ensure that they do not resonate.
- 39. TRACE STUBS ▪ For high speed signals it is important to minimize stubs on high speed traces to reduce increase insertion loss. Figure below depicts a high speed trace with a component on a stub. This stub can be reduced to:
- 40. INCREASE VIA ANTI-PAD DIAMETER ▪ Increasing the via anti-pad diameter reduces the capacitive effects of the via and the overall insertion loss. Ensure that anti-pad diameter for vias on any high-speed signal are as large as possible
- 41. SURFACE-MOUNT DEVICE PAD DISCONTINUITY MITIGATION ▪ Avoid including surface-mount devices (SMDs) on high-speed signal traces because these devices introduce discontinuities that can negatively affect signal quality. When SMDs are required on the signal traces (for example, the USB SuperSpeed transmit AC coupling capacitors) the maximum permitted component size is 0603. using 0402 or smaller is recommended. Place these components symmetrically during the layout process to ensure optimum signal quality and to minimize reflection. For examples of correct and incorrect AC coupling capacitor placement.
- 42. DO’S & DON’T’S IN HIGH SPEED DESIGN
- 43. ROUTING THROUGH ANTI-PADS DO NOT ROUT TRACES BY ANTIPADS WITHOUT ANY OVERHANG ENSURE 3 MIL OF GND PLANE OVERHANG WHEN ROUTING THROUGH ANTIPADS
- 44. JOINING ANTI-PADS 1 DO NOT JOIN ANTIPAD VOIDS TOGETHER SEPARATE THE VIA PAIRS SO THAT THE ANTIPAD VOIDS DO NOT JOIN
- 45. JOINING ANTI-PADS 2 THE SPACE BETWEEN THE P & N SIGNALS IS LARGER THAN THE SPACE TO THE NEXT PAIR THIS WILL INCREASE THE CROSSTALK BETWEEN THE DIFFERENTIAL PAIRS.C ARRANGE THE PINS IN GND - S – S - GND FORMAT. USE THE GND PINS TO ACHIEVE ISOLATION BETWEEN THE DIFFERENTIAL PAIRS.
- 46. TOO CLOSE ANTI-PADS ANTIPADS TOO CLOSE CAUSING NO GND PLANE FOR DIFFERENTIAL PAIRS REDUCE THE SIZE OF THE ANTIPAD TO ALLOW ADEQUATE GND PLANE OVERHANG
- 47. SKEW COMPENSATION - 1 THIS METHOD OF INCREASING LENGTH CAUSES CROSSTALK AND IMPEDANCE ISSUES FOR ANY SIGNAL ABOVE 500MHz LENGTHEN THE TRACE WITHIN THE ANTIPAD REGION AS SHOWN
- 48. SKEW COMPENSATION - 2 LENGTH MATCHING AT MATCHED ENDS LENGTH MATCHING AT MISMATCHED ENDS
- 49. SMT PAD TRANSITION NO GND VIAS FOR THE DIFFERENTIAL PAIR NO CLEARANCE UNDER PADS GND VIAS ADDED AS PER RECOMMENDAIONS FROM SI SIMULATIONS CLEARANCE UNDER PADS ON ADJACENT PLANE LAYER ONLY INCREASE IMPEDANCE FOR A BETTER MATCH FOR 100 OHMS
- 50. RELIEF UNDER AC CAPS ADD A RELIEF UNDER AC CAPACITORS ON THE ADJACENT GND PLANE TO INCREASE IMPEDANCE FOR 0402 CAPS ON 1MM PITCH Relief can be individual rectangular or a full rectangle encompassing both capacitors. This has to be verified by simulating since its stack-up and material dependent
- 51. THERMAL RELIEF ON PRESS FIT CONNECTOR DO NOT USE THERMAL RELIEFS ON PRESS FIT CONNECTORS CHANGE THERMAL RELIEFS TO DIRECT CONNECTION TO THE PLANES
- 52. TRANSITION GND VIAS NO GND VIAS FOR THE DIFFERENTIAL PAIR GND VIAS TO BE ADDED AS PER THE SI SIMULATION RESULTS
- 53. SMT PAD RECTANGULAR OR OVAL ANTI-PADS ON HIGH SPEED CONNECTORS TRANSITION DO NOT USE SIMPLE ROUND ANTIPADS ON HIGH SPEED CONNECTORS CHANGE TO RECTANGULAR OR OVAL SHAPE AS PER THE SI SIMULATION RESULTS
- 54. ROUTING OVER GROUND PLANE EDGES DO NOT ROUT OVER AND GROUND PLANE EDGE Move the etch away from the ground plane edge or increase the size of the ground plane edge. Differential Pair should be > 30 mil (8H) from edge of plane. H = Distance from signal layer to reference plane layer
- 55. DIFF PAIRS NOT CENTERED IN ROUTING CHANNELS DIFFERENTIAL PAIR RUNNING OVER ANTIPAD EDGES DIFFERENTIAL PAIR CENTERED IN THE CHANNEL