Pression Discrete Wavelet Transformer Architecture Design

PRECISION-OPTIMIZED SELF QUANTIZING
ARCHITECTURE FOR DWT
Guided By
Ms. E. Priya, M.E.,
AP /ECE
Kaliyaperumal
ME(CS)
MCE

ABSTRACT
• Designed VLSI Architecture for DWT.
• It has digit-serial (DS) precision-optimized implementations of the discrete
wavelet transform (DWT).
• Specific consideration given to the impact of depth (the number of levels
of DWT) on the overall computational accuracy.
• By using the bi-orthogonal lossless 9/7 filter banks, the proposed VLSI
architecture for lossless JPEG 2000
• Energy-minimal implementation, which increases the applicability of
DWT-based algorithms.

INTRODUCTION
• DWT: recursively decomposes an input image into sub bands with
different spatial frequency and orientation.
• Quantization in DWT: Quantization is a key element for the DWT in
governing Achievable compression performance. The JPEG 2000 standard
supports uniform dead-zone quantization, as well as Trellis coded
quantization
• Bit-parallel Architecture: It has integer bit-width (IB) and fractional bit-
width (FB) determination for Lifting Steps.
• Digit-serial Architecture: In a DS implementation, increasing the number
of iterations gives more precision and DS arithmetic has a significant
advantage over BP in terms of circuit area
• 5/3 and 9/7 DWT: They are mostly used DWT Filters in JPEG 2000 Std.,
9/7 integer is the biorthogonal lossless filter banks and lossy 5/3 floating-
point filter banks

EXSISTING SYSTEM
• Fixed bit-width approach Architecture (24 bit
data path for 2 level DWT)
• There is no Lifting approach for 9/7 wavelet
filter.
• 9/7 DWT implemented via convolution based
method.
• Some existing systems are used 5/3 Wavelet
filter (Lossy output).

PROPOSED SYSTEM
• Our system has high precision and variable bit
width according to DWT requirement.
• Proposed system has Lifting approach for 9/7
wavelet filter.
• Lifting approach reduce the computation and
memory requirements.
• Reduce the critical path by flipping
computation units.

MODULES
• It has 3 modules, Digit Series DWT, Dual Port
Buffer and Controller and ROM
• DS DWT has 1-D 9/7 DWT Filter and Lifting
process for quantization.
• Buffer and Controller used to store the data
and manage the over all process of filter.
• ROM is used to store the input data.

DS 1-D 9/7 DWT
• The incoming two’s complement data is first
serialized and then passed into the DS DWT.
• DS DWT is partitioned into nine pipeline
stages that run in parallel.
• This approach reduces the memory
• Both Serial Data (SD) addition and
multiplication produce one digit per cycle.

DUAL PORT BUFFER AND
CONTROLLER
• The dual-port buffer is large enough to hold
two data frames.
• It is used to store the original raw data,
intermediate data, and/or the final transformed
data.
• The controller manages the overall operation
for the buffer and the filter.

ROM
• Read Only Memory it is used for storing the
values
• It initiate the input Values.
• Mainly in this project we are giving input by
using ROM.

Phase 1 of Project Work
• In Phase-1, the existing systems are studied and part of the
9/7 DWT architecture implemented.
• The Lifting coefficients are determined using 9/7 filter
expression
Where α = -1.5861, β=-0.0529,γ=0.8829,δ=0.4435 and ζ=1.1496
• Multiplier coefficients are C0=1/ α, C1=1/(α β), C2=1/(β γ), C3=1/(γ
δ),C4= α β δ/ ζ and C5= α β γ δ ζ

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
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
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

/
1
0
0
1
)
1
(
0
1
1
0
)
1
(
1
1
)
1
(
0
1
1
0
)
1
(
1
)
(
1
1
z
z
z
z
z
P

Lifting Approach and Flipping Structure
• The DWT produce LL1, HL1, LH1 and HH1.
• In Second level DWT the sub bands LL2,HL2,LH2 and HH2
are generated.
• The poly phase matrix P(z) formed with the help of sub
bands.
• Then it is split into odd and even.
• Flipping structures shares the same computational with the
lifting scheme.
• It reduce the critical path by Flipping units with inverse of
multiplier coefficients
• Then the output si(smooth) and di(detail) are obtained
after the 9/7 DWT filter processing with the help of
coefficients.

Lifting Approach and Flipping
Structure…

Simulation Output
• BUFFERWITH CONTROLLER:

Merits
• Improve the in hardware resources
• Improve the execution time
• Avoiding overflows

Comparison of Result
Perticulars 9/7 DWT
Architecture[
10]
Self
Quantized 9/7
DWT[1]
This
Work
Area [gates] 17450 18680 14613
Clock Speed 152 MHz 435 MHz 557 MHz
Processing Time 65.7ms 29.8ms 18ns
Total Power No info. 25.2 mW 19 mW

Conclusion
• Highly flexible configurable DWT architecture.
• Low power and high speed DWT processor for
jpeg 2000.
• Increasing the number of iterations gives
more precision but it will take more execution
time.
• In future, it can be implemented for multi
level DWT and more precision.

REFERENCE
[1] Dong-U Lee, Lok-Won Kim, John D. Villasenor, “Precision – Aware Self-Quantizing
Hardware Architectures for the DWT” IEEE Trans. Image Processing, Vol.21 no.2,
Feb.2012.
[2] M. Rabbani and R. Joshi, “An overview of the JPEG 2000 still image compression
standard,” Signal Process.: Image Commun., vol. 17, no. 1, pp. 3–48, Jan. 2002.
[3] C. Huang, P. Tseng, and L. Chen, “Flipping structure: An efficient VLSI architecture for
lifting-based discrete wavelet transform,” IEEE Trans. Signal Process., vol. 52, no. 4,
pp. 1080–1089, Apr. 2004.
[4] K. Kotteri, S. Barua, A. Bell, and J. Carletta, “A comparison of hardware
implementations of the biorthogonal 9/7 DWT: Convolution versus lifting,” IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 52, no. 5, pp. 256–260, May 2005.
[5] C. Cheng and K. Parhi, “High-speed VLSI implementation of 2-D discrete wavelet
transform,” IEEE Trans. Signal Process., vol. 56, no. 1, pp. 393–403, Jan. 2008.
[6] B.Wu and C. Lin, “A high-performance and memory efficient pipeline architecture for
the 5/3 and 9/7 discretewavelet transform of JPEG2000 codec,” IEEE Trans. Circuits
Syst. Video Technol., vol. 15, no. 12, pp. 1615–1628, Dec. 2005.
[7] C. Xiong, J. Tian, and J. Liu, “Efficient architectures for two-dimensional discrete
wavelet transform using lifting scheme,” IEEE Trans. Image Process., vol. 16, no. 3, pp.
607–614, Mar. 2007.
[8] N. Mehrseresht and D. Taubman, “An efficient content-adaptive motion-
compensated 3-D DWT with enhanced spatial and temporal scalability,” IEEE
Trans. Image Process., vol. 15, no. 6, pp. 1397–1412, Jun. 2006.

[9] S. Barua, K. Kotteri, A. Bell, and J. Carletta, “Optimal quantized lifting coefficients for
the 9/7 wavelet,” in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., 2004, vol.
5, pp. 193–196.
[10] V. Spiliotopoulos, N. Zervas, Y. Andreopoulos, G. Anagnostopoulos, and C. Goutis,
“Quantization effect on VLSI implementations for the 9/7 DWT filters,” in Proc. IEEE
Int. Conf. Acoust., Speech, Signal Process., 2001, vol. 2, pp. 1197–1200.
[11] K. Kotteri, A. Bell, and J. Carletta, “Design of multiplierless, high-performance,
wavelet filter banks with image compression applications,” IEEE Trans. Circuits Syst.
I, Reg. Papers, vol. 51, no. 3, pp. 483–494, Mar. 2004.
[12] A. Benkrid, K. Benkrid, and D. Crookes, “Optimal wordlength calculation for forward
and inverse discrete wavelet transform architectures,” Opt. Eng., vol. 43, no. 2, pp.
455–463, Feb. 2004.
[13] I. Daubechies and W. Sweldens, “Factoring wavelet transforms into lifting steps,” J.
Fourier Anal. Appl., vol. 4, no. 3, pp. 247–269, May 1998.
[14] T. Acharya and C. Chakrabarti, “A survey on lifting-based discrete wavelet transform
architectures,” J. VLSI Signal Process., vol. 42, no. 3, pp. 321–339, Mar. 2006.
[15] M. Marcellin, M. Lepley, A. Bilgin, T. Flohr, T. Chinen, and J. Kasner, “An overview
of quantization in JPEG 2000,” Signal Process.: Image Commun., vol. 17, no. 1, pp.
73–84, Jan. 2002.
[16] K. Varma and A. Bell, “JPEG2000—Choices and tradeoffs for encoders,” IEEE
Signal Process. Mag., vol. 21, no. 6, pp. 70–75, Nov. 2004.

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