Public cielution imaps_chip_to_system_codesign
- 1. Kamal Karimanal Cielution LLC Technologies and Tools Enabling Chip-to-System Co-Design of Electronics
- 2. Agenda Introducing Cielution LLC Smartmobile Era & The Need for Thermally Aware Chip-System Co Design • Case Study Compact Thermal Model for Thermal/System Aware IC Design Chip-to-System Thermal Co-Design Flow Validation Conclusions
- 4. Cielution Product Pipeline CielSpot™ • Package Thermal Modeling • Package Compact Model Generation CielSpot-CTM™ • Thermally Aware IC Layout o Traditional Packages o 3D Stacked Assemblies CielMech™ • Thermo-Mechanical Analysis of Assembly o Warpage Mitigation o Packaging Yield Enhancement o Interconnect Reliability
- 5. Cielution Services Expertise Areas • Thermal and Mechanical Simulation • Chip, Package Board and System Level Engineering. Tools Expertise • ANSYS, Icepak, Fluent, CFX, Flotherm Business Model • Fixed Cost Fixed Time Projects • Hourly rate & Temporary Resources
- 6. Why Thermal Co-Design Methodology?
- 7. Thermal Management in the Pre-SmartMobile Era Used to be lesser Degree of separation between IC- Design and System Thermal Management • Chip/Package Vendor –System Vendor One way coupling of Power to Temperature was Sufficient IC used to be Single Core where uniform heat was a reasonable assumption • Rja was an simple answer to Chip-Package Co-Design • 2R & Delphi networks were sufficient Compact Thermal Models (CTM) in Package-System Co-design methodology. MCM and Stacked Dies used to be Exotic applications • Thermal Management was handled as a special case for those scenarios
- 8. SmartMobile & Implications on Thermal Management IC-Package-System can be a complicated web of thermally relevant information Low Power-Temperature is fully coupled due to leakage and the importance of Battery Life System On Chip (SOC) & Multicore Architectures mean Thermal Targets are Hot Spot Limited • Rja, 2R & Delphi Networks are not applicable TSV based 3D Stack is the future High Performance ICs. • Methodologies need to evolve to address Thermally Aware Chip-to- System Co-design System OEM Fabless Semi IP Vendor OSAT Foundry
- 9. Thermally Aware Co-Design Strategy for the supply Chain System OEM(System CTM, SOC CTM, Target Specs) Fabless Semi (Heat Distribution, Compact Thermal Model) IP VendorIP Block Thermal Characteristics OSAT (Package CTM) Foundry(Device Power,Leakage, PDK) CTM Methodology & Software Ecosystem Exists in the form of Formal PDK Methodologies Only Power Characteristics needed. Exists. Room for Improvement Non Existent Today. Needed
- 10. Gaps Addressed in this presentation System OEM(System CTM, SOC CTM, Target Specs) Fabless Semi(Heat Distribution, Compact Thermal Model) IP VendorIP Block Thermal Characteristics OSAT(Package CTM) IP Vendor (Device Power,Leakage, PDK) CTM Methodology & Software Ecosystem Exists in the form of Formal PDK Methodologies Only Power Characteristics needed. Exists. Room for Improvement Non Existent Today. Needed
- 11. Proposed Thermal Co-Design Methodology Fabless Semi/3D SOC Package Test and Assembly Package CTM System OEM Power Models/ Package CTM Temperature Specs & System CTM (for large Volume Products) Sub System/PCB Modules Heat Sink Fans & Blowers Already Existing Thermal Methodologies Proposed Methodology
- 12. © Cielution 3D Stacked IC Case Study
- 13. © Cielution 3D Stack on interposer 4 Stacked Dies(8X6) Logic 2(22x16) Interposer (36x24) Substrate (40 X 28) All Dimensions in mm
- 14. © Cielution Packaging & Cooling Scenario I PCB Package housing 3D IC stack Heat Sink Copper Heat Spreader
- 15. © Cielution Power Profile Scenario I-A-Non Overlapping (total Power=32.8W) Y X
- 16. © Cielution Temperature Distribution on the chips
- 17. © Cielution Power Profile Scenario I-B: overlapping. (total Power=32.8W) Y X
- 18. © Cielution Temperature Distribution on the chips Temperature increased by 16% due to hot spot proximity
- 19. © Cielution Packaging & Cooling Scenario II h = 25 W/sq.m/K, Tamb=20C 1 W 1 W 1 W 1 W 2 W Power Distribution Scenario II-A (total Power=12.7W)
- 20. © Cielution Temperature Profile for II-a
- 21. © Cielution Power Profile II-B (total Power=12.7W) 1 W 1 W 1 W 1 W 2 W
- 22. © Cielution Power Profile for II b Temperature increased by 26% due to hot spot proximity
- 23. © Cielution Summary of Hot spot proximity Study A 3D SOC example was used to study layout implications on for steady state temperature distribution 2 different packaging+cooling solutions were considered • Copper lidded package with Heat sink cooling • MC encapsulated package without heat sink Each package+cooling scenario was subjected to 2 different sets of power maps. • Sparsest distribution of hot spots on active chips. • Closest proximity of hot spots The case with copper lidded packaging with heat sink predicted 16% higher temperature rise when hot spots were in close proximity. The case with MC encapsulated package without heat sink predicted 26% higher temperature rise when hot spots were in close proximity. The reason for this difference in sensitivity to hot spot alignment is the better ability of the heat spreader and heat sink base to spread heat even when hot spots were in close proximity.
- 24. © Cielution Moral? Heat distribution plays an important role in chip temperature rise. Hot spot proximity between chips produce unintended consequences after heterogeneous integration. • This is a new twist which will obsolete the existing thermal management methodologies based on θja Predicted temperature from thermal model are highly sensitive to: • Packaging, Heat sinking, 3D layout of stacked chips, orthotropic nature of laminates, and interconnect arrays. Above sensitivities can only be captured by thermal models using 3D numerical discretization. • Spreading and t/KA resistance formulation based approaches have inherent assumptions which tend to introduce unknown uncertainties. However, the fast turn around & automation needed by IC design flow can only be addressed by effective compact models.
- 25. Compact Modeling Methodology for Distributed Heat Load Sikka, K., “An analytical temperature prediction method for a chip power map”, Semiconductor Thermal Measurement and Management Symposium, 2005 IEEE Twenty First Annual IEEE Karimanal, K. “Chip-package thermal co-simulation technique for thermally aware chip design”, 2010 Itherm.
- 26. CielSpot for Thermal IC Package Detailed & Compact Thermal Modeling © Cielution LLC
- 27. CielMech: High Level Workflow © Cielution LLC CielSpot™ Stack Info Package Info Material Properties Solve in Commercial Thermal Solver Access to Model in the commercial solver’s native format Automated Geometry, Meshing & Problem Setup Intelligent Solver Controls Automated Thermal Snapshots & Temperature data Compact Thermal Model
- 28. CielSpot Usage: Compact for Fast Solve Without C © Cielution LLC Input Data CielSpot Pre- characterization CielSpot CTM Pmap for Chip 1 Pmap for Chip 2 Pmap for Chip 2 … Etc… Automated Thermal Snapshots & Temperature data
- 29. Collaborative Thermal Modeling using CielSpot™ © Cielution LLC CielSpot Packaging Org. Compact Model Library Package Details & Typical Heatsinking Scenarios Fabless Customer Power Map for Each Chip Package A Package B Package C CielSpot CTM™ OSAT Proprietary Details. Need Third Party Solver Application Proprietary Details. Don’t Need Third Party Solver Data Cannot be Reverse Engineered
- 30. © Cielution CielSpot™ Compact Model Validation
- 32. Validation Approach CielSpot Stack Info Package Info Compact Thermal Model Pre-Characterization using Commercial Thermal Solver (ANSYS) CielSpot CTM Pmap for Chip 1 Pmap for Chip 2 Pmap for Chip 3 … Etc… Temperature Distribution (TCTM) CielSpot™ Stack Info Package Info Power Maps on all Chips Detailed FEA Thermal Simulation (ANSYS) Temperature Distribution (Tdet ) Compare%Error = (Tdet-TCTM )/(Tdet -Tamb )*100
- 33. © Cielution Layout x Y PMAP for 2.1.1 PMAP for 2.1.1.1
- 34. © Cielution Error histogram (for all the 1000 monitor locations %Error (FEA Vs 3D Solver) -1.00% -0.80% -0.60% -0.40% -0.20% 0.00% 0.20% 0.40% 0.60% ProbeLocation%Error (FEA Vs 3D Solver)
- 35. Summary Emphasized the need for exchange formats, compact models and effective methodologies. • Presented Case Study. • Simple rules of thumb such as Rja are obsolete metrics for distributed heat loads on monolithic Chips. • 3D stacks & complex supply chain complicate matters even further Introduced CielSpot™ & CielSpot-CTM™ • Proposed Chip-to-System thermal Co-design Methodology suited for the complex Electronics Eco-system Validation showed that CTM can be as accurate as detailed thermal model • Much faster than complete CFD o seconds for a complete stacked die with heat sink, PCB and distributed heat loads on each chip and thousands of probe points • Protects IP sensitive details o Suited for system OEM+OSAT to share with Fabless IC supplier.