ROS User Group Meeting #28 マルチ深層学習とROS
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ROS User Group MeetingでLTに使った資料です。 マルチ深層学習タスクをROS上で動かすことにチャレンジしています。
![Multiple DL Tasks
• Taskonomy [Zamir, CVPR2018 (best paper)]
• http://taskonomy.stanford.edu/
• 26種類のタスクを同時に学習・実⾏
• ロボットでやりたい︕
23](https://image.slidesharecdn.com/rosugmeeting2019mar13-190313105150/85/ROS-User-Group-Meeting-28-ROS-23-320.jpg)
ROS User Group Meeting #28 マルチ深層学習とROS
- 2. ⾃⼰紹介 • なかはら ひろき (Hiroki Nakahara) https://github.com/HirokiNakahara/ • 速いコンピュータを作りたい • 多値論理: Ternary, RNS • 計算機アーキテクチャ: FPGA, ASIC • 深層学習 • ツールとか: GUINNESS (GUI based neural network synthesizer) 2
- 10. Demo: Low‐end FPGA 10 Xilinx Inc. Zynq UltraScale+ MPSoC (ZU3EG) 30FPS (YOLOv2)
- 11. Demo: High‐end FPGA 11 Intel Corp. Arria 10 GX FPGA (10AX115N2F45E1SG), 166FPS (YOLOv2)
- 15. Convolutional Neural Network (CNN) • Convolutional + Fully connected + Pooling • State‐of‐the‐art performance in an image recognition task • Widely applicable 15Source: https://www.mathworks.com/discovery/convolutional‐neural‐network.html
- 16. Deep Learning Inference Device 16 Flexibility Power Performance Efficiency CPU (Raspberry Pi3) GPU (Jetson TX2) FPGA (UltraZed) ASIC (Movidius) • Flexibility: R&D costs for keeping on evolving algorithms • Power performance efficiency • FPGA has flexibility&better performance
- 17. Field Programmable Gate Array (FPGA) • Millions of Look‐Up Tables (LUTs) • Thousands of on‐chip memories and DSP blocks • Programmable channels • Dedicated IP macros (PCIe,DDR,MPU) 17Source: Intel Corp. Arria10 FPGA Device Family Overview
- 18. Improvements by Binarization 18 x1 w0 (Bias) fsgn(Y) Y z w1 x2 w2 xn wn ... x1 x2 Y ‐1 ‐1 1 ‐1 +1 ‐1 +1 ‐1 ‐1 +1 +1 1 x1 x2 Y 0 0 1 0 1 0 1 0 0 1 1 1 EXNORs → Many MACs Binary Precision → On‐chip Memory
- 19. Near Memory Realization by Binarization E. Joel et al., “Tutorial on Hardware Architectures for Deep Neural Networks,” MICRO‐49, 2016. 19 On-chip Memory J. Dean, “Numbers everyone should know” Source: https://gist.github.com/2841832 • High bandwidth (Left) • Less power consumption (Right)
- 20. PYNQ + ⾼位合成 + ROS http://www.pynq.io/ • C++で記述, HLSでIPコア(ROSノード)化 • Ubuntu 上のPythonでSW設計 →ROS Kinetic を利⽤ 20 ‐‐‐‐‐‐‐ ‐‐‐‐‐‐‐ ‐‐‐‐‐‐‐ ‐‐‐‐‐‐‐ ‐‐‐‐‐‐‐ ‐‐‐‐‐‐‐ http://www.pynq.io/
- 23. Multiple DL Tasks • Taskonomy [Zamir, CVPR2018 (best paper)] • http://taskonomy.stanford.edu/ • 26種類のタスクを同時に学習・実⾏ • ロボットでやりたい︕ 23
- 24. まとめ • FPGAを使うと⾼性能なDLをROSで扱える(といいな) • オンチップメモリ利⽤ • Pynqフレームワーク • 設計難易度が⾼いのがネック →フレームワークを開発中 • マルチ深層学習タスク • 複数画像処理＋⾳声処理も可能 24