Simon M. Sze (editor) - Very Large Scale Integration (VLSI) Technology-McGraw-Hill Inc.,US (1983).pdf

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VLSI
TECHNOLOGY
Edited by
S. M. Sze
Bell Laboratories, Incorporated
Murray Hill, New Jersey
McGraw-Hill Book Company
New York St. Louis San Francisco Auckland Bogota Hamburg
Johannesburg London Madrid Mexico Montreal New Delhi
Panama Paris Sao Paulo Singapore Sydney Tokyo Toronto

This book was set in Times Roman by Information Sciences Corporation.
The editors were T. Michael Slaughter and Madelaine Eichberg;
the production supervisor was Leroy A. Young.
The cover was designed by Joseph Gillians.
The drawings were done by Bell Laboratories. Incorporated.
Halliday Lithograph Corporation was printer and binder.
VLSI TECHNOLOGY
Copyright © 1983 by Bell Telephone Laboratories. Incorporated. All rights reserved. Printed in
the United States of America. Except as permitted under the United States Copyright Act of
1976, no part of this publication may be reproduced or distributed in any form or by any means,
or stored in a data base or retrieval system, without the prior written permission of Bell Tele-
phone Laboratories, Incorporated.
1234567890HALHAL89876543
ISBN n-D7-DbEt,flb-3
Library of Congress Cataloging in Publication Data
Main entry under title:
VLSI technology.
(McGraw-Hill series in electrical engineering.
Electronics and electronic circuits)
Includes index.
1 . Integrated circuits —Very large scale
integration. I. Sze. S. M., date
n. Series.
TK7874.V566 1983 621.38173 82-24947
ISBN 0-07-062686-3

CONTENTS
List of Contributors xi
Preface xiii
Introduction i
Chapter 1 Crystal Growth and Wafer Preparation 9
C. W. Pearce
1 . Introduction
"
1.2 Electronic-Grade Silicon 1"
1.3 Czochralski Crystal Growing 14
1 .4 Silicon Shaping 32
1 .5 Processing Considerations '+2
1 .6 Summary and Future Trends 46
References 47
Problems 49
Chapter 2 Epitaxy 51
51
52
74
80
85
92
2 Epitaxy
C. W. Pearce
2.1 Introduction
2.2 Vapor-Phase Epitaxy
2.3 Molecular Beam Epitaxy
2.4 Silicon on Insulators
2.5 Epitaxial Evaluation
2.6 Summary and Future Trends
References
Problems

vi Contents
Chapter 3 Dielectric and Polysilicon Film Deposition 93
A. C. Adams
3.1 Introduction 93
3.2 Deposition Processes 94
3.3 Polysilicon 99
3.4 Silicon Dioxide 106
3.5 Silicon Nitride 119
3.6 Plasma-Assisted Depositions 120
3.7 Other Materials 124
3.8 Summary and Future Trends 125
References 1 26
Problems 128
Chapter 4 Oxidation I3i
L. E. Katz
4.1 Introduction 131
4.2 Growth Mechanism and Kinetics 132
4.3 Oxidation Techniques and Systems 149
4.4 Oxide Properties 153
4.5 Redistribution of Dopants at Interface 157
4.6 Oxidation of Polysilicon 159
4.7 Oxidation-Induced Defects 160
References 1 65
Problems 167
Chapter 5 Diffusion 169
J. C. C. Tsai
5 .
1
Introduction 1 69
5.2 Models of Diffusion in SoHds 170
5.3 Fick's One-Dimensional Diffusion Equations 172
5.4 Atomistic Diffusion Mechanisms 177
5.5 Measurement Techniques 184
5.6 Diffusivities of B, P, As, and Sb 193
5.7 Diffusion in Si02 204
5.8 Fast Diffusants in Silicon 206
5.9 Diffusion in Polycrystalline Silicon 207
5.10 Diffusion Enhancements and Retardations 209
References 215
Problems 217

Contents vii
Chapter 6 Ion Implantation 219
T. E. Seidel
6.2 Ion Implant System and Dose Control 220
6.3 Ion Ranges 224
6.4 Disorder Production 235
6.5 Annealing of Implanted Dopant Impurities 242
6.6 Shallow Junctions (As, BF.) 253
6.7 Minority-Carrier Effects 255
6.8 Gettering 255
6.9 Effects in VLSI Processing 258
References 26
1
Problems 264
Chapter 7 Lithography 267
D. A. McGillis
7.2 The Lithographic Process 268
7.3 Optical Lithography 274
7.4 Electron Beam Lithography 281
7.5 X-Ray Lithography 287
7.6 Other Lithography Techniques 294
References 299
Problems 300
Chapter 8 Dry Etching 303
C. J. Mogab
8.2 Pattern Transfer 304
8.3 Low-Pressure Gas Discharges 312
8.4 Plasma-Assisted Etching Techniques 317
8.5 Control of Etch Rate and Selectivity 321
8.6 Control of Edge Profile 330
8.7 Side Effects 334
8.8 Dry Etching Processes for VLSI Technology 336
8.9 Summary of Future Trends 341
References 342
Problems 344

viii Contents
Chapter 9)
Metallization
D. B. Fraser
9.1 Introduction
9.2 Methods of Physical Vapor Deposition
9.3 Problems Encountered in Metallization
9.4 Metallization Failure
9.5 Silicides for Gates and Interconnections
9.6 Corrosion and Bonding
9.7 Future Trends
References
Problems
Chapter 10 Process Simulation
W. Fichtner
10.1 Introduction
10.2 Epitaxy
10.3 Ion Implantation
10.4 Diffusion and Oxidation
10.5 Lithography
10.6 Etching and Deposition
10.7 Device Simulation
References
Problems
Chapter 11 VLSI Process Integration
L. C. Parrillo
11.1 Introduction
2 Basic Considerations for IC Processing
3 Bipolar IC Technology
4 NMOS IC Technology
5 Complementary MOS IC Technology
6 Miniaturizing VLSI Circuits
7 Modem IC Fabrication
8 Summary and Future Trends
Chapter 12
12.1
12.2
References
Problems
Diagnostic Techniques
R. B. Marcus
Introduction
Morphology Determination
347
347
354
361
367
372
380
381
381
383
385
385
385
390
397
408
428
439
441
441
443
445
445
446
448
461
478
490
497
499
500
504
507
507
508

Contents ix
12.3 Chemical Analysis 520
12.4 Crystallographic Structure and Mechanical Properties 533
12.5 Electrical Mapping 539
References 547
Problems 549
Chapter 13 Assembly Techniques and Packaging 551
C. A. Steidel
13.2 Wafer Separation and Sorting 552
13.3 Die Interconnection 552
13.4 Package Types and Fabrication Teclinologies 570
13.5 Special Package Considerations 582
13.6 Package Application Considerations 584
References 595
Problems 598
599
599
600
603
612
614
617
624
632
635
636
637
639
639
641
643
644
Index 645
Chapter 14 Yield and Reliability
W. J. Bertram
14.1 Introduction
14.2 Mechanisms of Yield Loss in VLSI
14.3 Modeling of Yield Loss Mechanisms
14.4 Reliability Requirements for VLSI
14.5 Mathematics of Failure Distributions,
and Failure Rates
Reliability,
14.6 Common Distribution Functions
14.7 Accelerated Testing
14.8 Failure Mechanisms
References
Problems
Appendixes
A Properties of Silicon
B List of Symbols
C International System of Units
D Physical Constants

LIST OF CONTRIBUTORS
A. C. ADAMS
Bell Laboratories
W. J. BERTRAM
Bell Laboratories
Allentown, Pennsylvania
C. J. MOGAB
Bell Laboratories
Murray Hill. New Jersey
L. C. PARRILLO
Bell Laboratories
W. nCHTNER
Bell Laboratories
C. W. PEARCE
Western Electric
D. B. ERASER
Bell Laboratories
L. E. KATZ
Bell Laboratories
R. B. MARCUS
Bell Laboratories
T. E. SEIDEL
Bell Laboratories
C. A. STEIDEL
Bell Laboratories
J. C. C. TSAl
Bell Laboratories
Reading, Pennsylvania
D. A. McGILLIS
Bell Laboratories

PREFACE
VLSI Technology describes the theoretical and practical aspects of the most advanced
state of electronics technology—^very-large-scale integration (VLSI). From crystal
growth to reliability testing, the reader is presented with all the major steps in the
fabrication of VLSI circuits. In addition many broader topics, such as process simula-
tion and diagnostic techniques, are considered in detail. Each chapter describes one
aspect of VLSI processing. The chapter's introduction provides a general discussion
of the topic, and subsequent sections present the basic science underlying individual
process steps, the necessity for particular steps in achieving required parameters, and
the trade-offs in optimizing device performance and manufacturability. The problems
at the end of each chapter form an integral part of the development of the topic.
The book is intended as a textbook for senior undergraduate or first-year graduate
students in electrical engineering, applied physics, and materials science; it assumes
that the reader has already acquired an introductory understanding of the physics and
technology of semiconductor devices. Because it elaborates on IC processing tech-
nology in a detailed and comprehensive manner, it can also serve as a reference for
those actively involved in integrated circuit fabrication and process development.
This text began in 1979 as a set of lecture notes prepared by the contributing
authors for an in-hours continuing education course at Bell Laboratories. The course,
called "Silicon Integrated Circuit Processing," has been given to hundreds of
engineers and scientists engaged in research, development, fabrication, and applica-
tion work of ICs. We have substantially expanded and updated the lecture notes to
include the most advanced and important topics in VLSI processing.
In the course of writing VLSI Technology, many people have assisted us and
offered their support. We would first like to express our appreciation to the manage-
ment of Bell Laboratories and Western Electric for providing the environment in
which we worked on the book. Without their support, this book could not have been
written. We have benefited significantly from suggestions made by the reviewers:
Drs. L. P. Adda, C. M. Bailey, K. E. Benson, J. E. Berthold, J. B. Bindell, J. H.
Bruning, R. E. Caffrey, C. C. Chang, D. L. Flamm, G. K. Herb, R. E. Howard,

xiv Preface
E. Kinsbron, P. H. Langer, M. P. Lepselter, J. R. Ligenza, P. S. D. Lin, W. Lin,
C. M. Melliar Smith, D. F. Munro, S. P. Murarka, E. H. Nicollian, R. B. Penumalli,
J. M. Poate, M. Robinson, D. J. Rose, G. A. Rozgonyi, G. E. Smith, J. W. Stafford,
K. M. String, R. K. Watts, and D. S. Yaney.
We are further indebted to Mr. E. Labate and N4r. B. A. Stevens for their lit-
erature searches, Ms. D. McGrew, Ms. J. Ghee, Ms. E. Doerries, Mr. N. Erdos,
Mr. R. Richton, and Mr. N. Timm, with the assistance of Ms. J. Keelan, for technical
editing of the manuscript, and Ms. A. W. Talcott for providing more than 3,000
technical papers on IC processing cataloged at the Murray Hill Library of Bell
Laboratories. Finally, we wish to thank Ms. J. Maye and the members of the Word-
Processing Centers who typed the initial drafts and the final manuscript, Mr. R. T.
Anderson and the members of the drafting department who furnished the hundreds of
technical illustrations used in the book, and Mrs. T. W. Sze who prepared the Appen-
dixes and Index.
S. M. Sze

INTRODUCTION
GROWTH OF THE INDUSTRY
The electronics industry in the United States has grown rapidly in recent years, with
factory sales increasing by a factor of 10 since the early 1960s. [See Fig. 1, curve
(a).''^] Electronics sales, which were $114 billion in 1981, are projected to increase
at an average annual rate of 15% and finally reach $400 billion by 1990. The
integrated circuit (IC) market has increased at an even higher rate than electronic sales
[see Fig. 1, curve (b)]. IC sales in the United States were $6.6 billion in 1981 and are
expected to grow by 25% annually, reaching $50 billion by 1990. The main
impetuses for such phenomenal market growth are the intrinsic pervasiveness of elec-
tronic products and the continued technological breakthroughs in integrated circuits.
The world market of electronics (about twice the size of the US market) will grow at a
comparable rate.^ In 10 years, it will rival the automobile, chemical, and steel indus-
tries in sales volume.
Figure 2 shows the sales of major IC groups and how sales have changed in
recent years.' In the 1960s the IC market was broadly based on bipolar transistors.
Since 1975, however, digital MOS ICs have prevailed. At present, even the intrinsic
speed advantage of bipolar transistors is being challenged by MOSFETs. Because of
the advantages in device miniaturization, low power dissipation, and high yield, by
1990 digital MOS ICs will dominate the IC market and capture a major market share
of all semiconductor devices sold. This book, therefore, emphasizes MOS-related
VLSI technology.
DEVICE MINIATURIZATION
Figure 3, curve (a), shows the exponential growth of the number of components per
IC chip.'^ Note that IC complexity has advanced from small-scale integration (SSI) to
medium-scale integration (MSI), to large-scale integration (LSI), and finally to very-
large-scale integration (VLSI), which has 10^ or more components per chip.

2 VLSI Technology
1000 p
1930 1940 1950 1960 1970
YEAR
1980 1990
Fig. 1 (a) Factory sales of electronics in the United States for the 52 years between 1930 and 1981 and
projected to 1990. (b) Integrated circuit market in the United States for the 20 years between 1962 and
1981 and projected to 1990. (After Refs. 1 and2.)
Although the rate of growth has slowed down in recent years because of difficulties in
defining, designing, and processing complicated chips, a complexity of over 1 million
devices per chip will be available before 1990.
The most important factor in achieving such complexity is the continued reduc-
tion of the minimum device dimension [see Fig. 3, curve (b)]. Since 1960, the annual
rate of reduction has been 13%; at that rate, the minimum feature length will shrink
from its present length of 2 |xm to 0.5 fxm in 10 years.
Device miniaturization results in reduced unit cost per function and in improved
performance. Figure 4, curve (a), gives an example of the cost reduction. The cost
per bit of memory chips has halved every 2 years for successive generations of
random-access memories.^ By 1990 the cost per bit is expected to be as low as ~ 1
millicent for a 1 -megabit memory chip. Similar cost reductions are expected for logic
ICs.
As device dimension decreases, the intrinsic switching time in MOSFETs
decreases linearly. (The intrinsic delay is given approximately by the channel length

Introduction 3
100 C7
0.01
1960 1970 1980
YEAR
1990
Fig. 2 Sales of major IC groups in the United States. (After Ref.l.)
990
I960
YEAR
Fig. 3 (a) Exponential growth of the number of components per IC chip. (After Moore. Ref. 4.)
(b) Exponential decrease of the minimum device dimensions.

4 VLSI Technology
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1950 1960 1970
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1980
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Fig. 4 (a) Reduction of cost per bit of RAM chips. {After Noyce, Ref. 5.) (b) Power-delay product per
logic gate versus year. (After Keyes. Ref. 6.)
divided by the carrier velocity.) The device speed has improved by two orders of
magnitude since 1960. Higher speeds lead to expanded IC functional throughput
rates. In the future, digital ICs will be able to perform data processing, numerical
computation, and signal conditioning at gigabit-per-second rates. Another benefit of
miniaturization is the reduction of power consumption. As the device becomes
smaller, it consumes less power. Therefore, device miniaturization also reduces the
energy used for each switching operation. Figure 4, curve (b), shows the trend of this
energy consumption, called the power-delay product.^ The energy dissipated per logic
gate has decreased by over four orders of magnitude since 1960.
INFORMATION AGE
Figure 5 shows four periods of change in the electronics industry in the United States.
Each period exhibits normal life-cycle characteristics^ (i.e., from incubation to rapid
growth, to saturation, and finally to decline). The development of the vacuum tube in
1906 and the invention of transistors^ in 1947 opened the field of electronic circuit
designs. The development of integrated circuits^ in 1959 led to a new generation of
logic families. Since 1975, the beginning of VLSI, the frontier has moved to system
organization of ICs and the associated software designs.
Many system-oriented VLSI chips, such as speech analysis/recognition and
storage circuits, will be built in response to the enormous market demand for sophisti-
cated electronic systems to handle the growing complexities of the Information
^gg 10, 11
jj^ ^j^-g ^gg ^ niajor portion of our work force can be called "information
workers"; they are involved in gathering, creating, processing, disseminating, and
using information. Figure 6 shows the changing composition of the work force in the

Introduction 5
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I860 1900 1950 1990
YEAR
Fig. 5 Penetration of technology into the industrial output versus year for four periods of change in the US
electronic industry. (After Connell. Ref. 7.)
United States. Prior to 1906, the largest single group was involved in agriculture. In
the next period, until the mid 1950s, the predominant group was involved in industry.
Currently, the predominant group consists of information workers; about 50% of the
total work force is in this category. In Europe and Japan, information workers now
constitute about 35 to 40% of the work force, which is also expected to reach 50%
before the end of the century.'" Advances in VLSI will have a profound effect on the
world economy, because VLSI is the key technology for the Information Age.
ORGANIZATION OF THE BOOK
Figure 7 shows how the 14 chapters of this book are organized. Chapter 1 considers
crystal growth and wafer preparation. VLSI technology is synonymous with silicon
VLSI technology. The unique combination of silicon's adequate bandgap, stable
50
PERIOD I PERIOD 2 PERIOD m
40-
< 30-
20-
1860
^^ AGRICULTURE
/Information
.' "^ INDUSTRY
/
-
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X ^^
^^
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r
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vf^**;^ ....-A v^
... -^ >s
SERVICE
^^ "^ v.
^^ >v
^r N
1 1 1 1
1 1 1 1 1 1 i"""T~~
1900 1950 1990
YEAR
Fig. 6 Changing conposition of work force in the United States. {After Robinson, Ref. 10.)

6 VLSI Technology
YIELD AND
RELIABILITY (CHAP. 14)
CRYSTAL GROWTH AND
WAFER PREPARATION (CHARD
PROCESS SIMULATION
(CHAP, 10)
VLSI PROCESS
INTEGRATION (CHAP II)
DIAGNOSTIC TECHNIQUES
(CHAP. 12)
ASSEMBLY TECHNIQUES AND PACKAGING
(CHAP. 13)
Fig. 7 Organizationof this book.
oxide, and abundance in nature ensures that in the foreseeable future, no other semi-
conductor will seriously challenge its preeminent position in VLSI applications.
(Some important properties of silicon are listed in Appendix A.) Once the silicon
wafer is prepared, we enter into the wafer-processing sequence, described in Chapters
2 through 9, and depicted in the wafer-shaped central circle of Fig. 7. Each of these
chapters considers a specific processing step. Of course, many processing steps are
repeated many times in IC fabrication; for example, lithography and dry etching steps
may be repeated 5 to 10 times.
Chapter 10 considers process simulation of all the major steps covered in
Chapters 2 through 9. Process simulation is emerging as an elegant aid to process
development. This approach is attractive because of its rapid turn-around time and
lower cost when compared to the experimental approach. Process simulation coupled
with device and circuit simulations can provide a total design system that allows on-
line process design and simulation to predict desired device and circuit parametric
sensitivities and to facilitate circuit design and layout.
The individual processing steps described in Chapters 2 through 9 are combined
in Chapter 1 1 to form devices and logic circuits. Chapter 1 1 considers the three most
important IC families: the bipolar ICs, the NMOS (n-channel MOSFET) ICs, and the
CMOS (complementary MOSFET) ICs. As the device dimension decreases and cir-
cuit complexity increases, sophisticated tools are needed for process diagnostics.
Chapter 12 covers many advanced diagnostic techniques, such as scanning and
transmission electron microscopy for morphology determination, Auger electron
spectroscopy for chemical analysis, and x-ray diffraction for structural analysis.

Introduction 7
After completely processed wafers are tested, those chips that pass the tests are
ready to be packaged. Chapter 13 describes the assembly and packaging of VLSI
chips. Chapter 14 describes the yield at every step of the processing and the reliabil-
ity of the packaged ICs. As device dimensions approach 1 ixm, VLSI processing
becomes more automated, resulting in tighter control of all processing parameters. At
every step of production, from crystal growth to device packaging, numerous refine-
ments are being made to improve the yield and reliability.
To keep the notation simple in this book, we sometimes found it necessary to use
a simple symbol more than once, with different meanings. For example, in Chapter 1
S means 4-point probe spacing, in Chapter 7 it means resist sensitivity, while in
Chapter 14 it means slope of a failure plot. Within each chapter, however, a symbol
has only one meaning and is defined the first time it appears. Many symbols do have
the same or similar meanings consistently throughout this book; they are summarized
in Appendix B.
At present, VLSI technology is moving at a rapid pace. The number of VLSI
publications (i.e., papers with the acronym "VLSI" in the title or abstract) has grown
from virtually zero in 1975 to over 1000 in 1981 with an average annual growth rate
of over 300%! Note that many topics, such as lithography and process simulation, are
still under intensive study. Their ultimate capabilities are still not fully understood.
The material presented in this book is intended to serve as a foundation. The refer-
ences listed at the end of each chapter can supply more information.
REFERENCES
[1] Electronic Market Data Book 1982, Electronic Industries Association, Washington. D.C., 1982.
[2] "World Markets Forecast for 1982," Electronics, 55, No. 1, 121 (1982).
[3] "Ten-Year Worldwide Forecast for Electronic Equipment and Components," Electronic Business,
p. 92 (February 1981).
[4] G. Moore, "VLSI. What Does the Future Hold," Electron. Aust.,4,2, 14 (1980).
[5] R. N. Noyce, "Microelectronics," in T. Forester, Ed., The Microelectronics Revolution, MIT Press,
Cambridge, Mass., 1981, p. 29.
[6] R. W. Keyes. "Limitations of Small Devices and Large Systems," in N. G. Einspruch, Ed., VLSI
Electronics, Academic, New York, 1981, Vol. 1, p. 186.
[7] J. M. Connell, "Forecasting a New Generation of Electronic Components," Digest IEEE Spring
Compcon.. SI, 14(1981).
[8] W. Shockley, "The Path to the Conception of the Junction Transistor," IEEE Trans. Electron De-
vices, ED-23, 591 {916).
[9] J. S. Kilby, "Invention of the Integrated Circuits. ""
IEEE Trans. Electron Devices, ED-23, 648
(1976).
[10] A. L. Robinson, "Electronics and Employment: Displacement Effects," in T. Forester, Ed., The
Microelectrons Revolution, MIT Press, Cambridge, Mass., 1981, p. 318.
[11] J. S. Mayo, "Technology Requirements of the Information Age," Bell Lab. Rec, 60, 55 (1982).
[12] D. Kimbel, Microelectronics, Productivity and Employment, Organization for Economic Coopera-
tional Development, Paris, 1981, p. 15.

CHAPTER
ONE
CRYSTAL GROWTH AND WAFER PREPARATION
C. W. PEARCE
1.1 INTRODUCTION
Silicon, naturally occurring in the form of silica and silicates, is the most important
semiconductor for the electronics industry. At present, silicon-based devices consti-
tute over 98% of all semiconductor devices sold worldwide. Silicon is one of the most
studied elements in the periodic table. A literature search on published papers using
silicon as a search word yields over 25.000 references. Appendix A is a compilation
of some useful constants.' - Silicon is also a commercially important element for
several other major industries, such as glass and gemstones. The commercial value of
silicon derives in part from the utility of its mineral forms, which is the way silicon
occurs in nature, and from its abundance. Silica is integral to the manufacture of glass
and related products, while certain silicates are highly valued as semiprecious gem-
stones, such as garnet, zircon, and jade. By weight it comprises 25% of the earth's
crust and is second only to oxygen in abundance.
Although silicon is generally synonymous with the solid-state era of electronics,
as in the use of the term "silicon chip." its mineral forms were used in vacuum-tube
electronics. (Silica was used for tube envelopes.) Mica, a silicate, found application
as an insulator and capacitor dielectric. Quartz, another silicate, was and still is used
as a frequency-determining element and in passive filter applications.
The advent of solid-state electronics dates from the invention of the bipolar
transistor effect by Bardeen, Brattain, and Shockley."^ The technology progressed dur-
ing the early 1950s, using germanium as the semiconducting material. However, ger-
manium proved unsuitable in certain applications because of its propensity to exhibit
high junction leakage currents. These currents result from germanium's relatively nar-
row bandgap (0.66 eV). For this reason, silicon (1.1 eV) became a practical substitute

10 VLSI Technology
and has almost fully supplanted germanium as a material for solid-state device fabri-
cation. Silicon devices can operate up to 150°C versus 100°C for germanium.
In retrospect, other reasons could have ultimately led to the same material substi-
tution. Planar processing technology derives its success from the high quality of ther-
mally grown silicon dioxide. Germanium oxide is water soluble and unsuited for de-
vice applications. The intrinsic (undoped) resistivity of germanium is 47 H-cm, which
would have precluded the fabrication of rectifying devices with high breakdown vol-
tages. In contrast, the intrinsic resistivity of silicon is about 230,000 fl-cm. Thus,
high-voltage rectifying devices and certain infrared sensing devices are practical with
silicon. Finally, there is an economic consideration—electronic-grade germanium
costs 10 times as much as silicon.
Similar problems impeded the widespread use of compound semiconductors. For
example, it is difficult to grow a high-quality oxide on GaAs. One element oxidizes
more readily than the other, leaving a metallic phase at the interface. Such material is
difficult to dope and obtain in large diameters with high crystal perfection. In fact the
technology of Group III— V compounds has advanced partly because of the advances
in silicon technology.
1.2 ELECTRONIC-GRADE SILICON
Electronic-grade silicon (EGS), a polycrystalline material of high purity, is the raw
material for the preparation of single-crystal silicon. EGS is undoubtedly one of the
purest materials routinely available. The major impurities of interest are boron, car-
bon, and residual donors. Pure EGS generally requires that doping elements be in the
parts per billion (ppb) range, and carbon be less than 2 parts per million (ppm).'^
These properties are usually evaluated on test ingots rather than measuring on the
material itself.-^ In the case of the doping elements, ppb levels are below the capabili-
ties of most laboratory methods, so the doping level is inferred from resistivity meas-
urements on the test ingot.
To obtain EGS requires a multistep process."^ First, metallurgical-grade silicon is
produced in a submerged-electrode arc furnace, as shown in Fig. 1. The furnace is
charged with quartzite, a relatively pure form of Si02, and carbon in the form of coal,
coke, and wood chips. In the furnace a number of reactions take place, the overall
reaction being:
SiC (solid) + SiO. (solid) => Si (solid) + SiO (gas) + CO (gas) (1)
The process is power intensive, requiring 13 kWh/kg, and metallurgical-grade silicon
(MGS) is drawn off at a purity of 98%. Table 1 shows typical purities of various
materials used in the arc furnace. The MGS used in the making of metal alloys is not
sufficiently pure to use in the manufacture of solid-state devices.
The next process step is to mechanically pulverize the silicon and react it with
anhydrous hydrogen chloride to form trichlorosilane (SiHCl3), according to the reac-
tion:
Si(solid) + 3HCl(gas) => SiHClaCgas) + H2(gas) + heat (2)

Crystal Growth .^nd Wafer Prep.aration 11
f
SUBMERGED ELECTRODE
QUARTZITE.COAL,
COKE, WOOD CHIPS
CHARGE Si (=C>
FURNACE
Fig. 1 Schematic of a submerged-electrode arc furnace for the production of metallurgical-grade silicon.
(After Grossman and Baker. Ref. 4.)
Table 1 Comparison of typical impurity contents in various materials (values
in ppm except as noted)
Impurit' Quartzite Carbon MGS* EGS-i- Crucible quartz
Al 620 5500 1570
B 8 40 44 <1 ppb
Cu <5 14 0.4 0.23
Au 0.07 ppb
Fe 75 1700 2070 4 5.9
P 10 140 28 <2 ppb
Ca
Cr 137 1 0.02
Co 0.2 0.01
Mn 70 0.7
Sb 0.001 0.003
Ni 4 6 0.9
As 0.01 0.005
Ti 163
La 1 ppb
V 100
Mo 1.0 5.1
C 80 0.6
W 0.02 0.048
O
Na 0.2 3.7
*Metallurgical-grade silicon.
tElectronic-grade silicon.

12 VLSI Technology
RES I DUAL
GASES
REACTION CHAMBER
SILICON BRIDGE
SLIM R0D,4-MM DIAMETER
POLYCRYSTALLINE
SILICON ROD
QUARTZ BELL
GRAPHITE HOLDER
INSULATION
(—POWER INPUT
S iHCis + H 2
Fig. 2 Schematic of a CVD reactor used for EGS production. (After Grossman and Baker, Ref. 4.)
This reaction takes place in a fluidized bed at a nominal temperature of 300°C using a
catalyst. Here silicon tetrachloride and the chlorides of impurities are formed. At this
point the purification process occurs. Trichlorosilane is a liquid at room temperature
(boiling point 32°C), as are many of the unwanted chlorides. Hence purification is
done by fractional distillation.
EGS is prepared from the purified SiHCl3 in a chemical vapor deposition (CVD)
process similar to the epitaxial CVD processes that is presented in Chapter 2. The
chemical reaction is a hydrogen reduction of trichlorosilane.
2SiHCl3(gas) + 3H2(gas) => 2Si(solid) + 6HCl(gas) (3)
This reaction is conducted in the type of system shown in Fig. 2. A resistance-heated
rod of silicon, called a "slim rod," serves as the nucleation point for the deposition of
silicon. A complete process cycle takes many hours, and the results in rods, of EGS,
which are polycrystalline in structure, up to 20 cm (8 in) in diameter and several
meters in length. EGS can be cut from these rods as single chucks or crushed into
nugget geometries (Fig. 3). In 1982 the worldwide consumption of electronic-grade
polysilicon was approximately 3 x 10^ kg.
This CVD process is also used to grow tubes of EGS on carbon mandrils.^ These
tubes are of high purity and strength, and are used as furnace tubes in place of quartz
in high-temperature operations (over 12(X)°C). The tubes are also sectioned and
machined to form paddles and wafer carriers for the same high-temperature operations
(Fig. 4). In these applications, silicon competes with quartz and silicon-carbide. The
choice of silicon as a material for furnace use is advantageous because of its purity
and strength. Silicon process tubes show no sagging or similar deformation after
several years' use in a furnace process where they are repetitively cycled between 900
and 1250°C. Quartz tubes have limited life in the same process.

Crystal Growth and Wafer Preparation 13
Fig. 3 EGS in chunk form loaded into a quartz crucible.
Fig. 4 A polysilicon furnace tube and vafer rack.

14 VLSI Technology
^SILICON ATOMS TETRAHEDRALLY BONDED
SUBSTITUTIONAL IMPURITY
Fig. 5 Schematic of the crystal structure of silicon.
1.3 CZOCHRALSKI CRYSTAL GROWING
A substantial percentage (80 to 90%) of the silicon crystals prepared for semiconduc-
tor industry are prepared by the Czochralski (CZ) technique.'' Virtually all the silicon
used for integrated circuit fabrication is prepared by this technique.
1.3.1 Crystal Structure
Silicon has a diamond-lattice crystal structure (Fig. 5), which can be viewed as two
interpenetrating face-centered cubic lattices. Each silicon atom has four nearest neigh-
boring atoms to which it is covalently bonded. The lattice constant for silicon is
5.43 A, and simple geometry reveals that the spacing to the nearest neighbor is 2.35 A.
Dopant atoms (most of Group III and Group V) that substitute for silicon atoms are
considered to be occupying substitutional lattice sites. Phosphorous is a substitutional
donor, having four of its five valence-band electrons covalently bonded to the four
nearest neighbor silicon atoms, leaving the fifth free to support electrical conduction.
Similiarly, boron is a substitutional acceptor. Its three valence-band electrons also
covalently bond to nearest neighbor silicon atoms. The deficiency of an electron to
complete the bonding is the basis for hole conduction. Impurities or dopants that
occupy sites not defined by the structure are said to be in interstitial lattice sites.
The principal axes in a crystal can also be used to develop a notation for defining
specific directions and planes (Fig. 6). Termed "Miller indices,"*^ they are a series
of small integer numbers enclosed in carets, brackets, parentheses, and braces. For

CRYSTAL f
PLANE Ll
^
(100)
^[100] DIRECTION
1 ^
(110) (111)
Fig. 6 Schematic representation of Miller indices in a cubic lattice system.
example, [111] denotes a specific direction, whereas (1 1 1) denotes the family of all
eight directions equivalent to [111]. A (100) notation denotes a particular lattice
plane, and {100} denotes all the planes crystallographically equivalent of (100).
The processing characteristics and some material properties of silicon wafers
depend on the orientation. The {111} planes have the highest density of atoms on the
surface, so crystals grow most easily on these planes. Mechanical properties such as
tensile strength are highest for (1 1 1) directions. The moduli of elasticity also show an
orientation dependence (Appendix A). Processing characteristics such as oxidation are
similarly orientation dependent. For example, {111} planes oxidize faster than {100}
planes, because they have more atoms per unit surface area available for the oxidation
reaction to occur. The choice of crystal orientation, therefore, is generally not left to
the discretion of the crystal grower, but is a device design consideration. Historically,
bipolar circuits have preferred (1 1 1) oriented material and MOS devices (100). There
are, of course, exceptions. Growth on other orientations such as (110) has been
demonstrated, but is more difficult to achieve routinely.^
A real crystal, as represented by a silicon wafer, differs from the mathematically
ideal crystal in several respects. It is finite, not infinite; thus, surface atoms are
incompletely bonded. The atoms are displaced from their ideal locations by thermal
agitation. Most importantly, real crystals have defects'^' " classified as follows: (1)
point defect, (2) line defect, (3) area or planar defect, and (4) volume defect. Defects
influence the optical, electrical, and mechanical properties of silicon.
Point defects Point defects take several forms as shown in Fig. 7. Any nonsilicon
atom incorporated into the lattice at either a substitutional or interstitial site is con-
sidered a point defect. This is true whether the atom is an intentional dopant or unin-
tentional impurity. Missing atoms create a vacancy in the lattice called a "Schottky
defect," which is also considered a point defect. A silicon atom in an interstitial lat-
tice site with an associated vacancy is called a "Frenkel defect." Vacancies and inter-
stitials have equilibrium concentrations that depend on temperature. From thermo-
dynamic principles the concentration as a function of temperature can be derived and
has the following relation:
N^ = A exp {-EJkT) (4)

16 VLSI Technology
IMPURITY IN INTERSTITIAL SITE
SILICON
INTERSTITIAL
r
SILICON Z*' / A FRENKEL
ATOMS ^ / ^ DEFECT
IMPURITY ON SUBSTITUTIONAL SITE
VACANCY OR SCHOTTKY DEFECT
Fig. 7 The location and typjes of point defects in a simple lattice.
where N^j is the concentration of the point defect, A is a constant, E^ is the activation
energy (2.6 eV for vacancies and 4.5 eV for interstitials), T is absolute temperature,
and k is Boltzmann's constant.
Point defects are important in the kinetics of diffusion and oxidation. The diffu-
sion of many impurities depends on the vacancy concentration, as does the oxidation
rate of silicon. Vacancies and interstitials are also associated with defect formation in
processing.
'°
To be electrically active, atoms must usually be located on substitutional sites.
'"^
When in such sites they introduce an energy level in the bandgap. Shallow levels are
characteristic of efficient donor and acceptor dopants. Midgap levels act as centers for
the generation and recombination of carriers to and from the conduction and valence
bands. Some impurities are entirely substitutional or interstitial in behavior, but others
can exist in either lattice position.
Dislocations Dislocations form the second class of defects. Two general categories of
dislocations are spiral and line (edge), the terms being aptly descriptive of their shape.
Figure 8 is a schematic representation of a line dislocation in a cubic lattice; it can be
seen as an extra plane of atoms AB inserted into the lattice. The line of dislocation
would be perpendicular to the plane of the page. Dislocations in a lattice are dynamic
defects; that is, they can move under applied stress, disassociate into two or more
dislocations, or combine with other dislocations. A vector notation developed by
Burgers'^ characterizes dislocations in the crystal. The vector notation is also used to
describe dislocation interactions.
Crystals for IC usage are generally grown free of edge dislocations, '° but may
contain small dislocation loops from excess point-defect condensation.''^ These
defects act as nuclei for precipitation of impurities such as oxygen and are responsible
for a swirl pattern seen in wafers."^ Dislocations (edge type) are also introduced by
thermal stress on the wafer during processing'-^' '^
or by the introduction of an exces-
sive concentration of an impurity atom. Substitutional impurities with covalent radii
larger or smaller than silicon compress or expand the lattice accordingly. The strain 5

A
I • A > <t ^»-
Fig. 8 An edge dislocation in a cubic lattice created by an extra plane of atoms. The line of the dislocation
is perpendicular to the page.
(in dynes per cm ) induced depends on the size of the impurity and its concentra-
tion:
'^
5 = BCE
-V
(5)
where B is the lattice contraction constant reflecting the degree of distortion intro-
duced by the impurity (fi = 8 x lO"""^ cm^/atom for boron), C is the impurity concen-
tration, E is Young's modulus, and V is Poisson's ratio. Dislocations in devices are
generally undesirable, because as they act as sinks for metallic impurities and alter
diffusion profiles. Dislocations can be revealed by preferential etching (see Section
1.3.5).
Area (planar) defects Two area defects are twins and grain boundaries. Twinning
represents a change in the crystal orientation across a twin plane, such that a certain
symmetry (like a mirror image) exists across that plane. In silicon, the twin plane is
{111}. A grain boundary represents a transition between crystals having no particular
orientation relationship to one another. Grain boundaries are more disordered than
twins, and separate grains of single crystals in polycrystalline silicon. Area defects,
such as twins or grain boundaries, represent a large area discontinuity in the lattice.
The crystal on either side of the discontinuity may be otherwise perfect. These
defects appear during crystal growth, but crystals having such defects are not con-
sidered usable for IC manufacture and are discarded.
Volume defects Precipitates of impurity or dopant atoms constitute the fourth class
of defects. Every impurity introduced into the lattice has a solubility; that is, a con-
centration that the host lattice can accept in a solid solution of itself and the impurity.

18 VLSI Technology
Li
-
1400 1200 1000 800 600
TEMPERATURE CO
Fig. 9 Solid solubilities of impurity elements in silicon. (After MHues. Ref. 12.)
Figure 9 illustrates the solubility versus temperature behavior for a variety of elements
in silicon. Most impurities have a retrograde solubility, which is defined as a solubil-
ity that decreases with decreasing temperature. Thus, if an impurity is introduced (at a
temperature Tj) at the maximum concentration allowed by its solubility, and the crys-
tal is then cooled to a lower temperature T, a. supersaturated condition is said to exist
(also see Fig. 19). The degree of supersaturation is expressed as the ratio of the con-
centration introduced at Tj to the solubility at Tj. The crystal achieves an equilibrium
state by precipitating the impurity atoms in excess of the solubility level as a second
phase. The kinetics of precipitation depend on the degree of supersaturation, time,
and nucleating sites where the precipitates form.
Precipitates are generally undesirable, because they act as sites for dislocation
generation. Dislocations result from the volume mismatch between the precipitate and
the lattice, inducing a strain that is relieved by dislocation formation. Precipitation in
silicon processing has been observed for dopants such as boron, oxygen, and metallic
• • 17 18 10
impurities. • '
1.3.2 Crystal Growing Theory
Growing crystals, in the most general sense, involves a phase change from solid,
liquid, or gas phases to a crystalline solid phase. Czochralski growth, named for the
inventor, is the process used to grow most of the crystals from which silicon wafers
are produced. This process can be characterized, as applied to silicon, as a liquid-

interface boundary layer (liquid)
SOLID (CRYSTAL)
GROWTH
AXIS
MP
o IMPURITY ATOMS
• SILICON ATOMS
DISTANCE
Fig. 10 Temperature gradients, solidification, and transport phenomena involved in Czochralski growth.
Positions 1 and 2 represent the location of isotherms associated with Eq. 6 and the crystal solidification at
the interface. Impurity atoms are transported across the boundary' layer and incorporated into the growing
crystal interface. M. P. is the melting point.
solid monocomponent growth system. This section discusses some elements of this
process as it relates to the understanding of the properties of the grown crystals. For a
more complete treatment of crystal growth, refer to the many excellent books devoted
to the subject.^-
-^•-'
The growth of a CZ crystal involves the solidification of atoms from a liquid
phase at an interface. The speed of growth is determined by the number of sites on the
face of the crystal and the specifics of heat transfer at the interface. Figure 10
schematically represents the transport process and temperature gradients involved.
Macroscopically, the heat transfer conditions about the interface can be modelled by
the following equation:^'
dm
dt
+ k,-— A
dX]
1
dT ,
dx-)
(6)
where L is the latent heat of fusion, dm/dt is the mass solidification rate, T is the
temperature, kj and k^ are the thermal conductivities of the liquid and solid, respec-
tively, dT/dx I and dT/dxi are the thermal gradients at points 1 and 2 (near the inter-
face in the liquid and solid, respectively), and A
and A 2 are the areas of the iso-
therms at positions 1 and 2, respectively.
From Eq. 6 the maximum pull rate of a crystal under the condition of zero ther-
mal gradient in the melt can be deduced: '' ^^
- A_ 4L
U dx
V, (7)
where V^.^ is the maximum pull rate (or pull speed) and d is the density of solid sili-
con. Figure 1 1 is an experimentally determined temperature variation along a crystal.

20 VLSI Technology
CRYSTAL
3 4 5 6 7
DISTANCE (cm)
Fig. 11 Experimentally determined temperature gradient in a silicon crystal as referenced to insert showing
a growing crystal. (After deKock arid van de Wijgert, Ref. 14.)
The pull rate influences the incorporation of impurities into the crystal and is a
factor in defect generation. Generally, when the temperature gradient in the melt is
small, the heat transferred to the crystal is the latent heat of fusion. As a result, the
pull rate generally varies inversely with the diameter^' ~^ (Fig. 12). The pull rates
obtained in practice are 30 to 50% slower than the maximum values suggested by
theoretical considerations.^
The growth rate (or growth velocity) of the crystal, actually distinct from the pull
rate, is perhaps the most important growth parameter. Pull rate is the macroscopic
indication of net solidification rate, whereas growth rate is the instantaneous solidifi-
cation rate. The two differ because of temperature fluctuations near the interface. The
growth rate can exceed the pull rate and even be negative at a given time. When the
growth rate is negative, remelting is said to occur. That is, the crystal dissolves back
into the melt. The growth rate influences the defect structure and dopant distribution
in the crystal on a microscopic scale.
Pull rate affects the defect properties of CZ crystals in the following way. The
condensation of thermal point defects in CZ crystals into dislocation loops occurs as
the crystal cools from the solidification temperature. This process occurs above
950°C. The number of defects depends on the cooling rate, which is a function of pull
rate and diameter, through this temperature range. A pull rate of 2 mm/min eliminates
microdefect formation by quenching the point defects in the lattice before they can
agglomerate. We find from Fig. 12 that large diameters preclude this pull rate from
being achieved for crystal diameters above 75 mm. A related phenomenon is the
remelting of the crystal that occurs because of temperature instabilities in the melt
caused by thermal convection. This condition can also be suppressed by attaining a
pull rate of 2.7 mm/min,^^ which is half the maximum attainable pull rate (Eq. 7).
Crystals in which remelt has not been suppressed exhibit impurity striations and
defect swirls.
~'^' -^
Elimination of remelt results in more uniformly doped crystals, dis-

Crystal Growth and Wafer Preparâtion 21
7.5
6.0 -
1
"'
3.0 -
1.5
1 1 1
THEORETICAL
1 1 1
GROWTH RATE
• SOLIDIFIED WITHOUT
SINGLE- CRYSTAL STRUCTURE |
O SOLIDIFIED WITH
SINGLE-CRYSTAL STRUCTURE J

^
^^^
• "^ ~
^v ^
^. ^^
^S^
dv ^ 1
V.
^^w ^S. •
^V
^V ^S^^
Xv^ ^"W^ NSfc
Xs. ^^Ss^^ ^^
^^ô
^****>is,
w O ^*'^««w * """^ —
^PULL RATE
^~^^^
NEEDED TO
SUPPRESS REMELT
1 i 1 1 1
20 30 40 50 60 70
DIAMETER (mm)
80 90
Fig. 12 Theoretical and experimental pull rates for Czochralski-grown crystals. The dashed line is the
theoretical growth rate according to Rea (Ref. 7). (After Digges. Jr. andShima. Ref. 22.)
cussed below, but will not necessarily eliminate dopant striation if the growth velocity
still varies on a microscopic level (Eq. 10).
As mentioned earlier, every impurity has a solid solubility in silicon. The impur-
ity has a different equilibrium solubility in the melt. For dilute solutions commonly
encountered in silicon growth, an equilibrium segregation coefficient /cq may be
defined as:
(8)
where Q and Q are the equlibrium concentrations of the impurity in the solid and
liquid near the interface, respectively.
Table 2 lists the equilibrium segregation coefficients for common impurity and
dopant atoms. Note that most are below 1 , so that during growth, the impurities at the
Table 2 Segregation coefficients for common impurities in silicon
Impurit}' Al As B C Cu Fe OP Sb
ô 0.002 0.3 0.8 0.07 4x10-* 8x10"^ 1.25 0.35 0.023

22 VLSI Technology
10 20 30 40 50 60 70 80 90 100
MELT FRACTION SOLIDIFIED (%)
Fig. 13 Impurity concentration profiles for various Aig with Cq= I.
interface are left in the liquid (melt). Thus, as the crystal grows, the melt becomes
progressively enriched with the impurity.
The distribution of an impurity in the grown crystal can be described mathemati-
cally by the normal freezing relatione'
C, =koCo(-X)'''' (9)
where X is the fraction of the melt solidified, Cq is the initial melt concentration, C, is
the solid concentration, and /cq is the segregation coefficient.
Figure 13 illustrates the segregation behavior for several segregation coefficients.
Experimentally it is found that segregation coefficients differ from equilibrium values
and it is necessary to define an effective segregation coefficient k^ r^
L =
ko + (1 - ko) exp i-VB ID)
(10)
where V is the growth velocity (or pull rate), D is the diffusion coefficient of dopant
in melt, and B is the boundary layer thickness.
The boundary layer thickness is a function of the convection conditions, in the

melt. Rotation of a crystal in a melt (forced convection) produces a boundary layer B
dimensions defined byr^*^
B = 1.8 d'V'/^ Vy-'Z-
(11)
where W is the rotational velocity.
Our presentation so far represents a first-order approach to the problem. In large
melts the convection forced by rotation is often secondary to the thermal convection
caused by temperature gradients in the crucible. ^^ The effect is to reduce values of B
below those of Eq. 11. Since the thermal convection is a random process, the thick-
ness of the boundary layer fluctuates with time, resuhing in a variable value for B.
The net result of thermal convection effects is an inhomogeneous distribution of
dopant in the crystal on a microscale (Fig. 14). The boundary layer thickness also
varies radially across the face of the crystal, resulting in a radial distribution of
dopant. Generally, less dopant is incorporated at the edges.
Another effect occuring in heavily doped melts is constitutional supercooling.^^
This effect, particularly prevalent with Sb, occurs when the concentration in the melt
DOPANT STRIATIONS
p to w_=
Ecc (N =
E 1—(
^
poi o =
E r-t =
pg> =
E ^^
E 00 :^
OD
J^ =
GROWTH AXIS
gO 10 =
Fig. 14 Dopant striations in a Sb-doped ingot revealed by preferentially etching a longiuidinal section from
the seed end of an ingot.

24 VLSI Technology
ahead of the growing interface is sufficient to depress the sohdification temperature
(freezing point). When this occurs, the crystal solidifies irregularly and dislocations
appear. Constitutional supercooling limits the ultimate dopant incorporation for cer-
tain impurities.
The pull speed is also a factor in determining the shape of the growing interface,
as are the melt radial temperature gradient and the crystal surface cooling ccnditions.
A proper shape is needed to maintain stability of the growing crystal.^'
"^
1.3.3 Crystal Growing Practice
A Czochalski crystal growth apparatus, also called a "puller," is shown in Fig. 15.
The one pictured weighs 17,600 kg and is 6.5 m tall. This puller can be configured to
hold a melt charge of 60 kg of silicon, which can be transformed into a crystal of
Fig. 15 An industrial-sized Czochralski grower. Numbers relate to the four basic parts of the growers.

SEED SHAFT,
LIFT AND
ROTATION
SENSOR FOR
DIAMETER CONTROL

VIEW
PURGE
VPORT "^ T
TUBE I
^ ^
INSULATION-
HEATER
SUSCEPTOR
TEMPERATURE
SENSOR
"SUPPER HOUSING
CONTROL SYSTEM
AND
POWER SUPPLY
] ISOLATION VALVE
AMBIENT GAS INLET
SEED SHAFT a CHUCK
FURNACE CHAMBER
MELT
CRUCIBLE
EXHAUST
VACUUM
PUMP
CRUCIBLE ROTATION
AND LIFT
Fig. 16 Schematic representation of a crystal grower.
100-mm diameter and 3.0-m length. The puller has four subsystems as follows (Fig.
16):
1. Furnace: crucible, susceptor and rotation mechanism, heating element and
power supply, and chamber.
2. Crystal-pulling mechanism: seed shaft or chain, rotation mechanism, and seed
chuck.
3. Ambient control: gas source, flow control, purge tube, and exhaust or vacuum
system.
4. Control system: microprocessor, sensors, and outputs.
Furnace Perhaps the most important component of the growing system is the cruci-
ble (Fig. 3). Since it contains the melt, the crucible material should be chemically
unreactive with molten silicon. This is a major consideration, because the electrical
properties of silicon are sensitive to even ppb levels of impurities. Other desirable
characteristics for crucible material are a high melting point, thermal stability and
hardness. Additionally, the crucible should be inexpensive or reusable. Unfor-
tunately, molten silicon can dissolve virtually all commonly used high-temperature

26 VLSI Technology
materials, such as refractory carbides (TiC or TaC), thus introducing unacceptable
levels of the metallic species into the crystal/^^
Carbon or silicon carbide crucibles are also unsuitable. Although carbon is elec-
trically inactive in silicon, high-quality crystals cannot be grown with carbon-
saturated melts. -^^
During growth a two-phase solidification occurs, once the solid
solubility has been exceeded. The second phase is SiC, which is responsible for dislo-
cation generation and loss of single-crystal structure. The remaining choices for a cru-
cible are either silicon nitride (Si3N4) or fused silica (SiOi), which is in exclusive use
today.
Fused silica or quartz does, however, react with silicon, releasing silicon and
oxygen into the melt. The dissolution rate is quite substantial, as shown-^"^ by Fig. 17.
The actual rate of erosion is a function of temperature and the convection conditions,
either forced or thermal, ^^ in the melt. Most of the oxygen in the melt escapes by the
formation of gaseous silicon monoxide. The SiO condenses on the inside of the fur-
nace chamber, creating a cleanliness problem in the puller. Crystals grown with these
crucibles also contain substantial amounts of interstitial oxygen that can be either
beneficial or detrimental, as will be discussed later. The purity of the quartz itself
(Table 1) also affects the silicon purity, because the quartz can contain sufficient
acceptor impurities to limit the upper values of resistivity that can be grown. The
presence of carbon in the melt also accelerates the dissolution rate up to twofold.
^^
One possible reaction is:
C + SiO. -^ SiO + CO (12)
Crucibles for large CZ pullers have a diameter-to-height ratio of approximately 1 or
slightly greater; common diameters are 25, 30, and 35 cm for charge sizes of 12, 20,
and 30 kg, respectively. A 45-cm, 60-kg configuration has even been proposed. Wall
thicknesses of 0.25 cm are used, but the silica is sufficiently soft to require the use of
40
30
20 1-
(O 2
MELT TEMPERATURE CO
1500 1450 1400
1
1
1
^^^-^ ' v = 9.4cm/s
1
1
~~~
~—-V = 4.7Cnn/s
=
A V IS VELOCITY OF
X ' MELT RELATIVE
- v=0cm/s
TO CRUCIBLE
1 1
1 1 1
5.5 5.6 5,7 5.8 5.9
1000/T (K'l)
6.0
Fig. 17 The dissolution rate of quartz in molten silicon. (After Hirata and Hoshikawa, Ref. 32.)

Crystal Growth .and W,afer Prepar-ation 27
a susceptor for mechanical support. Upon cooling, the thermal mismatch between
residual silicon and quartz usually results in the fracture of the crucible.
The feasibility of using silicon nitride as a crucible material has been demon-
strated using CVD-deposited,nitride.
''"^
Such an approach is attractive as a means of
eliminating oxygen from crucible-grown cr>'stals. However, even the nitride is
eroded, resulting in a doping of the crystal with nitrogen, a weak donor. CVD nitride
is the only form of nitride with sufficient purity for crucible use. However, this
method needs further development before it becomes practical
.
The susceptor, as mentioned previously, is used to support the quartz crucible.
Graphite, because of its high-temperature properties is the material of choice for the
susceptor. A high-purity graphite, such as nuclear grade, is usually specified. This
high purity is necessary to prevent contamination of the crystal from impurities that
would be volitalized from the graphite at the temperature involved. Besides the sus-
ceptor, other graphite parts in the hot zone of the furnace require high purity. The sus-
ceptor rests on a pedestal whose shaft is connected to a motor that provides rotation.
The whole assembly can usually be raised and lowered to keep the melt level equidis-
tant from a fixed reference point, which is needed for automatic diameter control.
The chamber housing the furnace must meet several criteria. It should provide
easy access to the furnace components to facilitate maintenance and cleaning. The
furnace structure must be air tight to prevent contamination from the atmosphere, and
have a specific design that does not allow any part of the chamber to become so hot
that its vapor pressure in the chamber would be a factor in contaminating the crystal.
As a rule, the hottest parts of the puller are water cooled. Insulation is usually pro-
vided between the heater and the chamber wall.
To melt the charge, radio frequency (induction heating) or resistance heating
have been used. Induction heating is useful for small melt sizes, but resistance heating
is used exclusively in large pullers. Resistance heaters, at the power levels involved
(tens of kilowatts), are generally smaller, cheaper, easier to instrument, and more
efficient. Typically, a graphite heater is connected to a dc power supply.
Crystal-pulling mechanism The crystal-pulling mechanism must, with minimal
vibration and great precision, control two parameters of the growth process, the pull
rate and crystal rotation. Seed crystals, for example, are prepared to precise orienta-
tion tolerances, and the seed holder and pulling mechanism must maintain this preci-
sion perpendicular to the melt surface. Lead screws are often used to withdraw and
rotate the crystal. This method unambiguously centers the crystal relative to the cruci-
ble, but may require an excessively high apparatus if the grower is to produce long
crystals. Since precise mechanical tolerance is difficult to maintain over a long shaft,
pulling with a cable may be necessary. Centering the crystal and crucible is more dif-
ficult when using cable. Furthermore, although the cable provides a smooth pulling
action, it is prone to pendulum effects. However, since the cable can be wound on a
drum, the height of the machine can be smaller than a similar, lead-screw puller. The
crystal leaves the furnace through a purge tube, where (if present) ambient gas is
directed along the surface of the crystal to affect cooling. From the purge tube, the

28 VLSI Technology
crystal enters an upper chamber, which is usually separated from the furnace by an
isolation valve.
Ambient control Czochralski growth of silicon must be conducted in an inert gas or
vacuum, because ( 1) the hot graphite parts must be protected from oxygen to prevent
erosion and (2) the gas around the process should not react with the molten silicon.
Growth in vacuum meets these requirements; it also has the advantage of removing
silicon monoxide from the system, thus preventing its buildup inside the furnace
chamber. Growth in a gaseous atmosphere must use an inert gas, such as helium or
argon. The inert gas may be at atmospheric pressure or at reduced pressure. Growing
operations on an industrial scale use argon because of its lower cost. A typical con-
sumption is 1500 L/kg of silicon grown. The argon is supplied from a liquid source
by evaporation, and must meet requirements of purity relating to moisture, hydrocar-
bon content, and so on.
Control system The control system can take many forms, and provides control of
process parameters such as temperature, crystal diameter, pull rate, and rotation
speeds. This control may be closed loop or open loop. Parameters, including pull
speed and rotation, with a high response speed are most amenable to closed-loop con-
trol. The large thermal mass of the melt generally precludes any short-term control of
the process according to temperature. For example, to control the diameter an infrared
temperature sensor can be focused on the melt-crystal interface and used to detect
changes in the meniscus temperature. The sensor output is linked to the pull mechan-
ism, and controls the diameter by varying the pull rate. The trend in control systems is
to digital microprocessor-based systems. These rely less on operator intervention and
have many parts of the process preprogrammed.
1.3.4 Impurity and Defect Considerations
Oxygen in silicon is an unintentional impurity arising from the dissolution of the cru-
cible during growth. Typical values^^^ range from 5 x lO'^ to lO'^ atoms/cm The
reported segregation coefficient for oxygen is 1.25; however, the axial distribution of
impurities often reflects the specifics of the puller and process parameters in use,
because they influence crucible erosion and evaporation of oxygen from the melt. For
example, less dissolution of the crucible occurs as the melt level is lowered in the cru-
cible, and thus less oxygen impurity is available for incorporation.^^ Rotation speeds,
ambient partial pressure, and free melt surface area are all factors that determine the
level and distribution of oxygen in the crystal."^ Figure 18 shows a typical diagram of
concentration versus fraction solidified. A novel method to reduce crucible erosion is
by suppressing thermal convection currents, which can be done by applying a mag-
netic field to the melt.^^ Such an approach also reduces the thermal fluctuations in the
boundary layer, resulting in a more homogeneous distribution of dopant atoms.
As an impurity, oxygen has three effectsr^^ donor formation, yield strength
improvement, and defect generation by oxygen precipitation. In the crystal as grown,
over 95% of the oxygen atoms occupy interstitial lattice sites. Oxygen in this state

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
(FRACTION SOLIDIFIED)
Fig. 18 The axial distribution of oxygen in a Czochralski ingot. (After Liaw, Ref. 35.)
can be detected using an infrared absorption line^^ at 1106 cm"'. The remainder of
the oxygen polymerizes into complexes, such as Si04. T his configuration acts as a
donor, thus distorting the resistivity of the crystal caused by intentional doping. These
complexes form rapidly in the 400 to 500°C temperature range, with a rate propor-
tional to the oxygen content to the fourth power. The complex formation occurs as the
crystal cools. Crystals of larger diameter cool slower and form more complexes. For-
tunately, these complexes are unstable above 500°C; so as common practice, crystals
or wafers are heated to between 600 and 700°C to dissolve the complexes. During
cooling, following the 600 to 700°C treatment, complexes can reform in crystals.
Because wafers cool rapidly enough to circumvent this problem, treatment in wafer
form is preferred for large diameter material. Common treatment times are tens of
minutes for wafers and about an hour for crystals. The longer time for crystals is
needed to bring the center of the ingot up to temperature. A typical dissolution rate for
these complexes is 5 x lO'^ donors/cm-^-h at 700°C.
Oxygen will also combine with acceptor elements to create a second type of
donor complex. These complexes form more slowly, 2 x lO''^ donors/cm^-h at
700°C, allowing for a net improvement using the stabilization treatment previously
described. The acceptor-element complexes are more resistant to dissolution even
with high-temperature processing. From a device viewpoint it is important that
material be resistivity stabilized by a suitable heat treatment prior to processing. It is
also important to avoid prolonged exposure during processing to the temperature
ranges we have discussed. The trend toward low-temperature processing poses a
dilemma, because complex formation could occur during the device processing. Com-
plex formation has not been fully researched at the present time.
Oxygen in interstitial lattice sites also acts to increase the yield strength of sili-
^Qj^40,4i
ti^ough the mechanism of solution hardening. Improvements of 25% over
oxygen-free silicon have been reported. This beneficial effect increases with concen-

30 VLSI Technology
2X10^8 _
10^8
9
8
7
6
5
3 -
2 X10^^
T(°C)
1000 1100 1200 1300 1400
"I—
r
INITIAL
CONCENTRATION
8
PROCESSING
TEMPERATURE T,
SOLUBILITY Ci
7 exio-"*
1/T (K"l)
Fig. 19 The solid solubility of oxygen in silicon. {After Patel, Ref. 38.)
tration until the oxygen begins to precipitate. Oxygen at the concentration levels men-
tioned earlier represents a supersaturated condition at most common processing tem-
peratures and will precipitate during processing, given a sufficient supersaturation
ratio. Precipitation usually occurs when the oxygen concentration exceeds a threshold
value"^^ of 6.4 x 10^^ atoms/cm^. The precipitation may proceed homogeneously, but
native defects, usually in the crystal from growth, allow heterogeneous precipitation
to dominate the kinetics. Figure 19 details the solubility of oxygen in silicon and illus-
trates the supersaturation effect. A wafer containing an initial concentration of oxygen
Co when processed at a temperature T^ results in a supersaturated condition. The
supersaturation which is Cq/C results because the oxygen solubility at Ti is only
C 1 , and is less than Cq.
The precipitates represent an Si02 phase. A volume mismatch occurs as the pre-
cipitates grow in size, representing a compressive strain on the lattice that is relieved
by the punching out of prismatic dislocation loops. Actually, a variety of defects,
including stacking faults, are associated with precipitate formation. These defects
attract fast diffusing metallic species, which give rise to large junction leakage
currents. The ability of defects to capture harmful impurities (called "gettering") can
be used beneficially. Defects formed in the interior of a wafer getter impurities from
the wafer surface where device junctions are located (Fig. 20). Gettering of defects is
explained more fully in Section 1 .5.
Carbon is another unintended impurity'^^
in the polysilicon, and is transported to
the melt from graphite parts in the furnace. Carbon in silicon occupies a substitutional
lattice site and is conveniently measured using infrared transmission measurements of

DEVICE
JUNCTIONS
wafer front surface
y
iM I'J
BULK stacking ^q ^q O Q O O
FAULTS ty c/ fc/ (*- L/ c/
CAPTURED OR
GETTERED
I MPURITY
o o o o o h
Q o o o o o o
^ ^ t
MOBILE IMPURITIES
Fig. 20 Schematic of a denuded zone in a wafer cross section and gettering sites, a and h are zones
denuded of defects, c represents the region of intrinsic gettering.
an absorption line at 603 cm"'. Because carbon's segregation coefficient is small
(0.07), its axial variation is large. Typical seed-end concentrations range from lO'^
atoms/cm^ and down. For butt ends at a high percentage of melt solidification, values
range-'^ up to 5 x lO'^ atoms/cm-^. At these levels carbon does not precipitate like
oxygen, nor is it electrically active. Carbon has been linked to the precipitation kinet-
ics of oxygen and point defects.''^ In this regard, its presence is undesirable because it
aids the formation of defects.
1.3.5 Characteristics and Evaluation of Crystals
Routine evaluation of crystals (also called "ingots" or "boules") involves testing
their resistivity, evaluating their crystal perfection, and examining their mechanical
properties, such as size and mass. Other less routine evaluations include measuring
the crystals' oxygen, carbon, and heavy metal content. The evaluations of heavy
metal content are made by minority carrier lifetime measurements or neutron activa-
tion analysis.
After growth the crystal is usually weighed and the ingot is then visually
inspected. Gross crystalline imperfections like twinning are apparent to the unaided
eye. Sections of the ingot containing such defects are cut from the boule, as are sec-
tions of the boule that are irregularly shaped or undersized. Total silicon loss can
equal 50% at this step. Next the butt (or tang) end of the ingot, or a slice cut from that
position, is preferentially etched to reveal defects such as dislocations. A common
etchant is Sirtl's etch, which is a 1:1 mixture of HF acid (49%) and five molar
chromic acid."*^ This same etch can be used on polished and processed wafers to delin-
eate other types of microdefects or impurity precipitates. Cracks can be detected by a
method using ultrasonic waves.
"^^
Resistivity measurements are made on the flat ends of the crystal by the four-
point probe technique (Fig. 21). Current I (mA) is passed through the outer probes and
voltage V (mV) measured between the inner probes. The measured resistance {V 11) is
converted to resistivity (H-cm) using the formula
p = (V//)27t5 (13)

32 VLSI Technology
Fig. 21 Four-point probe measurement on crystal end. (Courtesy P. H. hanger.)
where 5 is the probe spacing in centimeters. Measurements can be reproduced ±2% if
care is taken in selecting instrumentation, probe pressure, and current levels.
'^^•'*^
For
example, current levels are raised as the resistivity of the material is lowered, such
that the measured voltage is maintained between 2 and 20 mV. The variation of resis-
tivity with ambient temperature is a significant effect —approximately 1%/°C at 23°C
for 10 ri-cm material. The resistivity of the material is related to the doping density
through the mobility."*^ Figure 22 shows the relationship for boron- and phosphorus-
doped samples.
Boron-doped CZ silicon is available in resistivities from 0.0005 to 50 ft-cm, with
radial uniformities of 5% or better. Arsenic- and phosphorus-doped silicon is avail-
able in the range 0.005 to 40 ft-cm, with arsenic being the preferred dopant in the
lower resistivity ranges. Antimony is also used to dope crystals in the 0.01-ft-cm
range. Antimony-doped substrates are preferred as epitaxial substrates because auto-
doping effects are minimized (Chapter 2). Radial uniformities for n-doped material
range from 10 to 50% depending on diameter, dopant, orientation, and process condi-
tions.
50
1.4 SILICON SHAPING
Silicon is a hard, britde material registering 72.6 on the Rockwell "A" hardness
scale. The most suitable material for shaping and cutting silicon is industrial-grade
diamond, although SiC and AI2O3 have also found application. This section
highlights major shaping methods, but in some cases alternatives do exist. This sec-
tion also elucidates the relationship of these operations to the device processing needs
required of silicon slices.
Conversion of silicon ingots into polished wafers requires nominally six machin-
ing operations, two chemical operations, and one or two polishing operations.'*^'
^'
Additionally, assorted inspections and evaluations are performed between the major
process steps. A finished wafer is subject to a number of dimensional tolerances, die-

10'
10'
10^9 k
AO^^W
10
10^
17
15
10
lO^** =
lo^n
10^
!^
1 null —1 1 mm —1 1 1 mil
—TTTTTm I 1 1 mil —1 1 1 mil
^
"
:

I
"
^
"

;
-
;
~ "

:
-
V

=HOSP^^ORus^
V)RON ^
-
Vy.
!
Ns :
-
Vs.
!

k
=
1 1
1 1 iiiii 1 1 null 1 1 1 IIIII

-
1 ^llHll
10" 10" 10" 10" 10^ 10^ 10' 10- 10'
RESISTIVITY (il-cm)
Fig. 22 Conversion between resistivity and dopant density in silicon. {After Thurber, Mattis. and Liu, Ref.
49).
tated by the needs of the device fabrication technology. As shown in Table 3, these
tolerances are somewhat loose compared to metal machining capability. The
existence of organizations to standardize these factors^^ and their measurement^-^
proves the maturity of the silicon materials industry. The motivation for standards is
twofold. First, it helps to standardize wafer production, resulting in efficiency and
cost savings. Secondly, producers of process equipment and fixturing benefit from
knowing the wafer dimensions when designing equipment, and so forth.
Table 3 Typical specifications for 100- and 125-mm diameter wafers
Diameter 100±1 mm 125 ±0.5 mm
Primary flat 30-35 mm 40-45 mm
Secondary flat 16-20 mm 25-30 mm
Thickness 0.50-0.55 mm 0.60-0.65 mm
Bow 60 |jLm 70 [xm
Taper 50|JLm 60 |jLm
Surface orientation (100) ±1° Same
(111) off orientation Same

34 VLSI Technology
Fig. 23 Schematic of grinding process, ('^/'^''^o"''''^' ^^Z^' '^'5. j
1.4.1 Shaping Operations
The first shaping operation removes the seed and tang ends from the ingot. Portions
of the ingot that fail the resistivity and perfection evaluations previously mentioned
are also cut away. The cuttings are sufficiently pure to be recycled, after cleaning, in
the growing operation. The rejected ingot pieces can also be sold as metallurgical-
grade silicon. The cutting is conveniently done as a manual operation using a rotary
saw.
The next operation is a surface grinding, and is the step that defines the diameter
of the material. Silicon ingots are grown slightly oversized because the automatic
diameter control in crystal growing cannot maintain the needed diameter tolerance,
and crystals cannot be grown perfectly round. Figure 23 shows schematically lathe-
like machine tool used to grind the ingot to diameter. A rotating cutting tool makes
multiple passes down a rotating ingot until the chosen diameter is attained. Precise
diameter control is required for many kinds of processing equipment, and is a con-
sideration in the design of processing and furnace racks.
Following diameter grinding, one or more flats are ground along the length of the
ingot. The largest flat, called the "major" or "primary flat," is usually located rela-
tive to a specific crystal direction. The location is accomplished by an x-ray tech-
nique. The primary flat serves several purposes. It is used as a mechanical locator in
automated processing equipment to position the wafer, and also serves to orient the IC
device relative to the crystal in a specific manner. Other smaller flats are called
"secondary flats," and serve to identify the orientation and conductivity type of the
material (Fig. 24). Secondary flats provide a means of quickly sorting and identifying
wafers, should mixing occur.
Once the above operations have prepared the ingot it is usually ready to be con-
verted to a wafer geometry. Slicing is important because it determines four wafer
parameters: surface orientation, thickness, taper, and bow. The surface orientation is

{111} n- TYPE TYPE
SECONDARY
FLAT U-,J SECONDARY
FLAT
[100} n- TYPE {100} p- TYPE
Fig. 24 Identifying flats on silicon wafer. (SEMI standard, used by permission.)
determined by cutting several wafers, measuring the orientation by an x-ray method,
and then resetting the saw until the correct orientation is achieved. Wafers of (100)
orientation are usually cut "on orientation" (Table 3). The tolerances allowed for
orientation do not adversely affect MOS device characteristics such as interface-trap
density. The other common orientation, (111), is usually cut "off orientation," as
required for epitaxial processing (Chapter 2). Routine manufacturing tolerances are
also acceptable here.
The wafer thickness is essentially fixed by slicing, although the final value
depends on subsequent shaping operations. Thicker wafers are better able to withstand
the stresses of subsequent thermal processes (epitaxy, oxidation, and diffusion), and
as a result exhibit less tendency to plastically or elastically deform in such processing.
A major concern in slicing is the blade's continued ability to cut wafers from the crys-
tal in very flat planes. If the blade deflects during slicing, this will not be achieved.
By positioning a capacitive sensing device near the blade, blade position and vibra-
tion can be monitored, and higher-quality cutting achieved. If a wafer is sliced with
excessive curvature (bow), subsequent lapping operations may not be able to correct
it, and surface flatness objectives cannot be obtained by polishing.
Inner diameter (ID) slicing is the most common mode of slicing. ID slicing uses a
saw blade whose cutting edge is on the interior of an annulus. Figure 25 shows a
schematic of the process. The ingot is prepared for slicing by mounting it in wax or
epoxy on a support, and then positioning the support on the saw. This procedure
ensures that the ingot is held rigid for the slicing process. Some success has been

36 VLSI Technology
SAW BLADE
BLADE TRANSLATION
Fig. 25 Schematic of ID slicing process.
obtained mounting ingots in a fixture using iiydraulic pressure. The saw blade is a thin
sheet of stainless steel (325 ixm), with diamond bonded on the inner rim. This blade is
tensioned in a collar and then mounted on a drum that rotates at high speed (2000
r/min) on the saw. Saw blades up to 58 cm in diameter with a 20 cm opening are
available. Thus, slicing capability up to nearly the ID opening of 20 cm exists. The
blade is moved relative to the stationary ingot. The cutting process is water cooled.
The kerf loss (loss due to blade width) at slicing is 325 fxm, which means that approx-
imately one-third of the crystal is lost as sawdust. Cutting speeds are nominally 0.05
cm/s, which, considering that wafers are sliced sequentially, is a rather slow process.
Another shortcoming is the drum's finite depth, which limits the length of the ingot
section that can be cut into wafers. Another style ID saw mounts the blade on an air-
bearing and provides rotation using a belt drive. This arrangement allows any length
of ingot to be sliced; after slicing, individual wafers are recovered opposite the feed
side and placed in a cassette. Such a saw, which hydraulically mounts the ingot,
represents a highly automatic approach to sawing.
The wafer as cut varies enough in thickness to warrant an additional operation, if
the wafers are intended for VLSI application. A mechanical, two-sided lapping opera-
tion (Fig. 26), performed under pressure using a mixture of AI2 O3 and glycerine, pro-
duces a wafer with flatness uniform to within 2 ixm . This process helps ensure that
surface flatness requirements for photolithography can be achieved in the subsequent
polishing steps. Approximately 20 fxm per side is removed.
A final shaping step is edge contouring, where a radius is ground on the rim of
the wafer (Fig. 27). This process is usually done in cassette-fed high-speed equip-
ment. Edge-rounded wafers develop fewer edge chips during device fabrication and
aid in controlling the buildup of photoresist (Chapter 7) at the wafer edge. Chip sites

Fig. 26 Double-sided lapping machine.
act as places where dislocations can be introduced during thermal cycles and as places
where wafer fracture can be initiated. The silicon chips themselves, if present on the
wafer surface, add to the Dq (defect density) of the IC process reducing yield
(Chapter 14).
1.4.2 Etching
The previously described shaping operations leave the surface and edges of the wafer
damaged and contaminated, with the depth of work damage depending on the specif-
ics of the machine operations. The damaged and contaminated region is on the order
of 10 |jim deep and can be removed by chemical etching.
Historically, mixtures of hydrofluoric, nitric, and acetic acids have been used,
but alkaline etching, using potassium or sodium hydroxide, has found application.

38 VLSI Technology
(a)
CONTOURED
EDGE
CUTTING TOOL
WAFER
(b)
Fig. 27 (a) Cassette feed edge-contouring tooL (b) Schematic of edge-contouring process.
The process equipment includes an acid sink, which contains a tank to hold the
etching solution, and one or more positions for rinsing the wafers in water. The pro-
cess is batch in nature, involving tens of wafers. The best process equipment provides
a means of rotating the wafer during acid etching to maintain uniformity. Processing
is usually performed with a substantial overetch to assure all damage is removed. A
removal of 20 xm per side is typical. The etching process is checked frequently by
gauging wafers for thickness before and after etching. Etch times are usually on the
order of several minutes per batch.

The chemistry of the etching reaction is electrochemical. The dissolution
involves oxidation-reduction processes, followed by a dissolution of an oxidation pro-
duct. In the hydrofluoric, nitric, and acetic acid etching system"*^-^' nitric acid is the
oxidant and hydrofluoric acid dissolves the oxidized products according to the reac-
tion:5^55
3Si + 4HNO3 + 18HF => 3H2SiF6 + 4N0 + SH.O (14)
Acetic acid dilutes the system so that etching can be better controlled. Water can also
be used, but acetic acid is preferable because water is a by-product of the reaction.
The etching can be isotropic or anisotropic, according to the acid mixture or tempera-
ture. In HF-rich solutions, the reaction is limited by the oxidation step. This regime of
etching is anisotropic, and the oxidation reaction is sensitive to doping, orientation,
and defect structure of the crystal (where the oxidation occurs preferentially). The use
of HN03-rich mixtures produces a condition of isotropic etching, and the dissolution
process is then rate limiting. Over the range 30 to 50°C, the etching kinetics of an
HN03-rich solution have been found to be diffusion controlled rather than reaction
rate limited (Fig. 28). Thus, transport of reactant products to the wafer surface across
a diffusion boundary layer is the controlling mechanism. For these reasons, the
HN03-rich solutions are preferred for removing work damage. Rotating the wafers in
solution controls the boundary layer thickness and thereby provides dimensional con-
trol of the wafer. The isotropic character of the etch produces a smooth, specular sur-
face. A common etch formulation is 4:1:3; aie concentrations are 70% by weight
HNO3, and 497c by weight HF and HC. H3 O2.
Unfortunately, the dimensional uniformity introduced by the lapping step is not
maintained across large diameter wafers (>75 mm) to a degree compatible with main-
taining surface flatness in polishing. The hydrodynamics of rotating a large diameter
wafer in solution do not allow for a uniform boundary layer, so a taper is introduced
into the wafer. Projection lithography places demands on surface flatness that necessi-
tates the use of alkaline etching. Alkaline etching is by nature anisotropic, since it
depends on the surface orientation. The reaction is apparently dominated by the
number of dangling bonds present on the surface. The reaction is generally reaction
rate limited, and wafers do not have to be rotated in the solution. Since boundary
layer transport is not a factor, excellent unformity can be achieved. As in the acid
etching case, the reaction is twofold when a mixture of KOH/H2O or NaOH/H20 is
used.''^ A typical formulation uses KOH and H2O in a 45% by weight solution at 90°C
to achieve an etch rate of 25 fim/min for {100} surfaces. An occasional problem with
the damage removal process is insufficient etching, which can lead to the generation
of dislocations in subsequent treatments because of residual damage.
1.4.3 Polishing
Polishing is the final step. Its purpose is to provide a smooth, specular surface where
device features can be photoengraved. A main VLSI concern is to produce a surface
with a high degree of surface flatness and minimum local slope to meet the require-
ments of optical projection lithography.^^ Values between 5 and 10 |xm are typical

40 VLSI Technology
TEMPERATURE CC
)
50 45 40 35 30 25 20
100
80
40 -
20
1 1 1 1 1 1 1 1
CV 45 7„HN03, 20 7„HF,35%HC2H302
N,,^ O NON - CATALYZED

-

-

-

REACTION KINETICS
-
REACTION KINETICS SURFACE DOMINATED
DIFFUSION DOMINATED- "n"* ETCHING IS
SMOOTH SURFACE PREFERENTIAL
1 1 1 1 1 1
3 1 3 2 33 3 4
1000/T (K' '
3 5
Fig. 28 Typical etch rate versus temperature curve for one mixture of HF, HNO3, and HC2H3O2 acids.
(After Robhins and Schwartz, Ref. 54.)
surface flatness specifications. The surface is also required to be free from contami-
nation and damage.
Figure 29 shows a typical polishing machine and a schematic of the process. The
process requires considerable operator attention for loading and unloading. It can be
conducted as a single-wafer or batch-wafer process depending on the equipment.
Economics determines the choice of single or batch processing; larger wafers are pre-
ferred for single-wafer processing. Single-wafer processing is also felt to offer a
better means of achieving surface flatness goals. In both single and batch processing,
the process involves a polishing pad made of artificial fabric, such as a polyester felt,
polyurethane laminate. Wafers are mounted on a fixture, pressed against the pad
under high pressure, and rotated relative to the pad. A mixture of polishing slurry and
water is dripped onto the pad to accomplish the polishing (which is both a chemical
and mechanical process). The porosity of the pad is a factor in carrying slurry to the

(a)
PRESSURE
I
WAFER holder"
WAFER
5 SLURRY
6
POLISHING PAD
(b)
Fig. 29 (a) Photograph of polishing machine, (b) Schematicof polishing process.
wafer for polishing. The slurry is a colloidal suspension of fine Si02 particles (lOO-A
diameter) in an aqueous solution of sodium hydroxide. Under the heat generated by
friction, the sodium hydroxide oxidizes the silicon with the 0H~ radical. This is the
chemical step. The mechanical step abrades the oxidized silicon aw^y, by the silica
particles in the slurry. Polishing rate and surface finish are a complex function of
pressure, pad properties, rotation speed, slurry composition, and pH. Typical
processes remove 25 |xm of silicon. In a batch process involving tens of wafers, sili-
con removal can take 30 to 60 min; single-wafer processing can be accomplished in 5
min. Single-wafer processes use higher pressures than the batch processes.

42 VLSI Technology
K
SECOND LAYER : RESILIENT,
CARRIER COMPRESSIBLE IN VOLUME
/ ^WAFER
TOP LAYER; —^
HIGH FRICTION COEFFICIENT,
PLIABLE .COMFORMABLE, WATERPROOF
Fig. 30 Schematic of Flex-Mount'™ (Flex-Mount is a trademark of Siltec Corp.. Menlo Park, California)
polishing process. (After Bonara, Ref. 58.)
The method of mounting wafers for poHshing also deserves attention. Histori-
cally, wafers were waxed onto a metal plate. This method is costly and may not give
the best surface flatness. An alternative (Fig. 30) is a waxless technique where wafers
are applied to a conformal pad, typically a two-layer vinyl. ^^ This method is cost
effective and eliminates the influence of rear surface particles on front surface flat-
ness. After polishing, wafers are cleaned with acid and/or solvent mixtures to remove
slurry residue (and wax), and readied for inspection. Polished wafers are subjected to
a number of measurements that are concerned with cosmetic, crystal perfection,
mechanical, and electrical attributes.
Figure 3 1 shows how the industry has used wafers of increasingly larger diameter
motivated in part by the trend to larger chip areas.
1.5 PROCESSING CONSIDERATIONS
In the IC processing of silicon wafers it is usually necessary to maintain the purity and
perfection of the material.
1.5.1 Gettering Treatments
Many VLSI circuits (dynamic RAMs), require low junction leakage currents.
Narrow-base bipolar transistors are sensitive to conductive impurity precipitates,
which act like shorts between the emitter and collector (the pipe effect). Metallic
impurities, such as transition group elements, are responsible for these effects. These
elements are located at interstitial or substitional lattice sites and are generation-
recombination centers for carriers. The precipitated forms of these impurities are usu-
ally silicides, which are electrically conductive. To remove impurities from devices, a
variety of processing techniques are available, termed "gettering" treatments."*"
"Gettering" is a general term taken to mean a process that removes harmful impuri-
ties or defects from the regions in a wafer where devices are fabricated. Among these
techniques are ways to pretreat (i.e., pregetter) silicon wafers prior to IC processing.
Pregettering provides a wafer with sinks that can absorb impurities as they are intro-
duced during device processing.

200
I960 1970 1980 1990
YEAR
Fig. 31 Diameter and chip area progression for silicon wafers by year.
One technique of removing impurities involves intentionally damaging the back
surface of the wafer. Mechanical abrasion methods such as lapping or sand blasting
have been used for this purpose. A more controllable process uses damage created by
a focused laser beam.''^ This process requires a threshold energy density of 5 J/cm^.
One configuration of this technique involves using a Q-pulsed, Nd:YAG laser. The
laser beam is rastered along the back surface to create an array of micromachined
spots. Depending on the energy density and proximity of the spots, the silicon lattice
is damaged and/or strained by the high-energy pulse. Upon thermal processing, dislo-
cations emanate from the spots. If the stresses placed on the wafer during furnace pro-
cessing are low, the dislocations remain localized on the back surface. The disloca-
tions represent favorable trapping sites for fast diffusing species. For example, the
diffusion length of iron for 30 min at 1000°C is 3000 (xm compared to slice
thicknesses of 300 to 500 xm. When trapped on the rear surface, these impurities are
innocuous.
Another series of methods uses the defects associated with oxygen precipitation
for trapping sites. These methods use one or more thermal cycles to produce the
desired result."^ They usually involve a high-temperature cycle (over 1050°C in nitro-

44 VLSI Technology
Fig. 32 (a) The left-hand photograph shows a denuded zone (DZ) in a wafer cross section after a preferen-
tial etch. K . Ki. and K :, are small stacking fault defects. The right-hand photograph is another wafer cross
section showing stacking faults (OSF) and precipitate features (H) below the DZ. (Courtesy G. A. Roz-
gonyi.)
gen), which removes oxygen from the surface of the wafer by evaporation. ^° This
lowers the oxygen content near the surface so that precipitation does not occur,
because the supersaturated condition has been removed. The depth of the oxygen-poor
region is a function of time and temperature, and depends on the diffusivity of oxygen
in sihcon (Fig. 32). The region represents a defect-free zone (denuded zone) for de-
vice fabrication. Additional thermal cycles can be added to promote the formation of
precipitates and defects in the interior of the wafer. This approach is called "intrinsic
gettering" because the oxygen is native to the wafer. Intrinsic gettering is attractive
because it fills the volume of the wafer with trapping sites. Otherwise, the bulk of the
wafer really serves no useful function beyond mechanically supporting the thin layer
where the device is formed. Both intrinsic gettering and intentionally damaging the
back of the devices have been successfully employed in circuit fabrication
processes.^''
^^

5 10 15 20 25 30 35 40 45 50 55
TIME (h)
(b)
Fig. 32 (b) Denuded zone width for two sets of processing conditions.
1.5.2 Thermal Stress Factors
We generally want to maintain the ctystal perfection of wafers through the device
fabrication process, and to keep them mechanically undeformed. Wafers are typically
processed in furnaces using racks with a high wafer-diameter-to-spacing ratio. Upon
removing the wafer from a high-temperature furnace, the wafer edges cool rapidly by
radiation to the surroundings, but the wafer centers remain relatively hotter.'^ The
resultant temperature gradient creates a thermal stress S that can be estimated as:
S = aE dT (15)
where a is the coefficient of thermal expansion, E is Young's modulus, and dT^ the
temperature difference across the slice.
If these stresses exceed the yield strength (the maximum stress the material will
accommodate without irreversible deformation) of the material, dislocations will
form. Stresses are usually kept to acceptable levels by slowly withdrawing wafers
from the furnace to minimize the temperature gradient, or by lowering the furnace
temperature'^ prior to removing the wafers to the point where the yield strength at the
removal temperature exceeds the stresses imposed (Fig. 33).
Material parameters must also be considered. Oxygen precipitates (useful for
gettering) can reduce the yield strength (critical shear stress) up to fivefold (Fig. 33).
Wafer thickness and bow must also be considered as bow enhances the thermal

46 VLSI Technology
50
20
10
(/) 1
-

v OXYGEN
_s. PRECIPITATED
(lo'^atoms/cm^)
-
v
1
1 1 1 1 1 1 1 i
1
1
10 7 4 1
1 1 1 1
<
I
0.5
a:
0.2
700 800 900 1000 1100
TEMPERATURE (°C)
Fig. 33 Yield strength of silicon showing the influence of oxygen precipitates. (After Leroy and Plougoven.
Ref. 63.)
Stress. ^^ Thus, the design of furnace cycles must consider the worst case combinations
of oxygen precipitation and bow present in the processed wafers. Therefore, because
of these effects the thickness of wafers is usually increased as the diameter increases.
1.6 SUMMARY AND FUTURE TRENDS
Silicon wafers have been and will continue to be the predominant material for solid-
state device manufacture. In the VLSI device arena, some other material technologies
will also become common. The two main contenders are silicon-on-insulator (e.g., Si
on Si02) and compound semiconductors (notably GaAs). These technologies will be
chosen when high-speed circuitry or the need to optimize other circuit parameters are
the deciding factors.
The specifications placed on wafers will become more sophisticated for VLSI
applications. Unintentional impurities that are now ignored in specifications will need
maximum allowable levels placed upon them. This would also be true for carbon and
metallic species.^ Oxygen is already subject to such specifications, but additional
control over oxygen precipitation behavior as it relates to the growing process and
thermal cycling will probably be forthcoming. Mechanical dimensions will continue
to be driven by equipment and processing needs. In particular, lithographic evolution
will require flatter wafers. Surface cleanliness and other surface characteristics,
because they influence oxide-silicon interface state density, may represent a new class
of specification and a new area of study. Laser marking of wafers for identification
purposes will also become a new attribute.

Large diameter wafers (>150 mm) are feasible and 200-mm wafers have been
produced. Practical implementation is awaiting the need for further productivity
improvements and improved circuit fabrication capability, particularly in the litho-
graphic area. Ingots of larger diameters will be grown in big pullers. The slower cool-
ing rates experienced by these such materials may alter the properties of the material,
particularly the point-defect kinetics. This topic provides an area for continued
research, because properties of the material are related to defects formed in device
processing, and thus related to IC yield.
REFERENCES
[1] C. L. Yaws, R. Lutwack, L. Dickens, and G. Hsiu, "Semiconductor Industry Silicon: Physical and
Thermodynamic Properties," Solid State TechnoL. 24, 87 ( 1981).
[2] J. C. Bailar, Editor, Comprehensive Inorganic Chemistry, 1, Pergamon Press, New York, 1973.
[3] W. Shockley, "The Theory of p-n Junctions in Semiconductors and p-n Junction Transistors," Bell
Syst. Tech. J., 28, 435 {949).
[4] L. D. Grossman and J. A. Baker, "Polysilicon Technology," Semiconductor Silicon 1977. Electro-
chem. Soc., Pennington, New Jersey, 1977, p. 18.
[5] Am. Soc. Test. Mater., ASTM Standard, F574, Part 43.
[6] W. Dietze, L. P. Hunt, and D. H. Sawyer, "The Preparation and Properties of CVD-Silicon Tubes
and Boats for Semiconductor Device Technology," J. Electrochem. Soc, 121 , 1112 (1974).
[7] S. N. Rea, "Gzochralski Silicon Pull Rate Limits," 7. Cryst. Growth, 54, 267 ( 1981).
[8] R. A. Laudise, The Growth of Single Crystals, Prentice Hall, Englewood Cliffs, New Jersey, 1970.
[9] L. D. Dyer, "Dislocation-Free Gzochralski Growth of (110) Silicon Crystals," J. Cryst. Growth, 47,
533(1979).
[10] K. V. Ravi, Imperfections and Impurities in Semiconductor Silicon. Wiley, New York, 198 1
.
[11] R. K. Watts, Point Defects in Crystals, Wiley and Sons, New York, 1977.
[12] A. G. Milnes, Deep Levels in Semiconductors. Wiley, New York, 1973.
[13] J. Friedel, Dislocations, Pergamon Press, New York, 1964.
[ 14] A. J. R. deKock and W. M. van de Wijgert. "The Effect of Doping on the Formation of Swirl Defects
in Dislocation-Free Gzochralski-Grown Silicon," J. Cryst. Growth, 49, 718 (1980).
[15] S. M. Hu, "Temperature Distribution and Stresses in Gircular Wafers in a Row during Radiative Cool-
ing," J. Appl. Phys., 40, 4413 ( 1969).
[16] K. G. Moerschel, C. W. Pearce, and R. E. Reusser, "A Study of the Effects of Oxygen Content, Ini-
tial Bow and Furnace Processing on Warpage of Three-Inch Diameter Silicon Wafers," Semiconductor
Silicon 1977, Electrochem. Soc, Pennington, New Jersey, 1977, p. 170.
[17] S. Kishino, Y. Matsushita, and M. Kanamori. "Carbon and Oxygen Role for Thermally Induced
IVIicrodefect Formation in Silicon," Appl. Phys. Lett.. 35, 213 ( 1979).
[18] A. Armigliato. D. Nobili. P. Ostoja, M. Servidori, and S. Solmi, "Solubility and Precipitation of
Boron in Silicon," Semiconductor Silicon 1977, Electrochem. Soc, Pennington, New Jersey, 1977,
p. 638.
[19] W. T. Stacy, D. F. Allison, and T. C. Wu, "The Role of Metallic Impurities in the Formation of Haze
Defects," Semiconductor Silicon 1981 , Electrochem. Soc, Pennington, New Jersey, 1981, p. 344.
[20] B. R. Pamplion, Crystal Growth, Pergamon Press. New York, 1983.
[21] W. R. Runyan, Silicon Semiconductor Technology, McGraw-Hill, New York, 1965.
[22] T. G. Digges, Jr. and R. Shima, "The Effect of Growth Rate, Diameter and Impurity Concentration
on Structure." J. Cryst. Growth, 50, 865 (1980).
[23] S. M. J. G. Van Run, "A Critical Pulling Rate for Remelt Suppression in Silicon Crystal Growth," J.
Cryst. Growth, 53, 441 (98).
[24] H. Kolker, "The Behavior of Nonrotational Striations in Silicon," J. Cryst. Growth, 50, 852 (1980).

48 VLSI Technology
[25] J. Chikawa and S. Yoshikawa, "Swirl Defects in Silicon Single Crystals," Solid State TechnoL, 23,
65(1980).
[26] J. A. Burton, R. C. Prim, and P. Slichter.y. Chem. Phys.. 21, 1987 (1953).
[27] J. R. Carruthers, A. F. Win, and R. E. Reusser, "Czochralski Growth of Large Diameter Silicon Cry-
stals - Convection and Segregation," Semiconductor Silicon 1977, Electrochem. Soc., Pennington,
New Jersey, 1977, p. 61
.
[28] K. M. Kim, "Interface Morphological Instability in Czochralski Silicon Crystal Growth from Heavily
Sb-Doped Melt," 7. Electrochem. Soc, 126, 875 ( 1979).
[29] K. E. Benson, ,V. Lin, and E. P. Martin, "Fundamental Aspects of Czochralski Silicon-Crystal
Growth for VLSI," Semiconductor Silicon 1981, Electrochem. Soc., Pennington, New Jersey, 1981,
p. 33.
[30] M. H. Liepold, T. P. O'Donnell, and M. A. Hagan, "Materials of Construction for Silicon Crystal
Growth," J. Crysi. Growth, 40, 366 (1980).
[31] F. A. Voltmer and F. A. Padovani, "The Carbon-Silicon Phase Diagram for Dilute Carbon Concentra-
tion," Semiconductor Silicon 1973, Electrochem. Soc., Pennington, New Jersey, 1973, p. 75.
[32] H. Hirata and K. Hoshikawa, "The Dissolution Rate of Silica in Molten Silicon," Jpn. J. Appl. Phys.,
19, 1573(1980).
[33] B. Bathey, H. E. Bates, and M. Cretella, "Effect of Carbon on the Dissolution of Fused Silica in
Liquid Silicon," J. Electrochem. Soc, 128, 771 (1980).
[34] M. Watanabe, T. Usami, H. Muroaka, S. Matsuo, Y. Imanishi, and H. Nagashima, "Oxygen-Free
Silicon Single Crystal from Silicon-Nitride Crucible," Semiconductor Silicon 1981, Electrochem.
Soc., Pennington, New Jersey, 1981, p. 126.
[35] H. M. Liaw, "Oxygen and Carbon in Czochralski-Grown Silicon," Semicon. Int., 2,1( 1979).
[36] T. Carlberg, T. B. King, and A. F. Witt, "Dynamic Oxygen Equilibrium in Silicon Melts during Cry-
stal Growth," 7. f/mrof/zt'm. 5oc., 127, 189(1981).
[37] T. Suzuki, N. Isawa, Y. Okubo, and K. Hoshi, "CZ Silicon Growth in a Transverse Magnetic Field,"
Semiconductor Silicon 1981 , Electrochem. Soc., Pennington, New Jersey, 1981, p. 90.
[38] J. R. Patel, "Oxygen in Silicon," Semiconductor Silicon 1977. Electrochem. Soc., Pennington, New
Jersey, 1977, p. 521.
[39] Am. Soc. Test. Mater., ASTM Standard, F121-76, Part 43.
[40] J. Doerschel and F. G. Kirscht, "Differences in Plastic Deformation Behavior of CZ and FZ Grown
Silicon Crystals," Phys. Status SolidiA, 64, K85 (1981).
[41] K. Sumino et al., "The Origin of the Difference in the Mechanical Strengths of Czochralski Silicon,"
Jpn. J. Appl. Phys., 19, L49 (1980).
[42] C. W. Pearce, L. E. Katz, and T. E. Seidel, "Considerations Regarding Gettering in Integrated Cir-
cuits," Semiconductor Silicon 1981 , Electrochem. Soc., Pennington, New Jersey. 1981, p. 705.
[43] T. Nozaki, "Concentration and Behavior of Carbon in Semiconductor Silicon," J. Electrochem. Soc,
117, 1566(1970).
[44] Y. Matsushita, S. Kishino, and M. Kanamori, "A Study of Thermally Induced Microdefects in
Czochralski-Grown Silicon Crystals: Dependence on Annealing Temperature and Starting Material,"
Jpn. J. Appl. Phys., 19, LlOl (1980).
[45] D. G. Schimmel, "A Comparison of Chemical Etches for Revealing (100) Silicon Crystal Defects," J.
Electrochem. Soc, 123, 734 (1976).
[46] A. C. Bonora, "Silicon Wafer Process Technology: Slicing, Etching, Polishing," Semiconductor Sili-
con 1977, Electrochem. Soc., Pennington, New Jersey, 1977, p. 154.
[49] W. R. Thurber, R. L. Mattis, and Y. M. Liu, "Resistivity Dopant Density Relationship for Silicon,"
Semiconductor Characterization Techniques, Electrochem. Soc., Pennington, New Jersey, 1978,
p. 81.
[50] S. E. Bradshaw and J. Goorissin, "Silicon for Electronic Devices," J. Cryst. Growth, 48, 514
(1980).
[51] R. B. Hening, "Silicon Wafer Technology - State of the Art 1976," Solid State Technol., 19, 37
(1976).

[52] Semiconductor Equipment and Materials Institute (SEMI), Mountain View, California.
[53] The American Society for Testing and Materials (ASTM), Committee F-1 on Electronics, Philadel-
phia, Pennsylvania.
[54] H. Robbins and B. Schwartz, "Chemical Etching of Silicon," J. Electrochem. Soc, 106, 505 (1959);
107, 108(1960); 108, 365 (196ir; and 123, 1909(1976).
[55] W. Kern, "The Chemical Etching of Semiconductors," RCA Rev., 39, 278 (1978).
[56] I. Barycka, H, Teterycz, and Z. Znamirowski, "Sodium Hydroxide Solution Shows Selective Etching
of Boron-Doped Silicon," J. Electrochem. Soc. 126, 345 (1979).
[57] W. A. Baylies, "A Review of Flatness Effects in Microlithographic Technology," Solid State Tech-
noi.lA. 132(1981).
[58] A. C. Bonara, "Flex-Mount Polishing of Silicon Wafers," Solid State Technol.. 20, 55 ( 1977).
[59] C. W. Pearce and V. J. Zaleckas, "A New Approach to Lattice Damage Gettering," J. Electrochem.
Soc, 126, 1436(1979).
[60] K. Yamamoto, S. Kishino, Y. Matsushita, and T. Lizuka, "Lifetime Improvement in Czochralski-
Grown Silicon Wafers by the Use of aTwo Step Annealing," .4/7/?/. Phys. Lett., 36, 195 (1980).
[61] L. E. Katz, C. W. Pearce, and P. F. Schmidt, "Neutron Activation Study of a Gettering Treament for
CZSilkon Substrates," J. Electrochem. Soc, 128,620(1981).
[62] M. Ogino, T. Usami, and M. Watanabe, "Microdefects Due to Oxygen Precipitates and Their Appli-
cation to CMOS LSI and CCD Sensor," Electrochem. Soc. Extended Abstracts, 80-2, Abs. 435
(1980).
[63] B. Leroy and C. Plougoven, "Warpage of Silicon Wafers," J. Electrochem. Soc, 127, 961 (1980).
[64] P. F. Schmidt and C. W. Pearce, "A Neutron Activation Analysis Sttjdy of the Sources of Transistion
Group Metal Contamination in the Silicon Device Manufacturing Process," J. Electrochem. Soc,
128,630(1981).
PROBLEMS
1 Iron is an impurity in quartz crucibles. Using a concentration value of 2 x lO'^ /cnr' in the crucible,
assume 300 cm-' of the crucible is dissolved into a 6500-g melt, all at the beginning of the cycle. Calculate
the seed (0% solidified) and tang end (90% solidified) iron concentration in the ingot.
2 Using the equation governing crystal growth (Eq. 6), derive an expression relating growth rate inversely
to crystal diameter. Assume no temp)erature gradient in the melt. Since the heat flow down the crystal is
small, assume heat flow from the crystal is predominantly from radiation.
3 Calculate the number of gallons of HF and HNO3 acid needed to remove the work damage from 5000
wafers of 100-mm diameter.
4 The seed crystal used in CZ growing is usually "necked down" to a small diameter (3 mm) as a means to
initiate dislocation-free growth. Using the yield strength of silicon, calculate the maximum mass of silicon
that could be supported by such a seed. Convert this to a length for 100- and 1 25-mm-diameter crystals.
5 Large growers, such as that pictured in the chapter, require 120 kWh to convert a kilogram of polysilicon
into a crystal. Account for this energy in terms of the energy needed to melt the silicon, the radiation loss
fiom the melt surface, and conduction down the crystal. Is all the energy accounted for? Assume that a 10-
kg charge of polysilicon is used to grow a 10-cm-diameter crystal from a 25-cm-diameter crucible at a rate of
0.0025 cm/s.
6 Solar cells have been suggested as an alternative energy source. Conduct the following feasibility calcula-
tion: How much polysilicon would be required to supply all the United States' electrical needs from 100-
mm-diameter Czochralski-grown silicon wafers, and how much land area would this require? Compare the
silicon used to current consumption. Use the following data:
1
.
The average U.S. weekly power consumption is 42 x lO' kWh.
2. Assume that each gram of silicon in the finished cell required 5 g of polysilicon.
3. The average solar energy falling on the earth's surface is 1340 W/m"; assume 50 h of daylight per
week.
4. The cell will convert 8% of all incident energy to electrical power.

7 There are several economic motivations to scale up the melt sizes of industrial crystal growers. Larger
melt sizes increase the time a machine is actually growing a crystal, thus making it more productive. Calcu-
late the minimum crucible wall thickness needed under the following conditions: given a charge size of 100
kg, a crucible with a 25% larger volume than that of the silicon volume, a 1 2. 5-cm-diameter crystal growing
at a rate of 0.002 cm/s, and a crucible erosion rate of 2 x 10"^ g/crrr-s. Assume a unity aspect ratio for the
crucible. Also calculate the energy loss in kilowatt-hours from the surface of the melt using a temperature of
1450°C.
8 Using the gradient of Fig. 1 1 and Eq. 7 calculate a maximum pull speed. Assume the latent heat of fusion
to be 264 cal/g and the solid thermal conductivity to be 0.05 cal/s-cm-°C. Compare the result to Fig. 12.
What do you conclude?
9 At a temperature of 1000°C, calculate the boron concentration in the crystal that would lead to misfit
dislocation formation.

CHAPTER
TWO
EPITAXY
C. W. PEARCE
2.1 INTRODUCTION
Epitaxy, a transliteration of two Greek words epi, meaning "upon," and taxis, mean-
ing "ordered," is a term applied to processes used to grow a thin crystalline layer on
a crystalline substrate. In the epitaxial process the substrate wafer acts as a seed crys-
tal. Epitaxial processes are differentiated from the Czochralski process described in
Chapter 1 in that the crystal can be grown below the melting point. Most epitaxial
processes use chemical-vapor deposition (CVD) techniques. A different approach is
molecular beam epitaxy (MBE) which uses an evaporation method. These processes
will be described in Sections 2.2 and 2.3, respectively. When a material is grown epi-
taxially on a substrate of the same material, such as silicon grown on silicon, the pro-
cess is termed homoepitaxy. If the layer and substrate are of different materials, such
as Al^ Gai_v As on GaAs, the process is termed heteroepitaxy. However, in hetero-
epitaxy the crystal structures of the layer and the substrate should be similiar if crys-
talline growth is to be obtained.
Silicon epitaxy was developed to enhance the performance of discrete bipolar
transistors.' These transistors were fabricated in bulk wafers using its resistivity to
determine the breakdown voltage of the collector. However, high breakdown vol-
tages necessarily need high-resistivity material. This requirement coupled with the
thickness of the wafer results in excessive collector resistance that limits high-
frequency response and increases power dissipation. Epitaxial growth of a high-
resistivity layer on a low-resistivity substrate solved this problem. Bipolar integrated
circuits utilize epitaxial structures in much the same way discrete transistors (Fig. 1)
utilize them. The substrate and epitaxial layer have opposite doping types to provide
isolation, and a heavily doped diffusion layer serves as a low-resistance collector con-
tact. Unipolar devices such as the junction field-effect transistor (JFET) employ an
epitaxial wafer as does the VMOS technology."
51

52 VLSI Technology
(a)
n EPITAXIAL LAYER
'n"^ BURIED -(^^^^^^
077777///////////^
,8unn, 20 n/D ---'^^'"^^^^^^^^^^^^^^^ ^
S/iPn, 1 n-cm
A
(b)
P SUBSTRATE 500/xm, 10 il-cm
Fig. 1 Cross-sectional schematic (b) of an epitaxial wafer used for integrated circuit fabrication. Part (a)
represents a rectangular pattern A present on the substrate prior to epitaxy, whose location is shifted by L
and shape distorted to shape B by the epitaxial process.
Epitaxial structures have also been used to improve the performance^ of dynamic
random-access memory devices (RAMs) and CMOS ICs. In JFETs and VMOS cir-
cuits the doping profile provided by the epitaxial process is integral to the device
structure. In the dynamic RAMs and CMOS circuits, devices could be fabricated in
bulk wafers, but certain circuit parameters are optimized using epitaxial material.
The fundamental advantages of epitaxial wafers over bulk wafers are thus two-
fold. First, epitaxial layers (one or more) on a substrate, often containing one or more
buried layers, offer the device designer a means of controlling the doping profile in a
device structure beyond that available with diffusion or ion implantation. Second, the
physical properties of the epitaxial layer differ from bulk material. For example, epi-
taxial layers are generally oxygen and carbon free, a situation not obtained with the
melt-grown silicon discussed in Chapter 1
.
2.2 VAPOR-PHASE EPITAXY
This section is concerned with several aspects of silicon vapor-phase epitaxy such as:
process chemistry, aspects of process hardware, and current capabilities. The CVD of
single-crystal silicon is usually performed in a reactor consisting in elemental form of
a quartz reaction chamber into which a susceptor is placed. The susceptor provides
physical support for the substrate wafers. Deposition occurs at a high temperature
where several chemical reactions take place when process gases flow into the
chamber.
2.2.1 Basic Transport Processes and Reaction Kinetics
A thorough study of the deposition process involves examining the thermodynamics
and kinetics of the chemical reactions and the fluid mechanics of the gas flows in the
reactor."^

Epitaxy 53
As a starting point for discussing the fluid mechanics of the gas flow let us con-
sider the Reynolds number R^ , a dimensionless parameter that characterizes the type
of fluid flow in the reactor.
R. = (1)
where D^ is the hydraulic diameter of the reaction tube, v is the gas velocity, p is the
gas density, and x is the gas viscosity.
Values of Df and v are generally several centimeters and tens of cm/s, respec-
tively, for industrial processes. These parameters result in gas flow in the laminar
regime,^ since R^ is less than 2000. Accordingly, a boundary layer of reduced gas
velocity will form above the susceptor and at the walls of the reaction chamber. The
thickness of the boundary layer v is defined as
V =
DrX
R.
'/2
(2)
where x is distance along the reaction chamber.
The carrier gas is usually hydrogen and using its typical values for p and |jl in Eq.
1 results in values fovR^ of about 100.
Figure 2 shows that the boundary layer forms at the inlet to the reaction chamber
and increases until the flow is fully established. Although fully established flows are
not always encountered in the short lengths of typical reactors, it is across this boun-
dary layer that reactants are transported to the surface. The reaction by-products dif-
fuse back across the boundary layer and are removed by the main gas stream. The
fluxes of species going to and coming from the wafer surface are a complex function
REACTANT
CONCENTRATION
CHANGES
DECREASE
VELOCITY
CHANGES
NCREASE
X
o
of
TEMPERATURE
CHANGES
NCREASE
X
FLOW
r
^d.
UPPER BOUNDARY LAYER
CENTRAL CORE
LOWER BOUNDARY
LAYER
'
• •
^
•
•
SUSCEPTOR
C- CONCENTRATION PROFILE
V - VELOCITY PROFILE
T- TEMPERATURE PROFILE
Fig. 2 Boundary layer formation in a horizontal reactor. {After Ban. Ref. 4.)

54 VLSI Technology
20
e
=^ 15
0-
05
V Re
1
= 250 —
-
1
92.6
^^50
1
-
1
10 20 30
POSITION ALONG THE SUSCEPTOR (cm
)
40
Fig. 3 The influence of R^ number on deposition uniformity. (Afte?- Manke andDonaghey, Ref. 6.)
of several variables, including temperature, system pressure, reactant concentration,
and layer thickness. By convention, the flux is defined as
J = D dn/dy (3)
and approximated as
Dirig - n,)
J
y
(4)
where tig and n^ are the gas stream and surface reactant concentrations, respectively,
D is the gas-phase diffusivity which is a function of pressure and temperature, y is the
boundary layer thickness, and J is the reactant flux of molecules per unit area per unit
time.
The first-order effect of v on the transport process must therefore be taken into
consideration when designing the reactor and evaluating the operating conditions. The
boundary layer must be adjusted relative to variation in temperature and reactant con-
centration within the reactor if uniformity of deposition is to be achieved. Figure 3
shows the sensitivity of layer growth rate to the Reynolds number. For a given reactor
and set of process conditions R^ is varied by changing the gas flow (velocity). There-
fore, >' is inversely proportional to gas velocity. Thus, Fig. 3 illustrates how the boun-
dary layer can be varied to achieve growth rate uniformity by varying the gas flow
(i.e., Re) in the reactor. This is a first-order approach to the problem. A rigorous
analysis of transport phenomena in a vertical cylinder reactor has been done.^ This
analysis is a numerical solution of the defining equations subject to appropriate boun-
dary conditions. The temperature dependance of the various parameters has been
included in this analysis. For example, Z) is a function of temperature T with a func-
tionality of approximately T'-. Figure 4 shows a substantial temperature gradient
normal to the susceptor surface. The steep temperature gradient also complicates the
fluid flow, because it creates some turbulence in the gas stream. The importance of
this effect relative to the laminar flow is described by the ratio of the Grashof number
(Gr ) to the square of the Reynolds number."^' ^^
The Grashof number is a dimensionless
parameter describing the effect of thermal convection in fluid flow. For Gr/Rg
greater than 0.5, the convection effects are found to be significant and can be seen as
oscillations in the temperature above the susceptor.

Epitaxy 55
3cm
Tg =I200°C, v = 50 cm/s
Fig. 4 Isotherms in a horizontal reactor. (After Ban. Ref. 4.)
Reaction kinetics Four silicon sources have been used for growing epitaxial silicon.
These are silicon tetrachloride (SiC^), dichlorosilane (SiH2Cl2), trichlorosilane
(SiHCl3), and silane^ (SiH^). Silicon tetrachloride has been the most studied and seen
the widest industrial use. It will be discussed here to exemplify the reaction chemis-
try. The outline of the discussion is applicable to the other halide compounds.
The overall reaction can be classed as a hydrogen reduction of a gas.
SiCUCgas) + 2H2(gas) => Si(solid) + 4HCl(gas) (5)
However, a number of intermediate and competing reactions must be considered to
understand the reaction fully. A starting point in the analysis is to determine for the
Si—CI—H system the equilibrium constant for each possible reaction and the partial
pressure of each gaseous species at the temperature of interest. Equilibrium calcula-
tions^ reveal fourteen species to be in equilibrium with solid silicon. In practice many
of the species can be ignored because their partial pressures are less than 10~^ atm.
Figure 5 shows the important species in the temperature range of interest. The plot is
for a particular Cl/H ratio (0.01) which is representative of the ratios that occur in
epitaxial deposition. Note that this ratio is constant in the reactor as neither chlorine
or hydrogen is incorporated into the layer.
The epitaxial process is not necessarily an equilibrium reaction. Thus, equili-
brium thermodynamic calculations may not present the total picture, but relate only to
the most probable reactions. In-situ measurements of the reaction process have been
made by infrared spectroscopy, mass spectroscopy, and Raman spectroscopy to deter-
mine which species are actually present in the reaction. Four species in a SiC^ + H2
reaction at 1200°C were detected.^ Figure 6 illustrates the concentrations of each
species at different positions along a horizontal reactor. Notice that the SiCl4 concen-
tration decreases while the other three constituents increase; thus the overall reaction
is postulated as
SiCl4 + H2 < = > SiHCl3 + HCl (6)
SiHCl3 + H2 < = > SiH2Cl2 + HCl (7)
SiH2Cl2 < = > SiCl2 + H2 (8)
SiHCl3 < = > SiCl2 + HCl (9)
SiCl7 + H2 < = > Si + 2HC1 (10)

56 VLSI Technology
300 500 700 900 1100 1300
TEMPERATURE (K)
1500 1700
Fig. 5 Temperature variation of the equilibrium gas phase composition at 1 atm and Cl/H =0.01. (After
Sirtl, Hunt, attd Sawyer, Ref. 8.)
This sequence of reactions is interesting from several viewpoints. The species SiHCl3
and SiH2Cl2 are seen as intermediates to the overall reaction. Thus, growth with these
halides would start at Eq. 7, 8, or 9. Accordingly, growth with SiC^ has the highest
reported activation energies (1.6 to 1.7 eV) decreasing in turn for SiHCl3 (0.8 to 1.0
eV) and SiH2Cl2 (0.3 to 0.6 eV). The reactions are also reversible, and, under the
appropriate conditions, the deposition rate can become negative causing the etching
process to begin. This observation leads to a more general question about how growth
rate varies with temperature. Figure 7 depicts the growth rate variation versus tem-
perature; note the negative deposition rate at low and high temperatures.
Figure 8 shows an Arrhenius plot of growth rate, illustrating the overall reac-
tion process. ^^ In region A the process can be characterized as reaction rate or kinetic
limited, that is, one of the chemical reactions is the rate-limiting step and is even
reversible. Region B represents the situation in which the transport processes are rate
limiting, that is, where the growth rate is limited either by the amount of reactant
reaching the wafer surface or by the reaction products diffusing away. This regime is
termed mass transport or diffusion limited, and the growth rate is linearly related to
the partial pressure of the silicon reactant in the carrier gas. The slight increase of the
growth rate with temperature in region B is due to the increased diffusivity of the
species with temperature in the gas phase. Industrial processes at atmospheric pres-
sure are usually operated in region B to minimize the influence of temperature varia-
tions.
2.2.2 Doping and Autodoping
Incorporating dopant atoms into the epitaxial layer involves the same considerations
as the growth process requires, for example, mass transport and chemical reactions.''

Epitaxy 57
^-3-
O
T = I200°C
INPUT Si CI4 6.25 X 10""* MOLES/
L
FLOW VELOCITY 44cm/s (25°C)
SI NORMAL DEPOSIT ZONE
'HCI
-• SiHCl3
-• SiCl4
SiHaCig
980 1100 1150 1180 1200
I
1 1 1 1 1 1
1 1 1
1
T(°C)
900 1050 1125 1170 1195 1200
5 10 15
X POSITION (cm)
Fig. 6 Species detected by IR spectroscopy in a horizontal reactor using SiCl4 + H2. (After Nishizawa and
Saito. Ref. 9.)
0.10
1200 1400
TEMPERATURE (K)
Fig. 7 Growth rate of CVD silicon versus temperature. (After Sirtl, Hunt, and Sawyer, Ref. 8.)

58 VLSI Technology
TEMPERATURE (°C)
1300 1200 1100 1000 900 800 600
IO''/T(K)
Fig. 8 Temperature dependence of growth rate for assorted silicon sources. (After Eversteyn, Ref. 10.)
Typically, hydrides of the impurity atoms are used as the source of dopant. We might
expect that these compounds would decompose spontaneously, but they do not. Ther-
modynamic calculations indicate that the hydrides are relatively stable because of the
large volume of hydrogen present in the reaction. Typical of the dopant chemistry is
the reaction for arsine, which is depicted with the deposition process in Fig. 9, which
shows arsine being absorbed on the surface, decomposing, and being incorporated
into the growing layer.
2ASH3 (solid) => 2As(gas) + H2(gas)
= > 2As(solid) => 2As+ (solid) + 2e (11)
Interactions also take place between the doping process and the growth process. First,
in the case of boron and arsenic the formation of chlorides of these species is a com-
peting reaction."' '^
Second, the growth rate of the film influences the amount of
SiCl2 HCI ^AsH3
<Cb Cb cCb
Fig. 9 Schematic representation of arsine doping and growth processes. (After Reif, Kamins, and
Saraswat, Ref. 13.)

Epitaxy 59
10
O.-l 0.2 0.4 0.6 0.8 ^.0
SILICON DEPOSITION RATE (/im/min)
2.0
Fig. 10 The influence of growth rate on layer concentration for arsenic doping. (After Reif, Kamins, and
Saraswat, Ref. 13).
dopant incorporated in the silicon as shown for arsenic in Fig. 10. At low growth rates
an equilibrium is established between the solid and the gas phase, which is not
achieved at higher growth rates.
'^
In addition to intentional dopants incorporated into the layer, unintentional
dopants are introducted from the substrate. The effect, shown in Fig. 1 1 , is termed
autodoping.'"^ Dopant is released from the substrate through solid-state diffusion and
evaporation. This dopant is reincorporated into the growing layer either by diffusion
through the interface or through the gas phase. Autodoping is manifested as an
enhanced transition region between the layer and the substrate (see Fig. 12). The
DIRECTION
MAIN GAS FLOW EPITAXIAL REACTOR
DOPANT DIFFUSING
FROM SUBSTRATE
DOPANT RELEASED
FROM BACK AND EDGES
OF SUBSTRATE
INTENTIONALLY
ADDED DOPANT
'V^^^ /DOPANT RELEASED FROM
/OTHER SLICES AND
/ SUSCEPTOR
LAYER
SUBSTRATE
Fig. 11 Sources of dopant for the epitaxial layer, schematically shown in a horizontal reactor. (After
Longer and Goldstein, Ref. 17.)

60 VLSI Technology
GAS-PHASE
AUTODOPING
TAIL S/B
INTENTIONAL DOPING
(GAS PHASE)
EPITAXY- -
SUBSTRATE-
VERTICAL DEPTH
Fig. 12 Generalized doping profile of an epitaxial layer detailing various regions of autodoping. (After
Srinivasan. Ref. 19.)
shape of the doping profile, close to the substrate, is dominated by solid-state diffu-
sion from the substrate and is a complementary error function'^ if
V > UDIi)'- (12)
where v is the growth velocity, D is the substrate dopant diffusion constant, and / is
the deposition time. The solid-state outdiffusion aspect of autodoping is easy to visu-
alize; it determines the shape of region A in Fig. 12.
Since the growth velocity easily outpaces the diffusion of dopant, the doping pro-
file in region B is dominated by dopant introduced from the gas phase. If the dopant
evaporated from the substrate exceeds the intentional dopant, an autodoping tail
develops. Autodoping is a time-dependent phenomena. The dopant evaporating from
the wafer surface is supplied from the wafer interior by solid-state diffusion. Thus, the
vaporization rate of dopant from an exposed surface is not constant, but decreases
with time.
Once the autodoping is diminished the intentional doping predominates, and the
profile becomes flat. The extent of the autodoping tail is a function of the substrate
dopant species and reaction parameters such as temperature and growth rate. Auto-
doping limits the minimum layer thickness that can be grown with controlled doping
as well as the minimum doping level. Because of the technological importance of
autodoping, it has been the subject of many studies.
^^""'
The discussion thus far has centered on equilibrium or at least steady-state reac-
tions. If the dopant flow in the reactor is abruptly altered, it does not result in a rapid
change in the doping profile. ^-^
Molecular beam epitaxy (discussed in Section 2.3)
does not have this constraint.

Epitaxy 61
In addition to the chemical cleaning of the substrate, an in-situ vapor-phase etch-
ing of the substrate with anhydrous HCl at a nominal temperature of I200°C usually
precedes deposition. The reactions involved are
2HC1 + Si => SiCl. + H. (13)
4HC1 + Si => SiCU + 2H2 (14)
Other gases such as HBr and SFg have also been proposed for substrate etching. ^^ The
HCl is supplied as a compressed gas and introduced into the hydrogen mainstream to
achieve a concentration of 2 to 3%. Etch rates are on the order of several tenths of a
micrometer/ min, and total etch depths of up to 5 [xm are used on substrates without
buried layers. When the sheet resistance of buried layers must be maintained, etch
depths are usually kept in the 0.1- to 0.3-|jLm range. Etching resuhs in a perfectly
clean substrate surface, free of native oxides. However, it is not a substitute for poor
pre-deposition chemical cleaning. An alternative to in-situ substrate cleaning is to
bake the wafers in hydrogen at a high temperature ( 10 min at 1200°C).
2.2.3 Equipment, Installation, and Safety Considerations
The earliest industrial epitaxial equipment was built by the user. Such equipment gen-
erally could handle only a small wafer load and was usually operated manually. In the
early 1970s commercial equipment which could handle larger wafer loads and offered
process automation became available.-'^ Now typical reactors (Fig. 13) weigh 2000 kg
and occupy 2 m" or more of floor space.
Fig. 13 A radiant-heated barrel reactor.

62 VLSI Technology
COOLING WATER ELECTRICAL POWER
EXHAUST TO ATMOSPHERE
WATER
Fig. 14 Schematic of an epitaxial reactor installation.
Several safety considerations must also be addressed in the operation of the reac-
tor. The reactor itself is usually designed with sufficient interlocks to prevent
accidents. However the user must safely remove and treat reaction by-products, and
arrange for proper delivery of process gases to the reactor. In fact several distinct
hazards require consideration: the explosion and fire potential of hydrogen, the corro-
sive nature of HCl, and the highly toxic nature of the doping gases. The last are par-
ticularly dangerous. Arsine, for example, is instantly lethal if a concentration of 250
ppm is inhaled, and exposure at lower levels (35 ppm) poses a health hazard depend-
ing on the length of exposure. A complete installation is depicted in Fig. 14. Environ-
mental considerations usually require a water-mist fume scrubber to remove most of
the unreacted and reaction products from the carrier-gas stream.
Susceptors in epitaxial reactors are the analogs of crucibles in the crystal growing
process. They provide mechanical support for the wafers and are the source of thermal
energy for the reaction in induction-heated reactors. The geometric shape or confi-
guration of the susceptor usually provides the name for the reactor. Figure 15 shows
three common susceptor shapes—horizontal, pancake, and barrel —which will be
discussed in more detail later. Like crucibles the susceptor must be mechanically
strong and noncontaminating to the process. Additionally, the susceptor must not
react with the process reactants and by-products. Induction-heated reactors require a
material that will couple to the rf field. The preferred material has been graphite,
although in radiant-heated reactors polysilicon or quartz susceptors are alternatives.
Polysilicon susceptors react with HCl, leading to a gradual erosion of the susceptor.
This erosion can be prevented with a coating of CVD silicon nitride. Graphite suscep-
tors also requiring a coating because they are relatively impure and soft. A carbon
blank is shaped to the required dimensions before the coating is applied. A coating of
longstanding use is 50 to 500 (xm of silicon carbide applied by a CVD process similar
to the silicon CVD process. Other possible coatings include glassy carbon and pyro-
lytic graphite. The latter forms a dense carbon layer in and on the carbon blank by the

Epitaxy 63
(a)
RADIANT BARREL
GAS FLOW 'RF HEATING oRADIANT HEATING
f
t l'
VERTICAL
^_n-
r
HORIZONTAL
(b)
Fig. 15 (a) Three common susceptor shapes: horizontal, pancake (vertical), and barrel, (b) Schematics of
three common reactors.

64 VLSI Technology
cracking of methane at elevated temperature. Pinholes and cracks in the coating are
persistent susceptor problems caused by the stresses encountered in repetitive thermal
cycling and by reactions with metal from tweezers used in wafer loading. These flaws
allow impurities in the carbon to escape,"^ which contaminate the epitaxial film and
cause defects. Another problem is variation in growth rate and doping caused by tem-
perature nonuniformity due to variable properties of the graphite and coating. The
reaction tubes or bell jars are made of high-purity quartz, either clear or opaque,
depending on the reactor.
In most reactors, the reaction tube is relatively cool during operation, that is, they
are operated "cold wall." Forced-air cooling carries away waste heat. Induction coils
and other metal parts are water cooled. Some cold-wall reactors have an outer tube,
allowing the reaction tube itself to be water cooled. By way of comparison the usual
process for the CVD of polysilicon is a hot-wall operation (Chapter 3) resulting in a
coating of silicon on the reactor tube itself.
Historically, energy for the reaction has been supplied by heating the susceptor
inductively. The energy is then transported to the wafer by conduction and radiation.
Because silicon at room temperature does not heat inductively unless the frequency is
above 50 MHz, motor generator sets at 10 kHz or self-excited rf oscillators at 500
kHz are used for heating. In the latter case, plate-input powers up to 100 kW are used
by large reactors. A water-cooled coil is placed close to the susceptor so coupling can
occur. The coil can be inside or outside the reaction chamber depending on the design
of the reactor. Radiant heating, a newer way of supplying energy to the reaction
chamber, provides more uniform heating than inductive heating provides"^"^. The
energy is supplied by banks of quartz halogen lamps.
In most cases, process control involves maintaining gas flows and temperatures at
the desired values. In modem equipment the process cycle is generally microproces-
sor controlled, and the operator only has to load and unload wafers. Sensors monitor
the temperature and the microprocessor makes adjustments when they are needed. An
optical pyrometer (focused on a wafer inside the reactor) has been used as the
temperature-sensing device in rf-heated reactors. Since the temperature is sensed
through the quartz reaction tube, the pyrometer actually senses an optically equivalent
temperature that is usually 50 to 100°C below the actual temperature due to the emis-
sivity of silicon. This temperature difference should be considered when
temperature-dependent curves are studied and compared. Radiant-heated reactors
employ sensing elements inside the reaction chamber. Gas flows can be metered using
rotometers or mass-flow controllers. The former determine the gas flow by calibrating
the position of a stainless-steel or sapphire ball in a glass tube. The calibration is a
function of gas viscosity, pressure, temperature, and molecular weight. A mass-flow
controller provides a better approach to metering flows. It measures the heat capacity
of the material flowing and compares that value to a setpoint. Control is by a solenoid
or thermal expansion valve. On-off control is provided by air-operated valves. These
valves eliminate any explosion hazard due to sparks, if a hydrogen leak occurs.
Three basic reactor configurations—horizontal, pancake or vertical, and
barrel—(Fig. 15) have found widespread use. Each design has its relative merits and
disadvantages.^^ Horizontal reactors offer high capacity and throughput; however,

Epitaxy 65
controlling the deposition process over the entire susceptor length is a problem. Pan-
cake reactors are capable of very uniform deposition, but suffer from mechanical
compexity. Radiant-heated barrel reactors are also capable of uniform deposition, but
are not suited for extended operation at temperatures above 12(X)°C.
A typical process for any configuration includes several steps. First, a hydrogen
carrier gas purges the reactor of air. The reactor is then heated to temperature. After
thermal equilibrium is established in the chamber, an HCl etch takes place at a tem-
perature between 1150 and 1200°C for 5 min nominally. The temperature is then
reduced to the growth temperature with time allowed for stabilization and flushing of
HCl as needed. Next, the silicon source and dopant flows are turned on and growth
proceeds at a rate of 0.2 to 3.0 |xm/min. Once growth is complete, the dopant and sil-
icon flows are eliminated and the temperature reduced, usually by shutting off power.
As the reactor cools toward ambient temperature the hydrogen flow is replaced by
nitrogen so that the reactor may be opened safely. Depending on wafer diameter and
reactor type, capacities range from 10 to 30 wafers per batch. Process cycle times are
about 1 h, giving throughputs of nominally 20 wafers per hour.
2.2.4 Process Selection and Capabilities
Epitaxial layers are rarely doped in excess of lO'^ atoms /cm^. This concentration is
used in a bipolar technology-^ where the epitaxial layer forms the transistor base. The
technical feasibility of doping to higher levels, approaching solid solubility, was
demonstrated for phosphorus."^'
-^
The majority of applications require dopings of lO''^ to 10^^ atoms/cm^. Lower
doping levels, in the 10^^ to lO'"^ atoms/cm^ region, are used for certain types of high
voltage and detector devices. These lower values are obtainable'^' -° if the reactor is
clean and the source is pure. Silicon sources with an equivalent purity of less than
10^^ atoms/cm^ are commercially available. Rear surface autodoping is often con-
trolled by sealing the rear surface with an oxide or nitride layer. An in-situ sealing can
be made in rf-heated reactors by first coating the susceptor with silicon. This layer
will be transferred to the wafer during the process. A theoretical lower doping limit of
1.45 X 10'^ atoms/cm^ is the intrinsic doping of silicon at 23°C. Radial uniformities
of ±10% are routinely obtained and ±5% are possible in some cases. Variations
within a run (batch) and from run to run are on the order of 20% or less, depending on
the process and reactor.
The practical upper limit of epitaxial thickness is reached just before the layer
overgrows the substrate and the film becomes contiguous with the silicon deposited
on the susceptor. If the layer overgrows the substrate, the wafers become hard to
separate from the susceptor, and cracking usually occurs. However, film thicknesses
of several hundred micrometers, close to the upper limit, are routinely grown for
some power device applications. As mentioned previously thin layers are constrained
by autodoping considerations, but layers as small as 0.5 fjim thickness have been pro-
duced."^ Layers with uniformities of ±5% are routinely produced with variations
between runs of ±5% and better.
As in the case of crystal growing, the choice of dopants for epitaxial processes is

66 VLSI Technology
limited. Boron is used for p-type doping, and arsenic or phosphrous are used for
n-type doping. The original method-'^ of introducing dopant to the reaction was to mix
halides (BCI3 or PCI3) of the dopants, which are liquids at room temperature, with the
silicon source (SiCU or SiHCl3) which is also liquid. Each species was vaporized in a
bubbler tank. Such a coupling of the silicon and dopant proved to be inconvenient.
For example, a change in doping level required the bubbler tank to be emptied and a
new mixture added.
A better approach uses hydrides of the dopants (PH3 , B2 H6 , or ASH3 ). These
compounds are gases at room temperature and are supplied in compressed-gas
cylinders. Since the concentration of dopant in the reactor is in the ppb range, the
hydrides are not supplied in pure form but are diluted to between 20 and 200 ppm in
hydrogen. Industry practice is to use a system of three flow meters to control the
dopant flow.'^ This procedure allows for a three order-of-magnitude range of doping
from one cylinder as each flow meter can control over a tenfold range of flows. There
is little difference in performance between arsine and phosphine, but most users
prefer arsine.
The choice of a silicon source is based on several considerations. Table 1 lists the
sources of each presently in use along with characteristic growth rates and tempera-
ture ranges.
^'^
Silane (SiH^) is usually chosen when a low deposition temperature is
needed to minimize boron autodoping and outdiffusion. (Arsenic autodoping
increases with lower temperatures.) Silane processes are prone to gas-phase nuclea-
tion (the formation of silicon particles in the gas stream above the wafer) which leads
to poor film quality. Gas-phase nucleation can be suppressed^ by adding HCl.
Another disadvantage is that silane tends to coat the reactor chamber rapidly, requir-
ing frequent cleaning. It also presents a production hazard as it is pyrophoric in con-
centrations above about 2%.
Dichlorosilane is a popular choice in many applications.-^' It offers high growth
rates at relatively low temperatures. Although a liquid at room temperature, dichloro-
silane has a high vapor pressure (>1 atm), so it can be metered directly from a
cylinder. No bubbler tank is needed. Trichlorosilane is used for the production of
electronic polysilicon as mentioned in Chapter 1 . It offers no physical or operational
advantage over silicon tetrachloride and is seldom used in epitaxial CVD processes.
Silicon tetrachloride is the least expensive and most used of all the silicon sources. It
is also a liquid at room temperature, but its low vapor pressure requires a bubbler tank
Table 1 Epitaxial growth of silicon in hydrogen atmosphere
Chemical Nominal Temperature Allowed
deposition growth rate (fx/min) range (°C) oxidizer level (ppm)
SiCl4 0.4-1.5 1150-1250 5-10
SiHClj 0.4-2.0 1100-1200 5-10
SiHjClj 0.4-3.0 1050-1150 <5
SiH4 0.2-0.3 950-1050 <2

Epitaxy 67
to help vaporization. The high deposition temperatures required of silicon tetra-
chloride make it less sensitive to oxidizers in the carrier gas and to the defects they
cause.
Epitaxial reactors can generally operate at temperatures between 900 and 1250°C.
Selecting the processing temperatures as well as the flow and growth rates is a com-
plex decision based on the film thickness uniformity, doping uniformity, level
required, and on the defect levels, pattern shift, and distortion allowed. This chapter
explains the process piecemeal, but does not tell how to design a process to meet all
the objectives, even though many are contradictory. For example, higher tempera-
tures to reduce pattern shift (see Section 2.2.5) increase autodoping. A systematic
approach to process design uses a factorial-design experimental approach to deter-
mine the optimum process condition for up to six variables including process tem-
perature.-^- ^^
After the factorial design has been used to determine the best operating
conditions, a silicon source can be chosen intelligently. Computer programs to simu-
late the epitaxial process are available— and are constantly being refined. Computer
simulations are considered in detail in Chapter 10. Such programs are a useful
adjunct to the factorial design experimental method in setting up a CVD process.
Historically, the silicon CVD process has been performed at atmospheric pressure
(760 Torr). However, operation in the range from 50 to 100 Torr has several advan-
tages.
^^•^'^
First, vertical and lateral autodoping effects (Fig. 16) are significantly
reduced. Second, pattern shift is also substantially reduced.
^^"^
10^7
1
1
f SiH
'
1 > 1 1 1
2C12
1
1 1
1
-
: i080°c
i
I
- 3 /i.m /mm
J
-
10 19 AS -DOPED
L -
n+ SUBSTRATE -
1016 -
1
-
1015 - 760T0RR J^ -
-
^,-*^20T0RR r/
1
-
-
^>-^ 80 AND
-
-
^-o'^-/ 40 TORR -
1014 1 1 1 1 1 1 i 1 1 1 1 1
0.5 1.0 15 20
DEPTH (^m)
2 5 3.0
Fig. 16 Doping profiles obtained over an arsenic-doped substrate for various reactor pressures. {After Her-
ring, Ref. 34.)

68 VLSI Technology
As in oxidation, diffusion, and LPCVD processes, wafers are cleaned before the
expitaxy process begins. All organic and metallic residues on the wafers must be
removed.^^ Particles are removed by using ultrasonic agitation in the cleaning baths,
by brush scrubbing with water, or by high-pressure water jets. Clean wafers must be
handled carefully to prevent recontamination, especially by particles. To prevent par-
ticle contamination, the entire reactor or load station is usually installed in a clean
room. A second method is to use a clean-air hood at the loading station.
2.2.5 Buried Layers
To fabricate bipolar ICs, usually one or more diffusions are applied to the substrate to
create the necessary isolation, collector, emitter, or base functions (Fig. 1). These dif-
fusions are applied to the substrate prior to epitaxy using the lithographic, oxidation,
diffusion, or ion-implantation processes discussed in other chapters. The diffusions
are called buried layers or diffusions under film. The presence of a buried layer com-
plicates the epitaxial process because of its effect on autodoping (vertical and lateral),
defects, pattern shifting, and pattern distortion.
The pre-epitaxial process leaves a step of 500 to 1000 A around the perimeter of
the buried layer that marks its location (A of Fig. 1). Subsequent masking levels must
be properly aligned with the buried layer pattern. Unfortunately, the deposition pro-
cess shifts the pattern (B of Fig. lb). Lithographic masks must compensate for the
amount of the shift (L of Fig. lb). A separate but related effect is pattern distortion or
washout, which alters the shape of the feature in the layer. Figure la also illustrates
the nature of pattern distortion. The pattern in the epitaxial layer is thus misplaced and
15 -
o 10
•
o
DATA
INTERPOLATED
EPITAXIAL THICKNESS ( f^m)
-
15
-
13
-
^1
-
9
- 7
-
M/^''^
-
1 1 1
5 -
30 60
SURFACE ORIENTATION
[minutes of arc off <100>]
Fig. 17 Pattern shift for a (100) orientation with various amounts of misorientation. (A.fxer Drum and Clark,
Ref. 37.)

Epitaxy 69
misshaped relative to its original configuration in the substrate. These effects place
limitations on the design of high-density circuits, and are a complicated function of
substrate orientation, growth rate and temperature, and silicon source.
^^
The crystal orientation has a profound effect on pattern shift.
-^^
Since the layer
does not grow normal to the substrate but rather by additions to microsteps (Fig. 9),
the macrostep marking the diffusion is shifted. As a result the microscopic growth
processes are altered by the orientation of the wafer. Current practice is to misorient
(1 1 1) wafers by 2 to 5° towards the nearest (1 10) direction and to orient (100) wafers
exactly on the orientation. Figure 17 illustrates the (100) case; note that the pattern
shift changes with epitaxial thickness. As shown in Fig. 18, pattern shift is indepen-
dent of reactor design, ^^^
but does show a pronounced dependence on growth rate and
VERTICAL GEOMETRY
ORIENTATION <111>
DEPOSITION RATE
o 1 0|im/min
5/j.m/min
/im/min
m /min
1000 1100 1200
3-
2-
1
-
0_
HORIZONTAL GEOMETRY
1000 1100 1200
3-
2-
cn 1 _
CYLINDRICAL GEOMETRY
1000 1100 1200
TRUE TEMPERATURE (°C)
- (a)
(b)
- (C)
Fig. 18 Pattern shift as a function of reactor [(a) vertical, (b) horizontal, and (c) cylindrical (or barrel)],
temperature, and growth rate. (After Lee etal., Ref. 38.)

70 VLSI Technology
1140 1180 1220 1260 2 4 0.6 0.8 1.0
TEMPERATURE {°C) GROWTH RATE (^m/min)
8
0,4
—
<111>
-
-04
-0 8
-1 2
-
/
/
/
J <100>
o
-1 6
~
1 1 1
-20246
NO. CHLORINE ATOMS
5 7 9 11 13 15
THICKNESS (^m )
Fig. 19 Parametric study of pattern distortion. (After Weeks, Ref. 36.)
temperature. Pattern shift increases with growth rate and reduced deposition tempera-
ture. The magnitude of the shift is largely equal for both (1 1 1) and (100) orientations.
These results are for an epitaxial process under atmospheric pressure. The pattern
shift is substantially reduced as the reactor pressure is lowered.^"* Pattern distortion-^^
exhibits an opposite relationship to the parameters previously mentioned, as shown in
Fig. 19. For example, pattern shift is reduced at higher growth temperatures, but dis-
tortion increases and is more dependant on orientation.
A complete explanation of how all the variables affect pattern shift is not avail-
able, but includes the following elements. The step face (Fig. 9) exposes a number of
crystal planes, which exhibit different growth rates. The anisotropy of growth
increases at lower temperatures as does the pattern shift. The growth rate dependence
of pattern shift is similar. The anisotropic nature of the layer growth rate increases
with growth velocity. The effects of pressure and the silicon source are less clear, but
apparently interrelated. Less chlorine as a by-product in the form of HCl correlates
with less distortion and shift. Reduced pressure operation would aid the escape of HCl
across the boundary layer.
The discussions of Section 2.2.2 relating to autodoping also apply to the vertical
autodoping profile above a buried layer. However, an effect termed lateral autodoping
can be observed in such structures. Figure 20a shows that lateral autodoping is a
front-surface autodoping phenomenon involving the transport of dopant to regions
adjacent to the diffusion. Figure 20b details the doping profiles on and off the buried
layer. The off-profile is totally attributable to gas-phase autodoping. Dopant in these

Epitaxy 71
T
EPI
I
VERTICAL AUTODOPING
LATERAL AUTODOPING
SUBSTRATE
/
BURIED I
LAYER
I
OUTDIFFUSION
I I
ARSENIC AUTODOPING
ON OFF (a)
10
fo -10
20
10
10
19
18
17
O
o 10
o 10
10 14
x=0FF
o = 0N
/ lOFF
1
1
BURIED
layer

EPITAXY SUBSTRATE
2 10 12
VERTICAL DISTANCE FROM METALLURGICAL INTERFACE (^m)
(b)
Fig. 20 Lateral autodoping effect, (a) Cross section of epitaxial wafer showing location of lateral autodop-
ing as adjacent to the buried layer, (b) Doping profiles above and adjacent to the buried layer. {After
Srinivasan, Ref. 16.)
regions is detrimental, because it produces an electrical short circuit between the adja-
cent devices,'^' '^
if it is not eliminated by a boron isolation diffusion. The peak con-
centration in the lateral autodoping profile is a function of the surface concentration in
the buried layer and processing conditions such as HCl etch time, temperature,
growth rate, and silicon source.
2.2.6 Epitaxial Defects
The crystal perfection of the layer never exceeds that of the substrate and is often infe-
j^Qj.
39, 40 jj^g crystal perfection is a function of the properties of the substrate wafer
and the epitaxial process itself. Defects arising from the substrate wafer can be

72 VLSI Technology
EPITAXIAL
LAYER
(a:
SUBSTRATE
"^ b' -"'^PilWI^"
*-
^^
t
'
^i.--
•jf
" #*' '.
•
v.^
>
• *«,
t ' *« »
-^ l>
..<• c e <
- "X fr ,
A '^
: *fc
.^^
.• -53
1
' -^ Ikr •
H %?
1 • '^
(1)
(3)
(b)
Fig. 21 Common defects occurring in epitaxial layers, (a) Schematic representation of line (or edge) dislo-
cation initially present in the substrate and extending into the epitaxial layer (item 1), an epitaxial stacking
fault nucleated by an impurity precipitate on the substrate surface (item 2), an impurity precipitate caused by
epitaxial process continuation (item 3), growth hillock (item 4), and bulk stacking faults one of which inter-
sects the substrate surface thereby being extended into the layer (item 5). (b) Photographs of defects in
actual wafers. Dislocations revealed as circular etch pits by Secco etching in a region of slip on a(lOO) wafer
(item 1), epitaxial stacking faults on a(l(X)) wafer (item 2). dislocations revealed by Sirtl etching in a(l 1
1)
wafer (item 3), and a growth hillock on a(l 1 1) wafer, visible without etching (item 4).

Epitaxy 73
related to the bulk properties of the wafer or its surface finish. Item 1 in Fig. 21a is an
example of an existing line dislocation continuing into the epitaxial layer. Impurity
precipitates'^^'
"^"
are one kind of surface defect that nucleate on an epitaxial stacking
fault (item 2). Process-related defects include slip and impurity precipitates from con-
tamination (item 3). Slip is a displacement of crystal planes past each other as the
result of stress. Dislocations accompany the formation of slip. Contamination from
the susceptor and the tweezers used in handling also contaminate the layer and sub-
strate and form precipitates that act as defect nuclei in subsequent processing."^^
Tri-
pyramids. hillocks, and other growth features (item 4) can be related to the process"^
or the surface finish of the wafer. Item 5 is an example of defects (bulk stacking fault)
created in a pre-epitaxial process, such as buried layer fabrication. These defects in
turn nucleate defects in the epitaxial layer. Figure 21b is a series of photographs of
defects in actual wafers. In general, the quality of the deposit is strongly related to the
quality of the substrate wafer, its cleaning, layer growth rate, and temperature.'^^ For
example, as the deposition temperature is lowered, minor flaws in the substrate sur-
face act as points of preferential nucleation giving rise to stacking faults and pyra-
mids. Higher growth rates aggravate the problem as discussed in the next section.
A temperature gradient exists normal to the substrate in an rf-heated reactor.'^
Slip due to this gradient (during epitaxy) is produced in the following manner. Heat
flow from the susceptor through the wafer equals subsequent radiation from the front
surface
EkT^ = ^^ (15)
ax-
where K is the thermal conductivity of silicon, dTI dx the normal temperature gra-
dient, E the emissivity of silicon, k the radiation constant, and T the nominal wafer
temperature. A front-to-rear temperature difference of only a few degrees causes a
differential expansion of the wafer. In effect, the wafer curls up on the susceptor.
When the wafer edge loses contact with the susceptor, the edge temperature drops,
causing still further bowing. This radial temperature gradient results in sufficient
stress to create dislocations the wafer (see the section on thermal stress in Chapter 1).
The inverted heat flow of the radiant-heated reactor minimizes this problem."^
Another class of defects are misfit dislocations caused by lattice mismatch when
the substrate is highly doped."^^
The resultant strain between the layer and substrate is
relieved by the formation of dislocations.
2.2.7 Microscopic Growth Processes
A final point to consider in the CVD process is the conditions under which single-
crystal films are obtained and the mechanism of their growth."^^ Figure 22 illustrates
the maximum attainable growth rates for atmospheric pressure epitaxy. The activation
energy obtained from that Arrhenius plot is 5 eV, which is equal to that of silicon
self-diffusion. The physical explanation is that silicon atoms are absorbed on the sur-
face of the substrate after a chemical reaction takes place. These atoms must migrate
across the surface to find a crystallographically favorable site where they can be

74 VLSI Technology
10*
1420 1100 1000 °c
1
-

1 1
POLY -REGION
c
~
V
E 102 -
E ^^
i Nv
1-
^t
< A ^^
01
X
1
'
>.
O
- MONOCRYST -REGION ^
10-2
1 1 1 1 1
060 70
^3
80
10VT (K-' )
Fig. 22 Maximum growth rate for which monocrystalline siUcon can be obtained as a function of tempera-
ture. (After Bloem, Ref. 48.)
incorporated into the lattice (Fig. 9). At high growth rates, insufficient time is allowed
for surface migration, resulting in polycrystall ine growth. The favorable sites are
positioned at the leading edge of atomic height steps. Thus, the growth is not vertical,
but lateral. This effect accounts for the variation in growth rate with surface orienta-
tion, availability and movement of steps being orientation dependent.''^
The adsorbed
silicon atoms compete with dopant atoms, hydrogen, chlorine, and foreign atoms for
these sites. Dopant atom concentration is usually low enough to be ignored, but
impurities such as carbon (initially present on the surface) affect how silicon is incor-
porated and nucleate a stacking fault or tripyramid defect. This growth mechanism
accounts for the effects that were discussed under pattern shift and distortion, and is
an additional reason to misorient (111) wafers. Growth of epitaxial layers on (111)
results in mounds being formed.'^
2.3 MOLECULAR BEAM EPITAXY
Molecular beam expitaxy (MBE) is a non-CVD epitaxial process that uses an evap-
oration method. Although the method has been known since the early 1960s, it has
only recendy been seriously considerated a suitable technology for silicon device
fabrication."*^ The two major reasons why MBE was not used are that, historically, the
quality was not commensurate with device needs, and no industrial equipment
existed. MBE has a number of inherent advantages compared to CVD techniques.'*^
Its main advantage for VLSI use is low-temperature processing. Low-temperature

Epitaxy 75
processing minimizes outdiffusion and autodoping, a limitation in thin layers
prepared by CVD. Another advantage is the precise control of doping that MBE
allows. Because doping in MBE is not affected by time-constant considerations unlike
CVD epitaxy, complicated doping profiles can be generated. Presently, these advan-
tages are not being exploited for IC fabrication, but they have found application in
discrete microwave and photonic devices. For example, the C-V characteristic of a
diode with homogeneous doping is nonlinear with aspect to reverse bias. Varactor
diodes used as FM modulators could advantageously employ a linear dependence of
capacitance on voltage. This linear voltage-capacitance relationship can be achieved
with a linear doping profile, which is easily obtained with MBE.
2.3.1 Process Description
In contrast to CVD processes, MBE is not complicated by boundary-layer transport
effects, nor are there chemical reactions to consider. The essence of the process is an
evaporation of silicon and one or more dopants as depicted in Fig. 23. The evaporated
species are transported at a relatively high velocity in a vacuum to the substrate. The
relatively low vapor pressure of silicon and the dopants ensures condensation on a
low-temperature substrate. Usually, silicon MBE is performed under ultra-high
vacuum (UHV) conditions of 10~^ to 10~'"^ Torr, where the mean free path of the
atoms^*^- ^'
is given by
L = 5xlO"V/? (16)
where L is the mean free path in cm, and/? is the system pressure in Torr. At a system
pressure of 10~^ Torr L would be 5 x 10^ cm.
THERMOCOUPLE
QUARTZ -CRYSTAL
THICKNESS MONITOR
HEAT SHIELDING-
MASS_jC"J
SPECTROMETER ^~^
I0NIZATI0N_,^^
GAUGE
e GUN, Si SOURCE-
TITANIUM -SUBLIMATION
PUMP
Sb EFFUSION
CELL
TURBO -MOLECULAR
PUMP
Fig. 23 Schematic of MBE growth system. (After Konig, Kibbel. arid Kasper. Ref. 54.)

76 VLSI Technology
CRUCIBLE MELT HEIGHT
MELT -^
Fig. 24 Angular distribution of flux from a crucible of radius r and melt height / referenced from the top of
the crucible. (After Luscher and Collins, Ref. 52.)
Because collisions between atoms are unimportant in a high vacuum, transport
velocity is controlled more by thermal energy effects than by diffusion effects, and
deposition and its uniformity can be controlled by the source characteristics.^^
Accordingly, evaporation from a crucible produces a flux of material varying with
time and angle, as shown in Fig. 24. The lack of intermediate reactions and diffusion
effects, along with relatively high thermal velocities, results in film properties chang-
ing rapidly with any change at the source.
A conventional temperature range for MBE is from 400 to 800°C. Higher-
temperature processes are technically feasible, but the advantages of reduced outdif-
fusion and autodoping are lost. Growth rates in the range 0.01 to 0.3 [xm/min have
been reported."*^' ^° The higher value is comparable to those obtained in CVD epitaxy.
In-situ cleaning for MBE is done in two ways. High-temperature baking between
1000 and 1250°C for up to tens of minutes^^ decomposes the native oxide and
removes other adsorbed species (notably carbon) by evaporation or diffusion into the
wafer. A better approach is to use a low-energy beam of an inert gas to sputter clean
the surface. A short anneal at 800 to 900°C is sufficient to reorder the surface.
MBE doping has several distinguishing features. A wider choice of dopants can
be used, compared to CVD epitaxy, and more control of the doping profile is possi-
ble, and two doping processes are available. In principle the doping process is similar
to the growth process. A flux of evaporated dopant atoms arrives at the growing inter-
face, finds a favorable lattice site, and is incorporated. The doping level is controlled
by adjusting the dopant flux relative to the flux of silicon atoms. In practice a Knud-
sen effusion cell^^ is used to evaporate dopants. Unfortunately, desirable dopants such

Epitaxy 77
10I8
10I6
15
10
10
K)"
10'°
10^-
10^ -
10
1
—I
—
——1
—I
—I
—n—I
—I
—I
—r~i—I
—I
—I
—T"!—I
—I
—
r
I ""^ I TiB, //^ ^
/ LI I I I I I I I 1 1 I I I I I I I I I I I L
500 1000 1500
DOPANT OVEN TEMPERATURE (°C)
2000
Fig. 25 Flux of various dopant species versus oven temperature. (After Bean. Ref. 50.)
as As, P, and B evaporate too rapidly or too slowly for controlled use. As a result
most workers use Sb, Ga, or Al for dopants which compare favorably to other dopants
as shown in Fig. 25. Another complication is the temperature-dependent sticking
coefficient shown in Fig. 26. A low value means re-evaporation occurs readily and
incorporation of the dopant is more difficult. This temperature dependence requires
precise control of substrate heating. A wide latitude in doping by evaporation has
been demonstrated.^'^' ^^^
Values in the range 10^^^ to lO'^ atoms/cm^^ have been
reported with 1% radial uniformities.
Another doping technique uses ion implantation^^ (see Chapter 6). This technique
uses a low-current ( 1 |jlA), low energy (0.1- to 3-keV) ion beam to implant dopant as
the layer is growing. The low energy beam places the dopant just below the growing
interface, ensuring incorporation. Doping profiles not obtainable with CVD processes
can be produced with ion implantation as depicted in Fig. 27. This technique also
allows the use of dopants such as B, P, and As. Since MBE is a vacuum process, it is
very adaptable to ion-implant doping, and in-situ monitoring of the beam is feasible.
^^
2.3.2 Equipment
An elementary MBE system is depicted in Fig. 23. It is, in essence, a UHV chamber
where furnaces holding electronic-grade silicon and dopant direct a flux of material to
a heated substrate. In fact an early MBE system was made by modifying a bell-jar
apparatus. Now, commercially designed and built equipment, although expensive and
complicated, has become available. Figure 28 illustrates the many components of a
comprehensive system. A distinguishing feature of MBE is the ability to use sophisti-
cated analytical techniques in-situ to monitor the process.

78 VLSI Technology
TCC)
1000 900 800 700 600 500
0.8 09 1.0 II
I0^/T(K)
1.3 14
Fig. 26 Sticking coefficient for Sb, Al, and Ga versus temperature. (After Bean, Ref. 50.)
In contrast to the CVD process, MBE does not require the extensive safety pre-
cautions, although sohd arsenic dopant must be handled carefully.
The vacuum system is the heart of the apparatus. To consistently attain a vacuum
level in the 10~"^-Torr range, materials and construction must be carefully con-
sidered. Materials should have low vapor pressure and low sticking coefficients.
Repeated exposure to air is detrimental to a UHV system because of the long bakes
needed to desorb atmospheric species from the system walls. A load lock system
minimizes this problem. Consistent low base pressure is needed to ensure overall film
perfection and purity. These needs are best met with an oil-free pump design, such as
a cryogenic pump.
Because of its high melting point, silicon is not volatilized by heating in the fur-
nace, but rather by electron-beam heating. Dopants are heated in a furnace. A con-
stant flux is assured by the use of closed-loop temperature control. Baffles and
shutters shape and control the flux, so uniformity of doping and depostion can be
attained without boundary layer effects being considered.

SUBSTRATE
4 6
DEPTH (^m)
Fig. 27 Doping profile obtained by ion implantation during MBE growth. (After Ota, Ref. 56.)
AUGER
ELECTRON
SPECTROMETER
ANALYZER
SAMPLE LOAD-LOCK
(TWO VAC-SORBS
+
3CH./S ION pump:
40-mA SPUTTER
CLEANING GUN
GAS
FEED SOURCE
FLANGE; TWO 14-kWe BEAM EVAPORATORS ,
THREE 2.5-cm KNUDSON CELLS /
AUTOMATIC SHUTTERS RASTER-SCAN
LIQUID NITROGEN SHROUD PLATES
EXTRACTION
+
DECELERATION FOCUSING
REFOCUS I
GAS
I
= 1 FEED
r-nr
—
td—n-i | | U—
ALVE U-^ iflJ
i
DEPOSITION CHAMBER
(2000-L/5 CRYOPUMP)
NEUTRAL BEAM
TRAP
(120t/s ION PUMP)
ION
WIEN MASS SOURCE
FILTER
ION DOPING SOURCE
(1000-L/S CRYOPUMP)
Fig. 28 Schematic of practical MBE system. ('4^^''^^^'^. ^^•'^9. j
79

80 VLSI Technology
I I05
<
PREHEATING
II60°C FOR 20min
T=860''C
10"° 10"' 10 °
PRESSURE (TORR)
Fig. 29 The dependence of stacking fault density on system pressure at a substrate temp)erature of 860°C.
(After Sugiura and Yamaguchi. Ref. 51 .)
Substrates are best heated when they are placed in proximity to a resistance
heater with closed-loop temperature control. Resistance heating generates tempera-
tures over the range of 400 to 1 100°C. A wide choice of temperature-sensing methods
is available, including thermocouples, optical pyrometry, and infrared detection.
2.3.3 Film Characteristics
The preparation of high-quality films by MBE requires an in-situ cleaning process to
remove absorbed contaminants and oxide films. Low base pressure is also a require-
ment to keep the surface clean. Figure 29 shows the effect of pressure on stacking
fault density. Lowering the pressure lessens the concentration of contaminants
absorbed on the substrate. These species would obstruct the single-crystal growth and
nucleate a fault as discussed in Section 2.2.7 on nucleation. The effects on dislocation
density can also be seen in the pre-heat time for substrate bakeout prior to growth and
in the temperature of growth (see Figs. 30 and 31).
2.4 SILICON ON INSULATORS
An all-silicon device structure has inherent problems that are associated with parasitic
circuit elements arising from junction capacitance. These effects are more of a prob-

Epitaxy 81
106
105 -
103 —
10'
"1 I I I I
r I
I I
1
r
J I u
—
o
o-
_l I L.
10 20
PREHEAT TIME OF SUBSTRATE (min)
Fig. 30 The dependence of film quality on predeposition heating time. (After Sugiura and Yamaguchi, Ref.
53.)
CVl 10
E
GROWTH TEMPERATURE (°C)
6 800 700
'
1 1
1
1
600
ti- 10-
en
z
t 10^ I-
en
2
LlI
Q
Z
H 10^ -
<
o
o
_l
en
10'
E= 3.5 ev
^ll
'
I I I I I I I I I I I I I I 1 I I I I ] I 1
0.9 1.0 1.1
10^ /T(K)
Fig. 31 The dependence of film perfection on growth temperature. (After Sugiura and Yamaguchi, Ref.
53.)

82 VLSI Technology
n+ BODY CONTACT -
INSULATING SUBSTRATE
Fig. 32 MOSFET device fabricated in silicon island on sapphire substrate. (After Schlatter, Ref. 59.)
problem as devices are made smaller (see Chapter 11). A way to circumvent the
problem is to fabricate devices in small islands of silicon on an insulating substrate as
shown in Fig. 32. The initial approach to fabricating such a structure was to grow sili-
con epitaxially on a substrate of sapphire (AI2O3) or spinel (MgAl2 04). Since the
substrate material differs from the layer, the process is termed heteroepitaxy. A more
recent approach, yet to be perfected, is silicon on amorphous substrates.
2.4.1 Silicon on Sapphire
The processes and equipment used for silicon on sapphire (SOS) epitaxy are essen-
tially identical to those employed for homoepitaxial growth. Silane is the favorite
choice for the silicon source according to the pyrolysis reaction
SiH4 => Si + 2H2 (17)
in a carrier gas of hydrogen. Silane is chosen mainly for its low-temperature deposi-
tion capability, which is used in SOS to control autodoping of aluminum from the
substrate. Common process parameters are deposition temperatures between 1000 and
1050°C and growth rates of 0.5 [xm/min. Film thicknesses are on the order of 1 xm or
less with film doping in the range of lO'"* to lO'^ atoms/cm^. Various substrate orien-
tations such as(0lT2), (IOT2), and(lT02), have been used to grow(lOO) oriented silicon
layers.^^'^^'^^ Significant problems, however, exist with the technology. Aluminum
autodoping from the substrate restricts the choice of doping level, and the films are
usually characterized by a high defect density. The latter characteristic results in very
low minority-carrier lifetimes (1 to 10 ns).^^ As a result only majority-carrier devices
are practical. Both CMOS and NMOS circuits have been fabricated by using SOS
epitaxy. The low minority-carrier lifetime also means that junction leakage currents
could be higher than in comparable circuits in bulk wafers.
The defect structure of SOS devices has been studied by a number of work-
gj.g
57, 58 -j^g £jjj^g ^g generally characterized by high densities of various defects
such as stacking faults, misfit dislocations, and dislocations. A key finding was that
defect density varies inversely with distance from the substrate (Fig. 33). This effect
is related to the lattice mismatch between the layer and substrate. The strain caused by
lattice mismatch is somewhat relieved by the formation of misfit dislocations near the

Epitaxy 83
IW
: ^o^ (100) Si/(0I2) SAPPHIRE
;
^-
°^a
-

10^ - Ox
o
:

-
oop
-
V
-
°
10''
^
- o
I

"
ooq
-

io3 1 1 1 1 1 1 1 1
1
1 1 1—1 Mill 1 1 1
1 1 1 1 1
10- 10'
DISTANCE FROM INTERFACE (A)
Fig. 33 Stacking fault density as a function of distance above the substrate for an SOS structure. (After
Abrahams atidBuiocchi. Ref. 58.)
original layer substrate interface. The transition layer between the epitaxial layer and
the substrate is complicated, involving the formation of aluminum silicate from the
outdiffusion of aluminum from the substrate. Such a layer is unavoidable in heteroepi-
taxy.^^ Another fundamental problem in SOS epitaxy is the thermal mismatch
between the layer and the substrate. The thermal expansion of sapphire is approxi-
mately twice that of silicon. This difference in thermal expansion causes a strain-
induced change in the band structure upon cooling that limits the carrier mobility
to 80% of the bulk value. The carrier mobility is also reduced by the high defect
densities.
These deficiencies have resulted in various attempts to improve SOS film quality.
MBE is one solution, becuase its lower process temperature reduces autodoping and
stress. Some workers^' ^'
have used laser annealing to improve the quality by melt-
ing and recrystallizing the layer. For example, a Q-switched ruby laser with energy
densities greater than 1 J/cm^ is used to reduce defect density and improve mobility.^
2.4.2 Silicon on Amorphous Substrates
Silicon on insulator (SOI) is a recent nonepitaxial approach to providing single-crystal
silicon. With this technology, amorphous or polycrystalline silicon is recrystallized on
an amorphous substrate. Figure 34 shows a setup for recrystallization using a strip
heater. The process is considered nonepitaxial as this silicon film is not single crystal
as-deposited. Energy for the process can also be supplied by electron beam^^ or
laser. ^^ The resultant structure is functionally similar to the heteroepitaxial SOS confi-
guration, but without the attendant disadvantages just discussed. The recrystallized

84 VLSI Technology
MOVABLE UPPER.
STRIP HEATER
LOWER
STRIP HEATER
Si3N4/Si02/CAP
Sl<IOO> Q^Q
SUBSTRATE ^ POLYSILICON
FILM
RECESSED S1O2
MASK
Fig. 34 Schematic of one technique used to recrystallize polysihcon on Si02. Region A acts as a seed for
the lateral recrystallization when the heater moves to the right. {After Tsuar et al.. Ref. 65.)
layers are potentially the equal of homoepitaxial silicon. SOI is not used commer-
cially at present, but possible device applications include VLSI circuits, photovoltaic
solar-energy conversion, and even three-dimensional ICs.
Several methods of preparing SOI have been investigated. Substrates can be con-
ventional silicon wafers covered with silicon nitride or silicon dioxide or even fused
quartz substrates.^ The last method would be the most cost effective. If the conven-
tional silicon wafer is used, it is processed in a manner which yields a pattern of
exposed silicon areas, whose surface is coplanar with the surrounding oxide. This
substrate is then coated with polysilicon in a low-pressure CVD process to a thickness
of 0.5 xm. A movable strip heater (Fig. 34), positioned above one of the openings to
the substrate, ^^ melts the polysilicon through to the substrate. The heater is then
moved laterally, and, with the substrate acting as a seed, single-crystal silicon is
grown laterally over the oxide-covered regions. The thermal stability of the molten
zone is improved if it is capped with oxide and nitride layers. Capping also prevents
contamination of the film. This technique is suitable for recrystallizing large areas,
such as an entire wafer. Similar procedures using a scanned CW argon laser have
been reported.^
Another approach is to pattern a polysilicon layer on an amorphous substrate. ^"^
A
laser is then rastered across the wafer to recrystallize the individual islands of silicon.
This method does not need seeding from the substrate. Adjusting the energy parame-
ters of the laser and its scan rate induces the islands to crystallize in a (100) orienta-
tion. High-quality n-channel depletion mode MOSFETs have been fabricated^^ in
recrystallized silicon. The device structure (Fig. 35) is similar to that of SOS devices,
but better. In particular, the surface electron mobility was reported at 600 to 700
cm^/V-s, a value near that of devices fabricated in single-crystal silicon. These
results are better than those obtained from SOS devices.
Additional work is needed before this technology is the equal of homoepitaxial
silicon technology, but it has the potential to revolutionize device design and fabrica-
tion.

Epitaxy 85
RECRYSTALLIZED
Si FILM
CVD
Si02'
POLYS ILICON GATE
7/0 THERMAL
/ / / ////i Si02
Fig. 35 Cross section of MOSFET formed in recrystallized polysilicon. (After Tsuar et al., Ref. 67.)
2.5 EPITAXIAL EVALUATION
To evaluate epitaxial slices layer doping and thickness, which are easily quantified,
are measured. Additionally, a cosmetic inspection is usually performed even though
this evaluation is somewhat subjective. The prime requisites for routine measurements
are high speed and repeatability. In an industrial environment, information is needed
at relatively short intervals (<1 h) to maintain process control. Absolute accuracy is
of lesser concern, because the material requirements are usually adjusted on an empir-
ical basis to satisfy device needs. Only a few evaluation methods are commonly
used.^^
2.5.1 Epitaxial Thickness
Lightly doped silicon is transparent in the near infrared region and heavily doped sili-
con (>1 X 10^^ atoms/cm-') is an absorber. However, increased doping reduces the
index of refraction (Fig. 36) below that of lightly doped silicon {n = 3.42). As a resuh
interference fringes in the 5- to 50-|jLm wavelength range can be observed in the
reflection spectra on a conventional infrared spectrophotometer. The epitaxial layer
thickness can be computed using the formula^^
t =
(P, - Vi + Pj ) W„
2(«2 - sin^ 6)
(18)
where W,, is the position of the maxima or minima in the spectra in micrometers, n is
the index of refraction, 6 is the angle of the incident light, F„ is the order of the max-
ima or minima, and Pj is a correction factor that depends on the substrate used.
An automated approach to the measurement employs a Michaelson interferome-
ter. This instrument samples all wavelengths simultaneously. Its output is called an
interferogram, which is the Fourier transform of the reflectance spectra obtained on a
spectrophotometer. A computer controls the interferometer and collects the data. The
thickness can be computed from the interferogram, or the computer can calculate the
Fourier transform and then proceed to calculate the thickness using Eq. 18. Equip-
ment for this second method is commercially available. Such equipment can measure
thickness from less than 1 xm to more than several hundred micrometers. Measure-
ment time is about 5 s with a measurement repeatability of ±0.05 jim.

86 VLSI Technology
3.6
3.5
z
2 3.4
(-
o
<
a:
LL
ir 3.3
O
X
S 3.2
3.1
3.0
X = 1 5^m
INTRINSIC SILICON T7 = 3.42
10' 10
16 10' 10
18 10^ 10
20
DOPANT DENSITY (Cm )
Fig. 36 Typical index of refraction versus doping level for silicon at one wavelength.
The equivalent point of reflection of infrared measurements is at a heavily doped
point on the outdiffusion tail. For common processing conditions, this point is usually
near the epi-substrate interface. Thus, an infrared measurement is a reasonable moni-
tor of the thickness added to the substrate, but is relatively insensitive to the shape or
extent of the outdiffusion autodoping tail.^°
For structures that are not amenable to infrared measurements, there are several
alternatives. The length of the side of an epitaxial stacking fault, nucleated at the sub-
strate, is linearly related to the layer thickness
'''
t = CiL (19)
where t is the layer thickness, L is the size of the fault, and Cj is an orientation-
dependent constant which is 0.707 for(lOO) and 0.816 for(l 1 1).
Wafers can also be sectioned and stained with a number of chemical solutions to
delineate the layer. '^
Spreading resistance''-^'
''^
profiling (see Chapter 5) is particularly
useful for structures that have multiple layers or structures where the total impurity
profile is important.
2.5.2 Epitaxial Doping
The uncertainties of doping kinetics, background effects, and autodoping effects do
not allow the doping in the layer to be established simply on the basis of the flows
into the reactor. Three types of electrical measurements—sheet resistance, diode
capacitance voltage, and spreading resistance —are used to measure doping levels.
^^
The control wafer technique is a widely used method that requires simple equip-
ment. It involves placing in the reactor a lightly doped slice of a conductivity type

Epitaxy 87
opposite to the layer to be grown. After deposition a four-point probe measures the
sheet resistance of the layer (see Chapter 5). The sheet resistance is converted to resis-
tivity using the infrared thickness of an adjacent product slice 7^ This method is highly
inaccurate in some cases 7^ Its suitability must be determined by correlating its meas-
urements to measurements made on product slices by another method. In other cases,
no correlation is possible due to a strong predeposition of substrate dopant onto the
control wafer. The control wafer technique is expensive and often wasteful of reactor
capacity.
The second method, the preferred approach, is the use of diode C-V measure-
ments (see Chapter 5). Implicit in the capacitance versus voltage characteristic
of a reverse-biased diode is the doping profile of the material according to the
relationships
N(x) = C^
dC
dV
CFiCFjqA^e, (20)
X = e,A /C (21)
where C is capacitance, V is voltage, q is charge, A is the diode area, e^ is the dielec-
tric permittivity of silicon, A^ is the doping density, and x is depth. CFj and CF2 are
correction factors for diffused-junction and depletion-layer widening effects. ^^' ^^
C-V measurements of a Schottky barrier diode, formed by using a mercury con-
tact,
^^''^
are a rapid nondestructive way to determine slice doping. If the depletion
layer can be spread to the substrate, some information on the autodoping tail can be
obtained. The measurement can also be performed on mesa or planar junction diodes
as a means of calibrating other measurements.^^ The principle drawbacks of a C-V
measurement are its high sensitivity to small errors in area and capacitance.
^°
The third method, spreading resistance measurements, was previously mentioned
as a profiling technique. This method can determine a wafer's resistivity by measur-
ing on the surface. The major difficulties are in maintaining accurate calibration as
the probes wear with repeated usage and in overcoming the influence of surface
effects that affect the measured resistance.
2.5.3 Cosmetic Inspection and Perfection Evaluation
The wafer is usually examined with the unaided eye under high-intensity illumination
to judge the quality of the deposit. Wafers may be rejected for any departure from a
specular, smooth surface, including projections which are seen as bright spots of
light, stains, haze, or scratches. The acceptance criteria is usually set empirically
based on the type of device being fabricated. Attempts to automate this inspection
using scanned laser or coUimated light to detect light scattering centers have generally
been unsuccessful. Additional inspection may be made at magnifications of from 50
to 2(X) to evaluate microdefect densities such as stacking faults and tripyramids.
Nomarski phase contrast microscopy is preferred for this inspection. Another useful
technique is to etch wafers^' in solutions such as Secco's or Sirtl's etch to determine
dislocation and saucer pit densities. The latter indicate that contamination is present in
the process.

88 VLSI Technology
2.5.4 Lifetime
The lifetime of minority carriers is generally not a consideration in structures intended
for IC fabrication, but could be of interest in some devices such as dynamic RAMs.
Several measurements involving the transient response of diodes or MOS capacitors
are applicable to epitaxial layers.
^^'^-^
However, the diffusion length of carriers is
often many times that of the layer thickness. This complicates the interpretation of the
measurement results.
Epitaxy as a process will remain integral to circuit manufacture. It offers doping pro-
files and material properties not obtainable otherwise. Homoepitaxial silicon struc-
tures will remain popular design choic in the foreseeable future. The advantages of
SOI technologies are compelling for h h-density and high-speed circuits. In particu-
lar, if silicon-on-Si02 can be perfected, it will offer the advantages of SOS without
the problems. Lateral-seeded SOI will undoubtedly receive considerable research
attention. MBE would be advantageous in fully ion-implanted VLSI circuits in which
the total thermal cycle is minimized so that the doping capabilities of MBE can be
exploited.
Although presently available equipment is adequate for most needs, several
aspects of the epitaxial process could be improved. In keeping with automation else-
where in the fabrication process, an autoloading epitaxial reactor remains a desirable
objective. This equipment could take the form of a cassette-fed machine processing a
single wafer at a time. Conceptually, a uniwafer reaction chamber could be optim-
ized for temperature and gas flows to produce wafers having exceptional uniformity.
The throughput of epitaxial reactors is less than that of LPCVD processes (Chapter 3)
by a factor of 5 to 10. However, monocrystalline silicon cannot be grown in LPCVD
equipment. One difficulty is the low growth rates in the usual LPCVD temperature
ranges (Fig. 8). An alternative reactor design, ^"^
termed the rotary disc, is similar in
load configuration to LPCVD equipment, and offers high capacity and efficiency.
Large-scale use of MBE will require equipment with throughputs comparable to
present-day epitaxial reactors.
Although epitaxial processes are well characterized and understood, the trend to
thinner layers for bipolar and unipolar ICs will result in incremental process improve-
ments and the continued study of autodoping effects. Additionally, contamination,
responsible for precipitates in epitaxial layers, needs to be reduced commensurate
with the requirements of VLSI devices. Contamination-free epitaxy will be a
worthwhile process improvement.
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90 VLSI Technology
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[58] M. S. Abrahams and C. J. Buiocchi, "Cross-Sectional Electron Microscopy of Silicon on Sapphire,"
Appl. Phys. Lett.. 27, 325 (1975).
H. Schlotter, "Interface Properties of Sapphire and Spinel." J. Vac. Sci. Technol.. 13, 29 (1976).
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92 VLSI Technology
PROBLEMS
1 In a l-h process at 1100°C using dichlorosilane, a 10-|xm layer is grown on 20 substrates of 100-mm
diameter in a horizontal reactor. Estimate the energy in kilowatthours for the process. Assume a growth rate
of 1 |a,m/min.
2 Determine the amount of mask compensation needed for an epitaxial wafer of (100) orientation containing
an antimony buried layer with an epitaxial thickness of 7 fjim.
3 Using the figures in the chapter estimate the temperature of zero growth rate for each silicon source. Com-
pare these temperatures to the nucleation temperature curve. What do you conclude?
4 Calculate activation energies from the Arrhenius plots for growth rate versus temperature and nucleation
versus temperature. What do you conclude about the process?
5 A reverse-biased diode has a voltage capacitance characteristic defined by the relation VC~ - N. What
would you conclude about the shap)e of the doping profile? Suggest a graphical way to determine doping
density from the C-V curve.
6 Using the diffusivity of boron at 1 100°C (Chapter 5) calculate the minimum growth rate such that the con-
dition of Eq. 12 is satisfied given a deposition time of 10 min.
7 Calculate the number of liters of hydrogen at STP that would be needed to be supplied into the reactor for
the process of Problem 1 . What do you conclude?
8 Does the thickness of the epitaxial wafer pose a problem in epitaxial processing from a stress viewpoint?
Discuss your answer.

CHAPTER
THREE
DIELECTRIC AND POLYSILICON FILM DEPOSITION
A. C. ADAMS
3.1 INTRODUCTION
Deposited films are widely used in the fabrication of modem VLSI circuits. These
films provide conducting regions within the device, electrical insulation between
metals, and protection from the environment. Deposited films must meet many
requirements. The film thickness must be uniform over each device and over the
large number of wafers processed at one time. The structure and composition of the
film must be controlled and reproducible. Finally, the method for depositing the film
must be safe, reproducible, easily automated, and inexpensive.
The most widely used materials are polycrystalline silicon, silicon dioxide,
stoichiometric silicon nitride, and plasma-deposited silicon nitride. The most com-
mon deposition methods are atmospheric-pressure chemical vapor deposition (CVD),
low-pressure chemical vapor deposition (LPCVD), and plasma-assisted chemical
vapor deposition (PCVD or plasma deposition). Several reviews of these materials
and their preparation are available.'"^
Polycrystalline silicon, usually referred to as polysilicon, is prepared by pyrolyz-
ing silane at 600 to 650°C. Polysilicon is used as the gate electrode material in MOS
devices, as a conducting material for multilevel metallization, and as a contact
material for devices with shallow junctions. Polysilicon is usually deposited without
dopants. The doping elements, arsenic, phosphorus, or boron, are added subsequently
by diffusion or ion implantation. The dopants can also be added during deposition,
which is advantageous for some device structures. Polysilicon containing several per-
cent oxygen is a semi-insulating material that is used for circuit passivation.
Dielectric materials are used for insulation between conducting layers, for diffu-
sion and ion implantation masks, for diffusion from doped oxides, for capping doped
93

94 VLSI Technology
films to prevent the loss of dopants, for gettering impurities, and for passivation to
protect devices from impurities, moisture, and scratches. Phosphorus-doped silicon
dioxide (P-glass, phosphosilicate glass, or PSG) is especially useful, because it inhib-
its the diffusion of sodium impurities and because it softens and flows at 1000 to
1 100°C, creating a smooth topography that is beneficial for subsequent metallization.
Silicon nitride is a barrier to sodium diffusion, is nearly impervious to moisture,
and has a very low oxidation rate. Stoichiometric silicon nitride (Si3N4), deposited at
700 to 900°C, is used as an oxidation mask to create planar structures and as a gate
dielectric in conjunction with thermally grown silicon dioxide in dual dielectric de-
vices. Plasma-deposited silicon nitride (plasma nitride or SiN) is formed at much
lower temperatures, 200 to 350°C, and is used as a passivation layer and for protec-
tion against scratches. The low deposition temperature allows this material to be used
over aluminum or gold metallization.
Many methods are available for depositing thin films.^ However, various CVD
techniques are most frequently used for semiconductor processing. These chemical
depositions occur under a large variety of conditions. Deposition temperatures vary
from 100 to 1000°C and pressures range from atmospheric down to about 7 Pa (0.05
Torr). The energy for the reaction can be supplied thermally, by photons (photo-
chemically), or by a glow discharge.
Historically, dielectric and polysilicon films have been deposited at atmospheric
pressure by using a variety of reactor geometries.'' ' ^ These include horizontal reac-
tors with the wafers lying on a hot suspector and the reactant gases flowing over the
surfaces, usually at very high velocities. The suspector is heated by radiation using
high-intensity lamps, by radio frequency induction, or by electrical resistance. Vari-
ous vertical reactors also exist, usually consisting of a bell-jar reaction chamber with
samples oriented in a vertical direction on a rotating assembly. As in the horizontal
reactors, the suspector is heated by radiation, induction, or resistance. All of these
atmospheric pressure reactors tend to have low wafer throughput, require extensive
wafer handling during loading and unloading, and provide thickness uniformities that
are usually no better than ±10%. As a consequence, they have been replaced by
low-pressure, hot-wall reactors. Plasma-assisted depositions in hot-wall reactors or
with parallel-plate geometries are also available for applications that require very low
sample temperatures, 100to350°C.
The potential advantages of the low-pressure deposition processes are: (1) uni-
form step coverage, (2) precise control of composition and structure, (3) low-
temperature processing, (4) fast deposition rates, (5) high throughput, and (6) low
processing costs. Compromises and trade-offs are made among these properties. For
instance, low deposition rates may be tolerated to achieve low deposition tempera-
tures. A goal in developing a deposition process is to best use the advantages of CVD
and to find the optimum compromise for specific device structures.
3.2 DEPOSITION PROCESSES
3.2.1 Reactions
Table 1 lists some typical reactions that may be used to deposit films on device
wafers. The choice of a particular reaction is often determined by the deposition tem-

Dielectric AND PolYSiLicoN FILM Deposition 95
Table 1 Typical reactions for depositing dielectrics and polysilicon
Product Reactants Deposition temperature (°C)
Silicon dioxide SiH4 + CO2 + H. 850-950
SiCliH^ + N.O 850-900
SiH4 + N2O 750-850
SiH4 + NO 650-750
Si(OC2H5)4 650-750
SiH4 + O2 400-450
Silicon nitride SiH4 + NH3 700-900
SiCl2H2 + NH3 650-750
Plasma silicon nitride SiH4 + NH3 200-350
SiH4 + N2 200-350
Plasma silicon dioxide SiH4 + N2O 200-350
Polysilicon SiH4 600-650
perature (which must be compatible with the device materials), the film properties,
and certain engineering aspects of the deposition (wafer throughput, safety, and reac-
tor maintenance).
The most common reactions for depositing silicon dioxide for VLSI circuits are
oxidizing silane with oxygen at 400 to 450°C, decomposing tetraethoxysilane at 650
to 750°C, and reacting dichlorosilane with nitrous oxide at 850 to 900°C. Doped
oxides are prepared by adding a dopant to the deposition reaction. The hydrides
arsine, phosphine, or diborane are often used because they are readily available gases;
however, halides and organic compounds can also be used. Silicon nitride is prepared
by reacting silane and ammonia at atmospheric pressure at 700 to 900°C, or by react-
ing dichlorosilane and ammonia at reduced pressure at about 700°C. Plasma-
deposited silicon nitride is deposited by reacting silane with ammonia or nitrogen in a
glow discharge between 200 and 350°C. This reaction is useful for passivation where
higher temperatures cause unwanted reactions between the silicon and the metal con-
ductors. Similarly, plasma-deposited silicon dioxide is formed from silane and
nitrous oxide in a glow discharge. Polysilicon is prepared by pyrolyzing silane at 6(30
to 650°C.
3.2.2 Equipment
Figures 1 and 2 give schematics of four reactors commonly used for depositions. Fig-
ure la shows a hot-wall, reduced-pressure reactor, used to deposit polysilicon, silicon
dioxide, and silicon nitride. The reactor consists of a quartz tube heated by a three-
zone furnace, with gas introduced in one end and pumped out the other. The mechan-
ical pump is sometimes augmented with a Roots blower. Pressures in the reaction
chamber are typically 30 to 250 Pa (0.25 to 2.0 Torr); temperatures range between
300 and 900°C; and gas flows are between 100 and 1000 std. cm^/min. Wafers stand
vertically, perpendicular to the gas flow, in a quartz holder. Each run processes 50 to
200 wafers. Special inserts that alter the gas flow dynamics are sometimes used.

96 VLSI Technology
3-ZONE FURNACE
(a)
^SAMPLES
PUMP
N2
1
GAS
1
HS
—^'
—Hh -
SAMPLES
EXHAUST
CONVEYOR
BELT
(b)
Fig. 1 Schematic diagrams of CVD reactors, (a) Hot-wall, reduced-pressure reactor,
atmospheric-pressure reactor.
(b) Continuous,
Thickness uniformities are within ±5%. Hot-wall, reduced-pressure reactors can be
easily scaled to hold 1 50-mm-diameter wafers. The major advantages of these reac-
tors are excellent uniformity, large load size, and ability to accommodate large diam-
eter wafers. The disadvantages are low deposition rates and the frequent use of toxic,
corrosive, or flammable gases.
Figure lb shows a continuous throughput, atmospheric-pressure reactor used to
deposit silicon dioxide. The samples are carried through the reactor on a conveyor
belt. Reactant gases flowing through the center of the reactor are contained by gas
curtains formed by a very fast flow of nitrogen. The samples are heated by convec-
tion. The advantages of these continuous throughput reactors are high throughput,
good uniformity, and ability to handle large-diameter wafers. The major disad-
vantages are that very fast gas flows are required and these reactors must be cleaned
frequently.

Dielectric and Polysilicon Film Deposition 97
INSULATED RF INPUT
Is
PLASMA
HEATED I
SAMPLE *
HOLDER PUMP
GAS
INLET
(a)
^^^.
GLASS
CYLINDER
LUMINUM
ELECTRODES
GAS
INLET
PRESSURE
SENSOR
3 -ZONE FURNACE
,GRAPH1TE
ELECTRODES
OOOOO PUMP
LOAD
DOOR GAS
INLET
(b)
Fig. 2 Schematic diagrams of plasma deposition reactors, (a) Parallel-plate, (b) Hot-wall.
Figure 2a shows a radial-flow, parallel-plate, plasma-assisted CVD reactor. The
reaction chamber is a cylinder, usually glass or aluminum, with aluminum plates on
the top and bottom. Samples lie on the bottom electrode, which is grounded. A radio
frequency voltage is applied to the top electrode to create a glow discharge between
the two plates. Gases flow radially through the discharge. They are usually intro-
duced at the outer edge and flow towards the center, although the opposite flow pat-
tern can be used. The gases are pumped with a Roots blower backed by a mechanical
pump. The grounded electrode is heated to a temperature between 100 and 400°C by
resistance heaters or high-intensity lamps. This reactor is used for the plasma-assisted
deposition of silicon dioxide and silicon nitride. Its main advantage is low deposition
temperature, while there are three major disadvantages. Capacity is limited, espe-
cially for large-diameter wafers. Wafers must be loaded and unloaded individually,
and wafers may be contaminated by loosely adhering deposits falling on them.

98 VLSI Technology
The hot-wall, plasma-deposition reactor shown in Fig. 2b solves many of the
problems encountered in the radial-flow reactor. The reaction takes place in a quartz
tube heated by a furnace. The samples are held vertically, parallel to the gas flow.
The electrode assembly, which supports the samples, contains long graphite or alumi-
num slabs. Alternating slabs are connected to the power supply, which generates a
discharge in the space between the electrodes. Advantages of this reactor are its high
capacity and low deposition temperatures. Its drawbacks, however, are that particles
can be formed while the electrode assembly is being inserted, and that wafers must be
individually handled during loading and unloading.
3.2.3 Safety
Many of the gases used to deposit films are hazardous. The safety problems are more
severe for low-pressure depositions because the processes often use concentrated
gases. For instance, 100% silane is used for polysilicon depositions at reduced pres-
sure, compared to only 3% silane in nitrogen for the same deposition at atmospheric
pressure. Low-pressure depositions which use pumps have additional safety problems
associated with them, because the gases can dissolve or react in the pump oil.
The hazardous gases fall into four general classes: poisonous; pyrophoric, flam-
mable, or explosive; corrosive; and dangerous combinations of gases. Table 2 lists
hazardous properties of common gases used in CVD. Examples of dangerous gas
combinations that may be encountered are silane with halogens, silane with hydrogen,
and oxygen with hydrogen.
Many of the flammable gases react with air to form solid products. Conse-
quently, small leaks cause particles to form within the gas lines. These particles
eventually plug the line or the gas metering equipment. The reactant gases and the
reaction products also accumulate in the pumps and may present hazards during pump
maintenance. Detailed safety precautions for CVD processes have been published.^
Table 2 Properties of common gases used in CVD
Gas Properties
Silane Toxic, flammable, pyrophoric
Dichlorosilane Toxic, flammable, corrosive
Phosphine Very toxic, flammable
Diborane Very toxic, flammable
Arsine Very toxic, flammable
Hydrogen chloride Toxic, corrosive
Ammonia Toxic, corrosive
Hydrogen Nontoxic, flammable
Oxygen Nontoxic, supports combustion
Nitrous oxide Nontoxic, nonflammable
Nitrogen Usually inert
Argon Inert

DffiLECTRIC AND POLYSILICON FiLM DEPOSITION 99
3.3 POLYSILICON
Polysilicon is used as the gate electrode in MOS devices. It is also used for high-
value resistors, diffusion sources to form shallow junctions, conductors, and to ensure
ohmic contact to crystalline silicon. The polysilicon is deposited by pyrolyzing silane
between 600 and 650°C in a low-pressure reactor (Fig. la). The chemical reaction is
SiHi^Si + 2H2 (1)
Subsequent processing for polysilicon gates involves doping, etching, and oxidation.
In some device structures a second polysilicon layer is deposited. This layer may be
used as a contact material in small windows or as an interconnect between conducting
features.
Two low-pressure processes are common for depositing polysilicon. One uses
100% silane at a pressure of 25 to 130 Pa (0.2 to 1 .0 Torr). The other process is per-
formed at the same total pressure but uses 20 to 30% silane diluted in nitrogen. Both
processes deposit polysilicon on 100 to 200 wafers per run with thickness uniformities
within 5%. The deposition rates are 100 to 200 A/min.^~^
3.3.1 Deposition Variables
Temperature, pressure, silane concentration, and dopant concentration are important
process variables in the deposition of polysilicon; wafer spacing and load size have
only minor effects.^- ^^
Figure 3 shows that the deposition rate increases rapidly as the
temperature increases. The activation energies, calculated from the slopes, are about
1.7 eV (40 kcal/mole), which is somewhat higher than the values observed for
atmospheric-pressure depositions." The difference is caused by changes in the
desorption of the hydrogen produced in the reaction and by differences in the roles of
mass transport and homogeneous reactions. Depositions at reduced pressure are lim-
ited to temperatures between 600 and 650°C. At higher temperatures, gas phase reac-
tions, which result in a rough, loosely adhering deposit, and silane depletion, which
causes poor uniformity, become significant.^^ At temperatures much lower than
6(X)°C, the deposition rate is too slow to be practical.
Polysilicon depositions frequently use a temperature ramp with the rear furnace
zone 5 to 15°C hotter than the front and center zones. The higher temperature
increases the deposition rate, which compensates for the silane depletion. Under
optimum conditions the increased deposition rate results in a uniform thickness
throughout the deposition zone. However, the structure of polysilicon is strongly
influenced by temperature, so a temperature ramp may cause a variation in structure
and film properties.
Pressure can be varied in a low-pressure reactor by changing the gas flow into the
reactor while keeping the pumping speed constant, or by changing the pumping speed
at a constant inlet gas flow. If the inlet gas is a mixture of silane and nitrogen, the
nitrogen flow can be changed while keeping the silane flow constant, or the silane and
nitrogen can both be changed while keeping the ratio constant. All three methods.

100 VLSI Technology
1000
700
TEMPERATURE (°C:
650 600
o<
100
10
2.7 Pa
.3 Pa
TOTAL PRESSURE 33. 3 Pa
.00 1.05 1. 10
lOOO/T (K-l)
1.15
Fig. 3 Arrhenius plot for polysilicon deposition for different silane partial pressures.
changing pumping speed, ciianging nitrogen flow, or changing total gas flow with a
constant ratio, are used to control the reactor pressure. If the total gas flow is varied
(constant ratio and pump speed), the deposition rate is a linear function of pressure.
But if the pumping speed or the nitrogen flow is changed, the rate only slightly
depends on pressure (see Fig. 4). Deposition reproducibility is best when the inlet gas
flows are kept constant and the pressure is controlled by the pumping speed.
The polysilicon deposition rate is usually not a linear function of the silane con-
centration.'^'" Figure 5 gives representative data for four deposition temperatures
and for a total pressure of 33 Pa (0.25 Torr). The nonlinear behavior may be caused
by mass transport effects, homogeneous reactions, or adsorbed hydrogen. '°~'^
Gas
phase nucleation occurs at high silane concentrations, thus imposing upper limits to
the concentration and the deposition rate at a given temperature and pressure.
Polysilicon can be doped during deposition by adding phosphine, arsine, or
diborane to the reactants. Figure 6 shows how the dopant affects the deposition rate.
Adding diborane causes a large increase in the deposition rate. In contrast, adding
phosphine or arsine causes a rapid decrease in the deposition rate. Similar effects
have been observed for depositions at atmospheric pressure. '^^
The thickness uniform-
ity across a single wafer degrades when dopants are added. Uniformity can be main-
tained by using an insert to control the flow of reactant gases around the samples.

200
100
.100
^
200
100
VARY PUMP SPEED
VARY N2 FLOW
VARY TOTAL GAS FLOW
20 40 60
PRESSURE (Pa)
80
Fig. 4 The effect of total pressure on the polysiUcon deposition rate.
800
698°C
628°C
30
10 20
SILANE PARTIAL PRESSURE (Pa)
Fig. 5 The effect of silane concentration on the polysiUcon deposition rate

102 VLSI Technology
300
02 04
DOPANT/SILANE
06
Fig. 6 The effect of dopants on the polysiUcon deposition rate at 610°C.
3.3.2 Structure
The structure of polysilicon is strongly influenced by dopants or impurities, deposition
temperature, and post-deposition heat cycles. Polysilicon deposited below 575°C is
amorphous with no detectable structure.'"^' ^^ Polysilicon deposited above 625°C is
polycrystalline and has a columnar structure. Crystallization and grain growth occur
when either amorphous or columnar polysilicon is heated.'"^' '^
Figure 7 illustrates all
three structures, showing transmission electron microscope (TEM) cross sections of
polysilicon deposited at 605°C (amorphous), 630°C (columnar), and annealed at 700°C
(crystalline grains). After high-temperature heat cycles, there are no significant struc-
tural differences between polysilicon that is initially amorphous or columnar.
The deposition temperature at which the transition from amorphous to columnar
structure occurs is well defined but depends on many variables, such as deposition
rate, partial pressure of hydrogen, total pressure, presence of dopants, and presence of
impurities (O, N, or C). The transition temperature is between 575 and 625°C for
depositions in an LPCVD reactor.''^' '^
Polysilicon recrystallizes when heated; how-
ever, the crystallization temperature is also strongly influenced by dopants and impur-
ities. Oxygen, nitrogen, and carbon impurities stabilize the amorphous structure to
temperatures above 1000°C, and arsenic stabilizes the columnar structure to 900°C.
The average diameter of the column, that is, the columnar grains, can be meas-
ured by TEM surface replication. The diameter, which depends on film thickness, is
typically between 0.03 and 0.3 (xm and is often reported as grain size.'"^"'^ The grain
size after crystallization depends on heating time, temperature, and dopant concentra-

- (a)
Poly-Sllicon
605°C
(b)
Poly-Silicon
630°C
— (c)
Poly-Siiicon
~ 700° C
Fig. 7 TEM cross sections (60.000X) of polysilicon. (a) Amorphous structure deposited at 605°C.
(b) Columnar structure deposited at 630°C. (c) Crystalline grains formed by annealing an amorphous sam-
ple at 700°C.
tion. Polysilicon doped with a high concentration of phosphorus and heated between
900 and 1000°C for 20 min has an average grain size of 1 |JLm.'^
Polysilicon deposited at 600 to 650°C has a {1 10}-preferred orientation.
'"^"'^
At
higher deposition temperatures the {100} orientation predominates, but the structure
contains significant contributions from other orientations, such as {1 10}, {1 1 1}, {31 1},
and {331}.^^ Dopants and impurities, as well as temperature, also influence the pre-
ferred orientation.
The structural changes in polysilicon during typical device processing can be
summarized as follows. Polysilicon deposited between 600 and 650°C has a columnar
structure with grain sizes between 0.03 and 0.3 |jLm and a {1 10}-preferred orientation.
During phosphorus diffusion at 950°C the structure changes to crystallites with an
average size of 0.5 to 1.0 fxm. The grains grow during oxidation at 1050°C to a final
size of 1 to 3 [xm. Polysilicon deposited at temperatures below 600°C behaves simi-
larly, except the initial film is amorphous.
3.3.3 Doping Polysilicon
Polysilicon can be doped by diffusion, implantation, or the addition of dopant gases
during deposition (in-situ doping). All three methods are used for device fabrication.
Figure 8 shows the resistivity of polysilicon doped with phosphorus by these three
methods. The diffusion data, taken from Ref. 17, show the resistivity after a 1-h dif-
fusion at the indicated temperature. The implantation data, taken from Ref. 18, show
the resistivity after a 1-h, 1100°C activation. The resistivities for the in-situ doped
samples are measured after deposition at 600°C and after a 30-min anneal at the indi-
cated temperature. Diffusion is a high-temperature process that results in very low
resistivities. The dopant concentration in diffused polysilicon often exceeds the solid

104 VLSI TECHNOLOGY
TEMPERATURE
(°C)
P-CONCENTRATION
(cm-3)
PH3/SiH4
Fig. 8 Resistivity of P-dop)ed polysilicon. (a) Diffusion. 1 h at the indicated temperature. (After Kamins,
Ref. 17.) (b) Implantation. 1-h anneal at 1100°C. (After Mandurah, Saraswat, and Kamins, Ref. 18.) (c)
In-situ. As-dep)osited at 6(X)°C and after a 30-min anneal at the indicated temperature. (After A. C. Adams,
unpublished data .
)
solubility limit, with the excess dopant segregated at the grain boundaries.'^ A good
correlation is found between the resistivity of diffused polysilicon and the dopant
solubility.'^ Diffusion of dopants is faster in polysilicon than in single-crystal silicon;
and lateral diffusion along a polysilicon film is faster than diffusion perpendicular to
the surface. ^°'^'
Hall mobilities for heavily diffused polysilicon are usually 30 to 40
Cm2/V-S.'^'22.23
The resistivity of implanted polysilicon depends primarily on implant dose,
annealing temperature, and annealing time.'^' '^' ^"^
The very high resistivity in lightly
implanted polysilicon (Fig. 8) is caused by carrier traps at the grain bound-
Once these traps have been saturated with dopants, the resistivity
anes 18, 19,24
decreases rapidly and approaches the resistivity for implanted single-crystal silicon.'^
The mobility for heavily implanted polysilicon is about 30 to 40 cm^/V-s,'^ similar to
the values for diffused polysilicon. Implanted polysilicon has about ten times higher
resistivity than diffused polysilicon, because of the differences in dopant concentra-
tions: approximately 10^° cm~-^ for a heavy implant and greater than 10^' cm"-' for a
heavy diffusion.
Polysilicon films that are doped during deposition by adding phosphine, arsine,
or diborane have resistivities that are strong functions of deposition temperature,

Dielectric and Polysilicon Rlm Deposition 105
100
1
o
1
o
~
10
1
-
e
"^1
-
Ol - -
001 -
A ^ n
3-P
-
A
0.001 1 ,
1
500 600
TEMPERATURE (°C)
700
Fig. 9 Resistivity of in-situ doped polysilicon deposited at different temperatures. The triangles denote
boron-doped polysilicon and the circles denote phosphorus-doped polysilicon.
dopant concentration, and annealing temperature. Figure 9 shows the resistivities for
in-situ doped polysilicon deposited at different temperatures. The transition from
high resistivity at low deposition temperature to low resistivity at high temperature
corresponds to the change from an amorphous to columnar structure. The
phosphorus-doped films in the figure (denoted by the circles) change structure at
625°C; the boron-doped polysilicon (denoted by the triangles) changes at tempera-
tures between 525 and 550°C. The resistivity of doped amorphous polysilicon
decreases during annealing, mainly because of crystallization (Fig. 8). After anneal-
ing the resistivity is not a strong function of the initial dopant concentration. Doped
polysilicon that is crystalline when deposited shows almost no change in resistivity
after annealing. The dopant concentration in in-situ doped polysilicon is high, 10^^ to
10^' cm"^, but the mobility is often low, 10 to 30 cm^/V-s.^^ The low mobility gives
a higher resistivity than expected for the high dopant concentration.
A comparison of the three doping processes shows that the major differences are
lower resistivity for diffusion, lower dopant concentration for implantation, and lower
mobility for in-situ doping. Implantation and in-situ doping, however, offer the
advantage of lower processing temperatures, which is often the dominant considera-
tion in VLSI processing.

106 VLSI Technology
3.3.4 Oxidation of Polysilicon
The details of polysilicon oxidation are discussed in Chapter 4. Polysihcon is usually
oxidized in dry oxygen at temperatures between 900 and 1000°C to form an insulator
between the doped-polysilicon gate and other conducting layers. Under these condi-
tions, oxidation is controlled by surface reactions. Undoped or lightly doped silicon
oxidizes at a rate between the rates for (111)- and (lOO)-crystalline silicon.
Phosphorus-doped polysilicon oxidizes faster than undoped polysilicon, and the rate
of oxidation is determined by the carrier concentration at the polysilicon surface. At
very high phosphorus concentrations, the oxidation rate saturates, because the solubil-
ity limit of phosphorus in silicon has been reached.
'^^
The silicon dioxide grown on polysilicon has lower breakdown fields, higher
leakage currents, and higher stress than oxides grown on single-crystal silicon. The
degraded oxide properties are related to the rough polysilicon-oxide interface, which
is caused by different oxidation rates at the polysilicon grain boundaries.
3.3.5 Properties of Polysilicon
The chemical and physical properties of polysilicon often depend on the film structure
(amorphous or crystalline) or on the dopant concentration. The etch rate of polysili-
con in a plasma and its thermal oxidation rate depend on the dopant concentration.
Polysilicon which is heavily phosphorus-doped etches and oxidizes at higher rates
than undoped or lightly doped polysilicon. The reaction rates for oxidation and etch-
ing are determined by the free carrier concentration at the doped-polysilicon surface.
Polysilicon' s optical properties depend on its structure. The imaginary part of the
dielectric function is particularly structure-sensitive.^^ Crystalline polysilicon has
sharp maxima in the dielectric function near 2950 and 3650 A (4.2 and 3.4 eV).
Amorphous polysilicon has a broad maximum without sharp structure. In addition,
amorphous polysilicon has a higher refractive index throughout the visible region than
crystalline polysilicon.'^' ^^' ^^
Other reported properties of polysilicon are its density, 2.3 g/cm^; coefficient of
thermal expansion, 2 x 10"^/ °C; and temperature coefficient of resistance,
I X 10~V°C. These are useful for modeling heat dissipation in devices.
3.4 SILICON DIOXIDE
Silicon dioxide films can be deposited with or without dopants. Undoped silicon
dioxide is used as an insulating layer between multilevel metallizations, as an ion-
implantation and diffusion mask, as a capping layer over doped regions to prevent
outdiffusion during heat cycles, and to increase the thickness of field oxides.
Phosphorus-doped silicon dioxide is used as an insulator between metal layers, as a
final passivation over devices, and as a gettering source. Oxides doped with phos-
phorus, arsenic, or boron are occasionally used as diffusion sources. The deposition
of oxide films has been reviewed.^^

Dielectric .^nd Polysilicon Film Deposition 107
The processing sequence for silicon dioxide depends on its specific use in the
device. Oxides used as insulators between conducting layers are deposited, densified
by annealing, and plasma-etched to open windows. In the flowed glass process,
phosphorus-doped silicon dioxide is heated to a temperature between 1000 and
1100°C so the oxide softens and flows, providing a smooth topography which
improves the step coverage of the subsequent metallization. Phosphorus-doped
oxides used for passivation are deposited at temperatures lower than 500°C, and areas
for bonding are opened by etching.
3.4.1 Deposition Methods
Several deposition methods are used to produce silicon dioxide. They are character-
ized by different chemical reactions, reactors, and temperatures. Films deposited at
low temperatures, lower than 500°C, are formed by reacting silane, dopant, and oxy-
gen.^'
^^' ^^
The chemical reactions for phosphorus-doped oxides are
SiH4 + 02-^ Si02 + 2H2 (2)
4PH3 + 5O2 -^ 2P2O5 + 6H2 (3)
Under normal deposition conditions, hydrogen is formed rather than water. The
deposition can be carried out at atmospheric pressure in a continuous reactor (Fig. lb)
or at reduced pressure in an LPCVD reactor (Fig. la). The main advantage of silane-
oxygen reactions is the low deposition temperature, which allows films to be de-
posited over aluminum metallization. Consequently, these films can be used for
passivation coatings over the final device and for insulation between aluminum levels.
The main disadvantages of silane-oxygen reactions are poor step coverage and parti-
cles caused by loosely adhering deposits on the reactor walls.
Silicon dioxide is also deposited at 650 to 750°C in an LPCVD reactor by decom-
posing tetraethoxysilane, Si(OC2H5)4.^'^'
^^^^
This compound, also called tetraethyl
orthosilicate and abbreviated TEOS, is vaporized from a liquid source. The overall
reaction is
Si(OC2H5)4 -^ Si02 + by-products (4)
where the by-products are a complex mixture of organic and organosilicon com-
pounds. The decomposition of TEOS is useful for depositing insulators over polysili-
con gates, but the high temperature required precludes its use over aluminum. The
advantages of TEOS deposition are excellent uniformity, conformal step coverage,
and good film properties. The disadvantages are the high-temperature and liquid
source requirements.
Silicon dioxide is also deposited at temperatures near 900°C and at reduced pres-
sure by reacting dichlorosilane with nitrous oxide^' ^'
^'^
SiCl2H2 + 2N2O -^ Si02 + 2N2 + 2HC1 (5)

108 VLSI Technology
This deposition, which gives excellent uniformity, is used to deposit insulating layers
over polysilicon; however, this oxide frequently contains small amounts of chlorine
which may react with the polysilicon or cause film cracking.^'*
Doping is achieved by adding small amounts of the dopant hydrides (phosphine,
arsine, or diborane) during the deposition. Other dopant compounds, such as halides
or organic compounds, can also be used, but they are not as convenient because they
must usually be vaporized from solids or liquids.
Dopant concentrations are reported by weight percent (wt. %), atom percent (at.
%), or mole percent (mol %). The relationships between these units for phosphorus-
doped oxides are
1 cy D/^ 6010 W ...
mole % P^O-; = -::rrT (6)
' ^ 6200 - 81.9 W ^^
12000 W
atom % P = (7)
18,600 - 81.9 W ^^
where W is weight percent of phosphorus. Occasionally weight percent, atom per-
cent, and mole percent are written as w/o, a/o, and m/o.
The doped oxides used as diffusion sources contain 5 to 15 wt. % of the dopant.
Doped oxides used for passivation or for interlevel insulation contain 2 to 8 wt. %
phosphorus. Doped oxides used for the P-glass flow process (described in Section
3.4.4) contain 6 to 8 wt. % phosphorus. Glass with lower phosphorus concentrations
will not soften and flow, and higher concentrations react slowly with atmospheric
moisture to form acid products, which corrode the aluminum metallization.
The dejx)sition of silicon dioxide depends on the same variables that are important for
polysilicon, that is, temperature, pressure, reactant concentration, and presence of
dopants. In addition, other variables, such as wafer spacing and total gas flow, are
important for some silicon dioxide depositions. Deposition variables for the reaction
of silane with oxygen at atmospheric pressure have been reviewed.^° The deposition
rate increases with temperature, but the apparent activation energy is very low, less
than 0.4 eV (10 kcal/mole). This activation energy is much less than the values usu-
ally observed for chemical reactions and is similar to the values for adsorption on a
surface or for gas phase diffusion. The deposition has a complicated dependence on
oxygen concentration. Namely, if the oxygen concentration is varied at a constant
temperature, the deposition rate increases rapidly, goes through a maximum, and then
slowly decreases. Figure 10 gives representative data, compiled from Ref. 35. This
relation has been explained by assuming surface-catalyzed reactions. ^^ At high con-
centrations the oxygen adsorbs on the surface and blocks further silane reactions.
When phosphine is added to the reaction, the rate rapidly decreases and then slowly
increases.^^ This deposition behavior may also be attributable to surface adsorption
effects.

Delectric and Polysilicon Film Deposition 109
3000
=< 20D0 -
UJ
1000
500°C
2000 4000 6000
OXYGEN PARTIAL PRESSURE (Pa)
8000
Fig. 10 The deposition rate of silicon dioxide at atmospheric pressure for different oxygen concentrations.
(After Maeda atidNakamura, Ref. 35.)
The reaction between silane and oxygen at reduced pressure follows similar
trends. The activation energy is very low, less than 0.4 eV (10 kcal/mole).-^' The
deposition rate is a linear function of the silane partial pressure. At high partial pres-
sures of silane the deposited silicon dioxide is hazy, probably because of gas-phase
reactions. •
The deposition rate goes through a maximum as oxygen partial pressure
is varied, which is similar to the result observed at atmospheric pressure. -^^
The gas-
phase transport of material to the wafer surface is very important. A special sample
holder which directs the gas to the wafers is required for uniform depositions.
-^''^^
The deposition rate also depends on wafer spacing.^'
^^
The deposition of silicon dioxide by decomposing TEOS occurs at temperatures
between 650 and 750°C. Figure 1 1 shows deposition rate as a function of temperature
for the TEOS decomposition (from Ref. 33) and for the silane-oxygen reaction (from
Ref. 31). The activation energy for the TEOS reaction is about 1.9 eV (45
kcal/mole). which decreases to 1.4 eV (32 kcal/mole) when phosphorus doping com-
pounds are present. ^-^
Note the contrast between these activation energies and the very
low activation energies required in silane-oxygen reactions. Figure 12 shows how the
deposition rate depends on the TEOS partial pressure. The data points are taken from
Ref. 33 and the solid line is from Ref. 32. The nonlinear behavior, which is similar to
polysilicon deposition, has been explained by assuming surface catalyzed reactions.
^^
At low TEOS partial pressures the deposition rate is determined by the rate of the sur-

110 VLSI Technology
1000
TEMPERATURE {°C)
800 700 600 425 375
100
10
09
P-DOPED
UNDOPED
SiH4 +O2
P-DOPED
UNDOPED
lOOO/T ( K'
16
Fig. 11 Arrhenius plots for the low-pressure deposition of SiO^. (After Adams and Capio, Ref. 33, for the
TEOS data and after Logar, Waiik, and Rosier, Ref. 31 . for the silane-oxygen data.)
500
400-
»< 300 -
200 -
20 40 60 80
TEOS PARTIAL PRESSURE (Pa)
100
Fig. 12 Deposition rate for different TEOS concentrations. (After Adams and Capio, Ref. 33, for the data
points and after Huppertz and Engl, Ref. 32, for the solid line.)

face reaction. At very high partial pressures, the surface becomes nearly saturated
with adsorbed TEOS, and the deposition rate becomes independent of the TEOS pres-
sure. The TEOS deposition also depends on the total pressure; however, this pressure
dependence has not been adequately explained.
-^^
The deposition of silicon dioxide at 900°C using dichlorosilane and nitrous oxide
has a strong nonlinear pressure dependence, which is a function of wafer position in
the reactor. Gas transport and depletion are significant in this deposition.^
^
Phosphorus-doped oxides are deposited by adding phosphorus compounds, usu-
ally phosphine, to the silane-oxygen or TEOS reaction. Doping is difficult with the
dichlorosilane-nitrous oxide reaction because of the high deposition temperature.
Adding phosphorus to the low-pressure depositions causes the thickness uniformity to
degrade. The deposition of phosphorus-doped silicon dioxide requires inserts, which
ensure uniform gas flow over the wafer surfaces.
3.4.3 Step Coverage
Three general types of step coverage are observed for deposited silicon dioxide. They
are schematically diagrammed in Fig. 13. Figure 13a shows a completely conformal
step coverage; the film thickness along the walls is the same as the film thickness at
(a)
(b)
(c)
Fig. 13 Step coverage of deposited films, (a) Conformal coverage resulting from rapid surface migration,
(b) Nonconformal step coverage for long mean-free path and no surface migration, (c) Nonconformal step
coverage for short mean-free path and no surface migration.

112 VLSI Technology
the bottom of the step. Conformal step coverage results when reactants or reactive
intermediates adsorb on the surface and then rapidly migrate along the surface before
reacting. The rapid migration results in a uniform surface concentration, regardless of
the topography, and gives a completely uniform thickness.
When the reactants adsorb and react without significant surface migration, the
deposition rate is proportional to the arrival angle of the gas molecules. Figure 13b
gives an example where the mean-free path of the gas is much larger than the dimen-
sions of the step. The arrival angle in two dimensions at the top horizontal surface is
180°. At the top of the vertical surface, the arrival angle is only 90° so the film thick-
ness is reduced by half. Along the vertical walls the arrival angle, <^, is determined
by the width of the opening, and the film thickness, which is proportional to the
arrival angle, can be calculated from
w
(f)
= arctan— (8)
a
where w is the width of the opening and d is the distance from the top surface. This
type of step coverage is thin along the vertical walls and may have a crack at the bot-
tom of the step caused by self-shadowing.
Figure 13c gives a diagram for no surface migration and for a short mean-free
path. Here the arrival angle at the top of the step is 270°, giving a thicker deposit.
The arrival angle at the bottom of the step is only 90° and the film is very thin. Gas
depletion effects are also observed along the step walls. The thick cusp at the top of
the step and the thin crevice at the bottom combine to give a concave shape which is
particularly difficult to cover with metal.
Figure 14 gives actual examples of the different types of step coverage. The sam-
ples are prepared by etching (110) single-crystal silicon in hot potassium hydroxide to
form vertical grooves 5 jxm wide and 50 |JLm deep. Approximately 1 fxm of oxide is
deposited. The samples are cleaved and a cross section examined to determine the
step coverage. A nearly conformal coverage is observed for the TEOS deposition at
reduced pressure (Fig. 14a). The mean-free path at the deposition conditions (700°C
and 30 Pa) is several hundred micrometers, much larger than the dimensions of the
groove. Consequently, gas-phase diffusion into the groove is negligible. However,
surface migration is very rapid, resulting in the conformal coverage.
Figure 14b shows silicon dioxide deposited from silane and oxygen at reduced
pressure. The mean-free path is still large, several hundred microns, but no surface
migration takes place, and the step coverage is determined by the arrival angle. Sili-
con dioxide deposited at atmospheric pressure by reacting silane and oxygen builds
up at the top of the step because of the very short mean-free path at atmospheric pres-
sure (less than 0.1 |xm). Figure 14c shows this step coverage. The nonconformal step
coverage shown in Figs. 14b and c causes metallization failures because of the con-
cave shape. The region at the bottom of the step often etches rapidly, causing addi-
tional serious problems in subsequent processing.
Other materials besides deposited silicon dioxide have the types of step coverage
shown in Figs. 13 and 14. Most evaporated or sputtered metals have step coverage
similar to that shown in Fig. 14b. Chemically deposited polysilicon and silicon
nitride have conformal coverage. Plasma-deposited silicon dioxide is similar to

Dielectric A^fD PolYsiLicoN Film Deposition 113
:b) (c)
Fig. 14 SEM cross sections (5(XX)X) showing step coverage of deposited oxides, (a) TEOS deposition at
7(X)°C. (b) Silane-oxygen reaction at 450°C and reduced pressure, (c) Silane-oxygen reaction at 480°C and
atmospheric pressure.
Fig. 14b, and plasma-deposited silicon nitride is intermediate between Figs. 14a
and b. In this intermediate case the film is thin along the vertical walls, but somewhat
thicker than expected for no surface migration.
3.4.4 P-Glass How
Phosphorus-doped silicon dioxide is frequently used as an insulator between polysili-
con gates and the top level metallization. A concave shape in the oxide going over
the polysilicon gate can cause an opening in the metal film, resulting in device
failure. The poor step coverage of the phosphorus-doped silicon dioxide can be
corrected by heating the samples until the oxide softens and flows. This process is
called P-glass flow.
P-glass flow is illustrated in the scanning electron microscope (SEM) photo-
graphs in Figs. 15 and 16. Figure 15 shows a polysilicon line crossing an oxide step
with the entire surface covered with 4.6 wt. % P-glass. The samples have been heated
in steam at 1 100°C for four different lengths of time between (Fig. 15a) and 60 min
(Fig. 15d). Flow is indicated by the progressive loss of detail. The SEM cross sec-
tions in Fig. 16 show P-glass covering polysilicon. The samples contain between
and 7.2 wt. % phosphorus and have been heated in steam at 1 1(X)°C for 20 min. Sam-
ples with no phosphorus do not flow (Fig. 16a). The concave shape, thick at the top
and thin at the bottom, is easily seen. As the phosphorus concentration in the oxide
increases, flow increases, decreasing the angle made by the P-glass going over the
step. As these figures demonstrate, P-glass flow is a time-dependent phenomenon.

114 VLSI Technology
(a) (b)
(c) (d)
Fig. 15 SEM photographs (32(X)X) showing surfaces of 4.6 wt. % P-glass annealed in steam at 1 100°C for
the following times: (a) min; (b) 20 min; (c) 40 min; (d) 60 min. (After Adams and Capio. Ref. 38.
Reprinted by permission of the publisher, The Electrochemical Society. Inc.)
(a) (b)
(c) (d)
Fig. 16 SEM cross-sections (10,000X) of samples annealed in steam at 1 100°C for 20 min for the follow-
ing weight percent of phosphorus: (a) 0.0 wt. % P; (b) 2.2 wt. % P; (c) 4.6 wt. % P; (d) 7.2 wt. % P. (After
Adams and Capio, Ref. 38. Reprinted by permission of the publisher. The Electrochemical Society, Inc.)

Dielectric AND PolYsiLicoN FtLM Deposition 115
Samples usually do not reach an equilibrium state during flow. Flow depends on
several variables: annealing time, temperature, rate of heating, phosphorus concentra-
tion, and annealing ambient.
Figure 17, which summarizes many of these effects, shows the angle made by the
P-glass going over a step after different flow treatments and for different phosphorus
concentrations. As deposited the steps are concave with 120° angles. Row is meas-
ured by the decrease in the angle. P-glass flow is greatest for high phosphorus con-
centrations, steam ambient, and high temperatures.^^
The P-glass flow process requires temperatures to be as high as 1000 to 1 100°C.
It also requires phosphorus concentrations of 6 to 8 wt. %. Less concentrated glasses
do not flow readily. Phosphorus concentrations greater than 8 wt. % may cause cor-
rosion of the aluminum metallization by the acid products formed from the reaction
between the phosphorus in the oxide and atmospheric moisture.
3.4.5 Properties of Silicon Dioxide
Table 3 summarizes properties of silicon dioxide deposited by different techniques,
including the plasma-assisted deposition of silicon dioxide. In general, oxides depos-
ited at higher temperatures resemble thermally grown silicon dioxide. However,
high-temperature oxides can not be deposited over aluminum and therefore can not be
120
1 1 1
Ny "^"^is^ ° STEAM 1050°C
^V • 02 iioo°c
^V ^ ^2 itoo-c
100 >^ ^^ A STEAM iiocc _
80
-
-
60
V
s,
40

-
20 ^V
^
1 1 1
1
4 6
WEIGHT %P
Fig. 17 Step angles made by P-glass after different flow treatments. (After Adams and Capio, Ref. 38.
Reprinted by permission of the publisher, The Electrochemical Society , Inc.)

116 VLSI Technology
Table 3 Properties of deposited silicon dioxide
Deposition Plasma SiH4 + O. TEOS SiCl2H2 + N2O
Temperature (°C) 200 450 700 900
Composition SiO,9(H) SiOoiH) SiO. Si02(Cl)
Step coverage Nonconformal Nonconformal Conformal Conformal
Thermal stability Looses H Densifies Stable Looses CI
Density (g/cm^) 2.3 2.1 2.2 2.2
Refractive index 1.47 1.44 1.46 1.46
Stress (
10^ dyn/cm-) 3C-3T 3T IC 3C
Dielectric strength
lO^V/cm
3-6 8 10 10
Etch rate (A/min)
(100:1 H20:HF)
400 60 30 30
used for the final device passivation. Consequently, the low-temperature, phospho-
rus-doped oxides are used for final passivation in spite of their poor step coverage and
somewhat inferior film properties.
Composition Silicon dioxide deposited at low temperatures, (400— 500°C) contains
hydrogen. This hydrogen is bonded within the silicon-oxygen network as silanol
(Si —OH), hydride (Si —H), or water (H2O). The bonded hydrogen can be observed
by infrared spectroscopy."^^ Silicon dioxide deposited between 400 and 500°C typi-
cally contains 1 to 4 wt. % SiOH and less than 0.5 wt. % SiH. The amount of water
in the film, which depends on the deposition temperature, increases with exposure to
atmospheric moisture. Silicon dioxide films deposited at 700°C by TEOS decomposi-
tion, or at 900°C by the dichlorosilane-nitrous oxide reaction, do not contain hydro-
gen that is detectable by infrared absorption. The films formed from dichlorosilane,
however, contain chlorine.
-^"^
The chlorine can react with the silicon substrate or
evolve from the film during high-temperature anneals.
Phosphorus concentrations in doped silicon dioxide can be measured by infrared
absorption, neutron activation, x-ray emission spectroscopy, sheet resistance of dif-
fused layers, etch-rate variation, the refractive index, or an electron microprobe.
Several of these techniques have been compared.'*'^'*' Figure 18 gives curves relating
sheet resistance and infrared absorption to the phosphorus concentration. For the
sheet-resistance method, the phosphorus-doped oxide is deposited on a lightly doped
p-type substrate. After deposition the sample is heated at 1100°C for 20 min, the
oxide film is removed by etching, and the sheet resistance of the n-type diffused layer
is measured. This method is useful in a processing facility where furnace and etching
operations are available; however, if the diffusion is performed at a different tempera-
ture or time, the calibration curve in the figure is displaced. The infrared technique is
convenient in a laboratory environment. It requires measuring the ratio of the P—
O
absorption at 1325 cm^^ and the Si—O absorption at 805 cm"'. Concentrations of

Delectric and Polysilicon Film Deposition 117
4 6
WEIGHT %P
Fig. 18 Calibration curves for measuring phosphorus concentration, (a) Infrared absorbance ratio. (After
R. M. Levin and A. C. Adams, unpublished data.) (b) Sheet resistance. (After Adams and Murarka, Ref.
40.)
Other dopants, such as boron and arsenic, can also be measured by sheet resistance or
infrared absorption.
Thickness Film thickness can be measured by a stylus instrument, reflectance spec-
troscopy, ellipsometry, or a prism coupler. Automated instruments, suitable for rou-
tine use, are available for all these techniques. Figure 19 compares them and shows
that they all attain similar accuracy and precision.'^^
While all four techniques are gen-
erally suitable for measuring silicon dioxide films, they each have specific limita-
tions. Stylus measurement requires etching a step or masking part of the substrate
during deposition. Prism coupling can not be used on oxide films that are less than
4000 A thick. Ellipsometry requires the oxide thickness to be known to within 2500
A, since the measured ellipsometric quantities are periodic functions of the thickness.
Reflectance spectroscopy requires empirical calibration or accurate values for the film
refractive index.
Structure Deposited silicon dioxide has an amorphous structure consisting of Si04
tetrahedra. Its structure is similar to that of fused silica. The film density ranges

118 VLSI Technology
04 0.8 1.2
THICKNESS (PRISM COUPLER) (^m)
1.6
Fig. 19 Correlation plot showing oxide thickness measured by four techniques. The points have been
separated by adding 0.2 ixm to the reflectance spectroscopy thickness and 0.4 |xm to the eUipsometry thick-
ness. (After Adams, Schinke, andCapio, Ref. 42. Reprinted by permission of the publisher, The Electro-
chemical Society , Inc.)
between 2.0 and 2.2 g/cm^. The lower densities occur in films deposited below
500°C. Heating deposited silicon dioxide at temperatures between 600 and 1000°C
causes densification; the oxide thickness decreases and the density increases to 2.2
g/cm-^. During densification the amorphous structure is maintained; however, the
arrangement of the Si04 tetrahedra becomes more regular.
"^-^
Densification causes
deposited silicon dioxide to take on many of the characteristic properties of thermally
grown oxides.
Reactivity Silicon dioxide deposited at a low temperature reacts with atmospheric
moisture, especially if the oxide contains phosphorus. The phosphorus-oxygen dou-
ble bond undergoes a reversible hydrolysis. This effect can be minimized by densifi-
cation at 800 to 900°C.
The etch rates of deposited oxides in a hydrofluoric acid solution depend on
deposition temperature, annealing history, and dopant concentration.-'^ These etch

Dielectric AND PolYsiLicoN Film Deposition 119
rates are important because solutions containing fluoride are frequently used for
cleaning. An etchant containing nitric acid, hydrofluoric acid, and water is useful for
evaluating and comparing deposited oxides. Etch rates in this solution (often called
P-etch) are sensitive to film density, porosity, and composition.-'^
Refractive index and stress The refractive index of silicon dioxide is 1.458 at a
wavelength of 0.6328 xm. Deposited oxides with refractive indices above 1.46 are
usually silicon-rich. Oxides with lower indices are porous. An example is the oxide
from the silane-oxygen deposition, which has a refractive index of about 1 .44.
Stress in silicon dioxide depends on deposition temperature, deposition rate,
annealing treatments, dopant concentration, water content, and film porosity.
Undoped silicon dioxide deposited at a temperature between 400 and 500°C usually
has a tensile stress of 1 to 4 x 10^ dyn/cm"^. Undoped oxides depxjsited at a tempera-
ture between 650 and 750°C have a very low compressive stress, to 1 X 10^
dyn/cm-, and oxides deposited at 900°C have a slightly higher compressive stress, 2
to 3 X 10^ dyn/cm". The stress is usually more compressive when phosphorus is
added.
3.5 SILICON NITRIDE
Stoichiometric silicon nitride (Si3N4) is used for passivating silicon devices, because
it serves as an extremely good barrier to the diffusion of water and sodium. These
impurities cause devices to corrode or become unstable. Silicon nitride is also used as
a mask for the selective oxidation of silicon. The silicon nitride is patterned and the
exposed silicon substrate is oxidized. The silicon nitride oxidizes very slowly and
prevents the underlying silicon from oxidizing. This process of selective oxidation is
used to produce nearly planar device structures.'^
Silicon nitride is chemically deposited by reacting silane and ammonia at atmo-
spheric pressure at temperatures between 700 and 900°C or by reacting dichlorosilane
and ammonia at reduced pressure at temperatures between 700 and 800°C. The
chemical reactions are
3SiH4 + 4NH3 -^ Si3N4 + I2H2 (9)
3SiCl2H2 + 4NH3 -^ Si3N4 + 6HC1 + 6H2 (10)
The reduced-pressure technique has the advantage of very good uniformity and high
wafer throughput. ''• ^' •'^
Thermal growth of silicon nitride by exposing silicon to
ammonia at temperatures between 1000 and 1100°C has been investigated. The
resulting films contain oxygen and are very thin.
Silicon nitride depositions at reduced pressure are controlled by temperature, total
pressure, reactant concentrations, and temperature gradients in the furnace. The tem-
perature dependence of the deposition rate is similar to that of polysilicon. The

120 VLSI Technology
activation energy for the silicon nitride deposition is about 1.8 eV (41 kcal/mole).
The deposition rate increases with increasing total pressure or dichlorosilane partial
pressure, and decreases with an increasing ammonia to dichlorosilane ratio. A tem-
perature ramp, with the furnace tube hotter at the exhaust end, is required for uniform
depositions. (See Section 3.3. 1 for a discussion of temperature ramps.)
3.5.2 Properties of Silicon Nitride
Silicon nitride, chemically deposited at temperatures between 700 and 9(X)°C, is an
amorphous dielectric containing up to 8 at. % hydrogen."*^ The hydrogen is bonded to
the nitrogen and to the silicon. The amount of bonded hydrogen depends on the depo-
sition temperature and on the ratio of reactants. More hydrogen is incorporated at low
deposition temperatures or at high ammonia to dichlorosilane ratios. Silicon nitride
deposited at low ammonia to dichlorosilane ratios contains excess silicon, which
decreases the electrical resistivity.
Silicon nitride has a refractive index of 2.01 and an etch rate in buffered hydro-
fluoric acid of less than 10 A/min. Both measurements are used to check the quality
of deposited nitrides. High refractive indices indicate a silicon-rich film; low indices
are caused by oxygen impurities. Oxygen impurities in the film also cause a higher
etch rate. Silicon nitride has a very high tensile stress, about 1 x lO'^ dyn/cm^.
Films thicker than 20(X) A sometimes crack because of the very high stress.
The resistivity of silicon nitride at room temperature is about 10 '^ O-cm. The
electrical conduction depends on the deposition temperature, ratio of reactants,
amount of the hydrogen in the film, and presence of oxygen impurities.
Silicon nitride is an excellent barrier to sodium diffusion. Its effectiveness is usu-
ally tested by evaporating radioactive sodium chloride (Na^^Cl) on the silicon nitride
and then heating the samples at 600°C for 22 h. The sodium is counted as the silicon
nitride is removed by step etching. Typically less than 10% of the original sodium
diffuses more than 50 A into the film.'*^
Table 4 summarizes the properties of silicon nitride and plasma-deposited nitride.
3.6 PLASMA-ASSISTED DEPOSITIONS
Plasma-assisted depositions provide films at very low sample temperatures. They do
this by reacting the gases in a glow discharge, which supplies much of the energy for
the reaction. Although the electron temperature in the discharge may be near 10^^ °C,
the sample temperature is between 1(X) and 400°C. This technique, often referred to
as plasma deposition, has been thoroughly reviewed."*' ^^'
^'^
A large number of inorganic and organic materials have been deposited by
plasma deposition but only two are useful in VLSI technology: plasma-deposited sili-
con nitride (SiN) and plasma-deposited silicon dioxide. Plasma-deposited silicon
nitride is used as the encapsulating material for the final passivation of devices. The
plasma-deposited nitride provides excellent scratch protection, serves as a moisture
barrier, and prevents sodium diffusion. Because of the low deposition temperature,

Table 4 Properties of silicon nitride
Deposition LPCVD Plasma
Temperature (°C) 700-800 250-350
Composition Si3N4(H) SiN^^Hy
GSi/N ratio 0.75 0.8-1.2
At. %H 4-8 20-25
Refractive index 2.01 1.8-2.5
Density (g/cm^) 2.9-3.1 2.4-2.8
Dielectric constant 6—7 6-9
Resistivity (O-cm) lO'^ lO^-lO'^
Dielectric strength (
10^ V/cm) 10 5
Energy gap (eV) 5 4—5
Stress ( 1
0''
dyn/cm-
)
1 OT 2C-5T
300 to 350°C, the nitride can be deposited over the final device. Plasma-deposited
nitride and oxide are both used as insulators between metallization levels. They are
particularly useful when the bottom metal level is aluminum or gold.
Silicon dioxide films are deposited by reacting silane and nitrous oxide in an argon
plasma. Silicon nitride is formed by reacting silane and ammonia in an argon plasma
or by reacting silane in a nitrogen discharge. The reactions are often assumed to be
SiH4 + 4N2O -^ Si02 + 4N2 + 2H2O (11)
SiH4 + NH3 ^ SiNH + 3H2 (12)
2SiH4 + N2 -^ 2SiNH + 3H2 (13)
However, the products depend strongly on the deposition conditions. The radial-
flow, parallel-plate reactor (Fig. 2a) and the hot-wall plasma reactor (Fig. 2b) are
commonly used for device processing.
Many variables must be controlled during a plasma deposition, such as fre-
quency, electrode spacing, power, total pressure, reactant partial pressures, pumping
speed, sample temperature, electrode materials, and reactor geometry.'*^ Some vari-
ables have a predictable effect on the deposition. For instance, the deposition rate
generally increases with increasing temperature, power, or reactant pressure. In
many cases, however, variables interact so measuring and interpreting the effect of a
specific variable becomes difficult. In other cases variables affect the deposition and
film properties, but the effects are difficult to explain. For instance, silicon nitride
that has been plasma-deposited at a frequency of 13.56 MHz has a tensile stress of
about 4x10^ dyn/cm^, whereas a similar film deposited at a frequency of 50 kHz
has a compressive stress of 2 x 10^ dyn/cnr. The strong dependence on deposition

122 VLSI Technology
conditions makes it very difficult to compare films from different reactors. All depo-
sition conditions must be carefully specified when discussing the properties of
plasma-deposited films.
3.6.2 Properties of Plasma-Deposited Films
Plasma-deposited films contain large hydrogen concentrations, which depend on the
deposition conditions.'^^"^' Plasma silicon nitride may contain between 10 and 35 at.
% hydrogen; however, most of the plasma nitride used in semiconductor processing
contains 20 to 25 at. % hydrogen. The hydrogen is bonded to the silicon as Si—
H
and to the nitrogen as N—H."*^' ^'
The plasma silicon nitride often contains 0.5 to 2.0
at. % oxygen as an impurity. Figure 20, compiled from Ref. 49, shows how the
plasma nitride composition varies with different deposition conditions. The relative
concentrations of Si—H and N—H change by large amounts, but the total hydrogen
concentration remains nearly constant except at low temperatures. The silicon to
nitrogen ratio, which varies between 0.7 and 1 .7, also strongly depends on the deposi-
tion conditions.
Figure 21 gives similar data for the hydrogen concentration in plasma-deposited
silicon dioxide. The hydrogen is bonded to silicon as Si—H and to oxygen as Si —OH
100 400 100 300 75 100 0.01 0.03
TEMPERATURE POWER PRESSURE SiH.^/No
(°C) (W) (Pa)
Fig. 20 Composition of plasma nitride for different deposition conditions: solid circles denote total H, open
squares denote SiH, open triangles denote NH, open circles denote Si, and closed squares denote N. (After
Dunetal.,Ref.49.)

10
E 30
o
o
^ 20
I 10
U
HJD
^
100
TEMPI
300
=C)
100
N20/SiH4
16 32
POWER (W)
0.4 1.2
%SiH4
Fig. 21 The concentration of hydrogen groups and the total at. % H in plasma Si02 for different deposition
conditions: triangles denote H2O, circles denote SiOH. squares denote SiH, and closed circles denote total
hydrogen. (After Adams et ai, Ref. 50.)
and H2O. The relative concentration of hydrogen in the three bonding sites strongly
depends on deposition conditions; however, the total hydrogen only varies between 2
and 9 at. %. The data in Figs. 20 and 21 show that the composition of the plasma-
deposited films depends on the specific deposition conditions. The subsequent varia-
tions in composition cause large changes in the film properties.
Stress is one of the most important properties of plasma silicon nitride, since high
stress can cause cracking during bonding operations. Films with low tensile stress,
about 2 X 10^ dyn/cur, can be prepared, but the stress depends on nearly every
deposition variable. Plasma nitride films deposited by reacting silane in a nitrogen
plasma are more compressive than plasma nitride produced from silane and ammonia.
In addition, films deposited at low frequencies are compressive, rather than tensile.
Plasma-deposited silicon nitride has a large range of resistivities (10^ to 10^^
fl-cm) and of breakdown fields (1 to 6 x 10^ V/cm). Figure 22 shows resistivity
data for plasma nitride, taken from Refs. 49 and 52. The correlation between resis-
tivity and film composition is excellent, even over resistivity changes of many orders
of magnitude. Correlations of dielectric breakdown field with film composition and
deposition conditions have also been made for plasma nitride and oxide."^^^ ^°' ^^
Tables 3 and 4 list general properties of plasma-deposited silicon nitride and silicon
dioxide.

124 VLSI Technology
10
22
20
10
10
o Ref. 49
• Ref. 52
Fig. 22 Resistivity of plasma silicon nitride. (After Dun et al., Ref. 49, and after Sinlm and Smith,
Ref. 52.)
3.7 OTHER MATERIALS
Several insulating materials have been investigated for IC applications, primarily for
passivation or for dual dielectric MOS devices. Silicon oxynitride is deposited by
reacting silane, nitric oxide, and ammonia or by reacting silane, carbon dioxide,
ammonia, and hydrogen.^^' ^'^
By adjusting the deposition conditions, any film com-
position between Si02 and Si3N4 can be obtained. Since silicon dioxide has a
compressive stress and silicon nitride is in tension, they form an intermediate compo-
sition of silicon oxynitride with zero stress. This composition is useful for passivation
in some applications.
Boro-phosphosilicate glass and lead silicate glass may also be useful for passiva-
tion. Both can be deposited at low temperatures (300 to 500°C), and both soften and
flow at temperatures below 1000°C. Aluminum oxide, aluminum nitride, and
titanium oxide have been evaluated as dielectrics for MOS applications. These films,
which are chemically deposited between 800 and 1 100°C, have high resistivities, high
dielectric constants, and high breakdown fields.

Semi-insulating polysilicon (SIPOS) is deposited between 600 and 700°C by
reacting silane and nitrous oxide. The deposited film, which contains 20 to 40 at. %
oxygen, may be a multiphase mixture containing amorphous silicon, crystalline sili-
con, silicon dioxide, and silicon monoxide. This material is useful for passivation.
Various organic compounds, usually polyimides, have been used as insulators
between metal levels. These compounds are applied by spinning and then are baked
above their softening temperature. This process produces a planar surface that is ideal
for metallization. The organic compounds have limited thermal stability and are very
porous to moisture penetration.
Table 5 summarizes current techniques for depositing dielectric and polysilicon films.
The low-temperature processes for depositing P-glass and SiN are particularly attrac-
tive for passivation, since the films can be deposited over aluminum or gold metalli-
zation. The poor step coverage, however, is a severe disadvantage if these processes
are used to deposit an insulating film between conducting layers. A higher tempera-
ture process (500-900°C), with conformal step coverage is generally much better.
Other deposition methods for dielectric and polysilicon films are available, such as
evaporation, sputtering, anodization, and molecular beam techniques, but they are not
widely used for VLSI processing. Their major problems include defects caused by
excessive wafer handling, low throughput, poor step coverage, and nonuniform depo-
sitions over many wafers.
Table 5 Comparison of different deposition methods
Methods
Deposition
properties
Atmospheric-
pressure CVD
Low-
temperature
LPCVD
Medium-
temperature
LPCVD
Plasma-
assisted CVD
Temperanire (°C) 300-500 300-500 500-900 100-350
Materials SiO.
P-glass
SiO.
P-glass
Poly-Si
Sid.
P-glass
Si3N4
SiN
S1O2
Uses Passivation,
insulation
Passivation,
insulation
Gate metal.
insulation.
passivation
Passivation,
insulation
Throughput High High High Low
Step coverage Poor Poor Conformal Poor
Particles Many Few Few Many
Film properties Good Good Excellent Poor
Low temperature Yes Yes No Yes

126 VLSI Technology
VLSI devices with very small dimensions require precise lithography, pattern
transfer with anisotropic etching, and very shallow junctions. These conditions
impose new requirements on the film deposition process. The major requirements are
low processing temperatures to prevent movement of the shallow junctions, confor-
mal step coverage over the anisotropically etched features, low process-induced
defects (mainly particles generated during wafer handling and loading), and high
wafer throughput to reduce cost. These requirements are met by hot-wall, low-
pressure depositions (chemical or plasma). The reactors for this type of deposition are
easily scaled to accommodate 125- or 150-mm wafers. In contrast, atmospheric-
pressure depositions and physical-deposition techniques are much more difficult to
scale and do not have the high throughput or the low defect densities. Consequently
these techniques are being replaced by LPCVD and plasma-assisted depositions as
critical device dimensions decrease and wafer size increases.
Low-temperature depositions will continue to increase in importance, because the
maximum processing temperature for devices with shallow junctions is about 900 to
950°C. Depositions at very low temperatures, 30 to 200°C, have been investigated
and they will probably find applications in new device technologies. These low-
temperature techniques include plasma-assisted depositions of organosilicon com-
pxDunds and photo-induced depositions of silicon dioxide and silicon nitride. The
photo-induced reactions occur at about 100°C and introduce almost no radiation dam-
age in devices.
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[2] W. Kern and G. L. Schnable, "Low-Pressure Chemical Vapor Deposition for Very Large- Scale
Integration Processing—A Review," IEEE Trans. Electron Devices. ED-26, 647 ( 1979).
[3] E. C. Douglas, "Advanced Process Technology for VLSI Circuits," Sold State Technol., 24, 65 (May
1981).
[4] J. L. Vossen and W. Kern, "Thin-Film Formation," Phys. Today, 33, 26 (May 1980).
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[7] R. S. Rosier, "Low Pressure CVD Production Processes for Poly, Nitride, and Oxide," Solid State
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[8] W. A. Brown and T. I. Kamins, "An Analysis of LPCVD System Parameters for Polysilicon, Silicon
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Polysilicon," in L. F. Donaghey, P. Rai-Choudhury, and R. N. Tauber, Eds., Chemical Vapor
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12] C. H. J. Van Den Brekel and L. J. M. Bollen. "Low Pressure Deposition of Polycrystalline Silicon
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13] F. C. Eversteyn and B. H. Put. "'Influence of ASH3. PH3. and B^H^, on the Growth Rate and Resis-
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—
Ht Mixture," J. Electrochem. Soc,
120.106(1973).
14] T. I. Kamins, M. M. Mandurah. and K. C. Saraswat, "Structure and Stability of Low Pressure Chem-
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15] T. I. Kamins. "Structure and Properties of LPCVD Silicon Films." J. Electrochem. Soc, 127. 686
(1980).
16] Y. Wada and S. Nishimatsu. "Grain Growth Mechanism of Heavily Phosphorus-Implanted Polycrys-
talline Silicon," 7. f/mroc/Tew. Soc. 125. 1499(1978).
17] T. 1. Kamins. "Resistivity of LPCVD Polycrystalline-Silicon Films," J. Electrochem. Soc, 126, 833
(1979).
18] M. M. Mandurah, K. C. Saraswat, and T. 1. Kamins, "Phosphorus Doping of Low Pressure Chemi-
cally Vapor-Deposited Silicon Films," J. Electrochem. Soc, 126, 1019 (1979).
19] M. M. Mandurah, K. C. Saraswat, C. R. Helms, and T. I. Kamins, "Dopant Segregation in Polycrys-
talline Silicon," J. Appl. Phys.. 51 , 5755 ( 1980).
20] T. I. Kamins, J. Manoliu, and R. N. Tucker, "Diffusion of Impurities in Polycrystalline Silicon," J.
Appl. Phys.. 43.^3 (1912).
21] D. J. Coe, "The Lateral Diffusion of Boron in Polycrystalline Silicon and its Influence on the Fabrica-
tion of Sub-Micron MOSTS," Solid State Electron., 20, 985 (1977).
22] T. 1. Kamins, "Hall Mobility in Chemically Deposited Polycrystalline Silicon," J. Appl. Phys., 42,
4357(1971).
23] S. Horiuchi, "Electrical Characteristics of Boron Diffused Polycrystalline Silicon Layers," Solid State
Electron., 18,659(1975).
24] G. Yaron, "Characterization of Phosphorus Implanted Low Pressure Chemical Vapor Deposited
Polycrystalline Silicon," Solid State Electron., 22, 1017 (1979).
25] M. Kuisl and W. Langheinrich, "Preparation and Properties of Phosphorus-Doped Polycrystalline Sil-
icon Films," in J. M. Blocher, Jr., H. E. Hintermann, and L. H. Hall, Eds., Chemical Vapor
Deposition —Fifth International Conference, Electrochemical Society. Princeton, N.J., 1975, pp.
380-389.
26] T. I. Kamins. "Oxidation of Phosphorus-Doped Low Pressure and Atmospheric Pressure CVD
Polycrystalline-Silicon Films." J. Electrochem. Soc, 126. 838 ( 1979).
27] B. G. Bagley, D. E. Aspnes, A. C. Adams, and C. J. Mogab, "Optical Prop)erties of Low-Pressure
Chemically Vapor Deposited Silicon Over the Energy Range 3.0-6.0 eV," Appl. Phys. Lett., 38, 56
(1981).
28] Ch. Kuhl, H. Schlotterer, and F. Schwidefsky, "Optical Investigation of Different Silicon Films," J.
Electrochem. Soc. 121, 1496(1974).
29] M. Hirose, M. Taniguchi, and Y. Osaka, "Electronic Properties of Chemically Deposited Polycrystal-
line Silicon," 7. Appl. Phys., 50, 377 (1979).
30] W. Kern and R. S. Rosier, "Advances in Deposition Processes for Passivation Films," J. Vac Sci.
Technol., 14, 1082(1977).
31] R. E. Logar, M. T. Wauk, and R. S. Rosier, "Low Pressure Deposition of Phosphorus-Doped Silicon
Dioxide at 400°C in a Hot Wall Furnace," in L. F. Donaghey. P. Rai-Choudhury, and R. N. Tauber,
Eds., Chemical Vapor Deposition—Sixth International Conference, Electrochemical Society, Prince-
ton, N.J. , 1977, pp. 195-202.
32] H. Huppertz and W. L. Engl, "Modeling of Low-Pressure Deposition of SIOt by Decomposition of
TEOS," IEEE Trans. Electron Devices, ED-26, 658 ( 1979).
33] A. C. Adams and C. D. Capio, "The Deposition of Silicon Dioxide Films at Reduced Pressure," J.
Electrochem. Soc, 126, 1042(1979).
34] K. Watanabe, T. Tanigaki, and S. Wakayama, "The Properties of LPCVD SiOj Film Deposited by
SiH^Cl, and N^O Mixtures," J. Electrochem. Soc, 128, 2630 (1981).
35] M. Maeda and H. Nakamura, "Deposition Kinetics of Si02 Film," J. Appl. Phys., 52, 6651 (1981).

128 VLSI Technology
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[38] A. C. Adams and C. D. Capio. "Planarization of Phosphorus-Doped Silicon Dioxide," J. Electro-
chem. Soc, 128,423(1981).
[39] W. A. Pliskin, "Comparison of Properties of Dielectric Films Deposited by Various Methods." J.
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[41] K. Chow and L. G. Garrison, "Phosphorus Concentration of Chemical Vapor Deposited Phosphosili-
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[47] J. R. Hollahan and R. S. Rosier, "Plasma Deposition of Inorganic Thin Films," in J. L. Vossen and
W. Kern, Eds., Thin Film Processes. Academic, New York, 1978, pp. 335-360.
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[49] H. Dun, P. Pan, F. R. White, and R. W. Douse, "Mechanisms of Plasma-Enhanced Silicon Nitride
Deposition Using SiH4/N2 Mixture," J. Electrochem. Soc, 128, 1555 (1981).
[50] A. C. Adams, F. B. Alexander, C. D. Capio, andT. E. Smith, "Characterization of Plasma-Deposited
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[53] M. J. Rand and J. F. Roberts, "Silicon Oxynitride Films from the NO—NH3 —SiHj Reaction," J.
Electrochem . 5oc. , 1 20, 446 ( 1 973)
.
[54] A. K. Gaind and E. W. Heam, "Physiochemical Properties of Chemical Vapor-Deposited Silicon
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PROBLEMS
1 Find the empirical formula for plasma silicon nitride containing 25 at. % H and having a Si/N ratio of 1 . 1
.
Find the empirical formula for LPCVD silicon nitride containing 5 at. % H and having a Si/N ratio of 0.75.
2 If plasma-deposited Si02 contains 3 x 10^' H/cm^, find the at. % H and the empirical formula.
3 If the average chlorine concentration within the first 1000 A of a deposited Si02 is 1 x lO'^ Cl/cm^, what
is the at. % CI in this region?
4 Derive the relationship between wt. % B, at. % B, and mol % B2O3 for boron-doped Si02.
5 A polysilicon deposition uses 30 % silane in nitrogen at 625°C and 53.3 Pa (0.4 Torr). The total gas flow
is 500 std. cm^/min. The volume of the LPCVD reactor is 20 L, its length is 150 cm, and a cross-sectional

Dielectric and Polysiucon Film Deposition 129
area between the wafers and the walls is 45 cm-. What is the partial pressure of the silane, and the linear
velocity and residence time of the gas?
6 If the reactor in problem 5 has an effective area of 4000 cm- and 100 wafers have a total area of 15,000
cm'^, how much silane is required to deposit 0.5 ixm of polysilicon if the reaction efficiency is 20%?
7 Consider Si02 deposited at 100 AVmin at 450°C with an activation energy of 10 kcal/mole. How much
must the temperaUire be increased to double the rate? Repeat the calculation for a deposition at 700°C and
an activation energy of 45 kcal/mole.
8 Sketch the step coverage expected for a conformal coating over a window 1 [im deep and 2 (jim wide.
Use fihn thicknesses of 0.5, 1 .0, 1 .5, and 2.0 iJim. Repeat the calculation for a deposition with no surface
migration, such as plasma oxide.

CHAPTER
FOUR
OXIDATION
L. E. KATZ
4.1 INTRODUCTION
The oxidation of silicon is necessary during the entire process of fabricating modem
integrated circuits. The production of high-quality ICs requires not only an under-
standing of the basic oxidation mechanism, but the ability to form, in a controlled and
repeatable manner, a high-quality oxide. In addition, to ensure the reliability of the
ICs, the electrical properties of the oxide must be understood.
Silicon dioxide has several uses: to serve as a mask against implant or diffusion
of dopant into silicon, to provide surface passivation, to isolate one device from
another (dielectric isolation as opposed to junction isolation), to act as a component in
MOS structures, and to provide electrical isolation of multilevel metallization sys-
tems. Several techniques for forming the oxide layers have been developed such as
thermal oxidation, wet anodization, vapor phase technique Ichemical vapor deposi-
tion (CVD)l, and plasma anodization or oxidation. When the interface between the
oxide and the silicon is required to have a low charge density level, thermal oxidation
has been the preferred technique. However, since the masking oxide is generally
removed, this consideration is not as important in the case of masking against diffu-
sion of dopant into silicon. Obviously when the oxide layer is required on top of a
metal layer, as in the case of a multilevel metallization structure, the vapor phase
technique is uniquely suited. This chapter concentrates on thermal silicon oxidation,
because it is the principal technique used in IC processing.
In this chapter we describe the oxidation process to provide a foundation for
understanding the kinetics of growth and interface properties. Section 4.2 examines
the oxidation model and its fit to experimental data; the effect of orientation, dopant
concentration, and HCl addition to the ambient; and surface damage on the kinetics of
131

132 VLSI Technology
oxidation. Section 4.3 describes standard thermal oxidation techniques, such as dry,
wet, and HCl dry as well as the less familiar high-pressure and plasma oxidation tech-
niques. It also describes the cleaning processes needed to remove surface contamina-
tion prior to oxidation. Section 4.4 covers the characteristics and properties of
oxides, with emphasis on oxide masking, oxide charges, and stresses in thermal
oxides. Sections 4.5 and 4.6 examine the redistribution of dopants at the Si-Si02
interface during thermal oxidation and during oxidation of polysilicon, respectively.
Section 4.7 considers oxidation-induced stacking faults and oxide isolation defects. A
summary and a discussion of the future trends are presented in the last section.
4.2 GROWTH MECHANISM AND KINETICS
Since a silicon surface has a high affinity for oxygen, an oxide layer rapidly forms
when it is exposed to an oxidizing ambient. The chemical reactions describing the
thermal oxidation of silicon' in oxygen or water vapor are given in Eqs. 1 and 2,
respectively.
Si(solid) + 0.
Si(solid) + 2H2O
Si02(solid)
Si02(solid) + 2H2
(1)
(2)
The basic process involves shared valence electrons between silicon and oxygen; the
silicon-oxygen bond structure is covalent. During the course of the oxidation process
the Si-Si02 interface moves into the silicon; however, the volume expands, resulting
in the external Si02 surface not being coplanar with the original silicon surface.
Based on the densities and molecular weights of Si and Si02, we can show that for
growth of an oxide of thickness d, a layer of silicon 0.44<af thick is consumed (Fig. 1).
The framework of a model to describe silicon oxidation has been created.
Radioactive tracer,' marker,^ and infared isotope shift^ experiments have established
that oxidation proceeds by the diffusion of the oxidizing species through the oxide to
the Si-Si02 interface, where the oxidation reaction occurs. Uncertainties exist, how-
ever, as evidenced by controversies in the literature as to whether charged or neutral
Si02<
Si02 SURFACE
ORIGINALS! INTERFACE
SILICON SUBSTRATE
Fig. 1 Growth of SiOj.

Oxidation 133
species are transported through the oxide, and on the details of the reaction at the Si-
SiO-. interface.
4.2.1 Silicon Oxidation Model
Deal and Grove's model describes the kinetics of silicon oxidation.'^ It is generally
valid for temperatures between 700 and 1300°C, partial pressures between 0.2 and 1 .0
atm (perhaps higher), and oxide thicknesses between 300 and 20,000 A for oxygen
and water ambients. Figure 2 shows the silicon substrate covered by an oxide layer
that is in contact with the gas phase. The oxidizing species (1) are transported from
the bulk of the gas phase to the gas-oxide interface with flux F i
(the flux is the
number of atoms or molecules crossing a unit area in a unit time), (2) are transported
across the existing oxide toward the silicon with flux Fj, and (3) react at the Si-Si02
interface with the silicon with flux F3.
For steady state, F
= F2 = Ft,- The gas-phase flux Fj can be linearly approxi-
mated by assuming that the flux of oxidant from the bulk of the gas phase to the gas-
oxide interface is proportional to the difference between the oxidant concentration in
the bulk of the gas Cq and the oxidant concentration adjacent to the oxide surface C5
.
F ,
= hciCc - Cs) (3)
where h(j is the gas-phase mass-transfer coefficient.
To relate the equilibrium oxidizing species concentration in the oxide to that in
the gas phase, we invoke Henry's law.
Co = Hps (4)
GAS
Ce-^-
SILICON
Fig. 2 Basic model for thermal oxidation of silicon. (After Deal arid Grove, Ref. 4.)

134 VLSI Technology
and
C* = Hpc (5)
where Co is the equiUbrium concentration in the oxide at the outer surface, C* is the
equihbrium bulk concentration in the oxide, p^ is the partial pressure in the gas adja-
cent to the oxide surface, pc is the partial pressure in the bulk of the gas, and H is
Henry's law constant. Using Henry's law along with the ideal gas law ^ allows us to
rewrite Cq and Cc
Cg = -r^ (6a)
kT
Ps_
kT
Ps
Cs = ^ (6b)
Combining Eqs. 3 to 6 gives
F, - h{C* - Co) (7)
where h is the gas-phase mass-transfer coefficient in terms of concentration in the
solid, given by h = Hq / HkT. When the concentration of the oxidant in the oxide at
the oxide-gas interface Co is less than the equilibrium bulk oxide concentration, F is
positive. Oxidation is a nonequilibrium process with the driving force being the devi-
ation of concentration from equilibrium.^ Henry's law is valid only in the absence of
dissociation effects at the gas-oxide interface. This implication is that the species
moving through the oxide is molecular.
The flux of this oxidizing species across the oxide is taken to follow Pick's law
^2= -D ^ (8)
da
at any point d in the oxide layer. D is the diffusion coefficient and dC / dd is the con-
centration gradient of the oxidizing species in the oxide. Following the steady-state
assumption, F2 must be the same at any point within the oxide (i.e., dFj/dd =0)
resulting in
^(Co - Q)
F2 = -^-^, (9)
do
where C, is the oxidizing species concentration in the oxide adjacent to the oxide-
silicon interface and do is the oxide thickness.
Assuming that the flux corresponding to the Si-Si02 interface reaction is propor-
tional to C,
F3 = k,Ci (10)
where k^ is the rate constant of chemical surface reaction for silicon oxidation.
After setting F] = Fj = Ft,, as dictated by steady-state conditions, and solving
simultaneous equations, we obtain the following expressions for C, and Co:

Oxidation 135
C, =
1 +
C
+
D
(11)
Cn =
1 +
Kdj
D
C
1 + — + -^-^
h D
(12)
The limiting cases of Eqs. 1 1 and 12 arise when the diffusivity is either very small or
very large. When the diffusivity is very small, C, —> and Cq—^C*. This case is
called the diffusion-controlled case. It results from the flux of oxidant through the
oxide being small (due to D being small) compared to the flux corresponding to the
Si-Si02 interface reaction. Hence the oxidation rate depends on the supply of oxidant
to the interface, as opposed to the reaction at the interface.
In the second limiting case, where D is large, C, = Cq — C*/(+kJh). This is
called the reaction-controlled case, because an abundant supply of oxidant is provided
at the Si-Si02 interface, and the oxidation rate is controlled by the reaction rate con-
stant k^ and by C, (which equals Cq).
To calculate the rate of oxide growth, we define N i
as the number of oxidant
molecules incorporated into a unit volume of the oxide layer. Since the oxide has 2.2
X 10~^ Si02 molecules /cm-^ and one Ot molecule is incorporated into each Si02
molecule, whereas two H2O molecules are incorporated into each Si02 molecule, A^i
equals 2.2 x 10~- cm~^ for dry oxygen and twice this number for water-vapor oxida-
tion. Combining Eqs. 10 and 1 1 along with the definition of flux, the flux of oxidant
reaching the oxide-silicon interface is given by
ddn k. C
(13)
A^,
dt
= F,=
1 + +
D
We solve this differential equation assuming that an oxide may initially be present
from a previous processing step or it may grow before the assumptions in the model
are valid, that is, do = dj at r = 0. The solution of Eq. 13 is
di + Ado = B(t + t)
where
A = 2D
L h
B = IDC
(14)
(14a)
(14b)
T =
dr + Adi
B
(14c)

136 VLSI Technology
The quantity t represents a shift in the time coordinate to account for the presence of
the initial oxide layer dj . Equation 14 is the well-known, mixed linear-parabolic rela-
tionship.^
Solving Eq. 14 for do as a function of time gives
A II
1 +
t + T
A2/4B
1/2
- 1
One limiting case occurs for long oxidation times when t >> t.
dl = Bt
(15)
(16)
Equation 16 is the parabolic law, where B is the parabolic rate constant. The other
limiting case occurs for short oxidation times when (r + t) << A '^/4B.
do = j(t + T)
Equation 17 is the linear law, where 5 /A is the linear rate constant given by
Lh C
yv,
(17)
(18)
k, + h
Equations 16 and 17 are the diffusion-controlled and reaction-controlled cases,
respectively.
TEMPERATURE (""O
o o o o o
o o Q o o
cj ^ o a> 00
o So
1 I I I I I
WET O2 DATA CORRECTED
TO 760 Torr HgO
NX, EA=0.71eV
0.7 0.8 0.9 1.0 1.1
1000/T(K-I)
(a)
Fig. 3(a) The effect of tempierature on the parabohc rate constant for dry and wet oxygen.

Oxidation 137
4.2.2 Experimental Fit
This section compares Deal and Grove's model to their experimental measurements.
Deal and Grove used (111) oriented, lightly boron-doped silicon wafers, that were
cleaned prior to oxidation in purified dry oxygen (less than 5-ppm water content) or in
wet oxygen (the partial pressure of water was 640 Torr). For wet oxygen oxidation
they found that d, = at r = by plotting oxide thickness versus oxidation time.
Algebraically manipulating Eq. 14 and using the plot of wet oxygen data, they graphi-
cally obtained the rate constants. Table 1 lists the values of these rate constants for
wet oxidation of silicon."* The absolute value of A increases with decreasing tempera-
ture, while the parabolic rate constant B decreases with decreasing temperature (Figs.
3a andb).
For dry O2 a plot of oxide thickness versus oxidation time does not extrapolate to
zero initial thickness, but instead to a value which equals about 250 A for data span-
ning a range of 700 to 1200°C. The faster initial oxidation rate during the initial
phase of oxidation implies a different mechanism in this region. Thus use of Eq. 14
for dry oxidation requires a value for t that can be generated graphically by extrapo-
lating the linear region back to the time axis. Problems arise at higher temperatures
where the linear-parabolic or parabolic ranges are encountered, in which case the
TEMPERATURE (°C)
10 =
IQl -^
E
m
10-1-
z
o
uj 10-2
H
<
tr
q:
< 10-5 _
10 -4 _
10-
-1 1 1 III 1 T^
^ WET O2 DATA CORRECTED
—
r- '
TO 760 Torr HgO —
^
-
V WET O2 (640 Torr)
-
: ^^/'95''C H2O _
- V^^ EA=1.96eV
V
—
V "^
-
-
— *s
V —
X
A.
r DRY 02^ —
" (760 Torr) ~
~ E/^ = 2 0eV V
V —
- -
- ^
1 1 1 1 1 1
0.7 0.8 0.9 1.0 1.1
1000/T(K-M
(b)
1.2
Fig. 3((b) The effect of temperature on the linear rate constant. (After Deal and Grove, Ref. 4.)

138 VLSI Technology
Table 1 Rate constants for wet oxidation of silicon
Parabolic rate Linear rate
Oxidation constant constant
temperature {°C) /(fxm) B((a,m-/h) BM(|jLnVh) T(h)
1200 0.05 0.720 14.40
1100 0.11 0.510 4.64
1000 0.226 0.287 1.27
920 0.50 0.203 0.406
value of T as defined in Eq. 14 must be used. Table 2 lists the values of rate constants
for dry oxidation of silicon."^
Examination of Eq. 14b reveals that B is expected to be proportional to C*,
which, according to Henry's law, is proportional to the partial pressure of the oxidiz-
ing species. However, A should be independent of the partial pressure. This has
indeed been confirmed experimentally for both wet and dry oxidations'* ^ in the tem-
perature range between 1000 and 1200°C and between 0.1 and 1 atm. The pressure
independence of A means that the linear rate constant B/A has the same linear pres-
sure dependence as B.
Figure 3a shows the effect of temperature** on the parabolic rate constant B for
both dry and wet oxygen at 640 Torr and for wet oxygen normalized to 760 Torr using
the linear pressure dependence. As might be expected from Eq. 14, the temperature
dependence of B is similar to that of D, that is, B increases exponentially with tem-
perature. For dry oxygen the activation energy for B is 1 .24 eV, which is comparable
to the value of 1.17 eV for the diffusivity of oxygen through fused silica (similar in
structure to thermal Si02). The wet oxygen activation energy (0.71 eV) also com-
pares favorably with the activation energy for the diffusivity of water in fused silicon
(0.80 eV).
Figure 3b shows the temperature dependence of the linear rate constant B/A for
both dry and wet oxygen at 640 Torr and for wet oxygen normalized to 760 Torr.
Once again an exponential dependence is observed with activation energies 1 .96 and
2.0 eV for wet and dry oxidation, respectively. Deal and Grove'* show that these
Table 2 Rate constants for dry oxidation of silicon
Oxidation constant constant
temperature (°C) A f|jLm) B(|jLm-/h) fi//((x/h) T(h)
1200 0.040 0.045 1.12 0.027
1100 0.090 0.027 0.30 0.076
1000 0.165 0.0117 0.071 0.37
920 0.235 0.0049 0.0208 1.40
800 0.370 0.0011 0.0030 9.0
700 0.00026 81.0

Oxidation 139
Table 3 C* values In SiOj at 1000°C
Species C* (cm ^)
O2 5.2 X 10'6
H^O 3.0 X 10'^
values reflect the temperature dependence of the interface reaction-rate constant k^
.
As stated previously, in the linear range the reaction is reaction controlled. Similar
values were obtained for the linear rate constants for both dry and wet oxidations,
indicating a similar reaction or surface control mechanism. Interestingly, the above
values are comparable to the 1 .83 eV required to break a Si —Si bond.
The equilibrium concentration C '^
of the oxidizing species in SiOo can be calcu-
lated from Eq. 14b by using appropriate values for B. D, and N i. Table 3 gives an
example."*
Even though the diffusivity of water in Si02 is lower than that of oxygen,^ the
parabolic rate constant B is substantially larger for wet oxidation than for dry. This is
the major reason why the parabolic oxidation rate in steam is faster than in dry oxygen;
the flux of oxidant, and hence B, is proportional to C*, which is approximately three
orders of magnitude greater for water than for oxygen (see Table 3). Furthermore,
since the linear rate constant B /A also is related to B and hence C*, we can also attri-
bute the faster linear oxidation rate for wet oxidation to the above mechanism.
Deal and Grove's simple model (Eqs. 14 and 15) for thermal silicon oxidation
provides excellent agreement with various normalized experimental data"* for both wet
and dry oxidations. The only exception is for Si02 films less than about 300 A thick
grown in dry oxygen. In this case an anomalously high oxidation rate is observed
with respect to the model.
4.2.3 Diffusing Species and Interface Considerations
The excellent agreement between the model and experimental observations supports
the use of Henry's law. This implies the lack of dissociative effects at the gas-Si02
interface indicating the species diffusing in the oxide is molecular for both oxygen
(dry) and steam (water-vapor) oxidations. Additional results^ indicate that the oxidant
is molecular for both water and oxygen oxidations, since good agreement is obtained
between the calculated (for fused silica) and measured oxidation rates (for oxidation
of silicon) with respect to absolute rate and pressure, and with respect to temperature
dependence.
A proposed modification^*^ to the Deal-Grove model provides an excellent fit to
the experimental data, including the thin, dry oxidation regime where the Deal-Grove
model breaks down. The physical basis of the proposed model is that while diffusion
through the oxide is still by molecular oxygen, the oxidation of silicon occurs by the
reaction of a small concentration of atomic oxygen.
As stated earlier, the question of whether the oxidizing species is charged or neu-
tral is still a subject of controversy. While the above discussion favors diffusion of a

140 VLSI Technology
molecular species, supportive evidence" for a charged species arises from experiments
showing that an applied electric field can influence the oxidation rate, either
accelerating it or retarding it, depending on whether the silicon is positive or negative
with respect to the oxide-gas interface. Another work,
'
' based on studies of electrical
conduction at elevated temperatures, concludes that the species responsible for ionic
conduction is doubly negative interstitial oxygen ions (O/").
We now shift our discussion from the unresolved question of the nature of the dif-
fusant to the Si-Si02 interface. The structure and oxidation mechanism at the inter-
face is particularly important since what occurs here from an atomistic point of view
can influence not only the oxidation kinetics but also allied areas of interest, such as
diffusion. Both the interface structure and its oxidation mechanisms are complicated
and a continuing source of discussion in the literature.
The controversies as to whether charged or neutral species are transported
through the oxide have been reviewed'^'
^'^
followed by the proposal of a model that
appears consistent with much of the earlier data. The model is based on a large
molecular volume difference between Si and Si02. This difference must be accom-
modated to allow a newly formed Si02 molecule to fit into the normal Si02 structure.
This leads to the proposal of an interface transition region, which consists of a net-
work of extra half planes that terminate at the Si side of the Si-Si02 interface. Move-
ment of this interface requires a supply of vacancies from the silicon to the interface,
the movement of Si interstitials from the interface into the bulk Si, or free volume
influx from the Si02 (i.e., viscous flow).^-"'"^ An additional proposal'"* relating to the
interface suggests that silicon is transformed to a-cristobalite plus interstitial Si ions.
Subsequent oxidation of the interstitials produces lattice distortion and transformation
to vitrous silica. Hence the crystalline Si02 phase exists only as a buffer between the
Si and vitrous Si02. The proposed interface mechanisms are consistent with qualita-
tive explanations related to oxidation-enhanced diffusion, stacking fault formation,
interface charge, and oxidation velocity.
Additional mechanisms have been proposed, which attempt to explain point-
defect-related interface phenomena. The presence of doubly negative interstitial oxy-
gen ions (0/~~) was discussed previously. Such ions at the Si-Si02 interface may
react with silicon and displace it to an interstitial position in the lattice to form
Si/ —O, which can combine to form Si02. A silicon interstitial flux can occur if the
Si/ —O pair dissociates before forming Si02.'"^ Such an incomplete oxidation occurs
for one out of every thousand silicon atoms. '^ Although the interface reaction gen-
erally goes to completion, even a small flux of silicon interstitials into the silicon can
have a large effect on defect formation or diffusion. The case of 0^~ reacting with
vacancies, as supplied from the silicon substrate, could lead to a vacancy flux. Such
a process may be significant in the case of heavy doping.
4.2.4 Thin Oxide Growth
As noted earlier, the structure of the oxide very close to the silicon-oxide interface
and the oxidation process itself both involve uncertainties. Our understanding is
further complicated by the observation of an initial rapid oxidation for the case of dry

Oxidation 141
oxide growth, which causes the linear portion of the oxide growth versus time curve
to extrapolate to an initial thickness of about 200 A.
With advanced MOS structures the ability to grow, with reproducible results, thin
^300-A. uniform, high-quality gate oxides has become increasingly important. In
another application, thin pad oxides of thicknesses between 50 and 1000 A have been
used routinely under masking nitride layers to prevent stress-induced defects in the
underlying silicon. The discussion in this section concentrates on the techniques and
properties of thin oxides.
The technology for thin oxide growth is still emerging with a variety of tech-
niques being used. Aside from the kinetics of oxide growth, other properties studied
typically include refractive index, oxide composition, etch rate, density, susceptibil-
ity to pinholes, stress, and dielectric breakdown.
From a practical point of view, thin oxide growth must be slow enough to obtain
uniformity and reproducibility. Various growth techniques include dry oxidation, dry
oxidation with HCl, sequential oxidations using different temperatures and ambients,
wet oxidation, reduced pressure techniques, and even high-pressure, low-temperature
oxidations. The oxidation rate will, of course, be lower at lower temperatures and
reduced pressures. Ultrathin oxides (<50 A) have been produced using hot nitric
acid, boiling water, and air at room temperature. For whatever technique is chosen,
the desired properties must be obtained.
In discussing the techniques used and properties obtained it should be emphasized
that thin oxide growth is influenced by the cleaning techniques used' ''
and the purity
of the gases used (especially moisture content). Figure 4 shows an example of thin
oxide growth versus oxidation time in dry oxygen.'^ This data demonstrates that a set
180
160 _ •
• 980" C •
140 - • •
,_^ • •
"5 120 - •
•
V)
V)
^ 100
•
-•
• • 89300
^ 80
O
•
••
40
20,
1 1 1 1 1 1
20 40 60 80 100
OXIDATION TIME (min)
120
Fig. 4 Oxide thickness versus oxidation time at 780, 893. and 980°C in dry oxygen. (After Irene, Ref. 18.)

142 VLSI Technology
of time-temperature conditions can be chosen to grow thin oxides compatible with
reasonable throughput.
Processing conditions have an important impact on oxide properties. For exam-
ple, oxide density increases as the oxidation temperature is reduced.'^ Additionally,
HCl ambients have typically been used to passivate ionic sodium, improve the break-
down voltage, and getter impurities and defects in the silicon. This passivation effect
only begins to occur in the higher temperature range. A two-step process sequence
has been devised^*^ in which a uniform, reproducible oxide of small defect density is
formed at a moderate temperature (10(X)°C or less) using a dry O2, HCl ambient. The
second step consists of a heat treatment in N2, O2, and HCl at 1 150°C to provide pas-
sivation and to bring the oxide thickness to the desired level. Such a processing
scheme takes advantage of beneficial effects occurring in both the lower and higher
temperature ranges.
Reduced pressure oxidation offers an attractive way of growing thin oxides in a
controlled manner. Oxides between 30 and 140 A thick have been grown in a CVD
reactor at 900 to 1000°C using oxygen at a pressure of 0.25 to 2.0 Torr.^^ The
observed kinetics are parabolic, and the rate constants agree with values extrapolated
from atmospheric pressure. Oxides obtained by this technique etch at the same rate as
dry oxides obtained at 950°C and 1 atm. The equal etch rate indicates a similar oxide
composition and structure between the two oxides. The intrinsic breakdown fields are
high (10 to 13 MV/cm) and distributed over a narrow range. All indications are that
the reduced pressure oxides are very uniform, homogeneous, and similar to thicker
oxides prepared at atmospheric pressure.
As a final example of thin oxide growth, we consider the use of high-pressure,
low-temperature steam oxidation of silicon. At 10-atm pressure and 750°C, a 300-A-
thick oxide can be grown in 30 min. Obviously the time, temperature, and pressure
can be changed to vary the thickness. Such a technique has been applied to the
growth of a thin gate oxide in the process to fabricate MOS dynamic RAMs.^^ At the
same time the thin oxide layer was grown, a thick oxide layer was grown over a
doped polysilicon layer as a result of concentration-enhanced oxidation. The proper-
ties of the oxides depended on the oxidation temperature rather than pressure. For
example, oxide density and refractive index decreased whereas chemcial etch rate and
residual stress increased with increasing temperature. The temperature and pressure
ranges were 700 to 1000°C and approximately 5 to 10 atm, respectively.
4.2.5 Orientation Dependence of Oxidation Rates
Experiments have indicated that the oxidation kinetics are a function of the crystal-
lographic orientation of the silicon surface. ^^ This relationship is attributed to the
orientation dependence of k^ (Eqs. 10 and 14a) and manifests itself in an orientation-
dependent linear rate constant. The linear rate constant is related to the interface
reaction kinetics and depends on the rate at which silicon atoms are incorporated into
the oxide. This depends on the silicon surface atom concentration, which is orienta-
tion dependent. As might be expected, the parabolic rate constant B is independent of
silicon surface orientation,^'^ since B is diffusion limited. Figure 5 shows"^^ oxide

Oxidation 143
2.00
1.00 -
eo.50
0.20
Q 0.10
X
o
0.05 -
0.02
llOO'C
1000°C
goo'c • (111) Si
O (100) Si
0.1 0.2 0.5 1.0 2.0
OXIDATION TIME (h)
5.0 10.0
F^. 5 Oxide thickness versus oxidation time for silicon in H2O at 640 Torr. (After Deal, Ref. 25.)
thickness as a function of oxidation time in water at 640 Torr for both (111) and (100)
oriented silicon. Table 4 gives rate constants obtained from this data.^^ This data
along with that for oxygen yields linear rate constants for (111) silicon that are 1.68
times those for (100) silicon at corresponding temperatures.
A model has been presented^^ to explain how the linear oxidation rate of the sili-
con depends on the orientation of the silicon surface. According to this model, a
direct reaction occurs between a water molecule in the silica and a silicon-silicon
bond at the Si-Si02 interface. At this interface all the silicon atoms are partially
Table 4 Rate constants for silicon oxidation in H2O (640 Torr)
Oxidation Orien- constant constant
temperature (°C) tation A(|jLm) B(x.vc?li) BIA (|j.m/h) fiM ratio (lll)/( 100)
900 (100) 0.95 0.143 0.150
(111) 0.60 0.151 0.252 1.68
950 (100) 0.74 0.231 0.311
(111) 0.44 0.231 0.524 1.68
1000 (100) 0.48 0.314 0.664
(111) 0.27 0.314 1.163 1.75
1050 (100) 0.295 0.413 1.400
(111) 0.18 0.415 2.307 1.65
1100 (100) 0.175 0.521 2.977
(111) 0.105 0.517 4.926
Average
1.65
1.68

144 VLSI Technology
Table 5 Calculated properties of silicon crystal planes
Area of Available
Orien- unit cell Si atoms Si bonds Bonds Bonds bonds, N(x N relative
tation (cm-) in area in area available X lO'^cm-2 10'4cm-2) to (110)
(110) V2~a- 4 8 4 19.18 9.59 1.000
(311) I/8V11 a- 1.5 3 2 24.54 16.36 1.707
(111) l/lVTa'- 2 4 3 15.68 11.76 1.227
(100) fl2 2 4 2 13.55 6.77 0.707
bonded to silicon atoms below and to oxygen atoms above. The orientation depen-
dence of the oxidation rate comes from terms representing the activation energy for
oxidation and the concentration of reaction sites. This concentration depends on the
concentration of silicon-silicon bonds available for reaction at a given time. The
bond is directional so its availability depends on its angle relative to the surface plane,
its position with respect to adjacent atoms, and the water molecule size being such
that when reacting with some angled silicon-silicon bonds, it can screen adjacent
bonds from other water molecules.^ These and other geometric effects are called
steric hindrances and result in the linear oxidation rate being orientation dependent.
Table 5 lists calculated properties of four silicon planes.^-' The orientation dependence
is related to the available bond density A^ and the orientation dependence of the activa-
tion energy.
As might be expected, steric hindrance results in higher activation energy.
Experimental data has been analyzed to determine the apparent activation energy,
which is the sum of two components: a term related to the enthalpy of solution of
water in the silica films and the orientation-dependent term related to the activation
energy of oxidation. Table 6 lists the values of some apparent activation energies.'^-'
The interaction between the available bond density and the activation energy deter-
mines the orientation dependence of the linear oxidation rates. Experiments"^ show
that the oxidation rate v in steam is ordered in the following manner
with a slower rate predicted for the (100) orientation. Additional measurements"'* in
steam show the following oxidation rate sequence
^'111 > ^'110 > ^'311 > "^'lOO
However, this set of measurements was made at a higher temperature than the former
set.^^
For dry oxidation a similar argument for steric hindrance can be made. The fol-
lowing sequence is experimentally obtained^^
vuo ^ ^'111 > ^'100
for the linear oxidation rate.

Oxidation 145
Table 6 Apparent activation energies
Orientation Activation energy (eVj
(110) 1.23 ±0.02
(311) 1.30 ±0.03
(111) 1.29 ±0.03
4.2.6 Effect of Impurities and Damage on the Oxidation Rate
Because wet oxidation occurs at a substantially greater rate than for dry oxidation,
any unintentional moisture accelerates the dry oxidation. In fact, both the linear and
parabolic oxidation rates are sensitive to the presence of water and other impurities.
The effects of some of these impurities are discussed in the following sections.
Water Experiments were done to study the effect of intentionally adding 15-ppm
water vapor to a process that normally used less than 1-ppm water. ~"^
A significant
acceleration in the oxidation rate was observed. For example, an 8(X)°C oxidation of
(100) silicon for 100 minutes grew an oxide approximately 300 A thick with less than
1-ppm moisture and an oxide approximately 370 A thick with 25-ppm moisture. In
these experiments the oxygen was from a liquid source and the oxidation chamber
was a double-wall, fused-silica tube with N2 flowing between the walls. A
precombustor and cold trap were used to achieve the less than 1-ppm moisture level.
Sodium High concentrations of sodium influence the oxidation rate by changing the
bond structure in the oxide, thereby enhancing the diffusion and concentration of the
oxygen molecules in the oxide.
^
Group III and V elements The common dopant elements in this group, when
present in silicon at high concentration levels, can enhance the oxidation behavior.
The dopant impurities are redistributed at the growing Si-Si02 interface."'' This effect
is discussed in greater detail in Section 4.5, but we consider it from a mechanism
standpoint here. The effect results in a discontinuous concentration profile at the
interface, that is, the dopant either segregates into the silicon or into the oxide. The
redistribution of the impurity at the interface influences the oxidation behavior. If the
dopant segregates into the oxide and remains there (which is the case for boron in an
oxidizing ambient), the bond structure in the silica weakens. This weakened structure
permits an increased incorporation and diffusivity of the oxidizing species through the
oxide, thus enhancing the oxidation rate. Impurities that segregate into the oxide but
then diffuse rapidly through it (such as aluminum, gallium, and indium) exhibit the
same oxidation kinetics as lightly doped silicon. Figure 6 shows oxidation rate curves
for various concentrations of boron for wet oxygen.^^ From the above discussion it is
not surprising that an enhancement in the oxidation kinetics is observed where diffu-
sion control predominates. For oxidation of phosphorous-doped silicon in wet oxy-
gen,"^ a concentration dependence is observed only at the lower temperatures where

146 VLSI Technology
Q 0.2
0.1
Cb= 2.5 X 1020cm-'
A Cb= 1 X 1020cm-'
• Cb= 10 X 10^^ cm-5
J I
0.1 0.2 0.4 0.6 0.8 1.0
OXIDATION TIME (h)
2.0 3.0
Fig. 6 Oxidation of boron-doped silicon in wet oxygen (95°C H^O) as a function of temperature and con-
centration . (After Deal and Sklar. Ref. 28 .
)
the surface reaction becomes important (Fig. 7). This dependence may be the resuU
of phosphorus being segregated into the sihcon. Figure 8 shows the oxidation rate
constants for dry oxygen as a function of phosphorus doping level.
-"^
Here B/A
increases substantially at high concentrations, thus reflecting the reaction-rate control,
whereas B is relatively independent of concentration, thus reflecting the diffusion-
limited control.
The oxidizing interface is a complicated and not fully understood region. Its high
concentration of dopant provides further complications. A theoretical model has been
developed"'^ to explain concentration enhancement. According to the model, the high
doping levels shift the position of the Fermi level, which results in enhanced vacancy
concentrations. These point defects may provide reaction sites for the chemical reac-
tion converting Si to Si02, thereby increasing the reaction rate.
0.1
0.1 0.2 0.4 0.6 0.8 1.0
OXIDATION TIME ( h)
2.0 3.0
Fig. 7 Oxidation of phosphorus-doped silicon in wet oxygen (95°C H2O) as a function of temperature and
concentration. (After Deal and Sklar, Ref. 28.)

Oxidation 147
10"
10-
10-
10-
B/A (^m/min)
(»)
10 17
I III J I I I J I I I
10' 1019
Co (cm-^)
I III
1020 1021
Fig. 8 Oxidation rate constants for dry oxygen as a function of phosphorus doping level at 900°C. (After
Hoetal..Ref.29.)
Figure 7 shows the large increase in oxidation thickness obtained for oxidation of
heavily doped phosphorus in wet oxygen at lower temperatures. A dramatic example
of this effect is seen in Fig. 9, which shows a bulk phosphorous-doped silicon wafer
(~7 X lO'^/cm^) after oxidation at 750°C in steam at 20-atm pressure to accelerate
the kinetics. The wafer was not preferentially etched. Phosphorus dopant variations
(striations), incorporated into the Czochralski crystal during solidification (see Sec-
tion 1.2), appear as color variations representing oxide thickness variations. These
striations clearly correspond to the concentration-enhanced oxidation of the more
heavily phosphorous-doped regions in the crystal.
Halogen Certain halogen species are intentionally introduced into the oxidation
ambient to improve both the oxide and the underlying silicon properties. Oxide
improvements include a reduction in sodium ion contamination, an increased dielec-
tric breakdown strength, and a reduced interface trap density. At or near the Si-Si02
interface, chlorine is instrumental in converting certain impurities in the silicon to
volatile chlorides, resulting in a gettering effect. A reduction in oxidation-induced
stacking faults is also observed. Chlorine is typically introduced into dry oxygen
ambients in the form of chlorine gas, anhydrous HCl, or trichlorethylene.
Experimental results^' for dry O2-HCI mixtures show that HCl additions
increase the oxidation rate. Typical HCl additions range from 1 to 5%. The parabolic
rate constant B increases linearly with HCl additions above 1%. At 1000 and 1 100°C
large increases in B are initially observed. The linear rate constant B/A shows an ini-
tial increase when 1% HCl is added, but no further increase with subsequent HCl
additions. The mechanisms associated with this enhanced growth rate are not fully
understood. However, the generation of water upon adding HCl to dry oxygen does
not account fully for the increased oxidation rate, since a similar increase occurs
when chlorine-'^ is added (even though no water is generated in that case).

148 VLSI Technology
Fig. 9 Concentration-enhanced oxidation, showing dopant variations in a heavily doped phosphorus sub-
strate.
For thermal oxidation of silicon in H2O, adding 5 volume % HCl decreases the
silicon oxidation rate by about 5%, apparently because of the reduced H2O vapor pres-
sure. ^^
Although it is not common practice to add HCl to H2O ambients, such addition
appears to reduce impurity contamination from the oxidation system.
Thermal oxidation of silicon at 1100°C with additions of up to 1% tri-
chlorethylene (TCE) yield oxidation rates comparable to similar concentrations of
chlorine. At lower tem-peratures the values for O2/TCE are larger. The mechanisms
involved are complicated and not fully understood.
Finally, a word of caution. Care must be taken in handling and using the halo-
gens mentioned since the system's metallic parts and exhaust can corrode. Addition-
ally, high concentrations of halogens at high temperatures can pit the silicon surface.
Effect of damage on oxidation rate Determining how damage to the silicon affects
the oxidation rate is not easy. To study these effects, the silicon is usually intention-
ally damaged by ion implantation of a nonelectrically active species (Si or A), or of a
group III or V dopant. Separating damage effects from dopant effects is difficult.
Enhanced thermal oxidation of implanted silicon as a function of ion species and
concentration has been studied.-^- Implanted into (100) silicon were 80-keV arsenic,
60-keV boron, 106-keV antimony, and 48-keV argon with ion doses ranging from
4 X lO''* to 1 X 10'^ cm"^. For wet oxidation at 900°C the maximum enhancement of
the oxidation rate was a factor of 1 . 1 for boron, 1 .3 for argon, 3.5 for antimony, and
7.5 for arsenic. The higher enhancements occurred for the higher doses. The

Oxidation 149
enhancement for argon is attributed to the damage effect; for the other cases the pres-
ence of the impurity atoms certainly contributes to the enhancement. Another study^^
found a retardation effect for oxidation, following implantation of Ge, Si, and Ga into
silicon. It also found an enhancement for B, Al, P, As, and Sb.
4.3 OXIDATION TECHNIQUES AND SYSTEMS
The oxidation technique chosen depends upon the thickness and oxide properties
required. Oxides that are relatively thin and those that require low charge at the inter-
face are typically grown in dry oxygen. When sodium ion contamination is of con-
cern. HCI-O2 is the preferred technique. Where thick oxides (i.e.. >0.5 xm) are
desired steam is used (~1 atm or an elevated presure of up to 25 atm). Higher pres-
sure allows thick oxide growth to be achieved at moderate temperatures in reasonable
amounts of time.
One-atmosphere oxide growth, the most commonly used technique, is carried out
in a quartz or silicon diffusion tube with the silicon wafers held vertically in a slotted
paddle (boat) made of quartz or silicon. Typical oxidation temperatures range from
800 to 1200°C and should be held to within ± TC to ensure uniformity. In a standard
procedure the wafers ai-e cleaned, dried, placed on the paddle, and automatically
inserted into an 800 to 900°C furnace, which is then ramped up to temperature.
Ramping is used to prevent wafer warpage. Following oxidation, the furnace is
ramped down and the wafers are removed.
Eliminating particles during oxidation is necessary to grow high-quality, reprodu-
cible oxides. In earlier procedures the paddle rested directly on the tube during inser-
tion and withdrawal or an integrated roller paddle design was used. In either case
particulates were generated. Innovative designs now use a cantilevered arrangement;
the paddle is inserted into the oxidation tube in a contactless manner and then lowered
onto the tube. It is removed by reversing the steps.
4.3.1 Preoxidation Cleaning
Before placing wafers in a high-temperature furnace they must be cleaned to elim-
inate both organic and inorganic contamination arising from previous processing steps
and handling. Such contamination, if not removed, can degrade the electrical charac-
teristics of the devices as well as contribute to reliability problems.
Particulate matter is removed by either mechanical or ultrasonic scrubbing.
Immersion processing techniques were the preferred chemical cleaning methods, until
the development of centrifugal spray methods which eliminate the build up of con-
taminants as cleaning progresses. The chemical cleaning procedure usually involves
removing the organic contamination, followed by inorganic ion and atom removal.
A common cleaning procedure-^"* uses a H2O-H2O2-NH4OH mixture to remove
organic contamination by the solvating action of the ammonium hydroxide and the
oxidizing effect of the peroxide. This process can also complex some group I and II
metals. To remove heavy metals a H2O-H2O2-HCI solution is commonly used.

150 VLSI Technology
This solution prevents replating by forming soluble complexes with the removed ions
and is performed between 75 and 85°C for 10 to 20 minutes, followed by a quench,
rinse, and spin dry.^^"*
Many "optimum'' cleaning procedures have evolved over the years. Reference
35 reviews the necessary considerations for optimizing the cleaning procedure for sili-
con wafers prior to high-temperature operations.
Modem diffusion (oxidation) furnaces are microprocessor controlled to provide
repeatable sequencing, temperature control, and gas flow (mass flow control). The
entire procedure previously described, from boat loading to boat withdrawal, is pro-
grammed. The microprocessor control provides a feedback loop for comparing the
various parameters to the desired ones and for making the appropriate changes. For
example, the actual temperature of operation may change when the gas flow is
changed. Direct digital control compares this temperature to the programmed tem-
perature and automatically makes any necessary power changes.
-^^
4.3.2 Dry, Wet, HCl Dry Oxidation
Dry oxidation or HCl dry oxidation is straightforward using microprocessor-
controlled equipment. The desired insertion and withdrawal rates, ramp rates, gas
flows, and temperatures are all programmable. Care must be taken in handling HCl
especially with the exhaust because HCl corrodes metal parts. Also remember that
trace amounts of water vapor can drastically effect the oxidation rate.
Wet oxidation can be conveniently carried out by the pyrogenic technique, which
reacts H2 and O2 from water vapor. The microprocessor controls the H2/O2 mixture.
The pyrogenic technique assures high-purity steam, provided high-purity gases are
used. If wet oxidation by the bubbler technique is used, a carrier gas is typically
flowed through a water bubbler maintained at 95°C. This temperature corresponds to
a vapor pressure of approximately 640 Torr.
4.3.3 High Pressure
As we saw in Eq. 14b, the parabolic rate constant B is directly proportional to C , the
equilibrium bulk concentration in the oxide, which in turn is proportional to the par-
tial pressure of the oxidizing species in the gas phase. Oxidation in high-pressure
steam produces a substantial acceleration in the growth rate.
High-pressure oxidation of silicon is particularly attractive, because thermal oxide
layers can grow at relatively low temperatures in run times comparable to typical
high-temperature, 1-atm conditions. The movement of previously diffused impurities
can be minimized. Low-temperature operating conditions also minimize lateral diffu-
sion, which is of great importance as device dimensions get smaller. Another advan-
tage is that oxidation-induced defects are suppressed (see Section 4.7). For higher-
temperature, high-pressure oxidations, the oxidation time is reduced significantly.
High-pressure oxidation has been under investigation since the early 1960s.
^-^'^^
Both experimental and production equipment are now available, along with device
applications. For example, a high-speed, high-density, oxide-isolated bipolar pro-

Oxidation 151
5.0
PYROGENIC STEAM
aoo-c
0.5 1.0 2.0 5.0
OXIDATION TIME (h)
20.0
Fig. 10 Oxidation thickness versus oxidation time for pyrogenic steam at 900°C for (1(X)) and (111) silicon
and pressures up to 20 atm. (After Razouk. Lie. and Deal. Ref. 40.)
cess^^ has been described. In the MOS arena application has been successfully made
to the growth of a thick-field oxide layer in a dynamic RAM.-^^ The high-pressure
technique is very promising and is beginning to be used more extensively.
Figure 10 shows oxide thickness versus time data'^^ for steam oxidation at various
pressures and 900°C. The substantial acceleration in the oxidation rate caused by the
increased pressure is apparent. In analyzing the kinetics of oxidation at elevated pres-
sure, several complications arise such as: continuous variations in pressure during
pressurization, slightly variable pressurization times, small temperature variations
that occur during pressurization and during the early part of the oxidation at full pres-
sure, varying partial pressure of steam during depressurization, and thickness varia-
tions from run to run and across a wafer. A linear-parabolic model was used to
analyze the data shown in Figure 10. A linear pressure dependence^ was observed
for both the linear and parabolic rate constants. Figure 1 1 shows the results for the
parabolic rate constant,"^ where the dotted lines represent 5, 10, 15, and 20 times the
parabolic rate constant at 1 atm. The figure shows that the rate constant is propor-
tional to pressure, and also indicates the presence of a second activation energy below
900°C. This may be related to structural changes in the oxide.'^ A typical 10-atm oxi-
dation cycle"*' is shown in Figure 12.
Both pyrogenic and water-pumped equipment can provide steam oxidation to 25
atm pressure and 1100°C.'^' The water-pumped system alleviates the concern associ-
ated with using hydrogen at high pressure and temperature, but requires extra atten-
tion to purity since the water quality and pumping apparatus determine the steam
quality. Equipment for growing dry oxides at pressures up to 700 atm is in the
developmental stages.

152 VLSI Technology
TEMPERATURE CO
o o o o o o
O lO O If) O If)
— O O <T) <T> OO
10.0
5.0
2.0
1.0
0.5
0.2 h
S 0.1 h
<
^ 0.051-
002
T—I
—I
—
r
^i

*^^
^Vn5 20o,m
^ ^
' * 15atm
jEA=0.78eV ^i S lOatm"
l" 5 atm_
EA=1.17eV
PYROGENIC STEAM
(100), (111) Si 1 atm
0.70 0.75 0.80 085 0.90 0.95 1.00
1000/T(K'M
Fig. 11 Parabolic rate constant versus 1000/7 for ( 100) and (111) silicon oxidized at pressures of 1 , 5, 10,
15, and 20 atm in pyrogenic steam. (After Razouk, Lie, and Deal, Ref. 40.)
4.3.4 Plasma Oxidation
The anodic plasma-oxidation process offers the possibihty of growing high-quality
oxides at temperatures even lower than those achieved with the high-pressure tech-
nique. This process"^^ has all the advantages associated with low-temperature process-
ing, such as movement of previous diffusions and suppression of defect formation.
Anodic plasma oxidation can grow reasonably thick oxides (on the order of 1 ixm) at
low temperatures (<600°C) at growth rates up to about 1 jxm/h.
Plasma oxidation is a low-temperature vacuum process usually carried out in a
pure oxygen discharge. The plasma is produced either by a high-frequency discharge
or a DC electron source. Placing the wafer in a uniform density region of the plasma
and biasing it positively below the plasma potential allows it to collect active charged
oxygen species. The growth rate of the oxide typically increases with increasing sub-
strate temperature, plasma density, and substrate dopant concentration.
The mechanisms involved with plasma oxidation are not fully understood.
Uncertainty exists as to whether the oxide grows by the inward migration of oxygen
species or by other, more complicated mechanisms. One model proposes that silicon
and oxygen ions and/ or their vacancies move across the oxide in opposite directions
as a result of the applied electric field across the oxide
."^^
The beneficial effect of plasma oxidation will occur with selective oxidation

Oxidation 153
SHELL
TUBE
DEPRESSURIZE
N2
•PRESSURIZE
H2O
J_J 1_1
30 40 50
TIME (min)
Fig. 12 Typical 10-atm steam oxidation cycle. (After Katz et ai. Ref. 41 .)
techniques (where portions of the wafer are masked against oxidation). Appropriate
oxidation masks include aluminum oxide, magnesium oxide, and silicon nitride pat-
terned by the photolithographic technique. Oxide properties, specifically the etch
rate, refractive index, stress, fixed charge, interface states, and breakdown strength of
plasma oxides grown at 5(X)°C compare favorably to the properties of thermal oxides
grown at 1 lOOT.^^"^^
4.4 OXIDE PROPERTIES
Although the literature quotes specific values for various oxide properties, it is
becoming apparent that these values are affected by the experimental conditions of
oxide growth. For example, the index of refraction of dry oxides'^ decreases with
increasing temperature, saturating above 1 190°C at an index of 1 .4620. Additionally,
the apparent density of oxides grown at 800°C is 3% greater than those grown'^ above
1 190°C. The etch rate of thermal oxides at room temperature in buffered HF (49%) is
generally quoted at about 1000 A/ min but varies with temperature and etch solution.
The etch rate also varies with oxide density and thus with oxidation temperature.
Measurements show that high-pressure oxides grown at 725°C and 20 atm exhibit a
higher index of refraction, higher density, and slower etch rate in buffered HF than
steam oxide grown at 900°C and 1 atm.'^^ This difference is partially caused by the
oxidation temperature effect.
For thin oxides the role of the interface in determining oxide properties is impor-
tant. Unanswered questions involve the effect of lattice mismatch on oxide structure,
optical properties, oxide kinetics, and oxide defects such as pinholes.
4.4.1 Masking Properties of Si02
A silicon dioxide layer can provide a selective mask against the diffusion of dopant
atoms at elevated temperatures, a very useful property in IC processing. A predepo-

154 VLSI Technology
Table 7 Diffusion constants in SiO
Diffusion constants at 1 100°C
Dopants (cm^/s)
B 3.4 X 10"'^ to 2.0 X 10"''*
Ga 5.3x10""
P 2.9 X 10"'^ to 2.0 X 10-'3
As 1.2X 10-'6to3.5 X 10-'5
Sb 9.9 X 10"'^
sition of dopant, by ion implantation, chemical diffusion, or spin-on techniques,
typically results in a dopant source at or near the surface of the oxide. During the
high-temperature drive-in step, diffusion in the oxide must be slow enough with
respect to diffusion in the silicon that the dopants do not diffuse through the oxide in
the marked region and reach the silicon surface. The required thickness may be deter-
mined by experimentally measuring, at a particular temperature and time, the oxide
thickness necessary to prevent the inversion of a lightly doped silicon substrate of
opposite conductivity. A safety factor is added to this value. The impurity masking
properties result when the oxide is converted into a silica impurity oxide "glass"
phase.
The values of diffusion constants for various dopants in SiO? depend on the con-
centration, properties, and structure of the Si02. Not surprisingly quoted values may
vary significantly. Table 7 lists diffusion constants for various common dopants."*^
The commonly used n-type impurities P, Sb, and As, as well as the most fre-
quently used p-type impurity B, all have very small oxide diffusion coefficients and
are compatible with oxide masking. This is not true for gallium or aluminum ( Al data
not shown). Typically, oxides used for masking common impurities in conventional
device processing are 0.5 to 0.7 |xm thick.
4.4.2 Oxide Charges
The Si-Si02 interface contains a transition region, both in terms of atom position and
stoichiometry, between the crystalline silicon and amorphous silica. Various charges
and traps are associated with the thermally oxidized silicon, some of which are related
to the transition region. A charge at the interface can induce a charge of the opposite
polarity in the underlying silicon, thereby affecting the ideal characteristics of the
MOS device. This results in both yield and reliability problems.
Figure 13 shows general types of charges. "^^
These charges are described by
N = Q/ q where Q is the net effective charge per unit area ( coulombs /cm^) at the
Si-Si02 interface, N is the net number of charges per unit area ( number/ cm~) at the
Si-Si02 interface, and q is the electric charge. A brief description of the various
charges follows.
Located at the Si-Si02 interface, interface-trapped charges Q^^ have energy states
in the silicon forbidden bandgap and can interact electrically with the underlying sili-
con. These charges are thought to result from several sources, including structural

Oxidation 155
^'
' CHARGE (Om)
^ / s,o,
OXIDE TRAPPED
^CHARGE (Oof)
( + + + FIXED OXIDE
^^_ _ _ CHARGE (Of)
+ + + + + + / SiO,
—)( ^ ¥. X X X X-
INTERFACE . „.
TRAPPED CHARGE (Qjt) ) ^'
Fig. 13 Charges in thermally oxidized silicon. (After Deal, Ref. 48.)
defects related to the oxidation process, metallic impurities, or bond breaking
processes. A low-temperature hydrogen anneal (450°C) effectively neutralizes
interface-trapped charga.'^^ The density of these charges is usually expressed in terms
of unit area and energy in the silicon badgap ( number/ cm'^-eV). Capacitance-voltage
(high frequency, low frequency, or quasistatic) and conductance-voltage techniques
are typically used to determine the interface-trapped charges.^ Values of 10'^/cm--eV
and lower have been observed.
The fixed oxide charge Qf (usually positive) is located in the oxide within
approximately 30 A of the Si-Si02 interface.
Qf cannot be charged or discharged. Its
density ranges from 10^^/cm~ to 10'~/cm-, depending on oxidation and annealing
conditions as well as orientation.
Qf is related to the oxidation process itself. For
electrical measurements Qf can be considered as a charge sheet at the Si-Si02 inter-
face. The value of this charge can be determined using the capacitance-voltage (C-V)
analysis technique and the following equation
-^ = (-Vfb + C})MS)— = i-VpB + CJ)MS)-T- (19)
q q qdo
where VpB is the flatboard voltage, cf^MS is the metal silicon work-function difference,
e^ is the dielectric permittivity of the semiconductor, dg is the oxide thickness, and
Cq is the oxide capacitance per unit area.
Qf values for ( 100) oriented silicon are less
than those for (111) silicon. This difference is apparently related to the number of
available bonds per unit area of silicon surface.
From a processing standpoint both temperature and ambient determine Qf
.'^^
In
an oxygen ambient, the last high-temperature treatment determines Qf rapid cooling
from high temperatures results in low values. Inert ambient annealing also results in
low Qf , however; at low temperatures enough time must be allowed for equilibrium
to be reached.
The mobile ionic charge Qf„ is attributed to alkali ions, such as sodium, potas-
sium, and lithium, in the oxide as well as to negative ions and heavy metals. The

156 VLSI Technology
alkali ions are mobile even at room temperature when electric fields are present.
Densities range from lO'^/cm^ to lO'^/cm^ or higher and are related to processing
materials, chemicals, ambient, or handling. Because of larger ionic radii and lower
mobility, the heavier elements contributing to this charge drift at a slower rate than
the lighter elements. Measurements can be made by using the C-V technique which
involves a change in the silicon surface potential or current flow in the oxide as a
result of ionic motion. Both the interface-trapped charge and oxide-trapped charge
must be annealed to ensure that they do not contribute to the mobile ionic charge.
Since alkali ions can be present at various places in the oxide, the MOS capacitor is
subjected to a temperature-bias stress test which is compared to the standard C-V plot.
The shift in flat-band voltage between the two curves allows the mobile ionic charge
to be calculated. Common techniques to minimize this charge include cleaning the
furnace tube in a chlorine ambient, gettering with phosphosilicate glass, and using
masking layers such as silicon nitride. Although chlorine in the oxidation ambient
and hence in the oxide can complex sodium, the temperatures at which this is effec-
tive are higher than the normal processing temperatures.
Oxide-trapped charge Q ot may be positive or negative due to holes or electrons
trapped in the bulk of the oxide. This charge is associated with defects in the Si02,
may result from ionizing radiation, avalanche injection, or high currents in the oxide,
and can be annealed out by low-temperature treatment (although neutral traps may
remain)."^^ Densities range from less than lO^/cm" to lO'-^/cm". Again the C-V tech-
nique can be used to measure the charge.
In addition to the earlier concerns, such as exposure of devices to ionizing radia-
tion encountered in space flights, additional concerns arise from the newer device-
processing techniques such as ion implantation, e-beam metallization, plasma or
reactive- sputter etching, and e-beam or x-ray lithography.
4.4.3 Oxide Stress
Understanding the stress associated with a film is important, because high stress lev-
els can contribute to wafer warpage, film cracking, and defect formation in the under-
lying Si. Room temperature measurements following thermal oxidation of silicon
show Si02 to be in a state of compression on the surface. Stress values of 3 x 10^
dynes /cm" are reported^*^ with the stress attributed to the differences in thermal
expansion for Si and Si02. Viscous (shear) flow of thermally grown SiOo occurs at
temperatures as low as 960°C, evidenced by the inability of the oxide-silicon structure
(oxide on one side only) to remain thermally warped above that temperature.^' In one
experiment the stress present in thermal (wet) SiOo during growth was measured as a
function of growth temperature''" in the range of 850 to 1030°C. Growth at 950°C and
below resulted in a compressive stress of approximately 7 x 10^ dynes /cm" in the
Si02. This at-temperature stress value is somewhat higher than the room temperature
value of 3 x 10^ dynes /cm" given above, indicating the possibility of some stress
relief during cool down. Stress-free growth at 975 and 1000°C was achieved.
During device processing, windows are cut into the oxide resulting in a complex
stress distribution. At these discontinuities exceedingly high stress levels can occur.

Oxidation 157
Typically such stress would be relieved by plastic flow or other stress-relief mechan-
isms. The stress reduction is further accomplished by shear components which aver-
age the load over adjacent areas
r^*^
The possibility of structural damage in the silicon is very real. Shear stresses at
the interface are comparable to the values of compressive stress given above.^' These
shear stresses are substantially higher than the values of 3.2 x 10^ dynes/ cm" to 4.3
X 10^ dynes /cm^ given for the critical stress of shear flow for silicon at 800°C.^^ This
leads to the possibility of plastic deformation in the silicon. The deleterious effect of
structural damage in the silicon (particularly when decorated with impurities) on junc-
tion leakage and on other device properties is well documented. Additionally, vis-
cous shear flow has been related to hole traps at the interface.
4.5 REDISTRIBUTION OF DOPANTS AT INTERFACE
When silicon is thermally oxidized, an interface is formed separating the silicon from
the Si02. As oxidation proceeds this interface advances into the silicon. A doping
impurity (initially present in the silicon) will redistribute at the interface until its
chemical potential is the same on each side of the interface. This redistribution may
result in an abrupt change in impurity concentration across the interface. The ratio of
the equilibrium concentration of the impurity (dopant) in silicon to that in Si02 at the
interface is called the equilibrium segregation coefficient. (Note: In some literature
an inverse definition is used, so care must be taken in using published values.) The
experimentally determined segregation coefficient may differ from the equilibrium
segregation coefficient. This will primarily be determined by the chemical potential
differences and the kinetics of redistribution at the interface.
Two additional factors that influence the redistribution process are the diffusivity
of the impurity in the oxide (if large, the dopant can diffuse through the oxide rapidly,
affecting the profile near the Si-SiOo interface) and the rate at which the interface
moves with respect to the diffusion rate. Figure 14 shows four different possibilities
of impurity segregation.^^
The segregation coefficient determined experimentally is called the effective or
interface segregation coefficient. It is particularly important to understand the con-
centration profile at the interface since electrical characteristics are affected. In
extreme cases inversion can occur.
Typically, to determine the segregation coefficient experimentally, a model for
diffusion has been formulated, diffusion profiles experimentally determined in the sil-
icon, and a segregation coefficient chosen to force the data to fit the model. Direct
determination of the segregation coefficient is possible using the secondary-ion mass
spectrometry (SIMS) technique to obtain concentration values in the oxide and in the
silicon.
Most of the effort in segregation coefficient determination has been related to
boron. The segregation coefficient, as defined above, increases with increasing tem-
perature, and is orientation dependent with values for (100) orientation being greater
than for (111) orientation. Reported coefficients^^"^'' are generally 0.1 to approxi-

158 VLSI Technology
OXIDE SILICON
f
m<l
(a)
OXIDE SILICON
(b)
OXIDE SILICON
-Cb
c XID i SILICON
c_ /
r Cb /
f
m>l
^
m>l
»-
(c) (d)
Fig. 14 Impurity segregation at the Si-Si02 interface resulting from thermal oxidation, (a) Diffusion in
oxide slow (boron); (b) diffusion in oxide fast (boron-H2 ambient); (c) diffusion in oxide slow (phos-
phorus); and (d) diffusion in oxide fast (gallium). {After Grove, Leistiko. atidSah. Ref. 54.)
TEMPERATURE CO
1200 1100 1000 900
1.0 —
<
o
^ 0.1
o
UJ
v>
^
Ill 1
-
^^^x^"^
-
-
^5^ (100)
^ (111)
-
A DRY Og (Ref. 57)
ONEAR DRY Og (Ref.55)
-
DNEAR DRY Og (Ref. 56)
• WET Og (Ref. 56)
1 1 1 1 1 1
.01
6.0 65 7.0 7.5 8.0 8.5 9.0 9.5
ioVt (k-1)
Fig. 15 Boron segregation coefficient as a function of temperature for dry, near dry, and wet oxidations.
(After Fair and Tsai, Ref. 56.)

Oxidation 159
mately 1.0 over the temperature range 850 to 1200°C, although values greater than 1
have been obtained in special cases. ^^ Figure 15 shows the results of some boron
segregation determinations. Because very small amounts of moisture can greatly
affect the segregation coefficient, a distinction must be made between dry, near dry,
and wet oxidations. A "dr' oxidation" containing even 20-ppm moisture exhibits a
segregation coefficient similar to that of wet oxidation. The data in Fig. 15 shows
that "near dry" oxidation (obtained in a furnace without special drying precautions)
and wet oxidation give virtually identical segregation coefficients. Larger segregation
coefficient values are obtained when special drying precautions are taken. ^^ Addition-
ally, boron implanted through oxide even when subsequent oxidations are performed
in ambients with trace amounts of H2O has segregation coefficients equal to those for
dry O2. These effects are particularly important at lower temperatures. For example,
at 900°C the surface concentration following a "near dry" oxidation is approximately
one-half that of pure dry oxidation.
^'^^
Quoted effective segregation coefficients (Weff)
for boron in silicon are^^
1
.
Pure dr>' O2, orientation independent
-0.33 eV
Wef, = 13.4 exp — (20)
kT
2. Near dr}' or wet O2
^^ ^ -0.66 eV ._.,
^iiKeff) = 65.2 exp — (21)
^^^A r>
—0.66 eV ,.-,
wiooieff) = 104.0 exp — (22)
kT
For phosphorous, arsenic, and antimony, where the dopant segregates into the
silicon (pile-up), segregation coefficient values of approximately 10 are usually
quoted, ^'^
although higher values (up to 800 at 1050°C) have been determined for
arsenic. With gallium, which diffuses rapidly in the oxide, a value of approximately
20 is given.
^'^
4.6 OXIDATION OF POLYSILICON
Polycrystalline silicon has been used in IC technology to provide conducting lines
between devices and gates. Thermal oxidation of polycrystalline silicon provides
electrical isolation which can be employed as an interlevel dielectric for multilayer
structures. An understanding of the oxidation mechanisms is necessary since device
reliability depends on the quality of the oxide. Various parameters of polycrystalline
silicon including growth method, growth temperature, doping level, grain size, and
morphology have been studied with respect to oxidation rate and oxide properties,
such as electrical conductivity and breakdown. Typically, comparisons are made
with oxides grown on single-crystal silicon.

160 VLSI Technology
In one study, ^^ using CVD doped and oxidized polycrystalline films, tiie
atmospheric-pressure polysilicon (deposited at 960°C) oxidized at the same rate as
low-presure polysihcon (deposited at 625°C). However, a substantial difference with
respect to single-crystal silicon was observed. At moderate doping levels, the electri-
cally active carrier concentration at the surface controlled the oxidation rate. While
the total amount of dopant introduced into polysilicon and single-crystal samples was
the same, the dopant diffused more deeply in the polysilicon reducing the
oxidation rate with respect to single-crystal silicon. This result should not be too
surprising in light of our previous discussion of concentration-enhanced oxidation.
Following a phosphorus "predeposition," having 10-Cl/r sheet resistance and 850°C
steam oxidation, oxide thickness values of approximately 3000 to 32(X) A on polysili-
con, approximately 3850 A on ( 100) single crystal , and approximately 4250 A on ( 1 1 1
)
single crystal were obtained. ^^ The ratio of polysilicon-consumed oxidation to oxide
grown was about the same as for single-crystal silicon (0.45).
In another study,
^'^
using CVD (at 625°C) undoped polysilicon and lightly doped
single-crystal silicon, the oxidation rate increased in the following order: (100),
(111), polysilicon, and (110). These observations are consistent with the transmission
electron microscope determination that the polysilicon was oriented between (111)
and (110). For heavily phosphorous-doped polysilicon, the parabolic rate constant is
saturated at concentrations greater than 2 x 10"° cm"^ while the linear rate constant
continues to increase.
If the oxidation rate of polysilicon depends on the random orientation of the
grains, which is true in the surface or reaction-controlled region, then a surface
roughening would be expected. Surface roughening, however, is not as pronounced
for oxidations at higher temperatures where diffusion control is predominant.
Transmission electron microscope results^ show that the oxide exhibits thickness
undulations coincident with previous grain boundaries. The oxide is thinner over
grain boundaries by approximately 25% and forms intergranularly in addition to form-
ing on the surface. For higher-temperature oxidations, the thickness undulations are
less severe because the oxide and silicon can flow and the reaction can enter the
diffusion-controlled region.
Device reliability may be affected when the oxide is removed to open the con-
tacts to the polysilicon; the oxide in the intergranular regions may also be removed
unintentionally. Subsequent metallization can form a conducting path along the
exposed regions between the grains in the polysilicon, and electrical shorts.^
4.7 OXIDATION-INDUCED DEFECTS
4.7.1 Oxidation-Induced Stacking Faults
Thermal oxidation of silicon can produce stacking faults lying on (1 1 1) planes. These
planar faults are structural defects in the silicon lattice that are extrinsic in nature and
are bounded by partial dislocations. The growth mechanism generally invoked
involves the coalescence of excess silicon atoms in the silicon lattice on nucleation

Oxidation 161
sites such as defects grown in during crystal growth, surface mechanical damage
present prior to oxidation, chemical contamination, or defects referred to as saucer
pits or hillocks. As a result of the oxidation process, excess interstitial silicon is
present near the Si-Si02 interface. A small fraction of these silicon atoms flow into
the bulk silicon. The silicon interstitial supersaturation in the silicon determines the
stacking fault growth rate.^' An alternative explanation involves a decreased vacancy
concentration in the silicon near the Si-SiO^ interface.
The deleterious nature of oxidation-induced stacking faults is well known.
Examples include degraded junction characteristics in the form of increased reverse
leakage current, and storage time degradation in MOS structures. These problems
occur when the stacking faults are electrically active as the result of being decorated
with impurities, typically heavy metals. The decoration occurs both on the stacking
fault itself and on the bounding dislocations. The dislocations, in particular, are
favorable clustering sites because they represent a disarrayed high-energy region in
the lattice. Diffusing impurity atoms prefer to reside in such a region because they
distort the lattice less here than in the perfect lattice; that is, the high-energy region is
energetically more favorable.
The growth of oxidation-induced stacking faults is a strong function of substrate
orientation, conductivity type, and defect nuclei present. Observations show that the
growth rate is greater for (100) than (111) substrates. Additionally, the density is
greater for n-type conductivity than for p-type conductivity. Figure 16 shows that
stacking fault length is a strong function of oxidation temperature.^^ The activation
energy in the growth region is 2.3 eV independent of surface orientation and ambient
(dry or wet). In the retrogrowth temperature range, stacking faults initially grow and
then begin to shrink as oxidation proceeds. Typically the distribution of surface
stacking fault lengths is very tight, except for an anomalous few percent which exhibit
substantially greater lengths. Shorter-length stacking faults are usually bulk-
nucleated stacking faults intersecting the surface. The length to depth ratio of the
surface-oxidation stacking fault is approximately 3 to 10.
The curves in Fig. 16 clearly show two regions: a growth region and a retro-
growth region. In the retrogrowth region, stacking fault formation is suppressed
while preexisting stacking faults shrink. The addition of HCl to the ambient can also
suppress stacking fault formation. ^-^
Additional observations show, for comparable
oxide thickness, shorter stacking faults are grown (in the growth region) when the oxi-
dation temperature is lower. Indeed even for oxides as thick as 1 |xm, stacking fault
formation is completely suppressed when the temperature is reduced below 950°C.^
Shrinkage of preexisting stacking faults can also be accomplished by high-
temperature inert ambient heat treatment. Nt for example, with an activation energy
of approximately 5 eV (which is almost equal to the activation energy of silicon self-
diffusion). This indicates that the shrinkage is probably related to the diffusion of sili-
con atoms.
Experimental observations show that at comparable temperature and time, the
oxidation stacking fault length is greater for steam ambients than for dry ambients.
This suggests that the oxidation rate strongly influences the point-defect mechanism

162 VLSI Technology
TEMPERATURE (°C)
1200 1150 1100
"T
0.64 0.66 0.68 0.70
lO'/T (K-l)
0.72 0.74
Fig. 16 Growth of oxidation-induced stacking faults versus temperature; for 3 h of dry oxidation. (After
Hu.Ref.62.)
responsible for stacking fault growth. Equation 23 is a proposed model^' in which the
oxidation rate is the controlling parameter in oxidation stacking fault length.
dt
K,
dT,
dt
K, (23)
where / is the stacking fault length, Tq^ is the oxide thickness, t is the time, n is the
power dependence, .^i is related to the growth mechanism and defect generation at
the Si-Si02 interface, and K2 is related to the retrogrowth mechanism. Applying this
equation to experimental data gives values for n, K], and Kj- A 0.4th power depen-
dence is observed. ^^ This less-than-linear dependence of oxidation stacking fault
growth rate on the oxidation rate means that smaller stacking faults will result for a
higher oxidation rate at the same temperature for the same oxide thickness. This, of
course, is the case with high-pressure oxidation where the oxidation rate is increased.
Figure 17 shows an experimental result for a 950 to 1 100°C temperature range at both
1- and 6.4-atm pressure.^ The above results confirm the proposed model. Additional
results^^ at 700°C and 20-atm pressure show complete stacking fault suppression for
all thicknesses studies (up to 5 [xm). Preexisting stacking faults tend to grow during

Oxidation 163
1 2 3 4 5
OXIDE THICKNESS (fim)
Fig. 17 Length of oxidation-induced stacking faults versus oxide thickness for 1-atm and 6.4-atm steam
oxidations. (After Tsubouchi. Miyoshi. and Abe. Ref. 64.)
this high-pressure, low-temperature oxidation. However, the net length of the stack-
ing fault is reduced by the consumption of silicon.
4.7.2 Oxide Isolation Defects
Selective oxidation of silicon represents an important process in IC processing. For
VLSI, oxide isolation is preferred to junction isolation. Stress along the edge of an
oxidized area especially in recessed oxides (that is, where the silicon has been
trenched prior to oxidation to produce a reasonably planar surface) may produce
severe damage in the silicon. Such defects result in increased leakage in nearby de-
vices. The stress generated by the growing oxide, whose volume is over twice that of
the consumed silicon, must be relieved without damaging the silicon. Various param-
eters have been examined for recessed isolation processes with the conclusion that the
oxidation temperature must be sufficiently high to allow the stress in the oxide to be
relieved by viscous flow. Temperatures (around 950°C) will prevent stress-induced
defect formation in a recessed structure (recess approximately 1 ixm and oxide growth
approximately 2.2 xm). This critical temperature correlates well with that for stress-
free growth in oxides at 1 atm.

164 VLSI Technology
The ability to mathematically describe the oxidation process reasonably well in its
simplest form has been demonstrated. Our understanding of the oxidizing species and
the point-defect mechanisms in the vicinity of the oxidizing interface is still evolving.
We can determine experimentally the effect of impurity species, dopant concentra-
tion, and orientation on the oxidation kinetics, but are somewhat less able to explain
some of the mechanisms involved.
An understanding of oxide charge is necessary in order to fabricate highly reli-
able devices. This is particularly important with the new processing techniques used
for VLSI fabrication. An understanding of how to form oxides without damaging the
underlying silicon is necessary when fabricating advanced structures, such as dielec-
trically isolated devices that may require thick recessed oxides. Oxide viscosity is a
first-order effect, and oxidation temperatures above 950°C minimize stress-related
defect formation.
Polycrystalline silicon usage has become increasingly important and has attracted
more study recendy both in its formation and oxidation. The polysilicon deposition
technique, polysilicon grain size, orientation, and doping level all affect oxidation.
Formation of oxide in intergranular regions and its removal when contacts to the
polysilicon are opened leads to the possibility of electrical shorts during metallization.
The impact of continually shrunken vertical and lateral dimensions, tighter
design rules, and lower-temperature processing cannot be overlooked in future
research. The recent availability of commercial high-pressure oxidation equipment
allows thick oxides to be grown at low to moderate temperatures. As an added bonus,
suppression of oxidation-induced stacking is obtained. This technique has not been
exploited to any great extent, but more utilization is undoubtedly in the offing.
A low-temperature technique for growing reasonably thick oxides (~1 (xm in
1 h), the anodic plasma-oxidation technique, offers vast potential. The low-tem-
perature processing suppresses defect formation and minimizes movement of previous
diffusions. Oxide properties are comparable to those of thermally grown oxides.
Uses should proliferate when commercial equipment becomes available.
The prevention of the bird's beak during selective oxidation is another area which
is receiving much attention and has a potentially big payoff. Bird's beak is associated
with the thin "pad" oxide necessary to prevent defect formation. The oxide is
between the silicon and masking nitride layer and results from the diffusion of oxygen
and growth of SIOt. Success has been demonstrated when the silicon is selectively
trenched, processed so that nitride is present on the trench sidewall, and subsequently
oxidized.^ Encouraging results have also been obtained with the anodic plasma-
oxidation technique for nonrecessed oxides.'*^
Oxide requirements on advanced structures are changing. As discussed earlier,
these requirements range from highly reliable thin oxides to thick isolation oxides that
can be grown at moderate temperatures. Renewed emphasis on oxidation techniques,
such as high-pressure and plasma oxidation, has occurred. It is inevitable that further
advances will be made in growth techniques, processing schemes, and understanding
of oxidation mechanisms.

Oxidation 165
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E. A. Irene, "The Effects of Trace Amounts of Water of the Thermal Oxidation of Si in Oxygen,"" J.
M. M. Atalla and E. Tannenbaum. "Impurity Redistribution and Junction Formation in Silicon by
Thermal Oxidation."" BellSxst. Tech. J.. 39. 933 (1960).

166 VLSI Technology
B. E. Deal and M. Sklar, "Thermal Oxidation of Heavily Doped Silicon," J. Electrochem. Soc. 1 12,
430(1965).
C. P. Ho, J. D. Plummer, J. D. Meindl, and B. E. Deal, "Thermal Oxidation of Heavily Phosphorus
Doped Silicon," J. Electrochem. Soc. 125, 665 (1978).
C. P. Ho and J. D. Plummer, "Si-Si02 Interface Oxidation Kinetics: A Physical Model for the Influ-
ence of High Substrate Doping Levels. I. Theory," J. Electrochem. Soc, 126, 1516 (1979); "11.
Comparison With Experiment and Discussion," J. Electrochem. Soc, 126, 1523 (1979).
D. W. Hess and B. E. Deal, "Kinetics of the Thermal Oxidation of Silicon in O2/HCI Mixtures," J.
J. F. Gotzlich, K. Haberger, H. Ryssel, H. Kranz, and E. Traumuller, "Dopant Dependence of the
Oxidation Rate of Ion Implanted Silicon," Radiat. Eff., 47, 203 (1980).
G. Mezey, T. Nagy, J. Gyulai, E. Kotai, A. Manuaba, T. Lohner, and J. W. Mayer, "Enhanced and
Inhibited Oxidation of Implanted Silicon," in Ion Implantation in Semiconductors, F. Chemow, J. A.
Borders, and D. K. Brice. Eds., Plenum Press, New York, 1977, p. 49.
W. Kem and D. A. Puotinen, "Cleaning Solutions Based on Hydrogen Peroxide for Use in Silicon
Semiconductor Technology," /?CA;?ev. 31, 187(1970).
D. Burkman, "Optimizing the Cleaning Procedure for Silicon Wafers Prior to High Temperature
Operations," Semicond. Int., 4, 103 (1981).
P. S. Burggraff, "The Case for Computerized Diffusion Control," Semicond. Int., 4, 37 (1981).
J. R. Ligenza, "Oxidation of Silicon by High Pressure Steam," J . Electrochem. Soc, 109, 73 (1962).
J. Agraz-Guerena, P. T. Panousis, and B. L. Morris, "OXIL, A Versatile Bipolar VLSI Technol-
ogy," IEEE Trans. Electron Devices. ED-27, 1397 ( 1980).
N. Tsubouchi, H. Miyoshi, H. Abe, and T. Enomoto, "The Applications of High Pressure Oxidation
Process to the Fabrication of MOS LSI," IEEE Trans. Electron Devices, ED-26, 618 (1979).
R. R. Razouk, L. N. Lie, and B. E. Deal, "Kinetics of High Pressure Oxidation of Silicon in Pyro-
genic Steam," y. Electrochem. Soc, 128, 2214 (1981).
L. E. Katz, B. F. Howells, L. P. Adda, T. Thompson, and D. Carlson, "High Pressure Oxidation of
Silicon by the Pyrogenic or Pumped Water Technique
, '
' Solid State Technol. , 24, 87 ( 1 98 1 )
.
J. R. Ligenza, "Silicon Oxidation in an Oxidation Plasma Excited by Microwaves," J. Appl. Phys.,
36,2703(1965).
V. Q. Ho and T. Sugano, "Selective Anodic Oxidation of Silicon in Oxygen Plasma," IEEE Trans.
Electron Devices. ED-27. 1436(1980).
J. R. Ligenza and M. Kuhn, "DC Arc Anodic Plasma Oxidation," Solid State Technol., 13, 33
(1970).
A. K. Ray and A. Reisman, "The Formation of SIOt in an RF Generated Oxygen Plasma," J. Elec-
trochem. Soc, 128, 2466 (1981).
L. E. Katz and B. F. Howells, "Low Temperature, High Pressure Steam Oxidation of Silicon," J.
Electrochem. Soc, 126, 1822(1979).
M. Ghezzo and D. M. Brown, "Diffusivity Summary of B, Ga, P, As, and Sb in Si02," J. Electro-
chem. Soc, 120, 146(1973).
B. E. Deal, "Standardized Terminology for Oxide Charges Associated with Thermally Oxidized Sili-
con," IEEE Trans. Electron Devices, ED-27, 606 (1980).
B. E. Deal, "The Current Understanding of Charges in the Thermally Oxidized Silicon Structure," J.
Electrochem. Soc. 121, 198C(1974).
R. J. Jaccodine and W. A. Schlegel, "Measurement of Strains at Si-Si02 Interface," J. Appl. Phys.,
37,2429(1966).
E. P. EerNisse, "Viscous Flow of Thermal SiOj," Appl. Phys. Lett., 30, 290 (1977).
E. P. EerNisse, "Stress in Thermal Si02 During Growth," App/. Phys. Lett., 35, 8 (1979).
S. M. Hu, "Tenperature Dependence of Critical Stress in Oxygen Free Silicon," J. Appl. Phys., 49,
5678(1978).
A. S. Grove, O. Leistiko, and C. T. Sah, "Redistribution of Acceptor and Donor Impurities During
Thermal Oxidation of Silicon," J. Appl. Phys., 35, 2695 (1964).
J. W. Colby and L. E. Katz, "Boron Segregation at Si-Si02 Interface as a Function of Temperature
and Orientation," y. Electrochem. Soc. 123, 409 ( 1976).

Oxidation 167
[56] R. B. Fair and J. C. C. Tsai, "Theory and Direct Measurement of Boron Segregation in SiO-i during
Dry. Near Dry and Wet O2 Oxidation." J. Electrochem. Soc. 125. 2050 (1978).
[57] S. P. Murarka. "Diffusion and Segregation of Ion-Implanted Boron in Silicon in Dr>' Oxygen
Ambients." Phys. Rev. B. 12. 2502 ( 1975).
[58] T. I. Kamins. "Oxidation of Phosphorous-Doped Low Pressure and Atmospheric Pressure CVD
PolycrN'Stalline-Silicon Films." J. Electrochem. Soc. 126. 838 ( 1979).
[59] H. Sunami, "Thermal Oxidation of Phosphorus-Doped Polycrvstalline Silicon in Wet Oxygen." J.
[60] E. A. Irene, E. Tiemey, and D. W. Dong. "Silicon Oxidation Studies: Morphological Aspects of the
Oxidation of Polycrystalline Silicon." J. Electrochem. Soc, 127, 705 (1980).
[61] A. Lin, R. W. Dutton, D. A. Antoniades, and W. A. Tiller. "The Growth of Oxidation Stacking
Faults and the Point Defect Generation at Si-SiOi Interface during Thermal Oxidation of Silicon." J.
[62] S. M. Hu. "Anomalous Temperature Effect of Oxidation Stacking Faults in Silicon." Appl. Phys.
Lett.. 1, 165 (1915).
[63] H. Shiraki. "Stacking Fault Generation. Suppression and Grown-In Defect Elimination in Dislocation
Free Silicon Wafers by HCl Oxidation." Jpn. J. Appl. Phys.. 15. 1 ( 1976).
[64] N. Tsubouchi. H. Miyoshi. and H. Abe. "Suppression of Oxidation-Induced Stacking Fault Forma-
tion in Silicon by High Pressure Steam Oxidation." J. Appl. Phys., 17, 223 (1978).
[65] L. E. Katz and L. C. Kimerling. "Defect Formation During High Pressure. Low Temperature Steam
Oxidation of Silicon." J. Electrochem. Soc, 125. 1680 ( 1978).
[66] D. Kahng. T. A. Shankoff. T. T. Sheng. and S. E. Haszko. "A Method for Area Saving Planar Isola-
tion O.xides Using Oxidation Protected Sidewalls." J. Electrochem. Soc, 127. 2468 (1980).
4.9 PROBLEMS
1 Show from the densities and molecular weights of Si and SIOt that a layer of silicon of thickness 0.45 dQ
is consumed when a SiOn layer of thickness cIq is formed. Use densitv' values of 2.27 gm/cm-^ for Si02 and
2.33 gm/cm- for Si.
2 Show that in Eq. 14. d^ + Ado = B(t + i) reduces to d^ = Bt for long times and to dQ = B I A {t + t)
for short times.
3 (a) Show that in Eq. 14. c/q + .4^0 ~ ^(' + "J"' can be used graphically to obtain an equation describing
the oxidation rate.
(b) Generate such a plot for the 1 100°C oxidation data of Fig. 5. Use t = and ( 100) orientation to
obtain rate constants. Compare your results to those of Fig. 3.
4 Using Eq. 14 and Table 1 . how long will it take to grow 2.0 fxm of SIOt at 920°C and 25-atm steam pres-
sure?
5 Define a set of conditions to minimize the chance of inverting the surface of an n-type substrate (contain-
ing a boron diffusion) when oxidizing the wafer.
6 List possible ways of growing an initial oxide on a substrate without forming oxidation-induced stacking
faults.
7 Solve Eq. 14 for oxide thickness as/ (r. t. A, B).
8 Make use of the equation derived in Problem 7. and the data in Tables 1 and 2, to generate oxide thick-
ness versus time curves for wet and dry oxidations at 1 100°C. Assume t = 0.
9 Generate a model showing possible interface reaction and point-defect fluxes at the interface.
10 Devise a processing scheme to generate selectively a planar recessed oxide in silicon. Show how you
might prevent lateral oxidation during the oxide growth.

CHAPTER
FIVE
DIFFUSION
J. C. C. TSAI
5.1 INTRODUCTION
Diffusion of impurity atoms in silicon is important in VLSI processing. The idea of
using diffusion techniques to alter the type of conductivity in silicon or germanium
was disclosed in a patent in 1952 by Pfann.' Since then, various ideas on how to intro-
duce dopants into silicon by diffusion have been studied with the goals of controlling
the dopant concentration, uniformity, and reproducibility, and of processing a large
number of device wafers in a batch to reduce the manufacturing costs. Diffusion is
used to form bases, emitters, and resistors in bipolar device technology, to form
source and drain regions, and to dope polysilicon in MOS device technology. Dopant
atoms which span a wide range of concentrations can be introduced into silicon
wafers in the following ways: (1) diffusion from a chemical source in a vapor form at
high temperatures, (2) diffusion from a doped-oxide source, or (3) diffusion and
annealing from an ion implanted layer. Annealing of ion implanted layers is for
activating the implanted atoms and reducing the crystal damages from ion implanta-
tion. When the annealing is at a high temperature, diffusion also occurs. Since ion
implantation provides more precise control of total dopants from lO" cm~- to greater
than lO'^ cm~~, it is used to replace the chemical or doped-oxide source wherever
possible. (Ion implantation and annealing properties are discussed in Chapter 6.) Ion
implantation is extensively applied in VLSI device fabrication.
Another aspect of the study of diffusion attempts to develop improved models
from experimental data for predicting diffusion results from theoretical analysis. The
ultimate goal of diffusion studies is to calculate the electrical characteristics of a
semiconductor device from the processing parameters. Diffusion theories have been
developed from two major approaches, namely, the continuum theory of Pick's diffu-
sion equation and the atomistic theory, which involves interactions between point
169

170 VLSI Technology
defects, vacancies and interstitial atoms, and impurity atoms. The continuum theory
describes the diffusion phenomenon from the solution of Pick's diffusion equation
with appropriate diffusivities. (This chapter uses the terms "diffusivity" and "diffu-
sion coefficient" interchangeably.) The diffusivities of a dopant element can be deter-
mined from experimental measurements, such as the surface concentration, junction
depth, or the concentration profiles, and the solutions of Pick's diffusion equation.
When impurity concentrations are low, the measured diffusion profiles are well
behaved and agree with Pick's diffusion equation with a constant diffusivity which
can be calculated readily. In these cases the detailed atomic movements do not have
to be known. When impurity concentrations are high, the diffusion profiles deviate
from the predictions of the simple diffusion theory, and the impurity diffusion is
affected by other factors, which are not considered in Pick's simple diffusion laws.
Since the diffusion profile measurements reveal concentration-dependent diffusion
effects, we apply Pick's diffusion equation with concentration-dependent diffusivities
to the high-concentration diffusions. The concentration-dependent diffusivities are
determined by a Boltzmann-Matano analysis'^ or other formulations of profile
analysis.
Various atomistic diffusion models based on defect-impurity interactions have
been proposed to explain the experimental results from concentration-dependent dif-
fusivities and other anomalous diffusions. The atomistic diffusion theory is still
undergoing active development. Theoretical and experimental results on the diffusion
of Group III and V elements in silicon have been incorporated into various process
models. Chapter 11 discusses the process models in detail. Because process model-
ing is still developing we have to be aware of the model's limitations.
5.2 MODELS OF DIFFUSION IN SOLIDS
At high temperatures point defects, such as vacancies and interstitial atoms, are gen-
erated in a single-crystal solid. When a concentration gradient of the host or impurity
atoms exists, the point defects affect atom movement (diffusion). Diffusion in a solid
can be visualized as atomic movement of the diffusant in the crystal lattice by vacan-
cies or self-interstitials. Pigure 1 shows some common atomic diffusion models" in a
solid, using a simplified two-dimensional crystal structure with lattice constant a.
The circles represent the host atoms occupying the low-temperature lattice positions.
The solid circles represent either host or impurity atoms. At elevated temperatures
the lattice atoms vibrate around the equilibrium lattice sites. Occasionally a host
atom acquires sufficient energy to leave the lattice site, becoming an interstitial atom
and creating a vacancy. When a neighboring atom (either the host or the impurity
atom) migrates to the vacancy site, the mechanism is called diffusion by a vacancy
(Pig. la). If the migrating atom is a host atom the diffusion is referred to as self-
diffusion; if it is an impurity atom the diffusion is impurity diffusion. [Self-diffusion
experiments are usually conducted by introducing radioactive isotopes of the host
atom (Pig. la).]

Diffusion 171
TRACER ATOM
HOST ATOM
o o o-
INTERSTITIAL ATOM
HOST ATOM
(a) (b)
o o o
o o~1
a
o o o-
(c)
o
o
o
o ;
o ;
o
I
I
a
,
o I
o ;
o
(d)
Fig. 1 Models of atomic diffusion mechanisms for a two-dimensional lattice, a is the lattice constant,
(a) Vacancy mechanism, (b) Interstitial mechanism, (c) Interstitialcy mechanism, (d) Crowdion mechan-
ism. (After Tuck. Ref. 2.)
If an interstitial atom moves from one place to another without occupying a lat-
tice site (Fig. lb), the mechanism is interstitial diffusion. An atom smaller than the
host atom often moves interstitially. The activation energies required for diffusion of
interstitial atoms are lower than those for diffusion of lattice atoms by a vacancy
mechanism.
Figure Ic shows that the atomic movement of an interstitial atom (a host or an
impurity atom) displaces a lattice atom, which in turn becomes an interstitial atom.
This is an example of the extended interstitial mechanism, sometimes called the
"interstitialcy" mechanism. A related interstitialcy mechanism is the crowdion
mechanism, in which an interstitial atom located half-way between two lattice sites
migrates into one of the lattice sites and displaces the lattice atom, which becomes an
interstitial atom at the half-way position (Fig. Id).
By applying statistical thermodynamics, the activation energies and concentra-
tions of the point defects for a given crystal can be estimated and diffusion theory can
be developed.-' The theoretical results may then be compared with experimental find-
ings. For example, in the case of silicon, Group III and V elements are generally con-
sidered to diffuse predominately by the vacancy mechanism. Group I and VIII ele-
ments have small ionic radii, and they are fast diffusers in silicon. They are usually
considered to diffuse by an interstitial mechanism. These simple atomic mechanisms
are not adequate for describing the diffusion when the impurity concentrations are

172 VLSI Technology
high, dislocations are present, or other impurities are present in high concentrations.
When the impurity concentration is low and the dislocation density is low, the impur-
ity diffusion can be described by a phenomenological law of diffusion, that is, by
using Pick's diffusion law with a constant diffusivity. Mathematical expressions are
obtained by solving Pick's diffusion equation and the diffusivities of the diffusant are
determined for different temperatures. Por high-impurity concentrations,
concentration-dependent diffusivities are related to an assumed atomistic-diffusion
mechanism or mechanisms.
5.3 PICK'S ONE-DIMENSIONAL DIFFUSION EQUATIONS
In 1855 Pick published his theory on diffusion. He based his theory on the analogy
between material transfer in a solution and heat transfer by conduction. "*
Pick assumed
that in a dilute liquid or gaseous solution in the absence of convection, the transfer of
solute atoms per unit area in an one-dimensional flow can be described by the follow-
ing equation:
d.X
where J is the rate of transfer of solute per unit area or the diffusion flux, C is the con-
centration of solute, which is assumed to be a function of .v and t only, x is the coordi-
nate axis in the direction of the solute flow, t is the diffusion time, and D is the diffu-
sion coefficient.
Equation 1 states that the local rate of transfer (local diffusion rate) of solute per
unit area per unit time is proportional to the concentration gradient of the solute and
defines the proportionality constant as the diffusion coefficient of the solute. The
negative sign on the right-hand side of Eq. 1 states that the matter flows in the direc-
tion of decreasing solute concentration (i.e., the gradient is negative). Equation 1 is
called Pick's first law of diffusion.
Prom the law of conservation of matter, the change of solute concentration with
time must be the same as the local decrease of the diffusion flux, that is,
dCjxj) ^ _ dJ(xj) ^2)
dt dx
Substituting Eq. 1 into Eq. 2, yields Pick's second law of diffusion in one-dimen-
sional form:
dCixj) ^ _±_
dt dx
^
dC{x,T)
dx
(3)
When the concentration of the solute is low, the diffusion coefficient can be con-
sidered as a constant, and Eq. 3 becomes
dCjxj) ^ ^
d~Cixj)
^4^
dt dx-

Diffusion 173
Equation 4 is often referred to as Pick's simple diffusion equation. In Eq. 4. Z) is
given in units of cm-/s and C (x,t) is in units of atoms/cm Sometimes D is also
expressed in |jLm-/h. Solutions for Eq. 4 with various simple initial and boundary
conditions have been obtained."^
**
The most commonly used solutions are given in the
following section.
5.3.1 Constant Diffusivities
Impurity diffusion for junction formation can be achieved easily under two condi-
tions, namely, a constant surface concentration condition and a constant total dopant
condition. In the first case impurity atoms are transported from a source vapor onto
the silicon surface and diffused into silicon wafers. The source vapor maintains a
constant level of surface concentration during the entire diffusion period. In the case
of a constant total dopant, a small amount of dopant is deposited onto the silicon sur-
face. Mathematically, this instantaneous deposition of dopant is like a delta function.
This condition can be achieved by diffusion at low temperatures, as in predeposition
diffusion. Diffusion from an ion implanted layer is similar to the second case. This
section gives solutions of Pick's diffusion equation, Eq. 4, for these two cases.
Constant surface concentration The initial condition at r = is
C(A-,0) = (5)
The boundary conditions are
C(O.r) = C, (6)
and
Ci^.t) = (7)
The solution of Eq. 4 that satisfies the initial and boundary conditions is given by
C (.V, r ) = Q erfc
2Dt
(8)
where Q is the constant surface concentration (in atoms/ cm-^). D is the constant
diffusion coefficient (in cm-/s), x is the distance coordinate (in cm), with .v = at
the silicon surface, t is the diffusion time (in s). and erfc is the complementary error
function.
Pigure 2 shows the normalized concentration profile for a complementary error
function distribution of Eq. 8. The position where the diffusant concentration equals
the substrate concentration is defined as the metallurgical junction a^, that is,
Ci.Xj) = Csub- Assuming that the substrate conductivity is opposite that of the dif-
fusant. and since the ordinate is a logarithmic scale, | C^ub/Q I
can be plotted to
show the concentration of the net dopants
N^ — N^
near a p-n junction.
Constant total dopant Suppose that a thin layer of dopant is deposited onto the sili-
con surface with a fixed (or constant) total amount of dopant S per unit area, and that

174 VLSI Technology
z/dT
Fig. 2 Normalized complementary error function distribution.
the dopant diffuses into the sihcon. The silicon substrate has an impurity concentra-
tion Csub (in atoms/cm^) of the opposite conductivity. The initial and boundary con-
ditions and the solution of the diffusion equation (Eq. 4) that satisfies these conditions
are given in Eqs. 9 through 13.
Initial condition:
Boundary conditions:
C(jc, 0) =
X,
r C{x,t) dx = S
Jq
C (x, ^) =
The solution of the diffusion equation Eq. 4 that satisfies Eqs. 9 through 1 1 is
S
Cixj) = exp
By setting jc = we obtain the surface concentration,
S
ADt
Cs = C(0,r) =
VttD7
(9)
(10)
(11)
(12)
(13)
Equation 12 is often called the Gaussian distribution and the diffusion condition is
referred to as the predeposition diffusion.

Diffusion 175
Redistribution diffusion In bipolar linear ICs, redistribution diffusion from a
predeposition diffused layer is an important step. The redistribution diffusion in a
nonoxidizing ambient has been studied extensively. In VLSI technology, no inten-
tional rediffusion is applied in order to keep the diffusion depth shallow. From an ion
implanted source, however, some redistribution diffusion can occur while thermally
annealing the ion implanted region for electrical activation at temperatures greater
than 1000°C. The solution to Pick's equation, Eq. 4, with an initial ion implanted
Gaussian distribution has been obtained.^
The equation for redistribution diffusion in an oxidizing ambient involves a mov-
ing boundary problem and is more difficult to solve. No analytical solutions have
been found. A mathematical formulation of diffusion in an oxidizing ambient from a
given initial profile has been obtained;'' however, the solution involves expressions
that require numerical integration. Segregation of impurity atoms during oxidation
between the growing oxide and silicon was discussed in Chapter 4. Since redistribu-
tion diffusion is not important in VLSI technology, we will not discuss it in this
chapter.
5.3.2 Concentration-Dependent Diffusivities
At high concentrations, when the diffusion conditions are close to the constant surface
concentration case or to the constant total dopant case, the measured impurity profiles
deviate from Eqs. 8 and 12, respectively. In these high-concentration regions, the
impurity profile can often be represented by concentration-dependent diffusivities.
Equation 3 is used to determine the concentration-dependent diffusivities from the
experimentally measured concentration profiles. This section considers diffusion
under two conditions: constant surface concentration and a constant total dopant.
Constant surface concentration The one-dimensional diffusion equation with a
concentration-dependent diffusion coefficient was given in Eq. 3. If D is only a func-
tion of the concentration C and the surface concentration is maintained at a constant
value, Eq. 3 can be transformed into an ordinary differential equation"^ with a new
variable iq, where
m =
^ (14)
Thus, both D and C depend on x implicitly. After a change of variable to t], Eq. 15
can be obtained from Eq. 3:
-V2/^ T] dC
D(C) = -^ (15)
dT
Equation 15 refers to an infinite system. To determine the concentration-dependent
diffusivity from Eq. 15, we first plot the measured diffusion profile as concentration
(or normalized concentration) versus r (see Fig. 3). We choose the origin of the
abscissa so that the area under the profile on the left-hand side equals the area under

176 VLSI Technology
SILICON
SURFACE
Fig. 3 The diffusion coordinate for the Boltzmann-Matano analysis for concentration-dependent diffusivity
D(C). Constant surface concentration.
the profile on the right-hand side. The concentration-dependent diffusivity can then
be determined by performing the numerical integration
L Ti dC or Co r V (C/Co)
and calculating the slope dC / dr for each value of t| over the region where the dif-
fusivity is not constant. To the left of the origin, r has negative values. Experimen-
tally, the condition that C is only a function of r can be checked by plotting x versus
(/)'/2 for a given value of concentration. (We should observe a straight-line relation-
ship.) The above derivation is called the Boltzmann transformation. Matano used this
method to study the interdiffusion of alloys across the interface of two metals. Thus
this method is also called the Boltzmann-Matano analysis.
Constant total dopants Equation 15 requires the concentration at a distance far to
the left of 71=0 (Fig. 3) to remain invariant with diffusion time. In most device fabri-
cations, the diffusion is done after the introduction of the impurity into silicon; thus,
Eq. 15 can not be used to determine the concentration-dependent diffusivity from the
measured concentration profiles. For example, Eq. 15 is not applicable to redistribu-
tion diffusion from a high-concentration predeposition-diffused layer or an ion
implanted layer at high ion doses. An alternative expression is used to remove the
constant surface-concentration condition and it is replaced by a requirement that the
total dopant remain invariant with diffusion time (i.e., constant total dopant).^' ^ This
requirement is expressed as
DC
5 = J C(x,t) dx constant (16)
where S is the total dopant per unit area in the diffused layer and is independent of the
diffusion time. Equation 16 has been applied to the redistribution diffusion of arsenic
from an ion implanted layer. '^ The expression for determining the diffusion coeffi-
cient from the concentration profile is given by
D
CiXQj)
C.
-C(.Yo.r).V(
2t
dC_
dx
(17)
-V =.Vo

Diffusion 177
where Q is the surface concentration, xq is the location at which D is determined,
and (dC I dx )^ =v is the concentration gradient oix — xq.
For diffusion in an oxidizing ambient, assuming that the oxidation rate is a Hnear
function of diffusion time, the equation corresponding to Eq. 17 is
D
C(xoJ)
C.
-C(XoJ) (Xq + d)
It
dC
dx
(17a)
-V =.Vo
where d is the oxide thickness, which equals 2vr, and v is the inward velocity of the
oxidizing silicon surface. Since Eq. 17a is derived under the assumption of a constant
total dopant, when impurity atoms are incorporated into the oxide layer, this assump-
tion is violated. For example, for boron redistribution in an oxidizing ambient, the
total amount of boron in silicon is not a constant (refer to Chapter 4) and thus Eq. 17a
can not be used.
5.3.3 Temperature Dependence of the Diffusivities
The diffusion coefficients determined experimentally over a range of diffusion tem-
peratures can often be expressed as
D = Dq exp
kT
(18)
where Dq is the frequency factor (in cm^/s), E is the activation energy (in eV), T is
temperature (in K), and k is the Boltzmann constant (in eV/K). Thus when D is plot-
ted versus l/T on semilogarithmic coordinates, D is a straight line with slope E/kT.
From the atomic diffusion theories involving the defect-impurity interactions, Dq is
related to the atomic jumping frequency or the lattice vibration frequency (typically
10'^ Hz) and a jumping distance of an impurity, a defect, or defect-impurity pairs. At
the diffusion temperatures Dq can often be considered temperature independent. The
activation energy E is related to the energies of motion and the energies of formation
of defect-impurity complexes.
In metals and for some elements in silicon for a simple vacancy diffusion model,
E is between 3 and 4 eV, while for the interstitial diffusion model E is between 0.6
and 1.2 eV. Thus by measuring the diffusivity as a function of temperature, we can
determine whether the diffusion is dominated by an interstitial or vacancy mechan-
ism. For fast diffusants, the measured activation energies are generally less than 2 eV
and the diffusion mechanism is considered to be related to interstitial atom move-
ments.
5.4 ATOMISTIC DIFFUSION MECHANISMS
The concept of point-defect impurity interaction and their effects on impurity diffu-
sion are further developed in this section. Experimental results for impurity diffusion
at low concentrations follow the phenomenological description of the diffusion pro-
cess defined by Pick's diffusion law with a constant diffusion coefficient. The upper

178 VLSI Technology
limit of the dopant concentration for which the diffusion coefficient is a constant can
be estimated from the intrinsic carrier concentrations /?, at the diffusion temperature.
When the impurity concentration C (,v ) is less than Hj , the diffusion results can be
described by a concentration-independent diffusion coefficient, and Eqs. 8 and 12 in
Section 5.3, with the appropriate boundary conditions, can be used to determine the
diffusion coefficients from the measured diffusion profiles. The diffusion coefficient
at low concentrations is often referred to as the intrinsic diffusion coefficient D,.
When the impurity concentration, including both the substrate doping and the dif-
fusant, is greater than rijiT), the silicon is considered as extrinsic silicon and the dif-
fusivity is considered as the extrinsic diffusivity Dg . Experimentally measured values
of D, and D^ for boron, phosphorus, arsenic, and antimony are summarized in Sec-
tion 5.5.
To understand the diffusion process at high-concentration levels and the physical
mechanisms for the impurity diffusion at various concentration levels, atomic models
of solid-state diffusion have been proposed and compared with experimental measure-
ments. The atomic mechanism of solid-state diffusion was established from the diffu-
sion study in metals. The vacancy mechanism is most probable in a cubic face-
centered crystal." Diffusion in silicon can be described by mechanisms involving
impurity and point-defect interactions with the point defects at different charge states.
Point defects can become electrically active when they accept or lose electrons.
A vacancy can be charged to act as an acceptor with a negative charge, V~
.
V + e <=> V~ (19)
Similarly an interstitial atom can be charged to act as an accepter/";
I + e <=> /- (20)
where V represents a vacancy and / represents an interstitial . These concepts of ion-
ized point defects have been applied to impurity diffusion in silicon with varied suc-
cess. It has been found that both vacancy and interstitial atoms can be neutral, singly
charged, or doubly charged. The probability of a charge state higher than 2 is very
small. The exact mechanisms that dominate a diffusion process depend on the species
under consideration; in many cases a consensus can not be reached.'"
Equations 19 and 20 express equilibrium reactions, so the law of mass action can
be applied to determine the equilibrium constants. The law of mass action states that
the equilibrium constant of a chemical reaction in the gas phase can be expressed in
terms of the chemical activity of the reactants and products. Consider a simple rever-
sible chemical reaction
aA + bB <=> cC (21)
The equilibrium constant of the reaction towards the right-hand side is
K, = ^-^ (22)
«c

Diffusion 179
where K^, is the equihbrium constant, a^ is the cheniical activity of element A, % is
the chemical activity of element B, qq is the chemical activity of the product C, and
a.h, and c represent the mole concentration of elements A, fi, and C of the reaction
shown in Eq. 21. For a dilute solution (a near ideal solution), the activities can be
replaced by the concentrations^ of the reactants and products according to Rault's law,
and Eq. 22 becomes
K^
CY
(23)
where [A] is the concentration of element A, {E is the concentration of element fi,
and [C] is the concentration of element C.
The law of mass action has been applied to dilute solid solutions where point
defects in a solid are considered as dilute solid solutions of defects in the crystal lat-
tice. The law of mass action is applicable to a dilute solid solution when the reactions
are in thermal equilibrium and sometimes applicable when the reactions are in quasi-
thermal equilibrium.
Vacancy and interstitial concentrations can be determined from statistical ther-
modynamics. They are expressed in terms of entropies of formation AS and forma-
tion energies A//. For a neutral monovacancy in silicon, the concentration Cy can be
expressed as
20
C^, =5.5 X 10-^ exp
'as^5
k
exp
kT
(24)
where XSy is the entropy of formation of a neutral monovacancy, A//v is the forma-
tion energy of a neutral monovacancy (expressed in eV). The superscript x represents
a neutral charge state of the defect. The subscript V denotes a vacancy defect.
For silicon. A/Zy is estimated to be greater than or equal to 2.5 eV and AS'v is
estimated to equal 1.1^. Thus the intrinsic concentration of monovacancy at the dif-
fusion temperatures of interest is rather low for silicon.
For an extrinsic silicon, the acceptor-type vacancy concentration can be
expressed as'^
1 + T^ exp
Cv" =
Ey - E,
kT
1 + ^/2 exp
Ev - Ef
QiV-)
Ey ~ Ej
kT
Ey - Ef
kT
kT
Q(V-)
(25)

180 VLSI TECHN0LCX3Y
for (Ey — Ef)'»kT and {By — Ei)y>kT. Cy is the acceptor vacancy concentration
in the extrinsic siHcon, C, (V") is the acceptor vacancy concentration in the intrinsic
sihcon, Ey is the acceptor vacancy energy level (in eV), £, is the intrinsic Fermi level
(in eV), and Ef is the Fermi level of the extrinsic silicon (in eV). Thus,
C,
exp
C,{V-)
But for the nondegenerate case, we obtain
n = /I, exp
for n-type silicon, and Eq. 26 becomes
Cy-
Ei
kT
Ef - Ei
(26)
kT
(27)
If the impurity diffusion is dominated by the acceptor monovacancy mechanism, the
diffusion coefficient is approximately proportional to the acceptor monovacancy con-
centration. Thus, we have
-^ = ^ (28)
D, n,
where D is the diffusion coefficient in extrinsic silicon, and D, is the diffusion coeffi-
cient in intrinsic silicon.
The intrinsic carrier concentration /i, can be calculated using the following empir-
ical formula:
'*
where
n] = 1.5 X 10-^3 j2>
expt(-1.21 + ^Eg)/kT]
•/2
^Eo = -7.1 X 10"
T
(29)
(30)
and an assumed fg = 1.21 eV.
Equation 28 states that the interaction of the impurity atoms with charged accep-
tor vacancies leads to a dependence of the diffusion coefficient on the Fermi level at
the diffusion temperature. Since vacancies and interstitials can have various charge
states, Eq. 28 can be generalized to include all possible combinations of impurity-
point defect interactions.'^
D = D' + % iD-') + t (E>^')
n,
(31)
where D x for neutral defects, (D "''
), and (D ^^ ) refer to the intrinsic impurity dif-
fusivities associated with the particular charge states, r, of the point defects that affect
the impurity diffusion and r is an integer 1, 2, 3, . .
.
, m. For example, D^ represents
the intrinsic diffusivity of impurity interaction with a neutral-point defect; (D "), (r =

Diffusion 181
1) represents the intrinsic diffusivity of impurity interaction with a singly charged
acceptor-point defect; and (D ^) represents the intrinsic diffusivity of impurity interac-
tion with a singly charged donor-point defect. The exponent r in {D~^) and [D^'^)
corresponds to the charge state of the point defect. For example, {D'^) (or D^~)
represents the intrinsic diffusivity of impurity interacting with doubly charged accep-
tor defects, and the corresponding contribution to the diffusivity is D^~ {n / rii)^. The
superscript r in Eq. 31 does not represent an exponent for (D "''
) and (D ^''
) but it is
the exponent for {n / HiY and («, / n Y terms. Thus when Eq. 31 is used to fit experi-
mental profiles with defects of different charge states, it does not specify the dominat-
ing diffusion mechanism or mechanisms. The exact mechanisms, either vacancy or
self-interstitial type, involved in the impurity-defect interaction during the diffusion
process have to be determined from other experimental evidence and/ or theoretical
considerations. We can therefore consider Eq. 31 as a phenomenological expression
of the concentration dependence of the diffusion coefficients, which provides a
description of diffusion phenomena by extending Pick's diffusion equation (Eq. 3).
The concentration-dependent diffusion coefficient can be determined from the
experimental diffusion profiles without knowing the details of the atomic diffusion
mechanisms. However, the measured diffusion coefficients as a function of diffusion
temperature can sometimes be fitted to appropriate impurity-point defect interaction
models.
Isolated point defects in silicon are generated at or below room temperatures by
high-energy (^ 1 MeV) electron, x-ray, or neutron irradiations. When these defects
are in various charge states, their electronic states and annealing properties can be
studied by electron paramagnetic resonance (EPR) measurements,'^ by infrared
absorption spectra analysis'^ for neutral defects, and by other techniques. The deep
level transient spectroscopy (DLTS) method has also been used to study electrically
active defects in proton-bombarded silicon crystals.'^ Theoretical calculations of
these defects have also been made, using various models of the charge states of these
point defects and their annealing properties to explain the experimental observations.
For vacancies in silicon, the EPR and optical absorption studies have identified four
charge states (V^, V^, V~, and V"~), where V^ is a donor vacancy, V^ a neutral
vacancy, V an acceptor vacancy, and V-~ a doubly charged acceptor vacancy.'^
Figure 4 shows a few examples of the geometrical configurations of vacancy and
interstitial point defects which have been established from theoretical and experimen-
tal studies. These three-dimensional models can be used to calculate the activation
energies and entropies of defects with different charge states. Figure 4a shows the
atomic arrangements of two tetrahedra in a silicon crystal lattice, and Fig. 4b shows a
simple vacancy. Figure 4c shows one of the possible configurations of a divacancy
which has atoms missing from two neighboring bonds'^ (the dotted circles in Fig. 4c).
Three kinds of interstitials have been used to calculate theoretically the characteristics
of the observed defect configurations, namely, the simple tetrahedron (Fig. 4d), the
bond centered (Fig. 4e), and the (110) split interstitial^^ (Fig. 4f). In a unit cell, the
positions for the five interstitial sites are (1/2, 1/2, 1/2), (1/4, 1/4, 1/4), (1/4, 3/4,
3/4), (3/4, 1/4, 3/4), and (3/4, 3/4, 1/4).
The investigations of point-defect formation by studying the radiation effects
have provided fundamental information on the defect configurations, energies, and

182 VLSI Technology
(b)
(c) (d)
(f)
Fig. 4 Geometrical configurations of vacancy and interstitial point defects, (a) 8 Si atoms form two adja-
cent tetrahedral bonds, (b) A simple vacancy, (c) Divacancies. (d) A simple tetrahedral interstitial,
(e) A bond centered interstitial, (f) An(lOO) split interstitial.
entropies of formation and migration. This information is used to analyze atomic dif-
fusion mechanisms in silicon from the measured diffusion coefficients as a function of
temperature.
Researchers have reasoned that silicon and Group III and V elements in silicon
should have a similar diffusion mechanism. Thus extensive efforts have been made to
study silicon self-diffusion. The measured silicon self-diffusion coefficients Ds; can
be explained by a vacancy model^' involving neutral vacancies V' singly charged
acceptor vacancies V, doubly charged acceptor vacancies V^~ , and singly charged
donor vacancies V"^:
Dci = Dl, + DcT —
r ^
2
n
+ Die
n
+ ^st
Hl
th n, n
with
Dl. =
D<
0.015 exp
16 exp
-3.89 eV
p
kT
4.54 eV
-
kT
(32)
(33)
(34)

Diffusion 183
>st
= 1180 exp
5.09 eV
Dir- = 10 exp
AT
-5.1 eV
kT
(35)
(36)
The values for D^" in Eq. 36 are estimated values with activation energy close to that
of Z)st ^d a. Dq — 10. Figure 5 shows the silicon self-diffusivity versus tempera-
ture. The units for all the diffusivity expressions are cm~/s. Thus the effect of Dsf
can be neglected in Eq. 32. Although the study of irradiation of silicon established
the existence of V~~, it contributes little to the silicon self-diffusivity. The V^~
becomes significant for high-concentration phosphorus diffusion, which we shall dis-
cuss later.
Similarly, over a narrow range of high temperatures, the silicon self-diffusion
data can be expressed in terms of Dsi- Ds". and Dsj with activation energies 5.23,
4.84, and 3.91 ev, respectively.'^ Note that these values for the activation energies for
Dsi and Dst are almost opposite to those of Eqs. 33 and 35. Calculations of diffusion
coefficients using experimental data and Eq. 31 are very sensitive to the accuracy of
these data, and thus, these results represent approximations. As the accuracy of the
T(°C)
1300 1200 1100 1000 900 800 700
Fig. 5 Silicon self-diffusivity vs. temperature.
X 10'^ cm"^; A arsenic doped to 8 x lO'^ cm"
(After Fair, Ref. 21.)
lO'*/! (K"')
• and Z intrinsic silicon; A boron doped to 2.5
;
phosphorus doped; o nickel doped in intrinsic silicon.

184 VLSI Technology
measurements improves, theoretical models also improve. A neutral self-interstitial
mechanism for silicon self-diffusion over a temperature range of 1050° to 1380°C has
also been proposed."- However, the mechanism for silicon self-diffusion has not been
clearly resolved.
5.5 MEASUREMENT TECHNIQUES
Diffusivity, an important parameter in diffusion study, must be determined experi-
mentally. This section discusses measurement techniques for determining diffusivi-
ties in diffusion study.
5.5.1 Junction Depth and Sheet Resistance
Diffusion results can be checked by two simple measurements, the junction depth and
the sheet resistance of the diffused layer. The junction depth is commonly measured
with a chemical staining of a beveled (1 to 5°) sample in a mixture of 100 cm^^ HF
(49%) and a few drops of HNO3. Sometimes HF alone is sufficient. If the sample is
put under a strong illumination for a minute or two, the p-type region will be stained
darker than the n-type region. With the aid of the interference-fringe techniques of
Tolansky,^^ the junction depths can be measured accurately from 0.5 to over 100 |xm.
The sheet resistance of a diffused layer can be measured by a four-point probe
technique (Section 1.3). A geometric correction factor is required to convert the
measured resistance WII into sheet resistance (also called the sheet resistivity). This
factor is a function of the sample size, shape, and the probe spacings. The sheet resis-
tance Rs is given by Eq. 37, and the correction factors for simple circular, rectangu-
lar, and square samples are given^"^ in Table 1
.
^. = y C.F. (37)
where R^ is the sheet resistance of a diffused layer (in H/c); V is the measured dc
voltage across the voltage probes (in volts); / is the constant dc current passing
through the current probes (in amperes); and C.F. is the correction factor that is a
function of the sample geometry and the probe spacings.
The correction factors for a circular sample (with a diameter d) and a rectangular
sample (with the side parallel to the probe line as a and that perpendicular to the probe
line as J) are given in Table 1 (where s is the probe spacing). Note that for a large
dis, the correction factor approaches that of a two-dimensional sheet extending to
infinity in both directions, that is, C.F. — 4.53. For the correction factors to be insen-
sitive to the sample size and the positions of the probe points with respect to the sam-
ple edge, a large dis is desirable. Equation 37 and the correction factors in Table 1
are valid only for shallow junctions which are diffused only on the front side of the
sample. Diffusion from a chemical source will have the diffused region wrapped
around the sample. The back side of the diffused layer has either to be removed or
isolated from the front side; otherwise a different correction factor should be used.
When measuring a shallow diffused layer at low concentrations, reliable meas-
urements free of noise are difficult to make. This problem is sometimes overcome by

Diffusion 185
Table 1 Correction factor C.F. for the measurement
of sheet resistances with the four-point probe-^
Circle Square
Rectangle
d/s diam d/s a/d^ 1 a/d = 2 a/d = 3 a /d^4
1.0 0.9988 0.9994
1.25 1.2467 1.2248
1.5 1.4788 1.4893 1.4893
1.75 1.7196 1.7238 1.7238
2.0 1.9475 1 .9475 1 .9475
2.5 2.3532 2.3541 2.3541
3.0 2.2662 2.4575 2.7000 2.7005 2.7005
4.0 2.9289 3.1137 3.2246 3.2248 3.2248
5.0 3.3625 3.5098 3.5749 3.5750 3.5750
7.5 3.9273 4.0095 4.0361 4.0362 4.0362
10.0 4.1716 4.2209 4.2357 4.2357 4.2357
15.0 4.3646 4.3882 4.3947 4.3947 4.3947
20.0 4.4364 4.4516 4.4553 4.4553 4.4553
40.0 4.5076 4.5120 4.5129 4.5129 4.5129
oc 4.5324 4.5324 4.5325 4.5325 4.5324
measuring the voltages for current flowing in two directions, and then averaging the
two readings. This average reading removes some of the effect of contact resistance.
If the voltage differences are large, however, probe points and the cleanliness of the
sample surface should be checked. To ensure that the readings are correct, the sheet
resistances at two or three current levels can be measured. These measurements show
whether the measured sheet resistances are constant over the range of measured
currents. For high-resistivity silicon, annealing the sample in N2 at 150°C for a few
minutes improves the accuracy of readings. Always try to use as low current as possi-
ble to avoid ohmic heating or to avoid reaching the punchthrough voltage.
For a diffused layer, an average sheet resistance R^ is related to the junction
depth Xj , the carrier mobility ji, and the impurity distribution C (x ) by the following
expression:
Rs =
-r-^ (38)
^ X' M-CU) dx
The depletion of charge carriers near Xj can be neglected in the above calculation. In
general, the mobility is a function of the total impurity concentration, and often an
effective mobility is defined as
P x[C{x)]C(x)dx
^Jleff - -—V (39)
fJC{x)dx

186 VLSI Technology
Equation 38 can be expressed as
Rs =
jj
(40)
^M-eff
X' C{x) dx
For a given diffusion profile, the average resistivity, p — Rs Xj , is uniquely related to
the surface concentration of the diffused layer and the substrate dopant concentration
for an assumed diffusion profile. Design curves relating to the surface concentration
and the average resistivity (or the average conductivity) have been calculated for sim-
ple diffusion profiles, such as exponential, Gaussian, or erfc distributions. They are
often called the Irvin curves. ^^ To use these curves, be sure that the diffusion profiles
agree with the assumed profiles. For high concentration and shallow diffusions, the
diffusion profiles cannot be represented by these simple functions. The measured
sheet resistance and junction depth can not be used to find the impurity surface con-
centration or calculate the diffusivities of the diffused layer with the Irvin curves.
Since both the junction-depth measurement and the sheet-resistance measurement
are simple and give important information about a diffused layer without using ela-
borate profile measurements, they are used routinely for monitoring diffusion
processes. For ion implanted samples, sheet-resistance measurement is a simple
method to check the electrical activity (the combined effects of mobilities and carrier
concentrations) after the sample is annealed or diffused.
5.5.2 Profile Measurements
The diffusivities and the diffusion models that describe the diffusion results are self-
consistent for the diffusion conditions for which the diffusion profiles are determined.
The accuracy of the diffusion model and its associated diffusivities depends on the
correctness of the diffusion profile measurements which are indispensable in diffusion
studies. The simple measurements of the junction depth and the sheet resistance of a
diffused layer, although useful for process monitoring, are grossly inadequate for dif-
fusion study. A few commonly used techniques for diffusion profile measurements
and their limitations are discussed in the following sections.
C-V technique From the p-n junction theory, the space-charge capacitance is a func-
tion of the reverse-bias voltage. For the depletion approximation, this capacitance
can be treated as a parallel-plate capacitor. For an abrupt junction where the impurity
concentration is very high on one side of the junction and decreases to a low value
abruptly on the other side (i.e. an n"^p or p^n junction), the following expression^^
can be derived:
C(x) 2 = ^^ -j- (4.)
ae - — dV
^ '
dV C{V)

Diffusion 187
and
X =
C(V)
(42)
where C {x ) is the impurity concentration at the space-charge layer edge, C (V) is the
junction reverse-bias capacitance per unit area at a reverse voltage V, and e^ is the
dielectric permittivity of silicon. To avoid confusion in the symbols, C(jc) means
concentration and C (V) means junction capacitance. Now,
V = Vo + Vy (43)
where V/j is the applied reverse bias, and Vbi is the built-in potential of the p-n junc-
tion.
Vbi = — In r~ (44)
where C^ is the acceptor concentration, and Co is the donor concentration. Thus,
C{V) = q^s
C, Vu ± V,
2kT
^^- ((BVbi ± PV - 2)-'/2
flLo
(45)
where C5 is the substrate doping concentration, ^ = q / kT, and
Lo = the Debye length
kT
qCb q
(46)
Thus, Vbi can be determined from the junction capacitance at zero reverse bias from
Eq. 45. The C-V method is limited to a few Lp 's away from the depletion layer edge
at zero bias and it can not resolve the concentration distribution within a few L^'s.
The impurity profile can be determined by measuring the reverse-bias capacitance as
a function of the applied voltage from Eqs. 41 , 42, and 45.
Figure 6 gives an example of the measured C-V profiles for phosphorus
implanted then diffused samples by using a Schottky diode. The zero-bias space-
charge width is close to 0.1 |jLm. The phosphorus concentration in this surface region
can not be easily measured and has to be estimated. The diffusion was at 1 100°C for
15, 30, and 60 min in O2. Note that all three profiles (data points shown in Fig. 6)
can be represented by a Gaussian distribution (Eq. 12) with a constant diffusion coef-
ficient D = 2.34 X 10"'^ cm-^/s and a total phosphorus concentration of

188 VLSI Technology
10" r
CALCULATED
GAUSSIAN
PROFILES
3.0
Fig. 6 Phosphorus profiles from C-V measurement. Phosphorus implantation: ion energy = 30keV. ion
dose = 10'- cm"'. Diffusion at 1100°C in oxygen. Calculation 2Dt = 1.7 x 10"^ cm-, ^Rp- =
1.7 X 10"'- cm-.5 = 8 x lO" cm"-.D = 2.3 x 10"''' cm-/s.
S = 8 X 10" cm~- which is within 20% of the implant dose. The Ai?^" is one-
thousandth of 2Dt; thus the implanted profile can be assumed to be a delta function
(i.e., all the implanted atoms are confined to a very thin sheet with a total phosphorus
concentration S and less than 20% of the implant dose is incorporated into the oxide
film which was grown during the diffusion).
Differential conductivity technique Differential conductivity is one of the oldest
techniques for measuring the diffusion profiles in silicon by the electrical method.-^
This technique involves repeatedly measuring the sheet resistance of a diffused layer
by the four-point probe measurement after removing a thin layer of silicon by anodic
oxidation and etching the oxide off in HF solution. Because the anodic oxidation is at
room temperature, the impurity atoms do not move in the diffused layer during oxida-
tion and there is no segregation effect; hence, a true distribution profile can be deter-
mined. To use this technique, either the carrier mobility is measured by the Hall
effect measurement or the resistivity versus impurity concentration curves are used."^
Figure 23 of Chapter 1 gives the composite curves of the resistivities for boron- and
phosphorus-doped silicon over a wide range of concentrations. The polynomial fit-
tings for calculating the impurity concentration from resistivity measurements are
given in Ref. 28. The differential conductivity technique is not suitable for diffusion
study in VLSI process development.
Spreading resistance technique The C-V technique has a limited range of junction
depths and dopant concentration that can be used for profile measurement, and the
differential-conductivity technique is a time-consuming method for profiling diffused
layers. Various techniques have been investigated to improve the spatial resolution
and to reduce the measurement time, and as a result, the two-point probe spreading

Diffusion 189
resistance technique has been developed^^ for diffusion profile measurement. Since a
refined and improved instrument is commercially available, the spreading resistance
technique for diffusion profile measurement is becoming a routine evaluation tech-
nique.
For a two-point probe arrangement, the total spreading resistance is given by
R.r =
la
(47)
where R^^ is the spreading resistance, p is the average resistivity near the probe
points, and a is the probe radius. The spreading resistance technique is very sensitive
to local impurity concentration variations, that is, it has high spatial resolution. How-
ever, measurements are also sensitive to the sample surface and the conditions of the
probe points. Unless very elaborate measuring and checking procedures are con-
ducted, this technique is best used to compare an unknown sample with a sample of
known profile. For profile comparisons, this technique is often sufficient. Concen-
tration profiles, however, should be checked with another method such as the dif-
ferential conductivity method or the SIMS method to be discussed next. To convert
spreading resistance into concentration, various correction factors have been derived
for different boundary conditions. Because we have imprecise knowledge of these
correction factors and varying probe conditions, empirical calibration curves have to
be used. Often only the spreading resistance profiles are used for comparing different
treatment results. Figure 7 shows an example of the spreading resistance profile of a
transistor structure; the collector-base junction jc^b and the emitter-base junction Xgb
SAMPLE
P -
Fig. 7 The spreading resistance profile of an n-p-n transistor structure. .Vgj, = the emitter-base junction
depth — 1.7 |i.m;A,,(, = the collector-base junction depth = 3.2 |xm.

190 VLSI Technology
are clearly shown. The emitter region n"^ is phosphorus diffused and shows a kink in
the profile about 1.2 fxm from the surface. This kink in the phosphorus profile has
been extensively studied and it will be discussed in Section 5.6.3.
SIMS technique Chapter 12 discusses the principle and instrument design of the
secondary ion mass spectroscope (SIMS), an important tool for diffusion profile meas-
urement. ^°
Since the SIMS technique is not a primary measurement, converting the
secondary ion signal into concentration requires the use of either a standard sample or
certain established procedures that are described in the following paragraphs.
Two methods are often used to convert the secondary ion signal into concentra-
tion: (1) using the ratio of the ion yield of the element of interest to that of the host
element (^^^Si in the present case), and (2) using samples with known concentrations
as calibration standards. When the impurity concentration is high (10^^ atoms/cm^ ),
the ion-ratio technique is accurate and convenient. This technique provides an inter-
nal standard; ion signals of the elements are collected under the same measurement
conditions. Any change in the measurement or the equipment conditions will be seen
as a change of the ion yield of the host element. Because of the limitation of the
counting system and the presence of background ion counts, the range of the SIMS
measurement is between 10^ to 10"^. For example if the boron surface concentration is
in the range of 10^° atoms/cm-^, the measurement limit will be between lO'^ and lO'^
atoms/cm^, although the detection limit for boron in silicon is below lO'^ atoms/cm
In the second method, samples of known impurity concentrations are measured
under the same conditions as the sample for which the diffusion profile is measured.
The ratio of the ion counts are assumed to be proportional to the concentration ratios,
and the ion counts are assumed proportional to the atomic concentrations. With the
measurement conditions optimized, both assumptions have been verified for common
impurity elements in silicon. Ion implanted samples provide a convenient set of stan-
dards over a wide range of ion doses. Experiments have shown that the ion counts at
the peak concentration are a linear function of the ion doses, and that the integrated
ion counts are also a linear function of the ion doses for samples implanted at the
same energy. Both results establish the relationship that the secondary-ion counts are
linear functions of the atomic concentration of the element. Figure 8 shows an exam-
ple, for boron-implanted samples, of the peak ion counts versus ion doses and the
ratio of the peak ion counts to ^^°Si ion counts versus ion doses. For measuring the
diffusion profiles of ion implanted samples, integrated ion counts are preferred over
peak ion counts, because integrated ion counts are not sensitive to slight variations in
the measurement conditions.
The SIMS technique measures the total impurity profile. Thus, other electrical
methods should be used for determining the electrically active portions. Since the
sputtering rates generally range from less than one angstrom per second to several
tens of angstroms per second, this technique is suited for measuring diffusion profiles
for depths less than 1 or 2 |xm.
Figure 9 gives a few examples of measured profiles. Figure 9a shows the SIMS
profile of a phosphorus-diffused layer and, for comparison, profile measured by the
differential conductivity technique. Figure 9b shows the boron profile in Si02 and Si

Diffusion 191
10
5 10^
§ 10'^
10'
10''
10 10
BORON ION DOSE (cm-2)
J
I I M ml I LXJ_LLLU|o-3
15 ,^16
10"
Fig. 8 SIMS analysis calibration curves. Peak boron concentration versus boron ion dose and normalized
peak ion counts to ^^ Si ion counts versus boron ion dose.
1022
1021
i 1020 ^
10 bi I I I
I
' ' ' '
I
' ' '
M ' ' ' '
I
' ' '
'=
I02°k
— ,^19
io'« h-
10'
- I
'--I

'>
—Si02-
2I50A
16 I .... I I . I I I I I I I I I
'
.(2)
1000 2000 3000 4000 5000
X(A)
(b)
Fig. 9 Examples of SIMS profiles, (a) Phosphorus diffusion profile in silicon. Diffusion at 900°C for
30min. POCI3 source, o Differential conductivity data. • SIMS data. {After Fair. Ref.21.) (b) Boron
implanted profile in Si02 and Si. (1) Ion dose = 5 x lO'^^ cm^-, (2) Ion dose = 1 x lO'^ cm"^.
Implant energy = 50 keV.

192 VLSI Technology
from a sample which has a 2150 A thermal oxide and in which the boron was
implanted at 50 keV. In this case, the boron concentration at the interface is nearly
continuous. Nearly half of the implanted boron atoms are in the oxide layer. These
examples show that the SIMS technique is a powerful tool for profile determination
and will, therefore, be extensively applied to diffusion studies in VLSI technology.
Summary of profiling techniques Various other techniques have also been used for
impurity profile measurements. These techniques often require special laboratory set-
ups or special equipment, but are useful for independently determining the total
impurity concentration profile and to verify the results from the electrical or SIMS
measurement. Table 2 summarizes the measurement techniques discussed in the pre-
vious sections and others that were not discussed in detail but are mentioned here.
The Rutherford backscattering (RBS) technique has been used for measuring dis-
tributions of heavy elements (such as arsenic, platinum, gold, etc.)^^-^ in silicon but
cannot be used for measuring boron or phosphorus profiles. In this technique high-
energy helium ions ( 1 to 3 MeV) are used as the incident ion beam, and the backscat-
tered He ion energy-loss spectra are analyzed. A few nuclear reaction processes have
been used for measuring the boron atom distribution nondestructively. For example,
thermal neutrons interact with "^B, causing the emission of monoenergetic "^He ions
at 1471 keV.^-^ By analyzing the energy losses of the helium ions, the depth of boron
atoms can be determined from the specific-energy loss spectra of "^He ions in silicon,
which are measured experimentally. The boron concentration can be related to the
^Li particle signals at 839 keV (94%) and 1014 keV (6%) that are generated in the
Table 2 Commonly used diffusion profile measurement techniques
Profile techniques Characteristics Ref
.
Capacitance-Voltage Carrier concentration at the edge of the depletion layer of a p-n 26
junction. Maximum total dopants 2x lO'- atoms/cm-.
Differential conductance Resistivity and mobility of net electrically active species. Requires 27
and Hall effect thin layer removal . 1
0^*^
to 1 ' ^ atoms/ cm-'
.
Spreading resistance Resistance on angle beveled sample. Good for comparison with 29
known profiles and quick semi-quantitative evaluation. Depth >1
ixm.
SIMS High sensitivity on many elements, for B and As detection limit 30
5 X 10'^ cm~^. Capable of measuring profiles in 1000 A range.
Needs standards.
Radioactive tracer Total concentration. Lower limit lO'^ cm"^^. Limited to radioac- 31
analysis tive elements with suitable half-life times: P, As, Sb, Na, Cu, Au,
etc.
Rutherford backscattering Only applicable for elements heavier than Si. 32
Nuclear reaction Measures total boron through '°B(«, ^He)''Li, or "B(p, a). 33
Needs Van de Graaff generator. 34

Diffusion 193
nuclear reaction of "^B(«/He)''Li. Another nuclear reaction for measuring boron
profiles involves the use of a proton beam at 400 keV which reacts with
^
' B in sili-
con.^"* The energy spectra of the a-particles from their reaction have been analyzed.
This reaction is expressed as " B(/?, a). For boron implanted profiles, the results of
this method and of the SIMS method agree.
5.6 DIFFUSIVITIES OF B, P, As, AND Sb
In VLSI technology, boron, phosphorus, arsenic and sometimes antimony are used as
dopant elements for junction formations. Hence, the diffusivities of these elements
are of interest and they are summarized in this section. We give both the intrinsic and
extrinsic diffusivities. By applying the vacancy-impurity diffusion model for multiple
charge states, we can tentatively identify the species contributing to the diffusivities.
Since this diffusion theory is still being developed, the identification of these species
has not been confirmed. Various effects on the diffusion results at high-concentration
levels and impurity interactions are also discussed.
5.6.1 Low-Impurity Concentration Diffusion into Intrinsic Silicon
Table 3 shows the intrinsic diffusivities"' of boron, phosphorus, arsenic, and
antimony in terms of a frequency factor Dq and an activation energy E. The expres-
sion of the diffusivity as a function of temperature was given in Eq. 18.
According to the multiple-charge-state vacancy model, the boron intrinsic dif-
fusivity is dominated by the interaction of boron with the donor-type vacancy V "^
and
is designated as (D,'^)b. For phosphorus, the intrinsic diffusivity is dominated by
interaction of impurity atoms with the neutral vacancy V* and is designated as {Df )p.
For arsenic, three sets of Dq and E are given in Table 3. Since each set of data
represents the measured values for the experimental conditions studied and all of them
Table 3 Intrinsic diffusivity of B, P, As and Sb
Arsenic
Unit Boron Phosphorus CS PD IS Antimony
(A^)b (AMp (A^)as iDth^
^0 cm-/s 0.76 3.85 24 22.9 60 0.214
E eV 3.46 3.66 4.08 4.1 4.2 3.65
*CS are results from chemical source and PD are results from predeposition diffusion of ion
implanted ^^ As and low-concentration predeposited layers (Ref. 10). IS are the results from iso-
concentration diffusion experiments (Ref. 35).

194 VLSI Technology
T rc)
1300 1200 1100 1000 900
T(°C)
300 1200 1100 1000 900 800
7.0 7.5 8.0
IO''/T{K"')
8.0 9.0 9.5
0''/T (K"')
(b)
Fig. 10 Intrinsic diffusivities vs. temperature, (a) Boron: • . A, r. Bdata from diffusion in intrinsic sili-
con; A data from diffusion in n-type silicon doped to 1 .5 x 10-^*^
cm~ o data from diffusion in p-type sili-
con doped to 5 X lO'^ cm^"*. (b) Phosphorus: • . A, data from diffusion in intrinsic silicon; o. A, D
data from high-concentration p diffusion; V data from diffusion in extrinsic silicon.
are within the scattering of the measurement, no attempt is made to express prefer-
ences for any of them. In Table 3, D, represents the impurity intrinsic diffusivity,
(D, )b for boron, (A )p for phosphorus, and so on.
Figure 10a through d summarizes the diffusivities of boron, phosphorus, arsenic,
and antimony as functions of diffusion temperatures. Detailed descriptions of the
experimental data on which the parts of this figure are based are given in reference
21.
5.6.2 The Electric-Field Effect
When impurity atoms are ionized at the diffusion temperature, a local electric field is
set up between the ionized impurity atoms and the electrons or holes. The concentra-
tion gradient of these ionized impurity atoms (donors or acceptors) produces an inter-
nal electric field that enhances the diffusivity of the ionized impurity atoms. This
internal electric field is related to the electrical potential ^{x ) as
E, = - ^ <^(x,t} (48)
dx

T (°C)
1300 1200 1100 1000 900
M
^ 10-'"
J
E
10-15
IO-'8
- ] 1 1
AX V —D» *D-
. lARSENICl :
^V^ —
= -
= Vf ^ _

' N^ ^ _
V 'A
r %

-07(4.05 eV)-''^^

^D*(3.44 eV) -^
"^-^
—
~
*s >^ -
- N1^.
y^ -
— ^v^ ^
- y *. 3
- y^
_ CALCULATED -''
^
= (3.42 eV)
^
- i&^Nx I
— —
^
N
1 1
1
1
60 6.5 7,0 7.5 8.0 85 9.0
ioVt(k-I)
(c)
Diffusion 195
TCC)
1300 1200 1100 1000 900
6.0 65 7.0 7.5 8.0 85 90
lO^/T (K"')
(d)
Fig. 10 (continued) (c) Arsenic: • . . Z. c. A data from diffusion in intrinsic silicon; , V data from dif-
fusion in extrinsic silicon, (d) Antimony: o data from diffusion in intrinsic silicon; • data from diffusion in
extrinsic silicon. (After Fair, Ref. 21 .}
For a donor impurity, (t)(.v,r ) can be expressed as
(|)CT,r) = (Ec - EpMq (49)
where Ec is the conduction band energy and Ef is the Fermi level. Assuming that a
charge neutrality exists between the ionized donor and the electron and that all donor
atoms Njj are ionized, we have np = rij^ and N^ = «. It can be shown that
kT d ,
E^ = — — In
q dx
The diffusion flux in an electric field can be expressed as
d^D q
y = - qD—^ - qZD-^ No E,
dx kT
(50)
(51)
where Z is the charge state of the donor atoms. For a singly charged donor atom,
Z = 1. By substituting Eq. 50 into Eq. 51 and by changing variables from 6/6jc to
id I dNo )idNo / a.r ), Eq. 5 1 becomes
dNo

196 VLSI Technology
and
h = I + Z Nd -t- In —
^
dNo n,
where h is the electric-field enhancement factor. It can be shown that
(52)
/? = 1 +
A^r
2«, 1-
2/7,
n'/2
(53)
+ 1
When Nj^ I Irij » 1 , /z equals 2 which means that the maximum enhancement of the
diffusivity from the electric-field effect is 2. For an acceptor diffusion with the
electric-field enhancement, N^ should be subsdtuted for Nq in Eq. 53.
For phosphorus-diffused samples at temperatures below 900°C, an electric-field
enhancement of the diffusivity has been observed in which neutral vacancies V^ dom-
inate the diffusion and the measured D^ / Df resembles /?, as shown in Eq. 53. Figure
1 1 shows this electric-field enhancement for phosphorus.
5.6.3 High-Concentration Effects
This section briefly summarizes diffusion results of arsenic, boron, and phosphorus at
high concentrations, when the surface concentrations are greater than «, . Expressions
for diffusivities which are derived from the impurity-defect interaction diffusion
10
1.0
OJ,
_ r I T I M I 1 I 1 1 1 1 1 1 1.
CALCULATED
r ELECTRIC-FIELD "
ENHANCEMENT -
1 1 1
Mill
1
1
1
Z
0.1 1.0
C/Oj
10
Fig. 11 Electric-field-enhanced diffusion of phosphorus in siHcon at 9(X)°C. • data from diffusion of
phosphorus in silicon in the temperature range 875—900°C. (After Fair, Ref. 21.)

Diffusion 197
model are given. For high-concentration arsenic, we discuss a model for the cluster
formation of impurity atoms. This model explains the observation that only a portion
of the diffused arsenic atoms is electrically active at room temperature. Similar
results are also observed for high-concentration boron-diffused layers. Results from a
phosphorus diffusion model are also given.
Arsenic According to the multi-charge-state, impurity-defect interaction model, the
arsenic diffusivity can be expressed as^^
Das = (2«/n,)(D,)As (54)
Equation 54 is similar to Eq. 28; the factor 2 represents the electric-field effect. A
similar expression based on interactions of charge vacancy with arsenic is-^^
1 + yn In;
Das = —TT (A)as (55)
1 + 7
with 7 = 100 for donor-impurity diffusions. Thus, D^s calculated from Eq. 54 is
almost twice that of D as calculated from Eq. 55.
The electric activity of arsenic from ion implanted samples depends on the ion
dose and the annealing or diffusion temperatures. For arsenic-ion doses below
1 X 10^^ cm~~ and diffusion temperatures greater than 1000°C, nearly all of the
arsenic atoms are ionized and contributing to the electrical activities. '° However, for
diffusion temperatures below 1000°C and an arsenic-ion dose greater than 10^^ cm"'^,
the concentration of ionized arsenic is a fraction of the total arsenic, and the differ-
ences become greater^^ as the diffusion temperature decreases below 900°C.
The difference between the ionized and the total arsenic can be explained by an
arsenic clustering model. In this model, arsenic atoms form clusters that are partially
active when their concentration is above 10^^ cm~^. The most recent clustering
model consists of three arsenic atoms and one electron that are electrically active at
the diffusion (or annealing) temperature and electrically neutral at room tempera-
ture.^'' The model is expressed as
high temp. 25°C
3As+ + e- ^_^ AS3+2 _^ As3 (56)
Applying the law of mass action to the high-temperature region, the equilibrium con-
stant is
[AS3+2]
K^ = :, (57)
and the carrier concentration at the annealing/diffusion temjDerature is
n = [As^] + 2[As3+2-] (58)
where [As"*"] is the carrier concentration from isolated arsenic atoms and 2[As3"^^] is
the carrier concentration as the arsenic clusters [As3^^] at high temperatures. At room
temperature, [As3^^] is electrically neutral and the carrier concentration is

198 VLSI Technology
[As^] = C. Thus, the total arsenic can be expressed as the sum of the unclustered
arsenic [As"*"] and the clustered arsenic, which has three arsenic atoms per cluster:
+2^
C = [As^] + 3[As3"^1
= C +
Kq^C
2A'eqC
(59)
The second term on the right-hand side of Eq. 59 can be obtained from Eqs. 57 and
58. Limiting values for the electrically active arsenic are determined by letting
or
^ max I,
/A. eq
2A'eqC
r^^ = 1.584 X
=
^23
10^^ exp
0.687
kT
(60)
A generalized model for cluster formation of arsenic atoms has been derived.
The model considers m arsenic atoms interacting with k electrons^^ and anlyzes all the
possibilities. The conclusions support the model shown in Eq. 56 where three arsenic
atoms and one electron form a cluster at high arsenic concentrations. The expression
forC, IS
38
22
Cmax = 1-896 X lO^'' exp
0.453
kT
(61)
Equations 60 and 61 give comparable values at temperatures above 900°C, but Eq. 61
gives a better fit to experimental data at temperatures below 900°C.
Figure 12 shows the maximum carrier concentration C^ax ^s a function of
annealing/ diffusion temperature for arsenic at high concentrations. Experimental
results agree with this model rather well.
- in20 _
500
-
*^^-'
ARSENIC
A
>P^'^
^Ai
-
^^
-
1 1
1
1 1 1
700 900
T (°C)
1000 1300
Fig. 12 Maximum carrier concentration of arsenic in silicon versus temperature. A, C, o. A, experimental
data, curve fits Eq. 61. (After Guerrero, el ai, Ref. 38.)

Diffusion 199
The diffusivity of arsenic clusters is negligible below 1000°C. At higher tem-
peratures, these clusters separate first (decluster) and diffuse as separate arsenic
species. At low diffusion temperatures (<10(X)°C), Eq. 54 or 55 is the diffusivity of
the portion of arsenic atoms that did not form clusters.
Boron When the multi-charge-state impurity-defect interaction mechanism is applied
to the experimental profiles, the diffusivity of boron at high concentrations can be
expressed as^^
Db = (A
Hi
(62)
by using Eq. 31 with D^''{r = 1). In ion implanted samples, when the boron con-
centration is above 10^^ cm~^ the concentration of the electrically active boron is also
less than that of the total boron in the high-concentration region. ^^ The diffusivity of
boron in the high-concentration region is reduced considerably, to nearly zero. The
limiting values for the electrically active boron have been obtained experimentally;
however, a physical model has not been developed. Figure 13 shows the experimen-
tal activity limits for boron at different temperatures.-^^
Phosphorus Phosphorus is not only useful as an emitter and base dopant, it also
possesses the property of gettering fast-diffusing metallic contaminants such as Cu
and Au. These contaminants, when precipitated out in crystal defects, cause junction
leakage current problems. Thus, phosphorus is indispensable in VLSI technology.
However, n-p-n transistors made with arsenic-diffused emitters have better low-
current gain characteristics and better control of narrow base widths than those made
with phosphorus-diffused emitters. Therefore, in VLSI, phosphorus as an active
10^
E
^ la
,20
- 1 1 1 1 1 1 —I— _
~
SOLID
SOLUBILITY ^y____-
^
—
- IboronI
TT
-
~
o
,o
O
0-® -
-
-i^-°*
.-">•
-
/'^
<^
— .
— _
ti /^ -
/ ^Cj —
/ A^ _
/ /
/ / —
/ A /
/n /( -
u'
/
1 1 1 1 1 1 1
700 800 900 1000 1100 1200 1300 1400
T CO
Fig. 13 Maximum carrier concentration of boron in silicon versus temperature. ©TEM data; o, O nuclear
reaction data; A, Z, • electrical data; , curves connecting data points. {After Rxssel et
al..Ref.39.)

200 VLSI Technology
TOTAL PHOSPHORUS CONCENTRATION
ELECTRON CONCENTRATION n
P V PAIR DISSOCIATION REGION
D = CONST- n^
.EMITTER DIP
TRANSITION REGION EFFECT
Fig. 14 A model for phosphorus diffusion in silicon. (After Fair, Ref. 21 .)
dopant in small, shallow junctions and low-temperature processing will be limited to
the base dopant of p-n-p transistors and as a gettering agent. Arsenic is the most used
dopant for the source and drain regions in n-channel MOSFETs.
For completeness the diffusion model for phosphorus is discussed briefly. The
characteristic profile of phosphorus can be described as consisting of three regions
(Fig. 14): the high-concentration region, the transition region (often called the
"kink" of the profile), and the low-concentration region (the tail region).
In the high-concentration region, a fraction of the phosphorus ion (P^) pairs with
V^~ vacancies as (PV)~. The concentration of (PV)~ is proportional to n^', the sur-
face electron concentration or the peak concentration for a Gaussian implanted pro-
file. The n^ has to be determined experimentally. The diffusivity of phosphorus Dp,
in this region, is proportional to n ^, the electron concentration, and is
x -I. r» 2
Dp = [Df + or {n/niY] (63)
where
and
Df = 3.85 exp(-3.66/^7) (64)
2-
Z),^- = 44.2 exp(-4.37/;tr) (65)

Diffusion 201
Near the transition region, the electron concentration decreases, and when the Fermi
level is close to 0. 1 1 eV below the conduction band edge, the (PV)~ pairs show signi-
ficant dissociations. The electron concentration in this transition region is
n, - 4.65 X 10'' Qxp{0.39 /kT) (66)
The dissociation of (PVy increases the vacancy concentration in the tail region
which can be expressed as
and
iPVr -^ (PVy + e~ (67)
(PVy < => P+ + V- (68)
The arrows shown in Fig. 14 next to (V~) signify that aXn = n^ the excess vacancies
diffuse into both directions from X = Xq. The diffusivity in the tail region increases
as V" is increased and is
^taii = Df + D- -^— [1 + exp(0.3 QV/kT)] (69)
rii Hi
where
D- = 4.44 exp(-4 eW/kT) (70)
The expression for the total phosphorus concentration and the electrically active
phosphorus is
Ct = n + 2.4 X 10"^' «3
(71)
for temperatures between 900 and 1050°C.
Emitter push effect In n-p-n narrow-base transistors using phosphorus-diffused
emitter and boron-diffused base, the base region under the emitter (phosphorus)
region is deeper than that outside the emitter region by 0.2 to 0.6 ixm. This
phenomenon is called the emitter push effect. Since the discovery of this
phenomenon, researchers have proposed various physical mechanisms to explain it.
However, a bandgap narrowing effect together with the phosphorus diffusion model
shown in Fig. 14 adequately explains the emitter push effect. The results are sum-
marized in the following paragraph. However, the derivations of the equations are
omitted.
The dissociation of P^V~~ pairs at the kink region of the phosphorus profile (Fig.
14) provides a mechanism for the enhanced diffusion of phosphorus in the tail region.
The diffusivity of boron under the emitter region (the inner base) is enhanced by the
dissociation of P^ V^~ pairs also. However, at phosphorus concentrations greater than
5 X 10^° atoms/ cm^, misfit between silicon and phosphorus atoms induce a lattice
strain (called the misfit-induced strain) and reduces the concentration of P'^V~~ pairs.

202 VLSI Technology
12
10-
rr 8-
6 6-
4-
1 1
V
1
STRAIN
EFFECT
INCLUDED
1
/ -
-
1
INTRINSIC
THEORY
-
/
/
/ /
/ /
Of /
/ /
/ /
-
V
>
1 1
1
0.4 08 1.2 1.6 2.0
Fig. 15 Inner base push-out depth versus total phosphorus surface concentration, o junction measurement,
A SIMS measurement phosphorus diffusion at IOOO°C for 60 min using POCI3 diffusion source. The
integrated initial base dopant 2 = 1-6 x lO'"* cm"-Cpo = IV x lO'^ cm"- (After Fair, Ref. 21 .)
This reduced concentration is related to a bandgap narrowing effect. The combina-
tion of the bandgap narrowing effect'^ and the P'^K^~ dissociation explains the
emitter push effect and agrees with experimental observations. The emitter push
depth as a function of phosphorus surface concentration is shown in Fig. 15. Based
on the mechanism of P"^V^~ of dissociation, the inner base (the base region under the
emitter diffusion area) depth enhancement (inner base push out) will be a monotonic
function of phosphorus surface concentration as given in Eq. 72.
Ut) = Wq 1 +
2Digr
yi
1 +
2 D^ t
Si
(72)
where 8(0 is the difference between the inner and outer base, and Wg is a quantity
relating to the integrated doping of a Gaussian profile of the base region prior to the
emitter diffusion,
M/q = 0.4
c
(73)
pQ
Din is the diffusivity of the inner base which is assumed to increase from the intrinsic
value by the same ratio as the diffusivities of the phosphorus tail.
D B _
(A)b (74)

Diffusion 203
Dj^ = (Z),)b which is the intrinsic diffusivity of boron, Qqis the integrated doping in
the base, and C^o is the peak concentration of the base dopant prior to the phosphorus
diffusion. However, the reduction of the concentration of P^V^~ pairs caused by the
bandgap narrowing effect, which is induced by the lattice strain, Hmits the maximum
depth of b(t ). For the data shown in Fig. 15, the maximum depth is close to 0.6 |JLm
for emitter diffusion at 1000°C.
For phosphorus diffusion in the tail region, the lattice strain from bandgap nar-
rowing effect on boron diffusivity D^ can be estimated because (D")p in Eq. 74 is
proportional to (n^ / tigf. The bandgap narrowing effect on the diffusivity is given in
Eq. 74,^*^ with
fh 1
(D-)p = (D-), = D- -^ — 1 + exp
0.3eV
kT
exp
kT
(75)
Where (D )^ represents the lattice strain effect and D, is given in Eq. 70.
5.6.4 Analytical Expressions for Arsenic
Although the concentration-dependent diffusivities in As can be determined from the
experimental diffusion profiles by numerical analysis, for some cases, approximate
analytical expressions represent the experimental data rather well. These expressions
are useful simplifications to estimate slight processing variations without the compli-
cations in using computer numerical analysis. Chebyshev orthogonal polynomials
can be used to represent ion-implanted-diffused As profiles. '° The expressions for As
profiles are given in Eqs. 76 and 77.
1 - 0.87r - 0.45y2
Y = X — (D,)Mr
n,
(76)
(77)
Expressions for x, , 7?^ , Q , and Qj can be derived from Eqs. 76 and 77:
^j =2 Qt
n,
(78)
Rs =
1.76 X 10'
Q
%
Q = 0.91
Qf n,
Qt = 0.55Q Xj
n,
'A
(79)
(80)
(81)

204 VLSI Technology
where Xj is the junction location at a concentration equal to O.OIQ, Qj is the ion
dose in cm~'^, (D/)as is the intrinsic diffusivity of arsenic in cm^/s, R^ is the sheet
resistance in O/n, and Q is the surface concentration in cm~ In order to calculate
Rs and Qj, we arbitrarily select 0.0 IQ for the location of .v^ . Since the arsenic pro-
files have a steep concentration gradient for concentrations below O.IQ, assuming
the junction depth to be 0.0 IQ introduces small errors in the estimation of sheet
resistance R^ and total Qj
.
Equation 78 gives an estimate of the junction depth only, whereas the angle lap
and staining technique gives a more accurate result; here the depth depends on the
dopant concentration level where the junction is formed.
Design curves are available"*' for arsenic implantation at 100 keV into random
equivalent direction on (100) oriented wafers. The curves are for ion doses from
1.2 X 10'^ to 2.4 X 10'^ cm~^ and diffusion temperatures between 925°C and
1000°C. The expression for Xj is the same as Eq. 78. The expression for the surface
concentration C, is
Q = 0.86e/'
'/3
(82)
By assuming that mobility is proportional to C , the expression for R^ is given in
Eq. 83,
Rs = (83)
K^qQi^'x/'
where ^^ is the mobility proportional constant 2.82 x 10^ cm/V-s, and Qt is the
total arsenic ion dose. Equations 82 and 83 extend the temperature range of arsenic
implantation/ annealing to 925°C. When the calculated Q from either Eq. 80 or 82 is
greater than that calculated from Eq. 61 , the arsenic clustering effect should be taken
into consideration and the approximations in this section will be subject to errors.
5.7 DIFFUSION IN Si02
VLSI and silicon planar device fabrication relies on the thermal oxide of silicon as a
mask to prevent diffusion of impurity atoms into silicon. Therefore, understanding
diffusion in Si02 films is important. The diffusivities in SIOt were deduced by
measuring the dopants in silicon that diffused through the oxide, and by using the
solutions of the diffusion equations from Pick's law with an assumed set of initial and
boundary conditions. The impurity distribution at the Si-Si02 interface is assumed to
be in equilibrium, and the concentration ratio is described by a segregation coefficient
which was discussed in Chapter 4. Both the diffusivity and the segregation coeffi-
cient are unknown. The diffusivities are calculated, and the segregation coefficient is
either assumed or deduced.

Diffusion 205
Since Group III and Group V elements are glass formers in Si02, they lower the
melting temperature of the oxide film. The diffusivities of these elements depend
strongly on their concentrations. For example, phosphorus at 3 to 6 at. % forms a thin
viscous film on Si02 that flows at 800 to 900°C. (Phosphorus is used for planarization
in VLSI circuits as discussed in Chapter 3.) However, outside the liquid-solid boun-
dary, the phosphorus concentration becomes too low to show any diffusion. With
P2O5 used as the diffusion source, a very-high-concentration layer is present on the
thermal oxide which is used to mask phosphorus diffusion. This phosphorus layer can
be considered as a liquid; the diffusion is from the liquid-solid interface into Si02 (the
thermal oxide layer).
For phosphorus diffusion in Si02 from a doped-oxide source, the out-diffusion
from the doped oxide at the ambient-oxide (phosphorus doped) interface and the in-
diffusion from the doped oxide and a nondoped oxide interface under the doped oxide
are represented by two diffusivities.'*'^ The diffusivity of the in-diffusion near the
oxide-silicon interface depends on the mole percent (the phosphorus concentration) of
phosphorus in the doped oxide. Although the in-diffusion profile can be fitted by an
erfc function, the diffusivity depends on the phosphorus concentration in the oxide.
The diffusivity also depends on the oxide structures, that is, the diffusivity is close to
twice as large in a wet oxide as in a dry oxide."^^
This fitting of a measured profile to
an erfc function (Eq. 8) with diffusivities varying with concentration is believed to be
the result of imprecise profile measurements.
The diffusivity for the out-diffusion portion near the ambient-oxide (doped) inter-
face has a larger value than the in-diffusion portion. At phosphorus concentrations
below 0.5 mol '7c of P2O5 in Si02, the diffusivity is independent of the phosphorus
concentration. The out-diffusion, which can be represented by
Dx = 7.23 exp
-4.44
k T
(84)
does not contribute to masking failure. The diffusion responsible for masking failure
has a smaller diffusivity and depends on the phosphorus concentration and the proper-
ties of the oxide. Moisture has a significant effect on the masking properties of Si02
against phosphorus diffusion.
Similar concentration-dependent properties of boron diffusion in silicon oxide
have been observed. '^^^
As a general rule, over the temperature range used in VLSI,
diffusivities of these elements (B, As, P, and Sb) are very low when their concentra-
tions are below 1 at. %. Hydrogen, He, OH, Na, O2, and Ga are fast diffusants in
Si02. At 900°C the diffusivities of these elements are greater than 10~'^ cm"/s.
Table 4 shows the diffusivities of some elements used in VLSI technology.** These
values represent the magnitudes of the deduced diffusivities for the diffusion condi-
tions listed. The calculated diffusivities at 900°C are from the Dq and E given in the
table using Eq. 18 and are subject to errors. The values of arsenic diffusivities in Si02
are calculated from measured profiles of arsenic in Si02 films rather than deduced
values from measurements in silicon. ^^^
Most of the deduced values of diffusivities in
Si02 are rather good estimates.

Table 4 Diffusivities in Sid
D
Ref. (cm^/s)
E
(eV)
D(900°C)
(cm-/s) (cm" Source and ambient
Boron 44
44
44
7.23X10"^ 2.38 4.4x10''^ lO'"^-
2 X 10-"
1.23 X lO""* 3.39 3.4 x lO""'*^ 6 x lO'*^
3.16x10"-* 3.53 2.2 xlO^'" Below
3 X 10-"
Bt O3 vapor,
O2 + N.
Bt O3 vapor. Ar
Borosilicate
44 1.04 X 10^^ 4.17 1.3 X 10" Ga.O^ vapor, H. + N. + H.O
44
42
5.73x10"-'^ 2.30 7.7X10"'-'^ 8x|0^"to P^Os vapor. N.
10-'
X 10" 4.03 9.3 X 10" 8 X 10'^-
8 X 10'^
Phosphosilicate. Ni
Arsenic 45
45
67.25
3.7 X 10"-
4.7
3.7
4.5 X 10"'''
4.8 X 10^'**
<5 X 10-"
<5 X 10-"
Ion implant. Nt
Ion implant. Ot
Antimony 44 1.31 X 10'^ 8.75 3.6 X 10"-- 5 X lO''^ Sbi O5 vapor. 0. + N.
Hydrogen
(H.)
5.65 X 10-^ 0.446 7 X 10"^
Helium 3 X 10-4 0.24 2.8 X 10-5
Water lO-*' 0.79 4 X 10-'"
Oxygen 2.7 X lO"'* 1.16 2.8 X IQ-'^
Gold 8.2 X 10"'" 0.8 3 X 10"'^^
Gold 1.52 X 10"^ 2,14 10-'^
Platinum 1.2 X 10"'-^ 0.75 7.2 X 10-'^
Sodium 6.9 1.3 1.8 X 10-5
Note: Q = Surface concentration on silicon after diffusion from the specified source and ambient in the
absence of an oxide barrier.
5.8 FAST DIFTUSANTS IN SILICON
Group I and VIII elements are fast diffusants in silicon. They form deep level traps
and affect the minority-carrier life time and the junction-leakage currents. For exam-
ple, gold and platinum are used to reduce the storage time of switching transistors.
These elements diffuse mainly through an interstitial mechanism that is modified to
account for the experimental results. Many factors affect the distribution and diffu-
sion rate of these elements. These factors include the dislocation concentration, the

Diffusion 207
precipitation and clustering of these elements near dislocations and point defects, the
cooling rates, the presence of high concentrations of dopant elements such as phos-
phorus and boron, and the heat treatment history of the substrate silicon crystal. It is
almost impossible to measure the diffusivities of these elements with any consistency.
For instance, the distribution of gold throughout a silicon wafer resembles a U-shape
with high concentrations near the front and the back surfaces of the silicon wafer, and
a nearly uniform low-concentration distribution in the center of the wafer.
Table 5 shows the diffusivities, solubilities, and the distribution coefficients at
melting temperature of the fast diffusants in silicon."^^ Diffusivities of hydrogen, oxy-
gen, and recent values for Pt, Cr, and Co are also given.
5.9 DIFFUSION IN POLYCRYSTALLINE SILICON
Polysilicon films are used in VLSI for two major purposes: ( 1) as a polysilicon gate in
a self-aligned structure; and (2) as an intermediate conductor in two-level structures.
To reduce the resistivity of polysilicon it is often doped with boron, phosphorus, or
arsenic. Since the gate electrode is over a thin oxide, typically 250 to 500 A, it is very
important that the dopant atoms in the polysilicon film not diffuse through the gate
oxide or cause degradation of the gate oxide. To minimize this problem, the polysili-
con film is deposited at a low temperature without doping elements. After the gate
region is defined, the polysilicon film is doped. Dopant atoms are introduced by dif-
fusion from a doped-oxide source, from a chemical source, or by ion implantation.
Impurity diffusion in polysilicon film can be explained qualitatively by a grain
boundary diffusion model.''' The diffusivity of impurity atoms that diffuse along grain
boundaries can be about 100 times larger than the diffusivities in a single-crystal lat-
tice. The polycrystal film is considered to be composed of single crystallites of vary-
ing sizes (from less than 1000 A to a few tens of micrometers) that are separated by
grain boundaries. Experimental results indicate that the impurity atoms inside each
crystallite have diffusivities comparable to that found in the single crystal. Impurity
atoms also diffuse along grain boundaries, so the diffusivity in a polysilicon film
depends strongly on the textures of the film. The textures of the films are functions of
the film deposition temperature, rate of deposition, thickness of the film, and compo-
sition of the substrate film which is an oxide layer, a silicon nitride film, or a single-
crystal silicon surface.
Although diffusion results that are universally useful are difficult to present,
some general observations can be made. Experimental profiles in polysilicon films
resemble simple diffusion results such as a complementary error function or a Gaus-
sian function which depends on the applicable diffusion conditions. Because of this
resemblance, the diffusivities can be estimated from the measured junction depth and
the surface concentration using Eq. 8 or 12.
The junction depths are measured by chemical staining of a beveled sample using
the same staining solution as for the single-crystal Si (a few drops of HNO3 in 100
cm-^ HP) or a chloroplatinic acid solution which consists of 0.5 to 1 g of H2 PtCle in
100 cm^ HP (49%). The surface concentrations can be assumed to equal the meas-
ured concentrations of companion single-crystal samples that were diffused at the

208 VLSI Technology
Table 5 The diffusivity, solubility, and distribution coefficient at melting
temperature of the fast diffusant in silicon
Element Ref.
Diffusivity Dq
(cm-/s)
E
(eV)
Solubility
(cm-3)
Distribution
coefficient
Li
(25-1350°C)
46 2.3 X 10"-
- 9.4 X 10"-*
0.63
-0.78
Max. 7 X 10''^
(1200°C)
10--
Na
(800- HOOT)
46 1.6 X 10"-^ 0.76 10'^ -9 X 10'^
(600-1200°C)
K
(800-1100°C)
46 1.1 X 10"-^ 0.76 9 X 10'^ -7 X 10'^
(600-1200°C)
Cu
(800-1100°C)
46 4 X 10"- 1.0 5 X 10'-^ - 3 X 10'**
(600-1300°C)
4 X 10"-^
(Cu),
(!300-700°C)
46 4.7 X 10-3 0.43
i'Ag
/(1100-1350°C)
46 2 X 10-3 1.6 6.5 X 10'5-2 X 10'^
(1200-1350°C)
1.1 X 10-^
Au 46 1.1 X 10-3 1.12 5 X 10'^ -5 X 10'^
(800-1200°C) (900-1300°C)
(Au), 2.4 X 10-'* 0.39
(Au), 2.8 X 10^3 2.04
(700-1300°C)
2.5 X 10"
Pt
(800-1000°C)
47 1.5 X Q'
-1.7 X 10^
2.22
-2.15
4x 10'^ -5 X 10'^
(800-lOOOT)
Fe
(1100-1250°C)
46 6.2 X 10-3 0.87 10'3-5 X 10'^
(900-1300°C)
8 X 10-"
Ni
(450-800°C)
46 0.1 1.9 6x 10'^
(1200-1300°C)
-lo-'*
Cr
(1100-1250°C)
48 0.01 1.0 2 X 10'3 - 2.5 X 10'5
(900-1280°C)
Co
(900-1200°C)
49 9.2 X 10^ 2.8 Max. 2.5 X 10'"
(1300°C)
8 X 10-"
O2
(7bo-1240°C)
50 7 X 10-- 2.44 1.5 X 10'^ -2 X 10'^
(1000-1400°C)
5 X 10-'
H2 46 9.4 X 10-3 0.48
1 Q/:
Kl

Diffusion 209
same time. For boron an empirical resistivity versus concentration curve for a
polysilicon film has been determined.-^- For arsenic-diffused samples, the Rutherford
backscattering (RBS) method has been employed to measure the diffusion profiles
and to determine the diffusivities.^^
The polysilicon film, deposited by a CVD or evaporation technique, grows with a
preferred grain orientation at substrate temperatures greater than 800°C. Below
800°C the grain growth demonstrates less orientation preference. Thick polyfilms
show columnar grain structures which are oriented in the (110) direction. Thin films
deposited at low temperatures have small grains and are more randomly oriented.
After heat treatment at high temperatures, thin films also show grain growth in the
(1 10) preferred orientations. Examination of a cleaved cross section of these films by
a defect etch shows grain boundaries that are almost parallel to each other at a slanted
angle with respect to the substrate surface, that is. the grains do not grow in a direc-
tion perpendicular to the substrate surface.
The electrical property of the As- and P-doped polyfilms indicates that these ele-
ments segregate at the grain boundaries. Heat treatment of these films between 800
and 900°C shows reversible change of the resistivities.
-''"^
The resistivity of As- and P-
doped polyfilms is influenced by both carrier trapping (electrons) and atom trapping
(P or As) at the grain boundaries. The resistivity increases when the dopant atoms are
trapped at the grain boundaries. However, boron atoms do not appear to segregate at
the grain boundaries.
Table 6 gives a few examples of the diffusivities of As, B, and P in polysilicon
films used in VLSI. Two values are given to stress that the diffusivities depend on
polyfilm textures and other factors.
5.10 DIFFUSION ENHANCEMENTS AND RETARDATIONS
Diffusion study is complicated not only by the presence of defects or high-concen-
tration effects but also by other processing factors. Diffusion in an oxidizing ambient
and the lateral enhancement of diffusivity can significantly affect VLSI structures.
Table 6 Examples of diffusivities in polysilicon films
^0 E D T
Elements (cm-/s) (eV) (cm-/s) (°C) Ref.
As 8.6 X 10"* 3.9 2.4 X 10-'^ 800 53
As 0.63 3.2 3.2 X 10-'^ 950 55
B (1.5-6) X 10"-^ 2.4-2.5 9x 10-'-*
900 56
B 4x 10-'-^
925 52
P 6.9 X 10-'3 1000 51
P 7 X 10"'^ 1000 51

210 VLSI Technology
5.10.1 Effect of Diffusion in Oxidizing Ambient
In addition to the high-concentration effect, such as the interactions between Group
III and V elements and the bandgap narrowing, a few processing conditions have also
been shown to enhance or retard diffusion. Among these, diffusion in an oxidizing
ambient of boron, phosphorus, and arsenic have been investigated extensively. Most
of the experimental data were obtained from samples that had been processed under
conditions similar to those under which self-aligned gate MOS devices and circuits
are fabricated.
The oxidation-enhanced diffusion (OED) of boron was first observed in high-
concentration diffusions into both (100) and (111) oriented silicon wafers.^'' Some
experiments attempted to separate the oxidation effect from the high-concentration
effect by diffusing dopants at concentration levels below rij at the diffusion tempera-
ture. This method introduces dopants at low concentrations to form a prediffused
layer from a chemical source or an ion implanted source at low dopant levels. A thin
oxide layer (100 to 500 A) is grown, at low temperatures, to protect the silicon surface
and is then covered by the deposition of a silicon nitride film 0.1 to 0.2 xm thick.
The thin oxide layer between the silicon nitride and the silicon surface also serves to
adjust the interface properties. The interface between a Si3N4 film and a silicon
surface exhibits a charge storage effect, which causes surface leakage current and
instabilities. Strips of silicon nitride and oxide films are removed by a selective pho-
tolithography and etching technique. These samples having alternating regions of
free silicon surface and nitride-oxide protected surface are oxidized at different tem-
peratures, in different ambients, for different time periods, and sometimes with both
(100) and (111) oriented wafers. Most of the data are from (100) silicon. The
enhancement or retardation is evaluated by measuring the junction depths, spreading
resistance profiles, or concentration profiles by the differential conductivity method.
Figure 16a shows the cross section of the diffusion structures with adjacent oxi-
dized and masked regions. ^^ The junction depth on the right-hand side under the sili-
con nitride mask is shallower than the one on the left-hand side. All the junction
depths are measured from the original sample surface prior to the oxidation but after
the silicon nitride deposition. The enhancement or retardation depth Axj can be
expressed as
Ajc, = (Xj)(o - ixj)f (85)
where (Xj)i is the initial junction depth (Fig. 16a); (Xj){o is the final junction depth
under the oxide region; and (Xj)^ is the final junction depth under the silicon nitride
mask. Figure 16b shows an example of the measured A.Xy as a function of the oxi-
dation time for boron at 1 100°C. Since the concentration levels are below Hj , the dif-
fusion under the masking nitride film is due to the intrinsic diffusivity and the
diffusivity under the oxide can be expressed as
^OED = A + AD (T, t, Poy orientation) (86)
where DOED is the diffusivity for oxidation-enhanced diffusion; Z), is the intrinsic dif-
fusivity or the diffusivity in a nonoxidizing ambient; and AD is the enhancement dif-
fusivity that can depend on diffusion temperature, time, partial pressure of oxygen,
Pq , and crystal orientations.

Diffusion 211
(a)
(b)
1.0 ZO 3.0 4.0
OXIDATION TIME (HR)
Fig. 16 Oxidation-enhanced diffusion, (a) Cross section of the experimental structure, (b) Axj versus
oxidation time. Boron diffusion at 1 100°C in wet oxygen, i measured value and range. (After Taniguchi,
Kurosawa, arid Kashiwagi, Ref. 58.)
Since the observed enhancement showed a strong dependence on the diffusion
time, but the measured results were from a given diffusion-oxidation period, an effec-
tive diffusivity, sometimes called the diffusion time average diffusivity, is used.^^ In
this manner, the time dependence of the enhancement is approximated by
t
-'0
^
(D-4/eff dt C87)
where D^ , a function of the oxidation rate, is the diffusivity of the dopant at diffusion
time t.
The diffusivity enhancement is proportional to a fractional power of the oxidation
rate.^
AD = a
dX,
dt
(88)
where a is a proportional constant that can be estimated from an assumed diffusion
model, and n is between 0.4 and 0.6. Results on arsenic and phosphorus diffusion in
dry oxygen showed that AD decreases as the oxidation temperature is increased.
^^
Oxidation enhancement of As and P have been investigated using prediffused

212 VLSI Technology
samples. ^^ In this case, the diffusion equation with a moving boundary during the oxi-
dation was solved by the numerical method with a measured initial profile after the
prediffusion and an assumed parabolic oxidation-rate relationship.'' For this assumed
relationship, the oxidation rate can be determined as follows:
_^ = ^(0-/2 (89)
at I
Equation 89 assumes that the initial thin oxide (20 to 30 A) on silicon surfaces can be
neglected and the linear growth portion is also negligible (see Chapter 4). The results
can be summarized as follows:
1. In dry N2, the diffusivities are the same in (100) and (111) oriented wafers for
both arsenic and phosphorus. This result agreed with observations by others. ^^' ^°
2. In dry O2, the diffusivities are enhanced for As and P in (100) oriented wafers
and for P in (1 1 1) wafers, but little enhancement was observed for As in (111)
silicon.
3. The enhancement in ( 100) Si is greater than that in (1 1 1) Si.
4. Since the oxidation rates are higher at shorter oxidation times, the enhancement
is larger for short oxidation time and decreases with increasing oxidation time.
5. The diffusivity enhancement AZ) = (D)o, - (D)j^^ can be expressed in terms
of an effective oxidation rate {Xo^/t )".
A retardation of antimony diffusion in silicon during oxidation was observed. ^^ In
addition, the stress at the silicon-silicon nitride edge caused junction retardation under
the silicon nitride film laterally to 20 to 30 ixm inside the nitride film edge. The junc-
tion retardation is depicted in Fig. 17 which is traced from a photograph of angle
lapped and stained sample. The retardation is a fraction of a micrometer for junction
depths of 3 to 6 |xm and diffusion temperatures between 1000° and 1200°C.
The observation of oxidation-induced stacking fault (OSF) and oxidation-
enhanced diffusion (OED) has lead to the proposal of a dual diffusion mechanism.
The diffusion of impurity under the nitride layer is considered to be dominated by the
vacancy mechanism, and the oxidation enhancement of diffusion is attributed to the
presence of silicon self-interstitials that also cause the extrinsic stacking faults to
grow.^ Interstitials are generated at the Si-Si02 interface during oxidation. By
assuming that the vacancy concentration is constant during oxidation, the enhance-
ment of boron and phosphorus diffusivities during oxidation is due to the excess of
interstitials diffusing away from the oxide-silicon interface and that these elements are
governed by a dual mechanism, vacancy and interstitialcy.^^'
^
The observation of oxidation-retarded diffusion of antimony suggests that, during
diffusion and oxidation, thermal equilibrium between vacancies and interstitial exists.
The generation of interstitials at the oxide-silicon interface causes the depression of
vacancy concentrations.^^^
The diffusion retardation of antimony could be due to the
reduction of vacancy concentrations; thus antimony diffusion is governed by a
vacancy mechanism. By a similar reasoning since silicon interstitials are enhanced at
the oxide-silicon interface, it has been suggested that both boron and phosphorus dif-
fuse via the interstitialcy mechanism in either an oxidizing or neutral ambient.

Diffusion 213
Si02 Si3N4 y^^i
t J
Sb
3" E
JO
T
Wf.y/////.
•— 1
50 Jim
Fig. 17 Junction retardation of antimony during oxidation witii the lateral effect shown under the Si3N4
layer. (After Miziio and Higiichi. Ref. 63.)
5.10.2 Lateral Enhancement of Diffusivity
Another enhancement effect that is important in VLSI devices is the lateral enhanced
diffusion at an oxide or silicon-nitride edge. Diffusion into narrow windows of sili-
con oxide can result in anomalous junction depths. ^^ Various enhancements and retar-
dations of the junction depth near the oxide window edges have been observed.
These are the results of elastic strain fields near the window edges.
For boron diffusion in a structure similar to that shown in Fig. 18, lateral-
enhanced diffusion extends under the nitride layer up to 30 ixm.^ Strips of silicon
nitride layers with widths varying from 2.5 to 100 ixm were separated with 100-|jLm
windows without oxide. The samples were oxidized after boron implantation and
annealing at 900°C. The junction depth at the center of the nitride-oxide strip was
measured as a function of the widths of the strips. Figure 18 shows the results. For
10 20 30 40
NITRIDE STRIPE WIDTH W (^m)
50
Fig. 18 Lateral enhancement of junction depth under a Si3N4 film during oxidation. (After Lin, Diitton.
and Antoniadis . Ref. 66.)

214 VLSI Technology
narrow strips the lateral enhancement of the diffusivity is significant for VLSI device
designs. In a narrow structure the junction depths under the silicon nitride film are
enhanced and nonuniform.
This chapter discusses diffusion results in silicon with emphasis on VLSI applica-
tions. Various factors affecting diffusion control are presented. Pick's classical diffu-
sion laws with constant diffusivities are obeyed for Group III and V elements when
the concentrations are below the intrinsic carrier concentration. When the concentra-
tions are high, concentration-dependent diffusivities are required, and Pick's general-
ized diffusion equation with concentration-dependent diffusivities can be solved by
numerical methods. The concentration-dependent diffusivities can be determined
from the measured profiles using mathematical formulations of a Boltzmann transfor-
mation or modifications of it.
Atomic diffusion mechanisms are being developed to relate the impurity diffu-
sion with lattice defects. Attempts have been made to construct diffusion models
based on defect-impurity interactions. The diffusivities are functions of the concen-
tration of the ionized point defects, vacancies, or interstitials. This approach is suc-
cessful in explaining the high-concentration diffusions of the Group III and V ele-
ments, especially for phosphorus in silicon. Various other models have also been pro-
posed and tested.
Diffusion in an oxidizing ambient also exhibits a time dependency because of the
parabolic oxidation rate of silicon. Observations of the coexistence of the oxidation-
enhanced diffusion and the formation of oxidation-induced stacking faults suggest
that an extrinsic mechanism for generating silicon self-interstials near the silicon-
oxide interface may also influence the impurity diffusivities. The oxidation-induced
stacking faults are extrinsic in nature, that is, they grow by absorbing silicon self-
interstitials. These observations have led to the proposal of a dual vacancy-
interstitialcy diffusion mechanism. Hence, the atomic diffusion mechanism is still an
area of active research.
The advancement of device technology and the development of complex circuits
require more precise diffusion measurements and good theoretical models, so that cir-
cuit performances can be modeled from process parameters. In theoretical modeling,
the dominating diffusion mechanism for Group III and V elements needs to be
resolved. Purther development of the dual vacancy-interstitialcy diffusion mechanism
is also needed.
Theoretical studies rely on good experimental data. As the device size becomes
smaller and smaller, the need for better measurement techniques becomes more
urgent. At present, the spreading resistance technique is widely used for profile
measurements. Unfortunately, it relies on a beveled sample technique that limits the
junction depth to 1 xm and it is a comparative and semiquantitative method. The dif-
ferential conductivity method has a comparable limitation in depth of less than 1 ixm.
Thus, both methods will be less attractive in VLSI development.

Diffusion 215
The SIMS analysis is a powerful tool for diffusion profile measurements. It can
measure boron and arsenic concentrations as low as 5 x 10^^ atoms/cm^ and has a
high depth resolution of a few tens of angstroms. Therefore, it is an ideal tool for
measuring shallow diffusion profiles. This technique will provide the needed preci-
sion for profile measurements in VLSI structures.
Conceivably, some pulse annealing procedures for annealing ion implanted
wafers in 5 to 20 s will be developed shortly through the use of an arc-lamp furnace or
a graphite heater in a vacuum environment.^^ Experimental and theoretical investiga-
tions on the effect of temperature transients on the diffusion-annealing properties of
these samples will definitely be addressed soon. Junction depths in the range of 1000
A or less can be realized and the impurity profiles from short period annealing have to
be evaluated. This need points to SIMS analysis technique again and further develop-
ment of this technique is required.
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B. L. Sharma, "Diffusion in Semiconductors," Trans. Tech. Pub. Germany, 87 (1970).
R. F. Bailey and T. G. Mills, "Diffusion Parameters of Platinum in Silicon," in R. R. Habarecht and
E. L. Kem, Eds., Semiconductor Silicon 1969, Electrochem. Soc., New York, 1969, p. 481.

Diffusion 217
[48] W. Wurker, K. Roy, and J. Hesse. "Diffusion and Solid Solubility of Chromium in Silicon,"" Mater.
Res. Bull.. (U.S.A.), 9, 971 (1974).
[49] H. Kitagano and K. Hashimoto, "Diffusion Coefficient of Cobalt in Silicon," J. Appl. Phxs. Jpn.. 16,
173(1977).
[50] J. C. Mikkelsen, Jr., "Diffusivity of Oxygen in Silicon During Steam Oxidation," Appl. Phys. Lett.,
40,336(1982).
[51] T. I. Kamins, J. Manolin, and R. N. Tucker, "Diffusion of Impurities in Polycrystalline Silicon,"' J.
Appl. Phys.. 43, ^3 (1912).
[52] C. J. Coe, "The Lateral Diffusion of Boron in Polycrystalline Silicon and Its Influence on the Fabrica-
tion of Sub-Micron Mosts." Solid State Electron.. 20, 985 (1977).
[53] B. Swaminathan, K. C. Saraswat, R. W. Dutton. and T. I. Kamins, "Diffusion of Arsenic in Poly-
crystalline Silicon,"" Appl. Phys. Lett., 40, 795 (1982).
[54] M. M. Mandurah, K. C. Saraswat, C. R. Helms, and T. I. Kamins, "Dopant Segregation in Polycrys-
talline Silicon,"" y. Appl. Phys., 51, 5755 (1980).
[55] K. Tsukamoto, Y. Akasaka, and K. Horie, "Arsenic Implantation into Polycrystalline Silicon and Dif-
fusion to Silicon Substrate," J. Appl. Phys.. 48. 1815 ( 1977).
[56] S. Horiuchi and R. Blanchard, "Boron Diffusion in Polycrystalline Silicon Layers,"" Solid State Elec-
tron.. 18.529(1975).
[57] W. G. Allen and K. V. Anand. "Orientation Dependence of the Diffusion of Boron in Silicon,"' Solid
State Electron.. 14. 397 (1971).
[58] K. Taniguchi. K. Kurosawa, and M. Kashiwagi, "Oxidation Enhanced Diffusion of Boron and Phos-
phorus in ( 100) Silicon,"" y. Electrochem. Soc, 127, 2243 (1980).
[59] S. M. Hu, "Formation of Stacking Faults and Enhanced Diffusion in the Oxidation of Silicon,"' J.
Appl. Phys., 45, 1567(1974).
[60] A. M. R. Lin, D. A. Antoniadis, and R. W. Dutton, "The Oxidation Rate Dependence of Oxidation-
Enhanced Diffusion of Boron and Phosphorus in Silicon," J. Electrochem. Soc, 128, 1 131 (1981 ).
[61] D. A. Antoniadis, A. M. Lin. and R. W. Dutton. "Oxidation-Enhanced Diffusion of Arsenic and
Phosphorus in Near Intrinsic^OO) Silicon." Appl. Phys. Lett., 33, 1030 (1978).
[62] Y. Ishikawa, Y. Sakina, H. Tanaka, S. Matsumoto, and T. Niimi, "The Enhanced Diffusion of
Arsenic and Phosphorus in Silicon by Thermal Oxidation,'" 7. Electrochem. Soc, 129, 644 ( 1982).
[63] S. Mizuo and H. Higuchi, "Retardation of Sb Diffusion in Si During Thermal Oxidation,"" J. Appl.
Phys. Jpn.. 20, 1?>9{9S).
[64] T. Y. Tan and U. Gosele, "Oxidation-Enhanced or Retarded Diffusion and the Growth or Shrinkage
of Oxidation-Induced Stacking Faults in Silicon," /ip/?/. Phys. Lett., 40. 616 ( 1982).
[65] C. F. Gibbon. E, I. Povilonis, and D. R. Ketchow. "The Effect of Mask Edges on Dopant Diffusion
into Semiconductors."" J. Electrochem. Soc. 119. 767 (1972).
[66] A. M. Lin, R. W. Dutton, and D. A. Antoniadis, "The Lateral Effect of Oxidation on Boron Diffusion
in(lOO) Silicon,"" Appl. Phys. Lett., 35, 799 ( 1979).
[67] D. F. Downey, C.J. Russo, and J. T. White, "Activation and Process Characteristics of Infrared
Rapid Isothermal and Furnace Annealing Techniques,"' Solid State Technol., 25, No. 9, 87 ( 1982).
PROBLEMS
1 (a) Derive expressions of concentration gradients for the erfc and Gaussian distributions. If the substrate
doping density is C^^b' derive the expressions of the junction depths.
fZ?) Assuming C, = lO'^ cm"^^ for an erfc distribution and 5 = 1 x lO'^ atoms/cm- for a Gaussian
distribution, C^ub = lO'"' atoms/cm and D = 1 x 10"'-^ cm-/s (which is close to the boron diffusivity
at 9(X)°C), calculate the junction depths and the concentration gradients for both distributions. Calculate the
integrated dopants for the erfc distribution and the surface concentration for the Gaussian distribution for dif-
fusion times of 10, 30, and 60 min.
(c) Compare and discuss the results of (a) and (b).

218 VLSI Technology
2 Derive Eq. 15 from Eq. 3.
3 Derive Eq. 25 assuming that the ionized acceptor vacancy concentration can be expressed as a function of
the Fermi level and Ey . the activation energy of the acceptor vacancy.
4 In order to determine if the intrinsic diffusivity of an impurity is appHcable at a given diffusion tempera-
ture, one has to know the intrinsic carrier concentration, n, . Thus the plot /;, versus temperature is a very
usefiil curve. Using Eqs. 29 and 30, construct «, versus T.
5 Using Eq. 48, derive the electric-field enhancement factor of Eq. 53.
6 A p-type (lOO)-oriented silicon wafer with a substrate doping at lO'^ atoms /cm-^ has been implanted and
diffused with arsenic to an ion dose of 1 x lO'^ cm"- at 30 keV and diffusion at 850°C for 30 min in nitro-
gen.
(a) Calculate the sheet resistance from Eqs. 79 and 83.
(b) Calculate the surface concentrations from Eqs. 80 and 82.
(c) Find the surface concentration of the electrically active arsenic.
(d) Discuss the results.
7 (a) Using Eqs. 76 and 77 for an arsenic implanted-diffused profile, derive the approximate expressions
forEqs. 78,79, and 80.
(b) For an arsenic dose less than lO'^ cm~- and a diffusion temperature greater than 1000°C, assum-
ing the electrically active arsenic equals the total arsenic (neglect As clusters), derive Eq. 79 using Eq. 40
and an effective mobility of
28.2 X 10^
fXgff = cm-/V-s
^ A
for 10'^ cm -^
< C^ < 6 X Qp cm ^ where C^ is the concentration of the electrically active As.
8 For an acceptor type impurity, the diffusion current including the electric-field term is
J = -QDa —^ +q i^A Ca E
where D^ is the diffusivity, C^ is the acceptor concentration, |x^ is the mobility, and E is the electric field.
If
Da = D, -^
show that
J = -q j^(D^C^)
The above expression reduces the computation time when it is used to numerically analyze diffusion
profiles.

CHAPTER
SIX
ION IMPLANTATION
T. E. SEIDEL
6.1 INTRODUCTION
Ion implantation is the introduction of ionized-projectile atoms into targets with
enough energy to penetrate beyond surface regions. The most common apphcation is
the doping of sihcon during device fabrication. The use of 3- to 500-keV energy for
boron, phosphorus, or arsenic dopant ions is sufficient to implant the ions from about
100 to 10,000 A below the silicon surface. These depths place the atoms beyond any
surface layers of 30-A native Si02 and therefore any barrier effect of the surface
oxides during impurity introduction is avoided. The depth of implantation, which is
nearly proportional to the ion energy, can be selected to meet a particular application.
The major advantage of ion implantation technology is the capability of precisely
controlling the number of implanted dopant atoms. Upon annealing the target (heat-
ing to elevated temperatures of approximately 600 to 1000°C), precise dopant concen-
trations between lO'"* to 10"' atoms/cm^ in silicon are obtained. Furthermore, the
dopant's depth distribution profile can be well controlled.
IXiring the 1960s important research in the calculation and measurement of ion
ranges,^ of radiation damage effects, and of ion channeling- was carried out. Many
radiation-induced point defects already were identified, ^^
aiding in a rapid understand-
ing of ion implantation phenomena. Device applications were also being reported in
the later 1960s. Variable-capacitance p-n junction diodes (varactors) with rapidly
varying doping concentrations and the first implanted self-aligned MOS transistor
using aluminum metal gates'^ were reported in 1968.
219

220 VLSI Technology
It took about six years (from 1969 to 1975) for ion implantation phenomena to be
well enough understood and documented so that it was routinely used in VLSI fabri-
cation. A summary of research during this time may be found in the extensive collec-
tion of articles from conference proceedings for the First through the Fifth Interna-
tional Conferences on Ion Implantation,
^^"^^
and in review articles.
^"^
Later work addresses topics important for the implementation of VLSI.^"^^ Shal-
low junctions with high concentration profiles are formed by using rapid annealing
techniques (e.g., lasers),'"* often making use of solid phase epitaxy. As high-beam-
current equipment became commercially available in the late 1970s, beam heating,
sputtering, oxide charge-up during implantation, and gas-beam interactions received
attention.
For dopant control in the lO''* to lO'^ atoms/cm^ range, implantation offers a
clear advantage over chemical deposition techniques. Masks can be made of any con-
venient material used in VLSI fabrication such as photoresist, oxides, nitrides,
polysilicon, etc. The implant process, which is done in a vacuum, is both clean and
dry.
Special damage configurations can be generated by implanting with ions such as
argon at high doses. Annealing then gives fine-grain polycrystalline layers and/or
dislocation-rich regions, to which unwanted impurities diffuse. These implanted
damage-induced defects are useful for capturing unwanted impurities, such as copper,
from junction regions. This process is called gettering.
This chapter covers the implantation system and dose control techniques, ion and
disorder distributions, annealing, gettering, other implantation effects, and future
trends.
6.2 ION IMPLANT SYSTEM AND DOSE CONTROL
This section discusses ion accelerators and the features needed for good dose con-
trol.'^'
'^
Figure 1 shows a schematic view of a commercial ion implantation system.
Starting at the source end, (bottom center), we have:
1. A gaseous source of appropriate material, such as BF3 or ASH3, at high (accel-
erating) potential V. An adjustable valve controls the flow of gas to the ion
source.
2. A power supply to energize the ion source, also at high potential.
3. An ion source containing an ion plasma with the species of interest:
^As'^^, ^B'^ or ^BF2^, at pressures of approximately ~ 10~^ torr. A source
diffusion pump establishes lower pressures for beam transport with reduced ion-
gas scattering.
4. An analyzer magnet that selects only the ion species of interest and rejects other
species. The desired ion species passes through a resolving slit (aperture) and is
then injected into the accelerator column.
5. An acceleration tube through which the beam passes. The beam is then ready for
transport to the target.

Ion Implantation 221
(4) ANALYZER
MAGNET
ION
BEAM
(5) ACCELERATION
TUBE
(6) Y SCAN
PLATFS
RESOLVING'
APERTURE
(7) WAFER
(TARGET
POSITION)
SOURCE
DIFF
PUMP
(3) ION
SOURCE
(2) ION SOURCE
POWER
SUPPLY
(7) WAFER
BEAM LINE 8. FEEDER
END STATION
DIFFUSION PUMPS
(DGAS
SOURCE
Fig. 1 Schematic diagram of a typical commercial ion implant system. (After Varian-Extrion, DF-3000
brochure.)
7.
Sawtooth voltages applied to x and y (electrically rastered) deflection plates to
scan the beam and give a uniform implantation. Beam-line and end-station diffu-
sion pumps keep pressure low enough to avoid charge-exchange effects (see
below).
A target chamber consisting of an area-defming aperture, Faraday cage, and
wafer feed mechanism.
We now develop the idea of ion dose. Consider an ion beam with mass M,
charge mq (m is the charge state of the ion and q is the electron charge), and energy E
as it moves through a vacuum drift space toward a target (Fig. 2). The ion beam is
swept by a charged-particle deflection scheme to obtain a uniform implantation over
the target area. The swept beam is limited by an aperture of area A. Behind the aper-
ture, the silicon wafer sample is placed inside the area of the aperture that is projected
onto the metal target holder. The sample is in good electrical contact with the target
holder which is connected in turn to a charge integrator. Electrons pass through the
integrator and neutralize the implanted charges as they come to rest in the silicon. An
integrated charge Q (coulombs) results in a dose <) defined by
<j) = —^— atoms /cm^
mqA
(1)
The integrated charge isQ = j I dt, where the beam current / (amps) is applied for
time t (seconds). For example, a beam current of 10~^ A swept over a 1-cm^ area for
1 second gives a dose of 0.6 x 10'° atoms/cm^ for m = 1. If the width of the
implanted layers is 6(X) A, control of the doping concentration is possible at a level of

222 VLSI Technology
METAL TARGET
HOLDER
SILICON TARGET
WAFER
^ .. . CHARGE
1-0' I INTEGRATOR
Fig. 2 Schematic of a rastered ion beam, showing the defining aperture and the target. The charge integra-
tor measures the time-averaged swept beam current.
10^^ atoms/cm^. The use of milliamp beam currents for 100 seconds give doping lev-
els up to the solid solubility values of approximately 10^^ to 10^^ atoms/cm"^ on 100-
mm-diameter wafers.
The control of the dose and its uniformity may be compromised because of neu-
tral beam species, charge exchange, secondary electron emission, and sputtering
effects. These effects, which are discussed below, can be made negligible by use of
good experimental techniques.
Neutral beam species are undeflected by charged-particle deflection schemes. If
the aperture and target are "off-set" from the neutral beam, the neutral beam is
stopped and trapped by a beam stop or chamber wall, and only charged species reach
the target.
Charge exchange can neutralize the beam if the vacuum in the drift space is poor.
In this process an ion collides with neutral gas and picks up an electron, leaving the
ion neutral. Significant neutralization can occur if pressures are greater than about
10"^ torr.
In secondary electron emission, ions hitting the target eject low-energy electrons
from the target. If these electrons (secondaries) are lost to chamber walls, there will
be an error in the dose measurement. Errors due to secondary electron emission are
minimized by the use of a Faraday cage (metal electrode configuration) that nearly
surrounds the target and has an opening facing the aperture (Fig. 1). A bias of a few
hundred volts can be applied to the Faraday cage relative to the target so most secon-
dary electrons are returned to the target and the integrator circuit.
Sputtering of aperture material onto the sample will always occur. This effect is
minimized if the aperture is made of low-sputter-coefficient or benign material such
as carbon or silicon. If the aperture is constructed of Fe or Ta, then a few percent of
heavy metal relative to the ion dose can be sputtered onto the target.
Sputtering of akeady implanted atoms from the target can be important at high

doses (—10^^ atoms/cm^). One may expect a "saturated-sputter limited" dose where
each new implanted atom removes one previously implanted ion by sputtering. In
practice, however, there may be less saturation than expected because of channeling
effects and thermal diffusion caused by beam heating. These effects place previously
implanted atoms further away from the surface than simple range theory suggests, and
tend to reduce the sputtering of already implanted atoms.
Other surface contamination during high-dose implantations can occur. The
physisorption of hydrocarbons from diffusion pump oil followed by radiation-induced
polymerization can occur. '^ This effect can result in high metal-to-semiconductor
electrical contact resistance. Implantation through thin protective (screen) oxides,
followed by contact lithography down to the bare silicon, can avoid the adverse effect
of polymerized hydrocarbons on silicon surfaces.
Silicon wafers are often implanted with both thin protective coverings and thick
Si02 layers (masks). Ion-induced charging of Si02 layers can have a deleterious
effect on the quality of the Si02 if dielectric breakdown (t^—lO^ V/cm) occurs.
Techniques used to avoid this are the use of an added electron source to neutralize
positive surface charge of the implanted beams, the use of thin conductive layers on
the oxide, intentionally causing excess conductivity in the Si02, and modification of
the oxide pattern by cutting bare silicon regions in the oxide (for example, in the grid
regions between chips).
In summary, the control of many parasitic effects are essential for accurate and
high-quality implantations. We now take up the question of ion mass selection.
A typical ion source produces many different elements, isotopes, and charge state
species. Separation of these species is obtained with a mass spectrometric analyzer
magnet. In a magnetic field B, an ion path takes on a radius of curvature R such that
RB = V2VM /mq , where V is the acceleration voltage. By adjusting the magnetic
field the species of interest is selected to pass through slits that define the radius of
curvature. The selection of the desired species (element, isotope, and charge state) is
certified by the signature of the entire mass spectrum. See Fig. 3, where the target
beam current is plotted against magnetic-field strength. A straight line relates the
mass and charge state to the magnetic-field strength. See Problem 3 for further dis-
cussion.
Use of a doubly ionized species extends the machine's energy capability by a fac-
tor of 2 (£ = 2qV). To determine an atom dose for a doubly ionized species, we
must count 2 electrons for every implanted atom, that is, in Eq. (1), m =2. Doubly
ionized species are usually less abundant and applications must recognize this limita-
tion.
Many applications use ion deposition followed by a thermal drive-in to obtain a
desired dopant distribution. Such applications use low, fixed energy. Relatively
inexpensive machines with an ion extractor at the terminal voltage, and magnetic-
mass spec analysis at low magnetic fields, form a class of "pre-deposition," dedi-
cated accelerators ( 10 to 30 keV). Accelerators with higher energies usually are made
with a variable energy range capability. A relatively large and expensive magnet is
needed to analyze the accelerated species.
Machines with high beam current (—10 mA) are now commercially available.

224 VLSI Technology
^f1AGNETIC FIELD B (ARB UNITS)
Fig. 3 A typical ion beam mass spectrum of a ASF5 gas source. Target current and magnetic field are in
arbitrary units. The major ionized species are labeled. The ratio of mass to charge state is determined from
the straight line.
To avoid target heating, the beams are defocused, and samples are placed on rotating
target plates and/or sometimes cooled. For rotating targets, the dose is defined by the
integrated charge corrected by the fraction of time the ion beam hits the sample.
Ion sources have been developed using ovens, rf plasmas, hot cathodes, and arc
discharges. Laser-pulsed and microwave-energized plasmas'^ provide larger fluxes.
Implantation, when interfaced with molecular beam epitaxy equipment (MBE),^^ can
yield impurity distributions at greater depths than is possible by implantation alone.
6.3 ION RANGES
6.3.1 Distribution Description
An individual implanted ion undergoes scattering events with electrons and atoms in
the target, reducing the ion's energy until it comes to rest. Point defects and even
small amorphous disorder zones may result (Fig. 4a). The total path length of the ion
is called the range, R (Fig. 4b). A typical ion stops at a distance normal to the sur-
face, called the projected range, Rp. Some ions are statistically "lucky"; they
encounter fewer scattering events in a given distance in the target, and come to rest
beyond the projected range. Other ions are
'
'unlucky"; they have more than the aver-
age number of scattering events, and come to rest between the surface and the pro-
jected range. The fluctuation or straggle in the projected range is A/^^ . There is also
a fluctuation in the final ion's position perpendicular to the incident ion's direction,
called the lateral straggle , A /? j^
.

INCIDENT ^
ION
AMORPHOUS
REGIONS
POINT DEFECTS
(a)
INCIDENT
ION
(b)
Fig. 4 (a) A "tree"" of disorder for a typical implanted ion. (b) A schematic of the ion range R, projected
range Rp . uncertainty in Rp or projected straggle ^Rp , and the lateral straggle AT? i .
The depth distribution or profile of stopped ions can be approximated by a sym-
metric Gaussian distribution function. The concentration of implanted atoms as a
function of position is
n{x) = n{Rp) exp
-(X - RpY
2ARf
(2)
where the maximum concentration occurs at jc = Rp, and A/?^ is the standard devia-
tion or "straggle" of the distribution. The integral / n(x) dx gives the dose (j), and
the maximum concentration n {Rp^ can be written as
niR,) = cf)
277 A/?,
0.4(f)
a;?„
(3)
The projected range and straggle of the Gaussian distribution give a good first-order
description of the implanted ions in amorphous or fine-grain polycrystalline sub-
strates. The data of some implanted distributions can be fit rather well by the Gaus-
sian distribution function; certain values are given in Table 1. Although the fit is
almost always good near the peak, there is a pronounced skewness in the actual distri-
butions. To account for the skewness and also any tailing character higher moment
descriptions are needed.
A three-moment approach^^ uses two Gaussians, each with their own straggle
ARp and A/?p2- The Gaussians are joined at their "modal range," R;^. From the
three fundamental calculated parameters Rp, ARp, and the third moment ratio CMi,p
,

226 VLSI Technology
Table 1 Gaussian and erfc values
x-Rp -{X--^p)^ y-a
Ai?|
0.5 erfc I- ^
V2A^^
^^ "' 2A/?/
1.00 0.50
1.0 0.61 0.28 0.39
1.18 0.50 0.56 0.28
1.5 0.325 0.70 0.24
2.0 0.14 1.00 0.16
2.14 0.10 1.26 0.10
2.5 0.044 1.4 0.078
3.04 0.01 2.0 0.022
3.5 0.0022 2.33 0.01
3.72 0.001 2.4 0.008
4.0 0.00034 3.07 10-3
4.3 10-4 3.7 10-4
4.8 10-5 4.3 10-5
5.25 10-^ 4.8 10-6
5.67 10-7 5.2 10-7
it is possible to calculate Rp, ARp2, and R;^ . A distribution is then obtained by the
joining of two Gaussians
n{x) =
nix) =
24)
V2'ni^Rp, + ^Rpi)
2^
VliriARp, + ARp2)
exp
exp
jx - Rm)~
2ARp J
jx - Rm?
2ARp J
x^ Rm (4a)
x^Rm (4b)
,21
A more exact description uses the "four-moment" approach: first (Rp), second
(ARp), third—skewness—(7), and fourth—kurtosis—(p). Kurtosis describes the
tail character of the distribution. Several equations lead to the Pearson-IV-type distri-
bution. Pearson distributions are based on the differential equation
dhjx) ^ (x'-a) hjx')
dx b2x'^ + bix' + Z?(
(5)
where h is the normalized distribution function, h(x) satisfies J^ hix) dx = I,
and x' = X -Rp . Four constants, a, bo, bi, and /?2 are defined in terms of the four
moments xi, [1.2, 71, and (5 where
r
fii (mean range) = Rp — j_ xh(x) dx
IJL2 (straggle) = ARp = J_ (x-Rpf h{x) dx
(6a)
(6b)

/_ {x-Rpfh{x)dx
7i (normalized skewness) = — ^ (6c)
^.Rp
j'^
(x-Rpf hix) dx
P (normalized kurtosis) = — (6d)
^Rp
Using these definitions, the four constants are related to the moments,
a = - 7i|X2 (3 + 3)M (7a)
^0 = - fX2^ (4P - 3yl)/A (7b)
^1 = a (7c)
b2= - (23 - 37? - 6)M (7d)
where A = lOp - 127f - 18. Only Pearson-IV solutions are applicable to
implanted profiles. The solution is
In «(£l = ^ 1„
hq lb
b,x'^ + b^x' + b<
—^ + 2a
bi 2b-, x' + bi
j^ arctan rr- (8)
(4b2bo - blV' {4b2bo - blV'
where hq — ^ / { h dx. Using these four m^oments, excellent fits to the implanted
distributions can be obtained.
Figure 5 shows measured, skewed boron atom profiles and their fitted four-
moment distributions for 30 to 800 keV.-^^ The implants were done into fine-grain
polycrystalline silicon to avoid channeling effects (described in Section 6.3.3). Gaus-
sians only fit the data well at low energy and over part of the profile. Pronounced
skewness is evident toward the surface (71 is negative so a maximum occurs at x
greater than the mean distance Rp). Arsenic profiles, however, show skewness on the
deep side of the implant profile (71 is positive). The different skewness can be visual-
ized by thinking of forward momentum. If light ions impact on the target atoms, they
will have a relatively large amount of backward scattering. The result is a filling-in of
the distribution on the surface side, as with boron. Conversely, if heavy ions impact
on a target atoms, they will have a disproportionate amount of forward scattering.
The result is a filling-up of the ion distribution on the deep side of the distribution, as
with arsenic.
Lateral ion straggle effects are an extremely important, practical aspect of ion
stopping. In applications of self-aligned implanted sources and drains (Chapter II),
the lateral ion straggle is a limiting fundamental factor which determines the doping
between source and drain and therefore the electrical channel length.

228 VLSI Technology
10
21
F"^—I
—
^
lo^V
<
o
o
o
^
—

—
r
1—^
—
r
"T
r
BORON IN SILICON
30keV
inn
300
• MEASURED
4-MOMENT
GAUSSIAN
0.2 0.4 0.6 0.8 1.0 1.2
DEPTH (^m)
1.4 1.6 1.8 2.0
Fig. 5 Boron implanted atom distributions, with measured data points, and four-moment (Pearson-IV) and
symmetric Gaussian curves. The boron was implanted into amorphous silicon without annealing. (After
Hqfker.Ref.21.)
Figure 6a shows a "thick" ion mask (thickness »Rp + ^Rp) with a vertical-
slotted window. In this figure the slot's long direction (z ) is into the paper, the short
direction (y) has a slot width of 2a, and x is the depth coordinate. The profile is
given by
n(x,y) = n{x)
erfc
y-a
fi LR
erfc
V +a
v^ ^R
(9)
where /i (jc ) is the depth distribution density far away from the mask edge. For a»
A/?|, n{x,a) = n{x)/2, which is the result" expected for a "half-source."
Figure 6a is for a >> A/? |, the edges are far removed from each other. Figure 6b
shows the contours of equal-ion concentration for 70-keV boron into a l-|JLm slit. The
lateral doping extends well under the mask edge and will effect the channel length of
a short gate.
6.3.2 Theory of Ion Stopping
The range of an ion is determined by Lindhard, Scharff, and Schiott (LSS) theory,'
where energy loss mechanisms are considered to be independent of each other and
additive. For electronic and nuclear stopping, the energy loss per unit length is
defined as
dE
dx total
dE
dx
+
nuclear
dE
dx
(10)
electronic
The nuclear and electronic energy loss, are both functions of energy.

ION BEAM
^TTTTTTX M t i ;, M M i
.J
M i M V/////////,
MASK
1.0
0.5
SURFACE OF TARGET
F(y)
0.0-
•1.0
"0.5
4—AR_L ARj_ *| y
_8 I I ' '1^^ I
y(A)
10000 5000 5000 10000
Fig. 6 Illustration of lateral profiles, (a) Ion concentration along the lateral direction (y) for a gate mask
with a »A/?j^ and infinite extension in the z-direction. (b) Contours of equal-ion concentrations for 70-
keV B+ {Rp = 2710 A, A/?^ = 824 A, and A/?^ = 1006 A) incident into siHcon through a l-|jun slit.
(After Furulcawa, Matsumura, and Ishiwara, Ref. 22.)
The range R of ions is given by
^^^) = /n
dE
'0
(dE /dxU^ N -'o S{E)
- r
dE
(11)
where A^ is the number of target atoms/cm-', S(E) is the stopping power, and E is the
initial incident ion energy.
A physical description of the scattering process is provided by classical mechan-
ics.^"^ The transferred energy T between an incoming ion (energy E^, mass Mj, and
atomic number Zj) and the target atom (mass Mj and atomic number Zi), having a
scattering angle in the center-of-mass system, is
£i4MiM2 . ,e Z7
• 2B
T = 1- sm'-— = yE sm —
(Ml + M2)2 2 ' '
2
(12)
When = 180° (head-on), T is a maximum value. The scattering angle is obtained

230 VLSI Technology
by integrating the equation of motion for the scattering trajectory, using an atomic
scattering potential
V{r) = ^^—^/,(r) (13)
V{r) is a coulombic- (Rutherford- )type potential with screening function /^ . (The
Thomas-Fermi function is one example of /^ .) The nuclear energy loss is given by
dE -^-
'0
dx -^^
(14)
where J a is the differential cross section. LSS has introduced a number of reduced
variables that make the integration tractable and also lead to a "universal" curve for
the nuclear energy loss.' The reduced quantities are e, p, and t:
e (energy) =
M- ZZiq'
M^ + Mj
(15)
e,£
where a is the screening length equal to 0.88a q/ (2 + ZJ ) and QqIS the Bohr
radius.
p (distance) — Nira'^yx
Px
t (scattering parameter) = —
—
(16)
(17)
Ml
The value t is also used as an integration parameter for the energy loss. In reduced
'A . '/2
units the nuclear energy loss is then
Je ei dE e J
dp P dx pi
-^0 ^ Jo J '
'
where the following relations have been used:
dd = ira'fit'^-) dt''"~
P
N dcr =
y It
dt
f^^V2^
3/2
lA .
f'^ = e sm —
2
(18)
(19a)
(19b)
(19c)
1/2
The scattering function /(f ) depends upon the form of V (r ). The use of Thomas-
Fermi screening over the full range of / values results in a universal nuclear de/dp

10^
10^
10^
^ As"
.,
r
'
—
,
'^
. "^
^ d'
y ? >y
pN ^ y
^
H "•^
L _.^^^ ^
i'
^
B« »• < y
y
^
^
;:
e
^s
^
^^ ^y'
1-
e
= P* V s s
^.
"^^y
^^^^^
^^^^^^
^^
"V,
V
N s
<
N
^s
V
N = NUC
e=ELE
LEA
CTR(
R STOPPING
DNIC STOPPirMG
1
N^
10 100
ENERGY (keV)
1000
Fig. 7 Calculated values of dEldx for As, P, and B at various energies. The nuclear (A' ) and electronic {e )
components are shown. Note the points (o) at which nuclear and electronic stopping are equal. {After
Smith. Ref. 24.)
energy loss curve. ^ Other functions may give better physical estimates of ranges,
straggles, etc. The universal nuclear loss de/dp is independent of Zi, Zj, Mj, M2,
or N. In general, nuclear energy loss is relatively low at high energies. Fast particles
have a smaller interaction time with the scatterer—that is, the cross section is
reduced. At intermediate energies dE I dx [nuclear rises, and at the lowest energies,
where screening effects reduce the effective value of the target's coulomb charge Z2,
the value oidE / dx nuclear again is reduced.
The LSS electronic stopping, which is similar to stopping in a viscous medium, is
proportional to the ion's velocity.
dE/dx I electronic
= K^ (20)
The coefficient k^ is a relatively weak function of Zi, Z2, Mi, and Mi, the atomic
charges and masses. Values""* of actual nuclear and electronic dE/dx (keV/fxm) for
B, P, and As are plotted in Fig. 7. The values at electronic dE/dx are not monotonic
with incident mass, but the values are based on experimental data. When the nuclear
and electronic stopping curves are added, it is noted that the total value of dE/dx is
nearly a constant over a very large range of energies. See Problem 5. As a result the
range from Eq. (11) is nearly proportional to the initial incident ion energy.
Curves of projected range, Rp for B, P, and As in silicon and thermal Si02 are
shown in Fig. 8. Figure 9 shows the projected straggle ARp and the transverse strag-
gle A/? ^ for the same elements.
^^

232 VLSI Technology
1.0
E
<
^ 0.1
0.01
1 1 1
1 1 1 B(Si02 )^
^j- <
"-^ -"V .*
K^
'
.^
? r
.i^ /
J^ / ^t
,/'** / /
'f y
r
/
/
P(Si)-
.'
/
A
/
f
PCSiOg)
/
/
f
/./
r
r ^"•".^
2 y*
y ^ A r />
/ f jfi
/ ^^ /^
/ // A^
/ A J
/
J?
, ^
*-k
-As(Si)
.-^ ^4"-^
^^
y"/.
^y
<*' A8(Si02)
10 100
ENERGY ( keV)
1000
Fig. 8 Projected range, /?„, calculated for B, P, and As at various energies. The results pertain to amor-
phous silicon targets and thermal Si02 (2.27 g/cm-' ). (After Smith, Ref. 24.)
0.1
0.01
0.001
.'
t^. A-
«^ ^
4
,'!
'"^B(^ Rj^)
1
^'^ v^ ,
<1*^ •
'"^^ / yS .^ 1
,<r.
' y ^ / "~
^_ 1 1
V
'>'
y y y /
J^
y>
,.< -^
v'
/
/ ^ -^^^AsCARp)
^l^
/,
/ ,
>^ / 1
^ /
y
^
/ /^>/ ^As(ARi)
y
/I
/
/
N
^ P(ARp)
1 III
X ' ^
P (ARj^)
/ ^ N
/
> ^
y /^
/ /
/
10 100
ENERGY (keV)
1000
Fig. 9 Calculated ion straggle ^Rp (vertical) and AT? i (transverse) for As, P, and B ions in silicon. (After
Smith, Ref. 24.)

The two-moment description tells where the ions are located and roughly how
broad the distribution is. Higher moments (skewness and kurtosis) determine the
detailed shape. In practice we can make use of the Gaussian two-moment description
to quickly estimate doping distributions and then "fme-tune" the dose or energy to
obtain better results. However, we can anticipate the effects of a non-Gaussian
behavior on device behavior. For example, the skewed boron implants result in
"high doping" at the surface when deep p-wells are implanted (in CMOS technol-
ogy), and skewed arsenic implants result in "deep junctions" when n"*^ sources and
drains are fabricated. The non-Gaussian effects are both an intrinsic property of the
distribution and important for VLSI consideration.
Monte Carlo techniques have been used to calculate histograms for representing
the profiles that are fitted to the Pearson-IV solution, Eq. 8. Table 2 lists a set of
values^^ forRp,ARp,y, and p.
As previously mentioned, the distributions of implanted atoms in amorphous and
small (~100-A) grain-size polycrystalline silicon are the same. All results discussed
so far are for this case. However, implanted distributions into single-crystal and
large-grain polycrystalline silicon show the effects of channeling.
Table 2 Valuesof four moments and A/? j^
£(keV)
Ion Parameter 10 30 100 300
B Rp 382 1065 3070 6620
^^ 190 390 690 1050
y -0.32 -0.85 -1.12 -1.59
P2 3.2 4.49 5.49 8.35
^R^ 190 465 871 1523
P Rp 150 420 1350 4060
^^ 78 195 535 1150
y 0.45 0.20 -0.37 -0.91
P2 3.4 3.1 3.26 4.89
A/?| 61 168 471 1097
As Rp 110 233 678 1946
ARp 40 90 261 667
y 0.57 0.46 0.45 0.30
P2 3.6 3.4 3.4 3.16
A/?| 33 64 187 481
Sb A^, 100 208 507 1303
^^ 30 62 158 390
y 0.54 0.51 0.40 0.18
32 3.5 3.5 3.3 3.1
a;?^ 23 46 108 266
Noie.AR^ Furukawa^^ scaled to A/?p of Fichtner.^

234 VLSI Technology
6.3.3 Ion Channeling
Channeling starts to occur when an incident ion finds entry into an open space
between rows of atoms. "^ Once the ion is inserted, steering forces of the atomic row
potentials become operative and steer the ion toward the center of the open space
(channel). The ion is stably guided along the channel over considerable distances.
The ion gradually loses energy through its gentle, glancing collisions on the edges of
the channel, and eventually scatters out of the channel. Channeled penetration dis-
tances can be several times the penetration in amorphous targets, because the energy
loss for channeled ions is low compared with non-channeled ions. If attempts are
made to avoid channeling in single crystal silicon targets by the orientation to dense
atom directions (e.g., the (763)) then channeling effects are minimized but not elim-
inated (Fig. 10).
Profiles obtained by implantation into single crystals in such a way as to avoid
channeling are characterized by tails of atoms [as determined by careful secondary ion
mass spectroscopy, or SIMS (see Chapter 12) and tails of free charge doping (as
determined by electrical data)] . The channeling tails often can be fit to an exponen-
tial function of position, exp( —x I ), where is typically found to be —0. 1 fxm. The
tails are more prominent for phosphorus than for boron because the acceptance or crit-
ical angle for channeling is larger for heavier atoms. The critical angle is proportional
to z/-. For 50-keV phosphorus, il^crit
= 5.9°, while for 50-keV boron, i|;crit
~ 4.8°
along the (110) axis. The critical angle (for relatively high energies)^^ is given by
^crit =
IZxZiq^
Ed
'/2
(21)
where d is the atomic spacing along the aligned row.
The primary mechanism for tail formation in crystalline targets that are oriented
off major axes is believed to be channeling into major axes. (An alternate proposal
invokes an interstitial diffusion mechanism at implantation temperatures.) Experi-
ments with phosphorus prove that the tail of the distribution is due to channeling.
^^
Transmission of phosphorus ions through thinned silicon shows that ions emerge with
measurable energies and therefore are unambiguously channeled. The crystals are
about 0.5 |JLm thick and implanted with radioactive P-^^. The ions corresponding to the
INCIDENT /
DIRECTION
<763>
RANDOM
DECHANNELED
Fig. 10 Schematic diagram of an ion path in a single crystal for an ion incident in a "dense" (763) direc-
tion. The path shown has non-channeled and channeled behavior.

deep tail part of the distribution are collected at a second target in back of the thinned
silicon. These results, obtained for targets aligned off any major axes, can only hap-
pen if the ions in the tail of the distribution are channeled (and the interstitial diffusion
mechanism is not operative).
The practical use of the deeper-penetrating channeling ions has been considered.
However, profile control and reproducibility are difficult because of the very critical
control of orientation which is required. Figures 1 la and 1 lb show the critical control
that is needed for phosphorus and boron. The ions were implanted into silicon for
various orientations away from major-index axes. After a relatively low temperature
anneal (850°C), free-carrier profiles were measured using C-V techniques. Here, an
angular variation of one degree is shown to be significant.^''
The self-aligned gate of an MOS transistor often uses polysilicon (or other
polycrystalline materials) as a mask against implantation. If the range of channeled
ions is larger than the thickness of the gate material, then channeled ions can arrive at
the gate-oxide interface with enough energy to penetrate the gate oxide. A patchy-
doping effect, observed under large-grain, polycrystalline silicon gates, ^^ results in a
small population of depletion-mode MOSFETs when the grain size is comparable to
the electrical channel length. This effect can be avoided simply by selecting a gate
thickness that is greater than the channeled range plus several straggle distances.
6.3.4 Knock-On Ranges
Device fabrication often uses processing in which surface coatings are present on the
targets. When implantations are done through Si02 layers, oxygen and silicon atoms
are knocked into the underlying silicon. The range and numbers of oxygen atoms
recoiled from surface coatings are comparable to implanted arsenic concentrations.
Experimental results show that the free-carrier mobility is not degraded for arsenic
implanted into (100) surfaces through Si02 layers, although it is degraded for(l 1 1) sur-
faces. ^^ When ions are implanted, a major part of the disorder production is due to the
recoil or knock-on effects of target atoms. The multiple scattering and the final rest-
ing place of the recoils determine the radiation damage distribution.
6.4 DISORDER PRODUCTION
When ions enter a silicon crystal, they undergo electronic and nuclear scattering
events, but only the nuclear interactions result in displaced silicon atoms. The
sequence is as follows: In —10"'^ second a given ion comes to rest (this is roughly the
ion range divided by the average ion velocity Rp / VE/2M), in —10"'"^ second ther-
mal vibrations settle down to equilibrium values, and in ~10~^ second the non-stable
crystal disorder relaxes and some ordering occurs by a local diffusion process.
Light and heavy implanted ions have a qualitatively different "tree of disorder"
along the stopping track. Light ions (e.g., B") which enter the surface initially suffer
mostly electronic stopping. They gradually lose energy until nuclear stopping
becomes dominant. While undergoing nuclear stopping they displace silicon atoms

236 VLSI Technology
1017
1016-
E
o
Q.
O
O
1015b
1014
—
1 1 1 1 1 1 1 1 1 -
• 0N<111> z
* 1/2° 0FF<111> -
- o 1° 0FF<111>
a 2" 0FF<111>
-
>- ^ 6.5° OFF <111> -
V
-
D -
-
T^ = 8 50°C ^
'-' "~
_ 300 keV P
- 1x10l2cm"2
1 1 1 1 III III
(a)
0.4 0.8 1.2 1.6
DEPTH (fxm)
2.0 2.4
Fig. 11 (a) Donor free-carrier profiles for various orientations away from the (111) axis for 300-keV P^'.
(After Moline and Reutlinger, in Ref. 5b.)
and also change direction. The displaced atom profile has a buried peak concentra-
tion. In contrast to this heavy ions (P^^ or As^^) enter the surface and immediately
encounter a relatively higher fraction of nuclear stopping. They displace large
numbers of silicon atoms close to the surface. As they slow down, the nuclear stop-
ping power of the primary incident ion is nearly constant over most of the energy
values but recoiled atoms transfer deposited energy to greater depths. The final dam-
age density profile exhibits a broad buried peak which is a replica of the recoiled
range distribution.
An individual energy transfer process can result in different displacement confi-
gurations. If the energy transferred to a given silicon atom, Af, is less than the dis-
placement energy E^ , no displacement occurs. If the value of A £ is greater than E^ ,
one displacement and simple isolated defects occur. If A £ >2£'^ , we obtain stable
defects and secondary displacements. If AE^^E^, there are multiple secondary
(recoil or knock-on) displacements accompanied by defect clusters. These highest-
density disorder regions may be locally amorphous, especially for heavy mass ion
implantations.
A complicated array of different kinds of defects along the ion track results
because of the displacement profile. This inventory of defects consists of vacancies

1017
lO
I
I 101B
o
z
0.
O
O
10
15
- 1 1 1 1 1 1 _
-
^ CHANNELED <100X
- 1.0° 0FF<100> -
~ '
o 2.0°0FF<100> -
-
* "RANDOM" -7.4« "
-
T^ = 850°C
150 keV B
v
7x 10^^cm"2
1 1 1 1 1 1
(b)
0.2 0.4 0.6 0.8 1.0
DEPTH (^m)
1.2 1.4
Fig. 11 (continued) (b) Acceptor profiles for various orientations away from the (100) axis for 150-keV
B " . (After Seidel. in Ref. 5b.)
(V ) and—at least before a reordering thermal relaxation can take place at a typical
implantation temperature of 300 K—divacancies (V^), higher-order vacancies
(V^ V^), or vacancy-impurity complexes (V-Donor, V-Acceptor, V-Oxygen). In
addition, if beam heating during implantation is severe and temperatures exceed about
500°C, dislocations will form. The actual inventory of defects is complicated and
depends on position, thermal history, and impurity species. A fair number of the
incident ions end up on substitutional sites when they come to rest. However, the
damage in the absence of annealing produces a larger number of deep-level states
than the implanted ion concentration.
The nature of the actual disorder is a complex topic and depends on many factors
such as the crystal orientation and temperature of the target. The total energy depos-
ited into atomic displacements (Q^ eV/A per ion) has been calculated assuming that
ion channeling, thermal diffusion, and saturation effects are negligible during the
stopping process. ^° Figure 12 shows the calculated damage density (QoRp /E^) plot-
ted against distance (x/Rp) for boron and arsenic implantations into silicon. The dam-
age density and distance values are normalized. The density of displaced silicon N^^
atoms/cm^ is approximated by <^Qd/E^, where cj) is the ion dose (ions/cm^) and E^
is the target atom's displacement energy. For silicon, £^ is taken to be about 15 eV.

238 VLSI Technology
2.8-
o
2.4-
>- 2.0
UJ
Q
UJ
CO
<
1.6-
g 1.2
0.8
O
0.4
1 1 1
I 1
1000 keV
1 1 1
- Iroo
1
-
: 11.400 _
-
.
ll
-
-
/,
-
_
'1
l _
jjhooX,
Afrs^.
"
/^A/Md^
/^ 7) vj
- y
/
^/^
10^
xi
//^
'y y//
f
W^
^
T Vw x^^>C^^.^
T .v-
1
1
1 1
1 Vs^. i ^^5i4»j=--^:r—-^
1.0
X/Rp
2.0
(a)
Fig. 12 Calculated damage density profiles of (a) boron and (b) arsenic. (After Brice, Ref. 30.) The values
of deposited energy Qq are obtained by multiplying the normalized damage density by E^/Rp (eV/A).
Some values of E^ /Rp for B are 12.9 ( 10 keV) and 6. 1 ( 100 keV); for As they are 91 .4 ( 10 keV) and 99.3
(100 keV).
We can also attempt to simply estimate the number of displaced silicon atoms,
both at the surface and for the peak value of the nuclear stopping. In this case,
/Vdis(cm-3) = -^ dE_
dx nuclear
(22)
The value of the nuclear stopping power, dE/dx Inuciear^ can be taken from Fig. 7.
For 300 keV, 10^^ boron ions/cm^ and E^o = 15 eV, we obtain surface disorder con-
centrations of about lO^^/cmr', and a peak disorder concentration of about
7 X lO^^/cm-'. For arsenic the surface concentration is about 8 X 10^' /cm^ and the
peak concentration is about 10^^/cm^. From this it is clear that the heavier ions will
give displacement disorder concentrations approximately equal to the silicon density
at doses of —lO^^/cm^. These are order of magnitude estimates only and differ from
the detailed calculations-^^ by a factor of 2 to 5.

1.4-
^12
cr
o
o
^ 1.0
z
UJ
Q 0.8
o
<
I 0.6
o
UJ
N
0.4
O
0.2-
1 1 1 1 1
1 1 1 I
- As''' -
-
'
1000 kev
-
-
/ /
/
100
'
—^
10

-
-
y -
-
1 1 1
1 1 1 1 > r~
-
1.0
X/Rp
2.0
;b)
Fig. 12 (continued) (b) arsenic.
The total number of displaced atoms per incident ion is given roughly by-^
A^(^)total
= EJ2E.do (23)
where £„ is the incident energy available for nuclear stopping processes (i.e., the area
under the dE/dx | nuclear curve). The buildup of disorder is linear with dose until
saturation occurs, where a previously displaced atom again absorbs energy from
another implanted ion. When the number of stably displaced silicon atoms reaches
A^si = 5 X XQplcm', that is certainly by the time every target atom is stably dis-
placed the material changes phase and becomes "amorphous."
Other views hold that there is a critical energy density-'^' ^^
that must be placed
into the crystal to make it amorphous. This critical energy is
E, = (f)Ns,E^
(24)

240 VLSI Technology
4 5
1000/T (K"')
Fig. 13 A plot of the critical dose necessary to make a continuous amorphous silicon layer, against recipro-
cal target temperature for various ions. Arsenic falls between P and Sb. The temperature at which silicon
cannot be made amorphous is higher for higher-mass ions. (After Morehead and Crowder, Ref. 34.)
This result is applicable for low-temperature implantations and when the prefactor /
for silicon is approximately 0.1-0.5. It is likely that an amorphous state will form
before every atom is displaced. If the thermodynamic free energy of the damaged
state equals that of the amorphous state, a transformation will occur. The critical
dose to form an amorphous layer is given by D^ = E^ / {dE/dx nuclear)-
The effects of substrate temperature on the accumulation of disorder is substan-
tial. For example, consider an individual ion track with a locally disordered amor-
phous region. Such a region was modeled to be amorphous in a cylinder with an orig-
inal radius Rq, and the radius can shrink by the thermal motion of defect vacancies out
of the core of the cylinder. ^^ With the use of the vacancy out-diffusion idea, the tem-
perature dependence of the critical dose for an amorphous layer formation can be
estimated. For light ions such as B'^ a 50°C rise in temperature above room tempera-
ture prevents the formation of amorphous material at any dose (Fig. 13). This is
because boron implanted at room temperature produces only a few stably displaced
silicon atoms during implantation, and a slight rise in temperature allows the recombi-
nation of vacancy-silicon interstitial pairs.
The effects of non-uniform ion beam heating across wafers are interesting. If a
wafer is uniformly heated during implantation the accumulation of disorder will be
uniform and eventually a uniform buried amorphous layer will be formed. Since the

RED
BLUE
XS!-«A«'..**fe'<t.
1 000 A
SURFACE
CRYSTAL
AMORPHOUS
*,,« '^A>; n-fS-.W CRYSTAL
TEM
CROSS
SECTION
OF
SURFACE
DEEP
DISORDER
SMALL LOOPS
Fig. 14 Schematic showing color band effects. The transmission electron microscopy (TEM) cross-section
shows a buried amorphous layer. The implant was lO'^ argon / cm^ at 200 keV and 0.5 mA. (After Sheng
andSeidel, unpublished.)
index of refraction of amorphous layers is higher than that of crystalline layers we can
obtain interference effects (a color) from the buried amorphous layers. However, if a
wafer is non-uniformly heated (laterally across the wafer) the colder region will have
a thicker buried amorphous layer. These non-uniformly heated wafers exhibit a rain-
bow of colors.-'^ Figure 14 shows a schematic of a wafer with cold and hot ends
labeled, a side view schematic of the buried disorder, and a transmission electron
microscopy (TEM) cross section of a thin slice. The TEM structure is rich in detail,
showing light-dark contrast in the strained surface crystalline region, the buried amor-
phous layer, a buried dislocation layer deeper than the amorphous layer, and evidence
of very small dislocation loops in the tail of the disorder. Amorphous surface layers
also give interference effects. High optical absorption in the visible range limits color
effects to very thin amorphous surface layers. Disordered layers with mixed amor-
phous and crystalline phases also give visible interference effects.
^^

242 VLSI Technology
6.5 ANNEALING OF IMPLANTED DOPANT IMPURITIES
This section covers the increase in the free-carrier content and the decrease of
disorder as a function of anneal temperature for boron and phosphorus. A study of the
detailed annealing behavior leads to a unified view of annealing: The annealing of
amorphous layers is contrasted with annealing of point and extended defects.
One of the fundamental questions in the field of ion implantation is: What
minimal tem.peratures and times are required to achieve full donor or acceptor activity
without leaving degrading residual defects? A related question is: Can complete
electrical activity be obtained without significant atomic diffusion? The second ques-
tion is prompted by the need for very shallow junctions for the micrometer-size
designs of VLSI.
The systematics of annealing are both ion-dose- and ion-species-dependent. The
annealing will be discussed first in terms of the spatially integrated electrically active
charge (donors or acceptors) Nicm~^) = Jn{cm~^) dx. This data—the "areal"
density—is approximately obtained using the Hall effect technique. The Hall effect
measures an average, effective doping, which is an integral over local doping densi-
ties and local mobilities.
A^Hall =
2
X
'
M-n dx
I ' "M-^ d.x
(25)
where fx is the mobility and Xj is the junction depth. ^^^
For uniform doping layers, or
where the mobility is not strongly dependent on position, the relation gives A^Haii
~
J
^
n dx. In the data presented below, the measured Hall density is normalized to
the implanted dose <^. When all the atoms of the distribution become electrically
active, A^Haii ~ 4*' which is taken to be the condition for "full electrical" activity.
The Hall effect measures equilibrium majority-carrier concentrations and gives no
direct information about minority-carrier effects.
The number of displaced silicon atoms is almost always greater than the number
of implanted atoms. Thus the usual situation for a non-annealed sample is an electri-
cal layer dominated by deep-level traps. If an implantation is done into either n- or
p-type substrates of moderate doping (10^^ atoms/cm^^), the result is a high-resistivity
layer. Both electron and hole traps are produced.
6.5.1 Isochronal Boron Annealing
Figure 15 shows the isochronal (same time, different temperatures) annealing
behavior for boron, implanted at 150 keV and at three different doses. Three anneal-
ing temperature regions are noted as I, II, and III. The low-dose case shows a mono-
tonic increase in electrical activity, the two higher doses show a reverse anneal in
region II between 500 and 600°C.
Region I is characterized by point-defect disorders that dominates the electrical
free-carrier concentration. TEM shows no extended defects (dislocations) in this

"^ 0.1
I
001
1 1 1 1 1^-- J^ ^-H'
_ _
-^-^ Sxlo'Vcm^ / /
^^' / /
/ /
/ /
1
-
1 ^v / /
1
Ky 1
1
1
1
1
1
1 /^ ,« /
- / / ^'"^ / "HIGH TEMP
/ STEP"
-
- / /
-
- / /
-
- / /
V^^/^ -
/
"
/
/
/
/
- /
~
_
-
/
/
150 keV BORON
REGION I
1
REGION II
1
REGION m Ts=25°C
ta= 30min
1 1 1 1
400 500 600 700 800 900 1000
T^rc)
Fig. 15 Isochronal annealing behavior of boron. The ratio of free-carrier content (P^^) to dose (<t)) is plot-
ted against anneal temperature (r^ ) for three doses of boron. At T^ ^ 9(X)°C, the free carriers approach the
dose. {After Seidel and MacRae, in Ref. 5a.)
region. Increasing the annealing temperature from room temperature to approxi-
mately 500°C results in the removal of point defects such as divacancies. The boron
substitutional concentration also decreases up to approximately 5(X)°C,^^ but by a fac-
tor of ~2, while the free-carrier concentration increases by orders of magnitude,
which reflects the removal of trapping defects.
TEM studies show a dislocation structure in region II coincident with the removal
of substitutional atoms. ^^ Dislocations form above 500°C. Compared to the situation
at 500°C, the final state of region II at 600°C is a smaller boron substitutional concen-
tration and a larger nonsubstitutional boron concentration with an undefined^^ lattice
location. Therefore, the boron may be precipitated on or near dislocations.

244 VLSI Technology
In region lU, the substitutional concentration increases with approximately 5.0-
eV activation energy.'*^ This energy corresponds to the generation and migration of a
silicon self-vacancy species at elevated temperatures. Vacancies are generated and
then move to the nonsubstitutional boron (precipitate), allowing the boron to dissoci-
ate from the nonsubstitutional precipitate site. For lower doses of boron where no
reverse annealing occurs, substitutional behavior may occur without the need for ther-
mally generated vacancy species. At doses of approximately 10'~/cm'^, complete
annealing takes place at 800°C in minutes. A small but measurable diffusion is espe-
cially observable for lower-energy implantations where the straggle is only 250 A.
For higher doses of boron implanted at room temperature, complete electrical activity
requires a higher temperature. For higher doses of boron implanted at room tempera-
ture amorphous layers are not formed unless doses are above 5 x lO'^/cm"^. How-
ever, an amorphous condition for —10^^ boron/cm^ can be obtained by reducing the
target temperatures.
6.5.2 Isochronal Phosphorus Annealing
Phosphorus layers implanted in room-temperature substrates anneal in a qualitatively
different way.'*' At doses up to about lO'^^/cm", the implanted layers are not amor-
phous. Increasing the dose from 3 x lO'- to 3 x 10''*/cm'^ requires increasingly
higher annealing temperatures to anneal out the progressively more complex disorder,
similar to the case with boron annealing. In Fig. 16 the dashed curves are for implan-
tations where the damage is not amorphous and the solid curves represent amorphous
layers. After the phosphorus-implanted layer becomes amorphous at doses greater
than 3 x lO'^^/cm^, a different annealing mechanism comes into play. For all higher
doses the annealing temperatures are essentially fixed at about 600°C. This tempera-
ture is lower than that for annealing the non-amorphous (~10''*/cm'^) case! The
effect is associated with the solid phase epitaxial regrowth process that goes on for an
amorphous layer regrowing on a single-crystal substrate. Group V donor atoms are
essentially indistinguishable from the silicon atoms in the regrowth process, so
the implanted atoms are incorporated as substitutional during the recrystallization
process.
When the amorphous layer is not continuous in depth but is buried, a more com-
plex behavior occurs. Epitaxial annealing takes place at both interfaces and a
mismatch can occur when the annealing interfaces meet. Another interesting feature
occurs when a continuous amorphous layer is epitaxially annealed, for example
at 600°C. We can now consider the different annealing behavior for different parts
of the profile. Low concentration (
— lO'^/cm-^) doping (locally equivalent to
~ lO'^/cm"^ ) in the tail of the phosphorus distribution is well annealed, but the dop-
ing in the subamorphous—intermediate concentration ~ 5 x 10'''/cm-^ —part of the
profile has a low electrical activity. The low electrical activity is due to a high defect
concentration between the as-implanted, amorphous crystal boundary and the low-
concentration tail of the distribution. We will return to this feature when we compare
implanted phosphorus and BF2 annealed layers below.

10 -
08
06
04
2 -
5X10
1X10
280 kev PHOSPHORUS
Is = 25'='C
to - SOmin
3X10
6X10
13
1X10^^
14
3X10
NOT AMORPHOUS
AMORPHOUS
400 500 600 700
Ta(X)
800 900
Fig. 16 The ratio of free-carrier content to dose plotted against anneal temperature (T^ ) for various phos-
phorus doses. The solid curves represent amorphous layers that anneal by solid phase epitaxy. The dashed
curves represent implantation where the damage is not amorphous. {After Crowder andMorehead, Jr.. Ref.
41.)
The annealing behavior for room-temperature-implanted arsenic and antimony is
similar to that of phosphorus, except that lower doses are required to make the layer
amorphous.
6.5.3 Synthesis of Annealing Behavior
One way to test the basic explanations offered for the annealing of implanted boron
and phosphorus is to implant boron into cold substrates to produce an amorphous
layer and also to implant phosphorus into hot substrates to prevent the formation of
amorphous layers. Figure 17 shows the result of such a study for boron and phos-
phorus."^- The annealing behavior of both boron and phosphorus in the presence of
amorphous layers is similar. There is no reverse anneal for boron at a dose of
lO'^'/cm- when the layer is amorphous, and rather complete annealing occurs for
600°C epitaxial annealing. The annealing behavior of boron and phosphorus in non-
amorphous layers is also similar. Figure 17b shows a reverse anneal for the electrical
activity of the 200°C implant for high-dose (5 x lO'^/cm") phosphorus. This occurs
without the accompaniment of an amorphous to crystalline, solid phase epitaxial
mechanism. Instead, as seen in TEM studies, a dislocation structure is associated
with the reverse anneal of phosphorus implanted into hot targets.

246 VLSI Technology
10''
10'
/
cf
,^
.--c<
/ 400''C
BORON 50kev,io'^/cm2
ANNEAL lOmin
(a)
400 500 600 700 800 900 1000
10^
10 -
10"^ -
1 1
—U~^.l—^^^—'
A-v
if- A ^^^-'
/ 9 Q-^^^T-
/ /^—-o'"
/
^
/p eoooQ
200 °C
y
/ b 1/
/ 7^
V J
d PHOSPHORUS
IOOkev,5xio^'*/cnn^
^^25 "C
1 1
ANNEAL; 60min
1 1 1 1
(b)
300 400 500 600 700 800 900
ANNEALING TEMPERATURE (°C)
1000
Fig. 17 (a) Isochronal annealing curves for boron implanted at various substrate temperatures. (After
Yoshihiro et al., Ref. 42.) (b) Isochronal annealing curves for phosphorus implanted at various temperatures.
(After Tamura, Ikeda. and Tokuyama, in Ref. 5b.)
In summary, the annealing behavior for boron and phosphorus is similar if amor-
phous layers are formed and solid phase epitaxy occurs. If no amorphous layer is
formed, a reverse anneal occurs at about 5(X)°C and this is accompanied by the forma-
tion of extended defects. These dislocations require 900 to 1000°C temperatures to be
removed.
One other aspect for annealing of implanted impurities is the existence of small
dislocations in the deep tail side of the distribution.^-^ If arsenic is implanted (amor-
phous layer) for sources and drains, and annealed in the 600 to 850°C temperature
range to make use of solid phase epitaxy, there will be small (~ 50-A) dislocations in
the tail of the distribution.

TIME (min)
Fig. 18 Isothermal annealing of boron. (After Seidel and MacRae, Ref. 40.)
6.5.4 Isothermal Annealing (Kinetics)
Additional information can be obtained by annealing at fixed temperatures for various
times. We will first discuss the example of a non-amorphous case: implanted boron
annealed at temperatures above 600°C and for doses between lO'^ and lO'^ ions/cm^.
As time is increased, the doping increases rather "slowly," requiring several orders
of magnitude of time to go from the initial fractions to >90% (Fig. 18). The shape
results because the lower concentration part of the profile anneals first, and the central
region anneals last. After approximately 35 minutes the 10 '^/cm^ profile has electri-
cally active boron in the wings of the distribution and inactive boron in the central
region^' (Fig. 19). If the time constants for the annealing are plotted on a log t versus
7"' (assuming t ~ ^ " /T ), straight lines give about a 5.0-eV activation energy."^
This high activation energy corresponds to the generation 3.4-eV and migration
1.6-eV energy of thermally generated vacancy species. The intrinsic silicon self-
diffusion, interpreted as vacancy generation and migration, has been independently
measured using radio tracer techniques.'^ Non-substitutional boron in the central part
of the distribution is considered to be associated with both boron impurity disorder
complexes and boron impurity pinning at dislocations. Thermally generated vacan-
cies migrate to these nonsubstitutional locations, and substitutional behavior occurs.
Various mathematical models using specific point defect species can be
developed.'*^ One such model uses coupled diffusion equations with three species:
boron substitutional concentrations (B~ ), positively charged vacancy concentrations
(V"^ ), and neutral boron-vacancy complexes (B~ V^ ). The boron vacancy complex
is viewed as electrically inactive but rapidly diffusing. By comparing channeling
measurements with electrical activity, it is clear that most, if not all, of the substitu-
tional boron is electrically active in the 700 to 1000°C annealing temperature range.
Precipitation associated with boron on dislocations can be added to the model to
account for the non-substitutional boron.
Amorphous implanted layers anneal by the solid phase epitaxy process. The rate
of regrowth has been studied in detail for various crystal orientations and doping con-
ditions.'^^ When silicon is made amorphous by implanting silicon into silicon, the
rates of regrowth are: approximately 100 A/ min for (100) orientation and 3a/ min for

248 VLSI Technology
^20
• o o •
U«ooo° Oq •.
- 10"
10'
10'-
ii 10
u
z
o
10'
10
1
^^7^ ^
r 1

^
r
T. =800°C
Oo«
o •
o •
70kev
lo'^cm^
ta = 35 min
•••••
T. =900°C
• BORON
O FREE CARRIERS
I I I I I
(a)
(b)
0.2 0.4 6 0.8 10
DEPTH (/i.m)
Fig. 19 Concentration profiles of boron atoms (SIMS—solid dots) and corresponding free-carrier concen-
trations (HaU data—open circles), (a) At 800°C and (b) at 900°C. (After Hqfker. Ref. 21.)
(Ill) orientation at 550°C (Fig. 20). For the (1 1 1) surface, the slower rate is accom-
panied by defective (twinned) silicon. This is proposed to be due to growth along
inclined (111) planes.
Plotting the regrowth rates against reciprocal temperature gives an activation
energy of 2.3 eV. This low temperature process is associated with bond breaking to
allow reordering at the interface. Adding impurities such as O, C, N, or Ar slows or
disorganizes the regrowth, presumably because the impurities tie up (remove) broken
bonds. Impurities such as B, P, or As increase the growth rate (by a factor of about 2
for I0^° impurity atoms/cm-^) because the substitutional impurities weaken and
increase the likelihood of having broken bonds.
For certain cases (such as high-dose arsenic), annealing at temperatures near
550°C followed by a high temperature results in a more orderly recrystallization proc-
ess.'*^ If the formation of polycrystals or high-concentration dislocations can be

TCC)
600 575 550 525 500
Fig. 20 The solid phase epitaxial regrowth rate of amorphous siUcon as a function of temperature for vari-
ous crystal orientations. (After Csepregi. Mayer. andSigmon. Ref. 46.)
avoided (which could happen with a fast high-temperature anneal), then isolated
dislocations can be annealed out by a second anneal"^^ at ~1000°C.
6.5.5 Diffusion of Implanted Impurities
The diffusion of implanted impurities in silicon is complex even when there is no ion
damage. The role of thermal silicon vacancies (their associated charge states) and sil-
icon interstitials are important as are the effects of sinks of sources or these species
(Chapters). Diffusion of implanted impurities requires consideration of damage-
induced vacancies, interstitials. their vacancy-impurity species, and extended defects.
Consider the case of 10^^ boron atoms /cm~ implanted at room temperature, giv-
ing a non-amorphous layer."' Figure 21 shows that the profile broadens in the tail
region (at 7(X) to 800°C in 35 minutes) while the peak concentration remains undif-
fused. This tail diffusion is anomalously high compared to published boron diffusion
coefficients. This diffusivity may be enhanced because of the break-up of silicon-
vacancy and interstitial-cluster species; vacancies should enhance the substitutional
diffusivity, and silicon interstitials can replace substitutional boron resulting in a
rapidly diffusing interstitial-boron species. The undiffused peak concentration has
disorder that does not break up at 700 to 800°C.
At 900°C the peak concentration broadens, while the boron on the sides stays
rather fixed. One probable explanation is that the dislocation disorder in the peak

250 VLSI Technology
20
10'
E 10*^
10"
10
ANNEALING TEMPERATURE
• NO ANNEALING
700°C
800°
C
A 900°C
+ lOOCC
o IJOOX
70keV BORON
lO'^ BORON ATOMS/cm^
I i I L
0.2 0.4 0.6 0.8
DEPTH (/i.m)
1.0 1.2
Fig. 21 Boron atom concentrations as a function of annealing at various temperatures. The anneal time is
35 minutes. (After Hofker. Ref. 21.)
concentration begins to anneal, giving silicon vacancies and interstitials that can pro-
mote diffusion. The profile of boron at 900°C and 35 minutes can be fit by an effec-
tive diffusion constant which is about three times that for the ''normal" 900°C value
(3 X 10"'^ cm'/ s versus 1 x I0"'^cm2/s).
At 1000°C additional thermal broadening occurs, but the effects can be described
by ordinary diffusion theory. The diffusion constant is independent of position on the
profile. Thermal vacancies and interstitials can participate in the diffusive motion.
If one assumes that the diffusion coefficient is constant, and therefore indepen-
dent of position, time, defect concentration, etc., then a simple solution can be writ-
ten for a Gaussian distribution."^^ The initial implanted distribution is taken to be a
Gaussian, and the solution to a limited-source diffusion is also a Gaussian. Thus a
solution to Pick's equation dn/dt = D d^n/dx^ is obtained if ^,Rp is replaced by
The solution is:
^R^ + mt
n{x,t) = cl>
V2^VA/?/ + IDt
exp
-ix Rr
2(A/?„- + IDt)
(26)
Boundary conditions also may be imposed, for example, which require no particle
current to leave the surface during the diffusion. Solutions with oxides present have
also been developed.^*^
6.5.6 Rapid Annealing
Implanted layers can be annealed using laser beams with energy densities of
~ 1 - 100 J/cm^. Many potential advantages of this method have been proposed. ''^^ ^'
Because of the short duration of the heat, profiles of implanted impurities may be
annealed without appreciable diffusion. An implanted amorphous layer 1 kA thick is

10
DEPTH (A)
4 176 528 880 1232 1584 1936
10^
' r I
r
FURNACE ANNEAL
(I000°C 30min)
40 80 120 160 200
SPUTTERING TIME (s)
240 260
Fig. 22 Profile of arsenic implanted into silicon and annealed both with a CW laser and with a standard
thermal anneal. The as-implanted Pearson-IV distribution and the laser annealed profiles are virtually identi-
cal . (After Gat etal., Ref. 52 .
)
annealed in a few seconds at 800°C using solid phase epitaxy. The diffusion length
Vot of dopant impurities is only a few angstroms. Figure 22 shows a plot of the con-
centration (counts) from a SIMS measurement against depth for arsenic using a CW
laser and solid phase epitaxy (SPE). Electrical measurements on the annealed layer
shows that the electrical activity from sheet resistance is comparable to a 1000°C,
30-min standard thermal furnace anneal. The impurity profile of the laser annealed
sample is identical to that of an "as-implanted" distribution.
The rapid annealing process is inherently clean—furnace contamination in the
usual sense is not a problem. Laser energy may be localized over part of an IC chip
so some junctions of the circuit can be diffused more, while others are not altered.
One possible use would be the fabrication of a locally adjustable junction depth, or
the production of different breakdown voltages on this same chip.

252 VLSI Technology
z
UJ
o
PULSED LASER
PULSED LASER, ELECTRON, IONS
CW LASER
FURNACE ANNEALS
hSCANNED ELECTRON-
BEAMS
_ HIGH CURRENT IMPLANT"
I I I
10-12 10-10 10-8 10-6 10-4 10-2
ANNEAL TIME (S)
INCOHERANT
ANNEALS
J L
I02 lO'*
Fig. 23 Power density plotted against anneal time (pulse duration) for various rapid thermal annealing tech-
niques . (After Current and Pickar, Ref. 11 .)
An exciting discovery of the pulsed laser annealing technique is that after
implanted amorphous layers are melted and undergo liquid-phase epitaxy, no
extended defects are observed by TEM. This process is believed to involve a melting
of the amorphous material and resolidification on the underlying single-crystal tem-
plate. There are, however, substantial point defect concentrations that exist as a
result of the rapid resolidification process. Low-temperature (400°C) annealing and
use of hydrogen plasma ambients reduce the effect of point defect concentrations.
Devices have been made with varying success, such as bipolar and MOS transistors
and silicon solar cells. The performance of these laser annealed devices are generally
comparable, but not substantially superior to their thermally annealed counterparts.
Rapid thermal annealing techniques now include pulsed lasers (with times down
to a few picoseconds), pulsed electron and ion beams, scanned electron beams, CW
(scanned) lasers, high-beam-current implants, and broad-band spectral sources (high-
intensity lamps^^) with "fast" (50-second) programmable anneals. These techniques
are illustrated in Fig. 23, where the power density (W/cm^) is plotted against the
anneal time. Most of the techniques fall along a locus of 1 .0-i/crn^ energy density.
Use of broad-band spectral sources and heating with electron or ion beams avoid
optical interference effects and still keep the advantages of rapid thermal annealing.
The practical use of rapid thermal annealing appears to be close at hand.
6.5.7 Annealing in Oxygen Ambients
Annealing processes that result in the complete return of implanted ions to electrically
active substitutional positions usually leave microdefects. These microdefects, which
are observable by TEM, are referred to as secondary defects.
Studies show that if implantations (of B, Ne, or P) at room temperature are fol-
lowed by thermal oxidation, any extrinsic microdefects are expanded into large dislo-

50^ m
Fig. 24 Photomicrograph of a silicon surface that was implanted with boron (lO'^'/cm^) on the left-hand
part, oxidized at 1 150°C for 6 hours in oxygen and then Secco-etched. (After Prussin, Ref. 53, and Robin-
son el al., Ref.54.)
cations and stacking faults. These defects, referred to as ternary defects,^-^ are large
enough to be seen with optical microscopes after cheniical etching (Fig. 24).^"^ Oxida-
tion creates an excess concentration of silicon interstitials at and near the Si-Si02
interface. These interstitials "plate out" on any microdefect (nuclei), forming a
stacking fault. Thus implantation provides defect nuclei which will grow when fed by
a high concentration of silicon interstitials. These defects can degrade device perfor-
mance. To avoid these defects, the recommended procedure is to anneal in neutral
ambients (e.g., N, Ar) and then follow with any necessary oxidation.
6.6 SHALLOW JUNCTIONS (As, BF2)
The requirements for VLSI shallow junctions for n^ layers are rather easily met by
the implantation of As. Arsenic has a very shallow range Rp ( ~300 A) while using a
convenient implantation energy, 50 keV. This moderate energy allows the use of
relatively high beam currents in most accelerators. The heavy ion species results in
an amorphous layer, so low-temperature solid phase epitaxy can be used to produce
doped layers without appreciable atomic diffusion. If necessary, the arsenic layer can
be annealed at 900°C with very little diffusion.
Future implementation of VLSI includes CMOS designs; therefore, shallow p"^
junctions are also of great importance. These junctions are not easily obtained using
B"^ implantation, since high-dose B^ implantation at room temperature targets does
not give amorphous layers. Anneal temperatures > 900°C are required to get full
electrical activity and considerable diffusion occurs. The implantation range at
30 keV, which is the lowest practical energy for obtaining high beam currents, is
1000 A and undesirably large.
The problems associated with boron are practically alleviated^^ by using the
molecular species BF2. The dissociation of BF2^ upon its first atomic scattering event

254 VLSI Technology
gives a lower-energy boron atom. The energy of the boron atom is (Mq /Mqp^)Eq =
(ll/49)£'o, where Ms and Mbf, are the masses of the boron and BF2 molecule,
respectively, and £0 is the incident energy of the BF2 molecule. Thus, 50-keV BF2
gives a boron range of —300 A.
Also, BF2 provides an annealing advantage. Flourine ions are relatively heavy,
giving an amorphous zone that contains most, but not all, of the boron (Fig. 25a).
„ 10'
E
10"
1 1 1
SSO'C ANNEAL
-
BORON ATOMIC
PROFILE
lOmin — o
20min — V
30min —
O
eomin — A
100 mm - n
INACTIVE
DOPANT
r.^'^
' 1 ' 1
1 1 1 1 1
U
E" 0^^ ^
7 c
-
lb
eOO'C ANNEAL -
GAUSSIAN I
- °r ° tQ = 30min
1

- 0.

,-,18
1 1

U • 1 »H
-
?- -
: ° I • ^. :
- /
• 1
Q
UJ
-
>
1-
<
•
17
_
— 1
—
<

-
/
-
/ ' •
till 1 1

,> 1 ,
100
-k
1 1 1 1 1
80 -
fiO -^. _
13 •OD-D-OOOO-
40 -
1 1 1 1
1
500 1000 I500_^ 2000 2500 3000
DEPTH (A)
02 04 06 01
DEPTH (micrometers)
(a) (b)
Fig. 25 Free-carrier concentration and mobility profiles for implanted layers which illustrate dopant incor-
poration by soUd phase epitaxy (SPE). (a) Profiles for BF2^ implanted into (100) silicon at 150 keV and
lO'^/cm^ after different isothermal anneals. The dotted curve is the as-implanted atomic profile from SIMS
analysis. The original amoiphous-crystaUine interface is denoted by the arrow, SPE is complete after —100
minutes. The hatched region is electrically inactive. (After Tsai and Streetman. Ref. 55.) (b) Profile for sili-
con implanted at 280 keV and 3E14 P'''/cm'^. The original amorphous-crystalline interface is denoted by
the arrow. The inactive region is also noted. (After Crowder. Ref. 56.)

Solid phase epitaxy can be used to anneal the amorphous layer in the order of minutes
at temperatures of 550 to 700°C. The portion of the B profile that is initially con-
tained within the amorphous layer shows full electrical activity. The region between
the tail (not measured in Fig. 25a) and the amorphous layer has free carriers compen-
sated by defect traps, which need higher temperatures to anneal. Similar effects were
found for the phosphorus P^ implantations'*^ previously mentioned (see Fig. 25b).
The similarity and comparison of the two implanted layers should be noted. Finally
BFt^ implants exhibit less ion channeling than B implants due to the formation of an
amorphous region, and boron redistributes in the damaged and flourine-rich regions
during annealing.
6.7 MINORITY-CARRIER EFFECTS
Various measurements characterize the effects of residual disorder on minority car-
riers. These measurements include junction leakage, bipolar transistor gain,
forward-to-reverse bias recovery time, MOS pulse recovery technique, thermally
stimulated currents, deep-level transient spectroscopy (DLTS),^^'' and electron-beam-
induced current (EBIC).
Junction leakage typically recovers to within about one order of magnitude of an
unimplanted control, when implant-induced damage is annealed above 8(X)°C.^^ This
incomplete recovery is perfectly adequate for digital MOS, bipolar, and most memory
applications. Present VLSI manufacture uses annealing conditions that diffuse the
ions slightly beyond the original ion and damage distributions. Future annealing stu-
dies will need to consider the applicability of minimum annealing and thermal diffu-
sion for devices with high lifetime requirements.
6.8 GETTERING
Physical phenomena which use the concepts of gettering (the removal of impurities
and defects from junction regions) can help control leakage currents for very shallow
junctions of VLSI application. The use of ion implantation damage for gettering of
heavy metal impurities has been known for some time. Gettering action requires
three physical effects, regardless of the specific method used: (1) the release of
impurities or the decomposition of the constituents of extended defects (here we are
distinguishing impurity removal from defect removal), (2) the dijfusion of the impuri-
ties or constituents of a dislocation (that is silicon self-interstitials) to a capture zone,
and (3) the capture of the impurities or self-interstitials at some sink.
Thus to get good gettering, "impurities'" must be released, diffused, and cap-
tured. If any one of the three mechanisms is inoperative, then gettering will not be
effective. For example, the capture mechanism can be perfect, so that every impurity
atom which enters the capture environment is captured and no particles come back
out. However, if no impurities are released or diffused then gettering will be poor and
can be thought to be rate-limited by the release or diffusion effects. For

256 VLSI Technology
implantation-induced disorder, the "sink" is either a dislocation array or polycrystal-
line grain boundaries.
We will now classify and discuss four major techniques for the gettering (cap-
ture) of impurities.
6.8.1 Ion Pairing
Phosphorus diffusion is an effective gettering technique. Impurities such as copper,
which are known to be mainly interstitial in undoped silicon and to diffuse by an
interstitial mechanism, take the shape of the diffused phosphorus profile. ^^ Thus the
diffused phosphorus in the silicon and Cu are correlated. It is further known that all
the Cu is on substitutional lattice locations within the phosphorus profile. This has
been demonstrated using analysis by He ion backscattering from copper combined
with channeling. In this experiment the sample under study was first contaminated
with Cu and then getter-diffused with phosphorus, so both gettered Cu and the P are
near the surface. The probing ion (He) is then channeled into a silicon surface. The
He ion backscattered yield versus backscattered energy is shown in Fig. 26a. The
channeled yield is reduced from the random yield, the random yield is obtained with a
non-channeled condition. Since the Cu is substitutional, the channeled probing He
ions do not backscatter from the copper. The non-channeled or random spectra show
2 X lO^^/cnr gettered copper to be located in a layer about 2500 A thick, which is the
10^^
1
I 1 1 M
7
1
1
1 '
1
1 1 1 1 1
: RANDOM
,
:
10^
-°°°n^
•
E °D ^ :
^D . -
- <^io>
/^ -
o
-• 2
CHANNELED' D ,
^ 10 - -
>- : a* z
-_
% CU
-
•
T^'P
io'
E
d
• ;250CV
- . (XD- '-4
10° 1 1
•cm cm*——"
1 1 rmniiiiiuLiiiin.
20 40 60 80 100 120 140 160 180 200
CHANNEL NUMBER
(BACKSCATTERED ENERGY)
(a)
ElO'
u 10''
O
10'
10'
A PHOSPHORUS (ARB UNITS)
o GOLD, AFTER PHOSPHORUS
DIFFUSION
0.1 0.5
DEPTH (;i.m)
(b)
Fig. 26 Data for Cu and Au gettered in phosphorus diffused silicon, (a) Spectrum from Rutherford back-
scattering for Cu contaminated sample gettered by phosphorus diffusion at 1 100°C. The channeled spectrum
(D) shows the Cu is substitutional. (After Seidel and Meek, Ref. 59.) (b) Profiles of gold and phosphorus
obtained by neutron activation analysis on a 900°C phosphorus-diffused gettered sample. (After Lecrosnier
etal..Ref.60.)

high-concentration part of the phosphorus profile. Phosphorus donates a large
number of electrons to the substitutional acceptor charge state of copper, making it
Cu~'^. This gives a large coulomb binding energy between substitutional Cu and P.
In summary', copper diffuses, as an interstitial atom with a very large diffusion
coefficient, to reach the phosphorus in its diffusing profile, and then copper finds a
vacancy next to the phosphorus atom and "ion pairs'" as P^Cu~-^. The binding
energy and diffusion are both species-dependent.
Results for iron or gold are only quantitatively different because of their singly
charged state ( — ) and their lower thermal diffusivity. Gold, which is gettered under
the phosphorus-diffused profile, not only follows the phosphorus profile near the sur-
face but also follows the shape of the phosphorus diffusion tail (Fig. 26b).
^^
Phosphorus diffusion gettering requires both a high concentration and a thick
layer of phosphorus. Lowering diffusion temperatures to conform to VLSI applica-
tions reduces the concentration and depth of phosphorus. Below about 900°C, dam-
age capture mechanisms can become better than phosphorus diffusion.^'
6.8.2 Damage Gettering
Damage gettering has been demonstrated using: sandblasting, mechanical shot abra-
sion ("sound stressing"), laser-induced damage, and ion implantation.
Certain ions when implanted at high doses (lO'^/cm") do not allow good solid
phase epitaxy. Under annealing, the strain, precipitation, or defect character result in
dislocations and polycrystalline material with grain boundaries. In particular, when
inert gas ions are implanted (such as Ne, Ar, and Kr) and are annealed the gas
coalesces to form internal bubbles with faceted crystallographic surfaces.^" These sur-
faces form multiple platlet substrates upon which multiply seeded solid phase epitaxy
takes place, resulting in a polycrystalline structure. The detailed damage is
concentration- and species-dependent.
Although grain boundary gettering is quite efficient, it has been shown that iso-
lated dislocations with large '/2(110) Burgers vectors efficiently getter at a lower
dose^^ (Fig. 27). When dislocations overlap and relieve strain, their ability to getter is
reduced. In Fig. 27 this effect occurs at a dose of approximately 3 x 10'^''/cm^.
An optimum gettering temperature has been reported, again for specific cases;
this may be the manifestation of the idea that too low a temperature gives a diffusion-
limited gettering and too high a temperature results in too much thermal energy to
hold the gettered impurities in the "sink" provided^ (Fig. 28). Figure 28 also shows
substantial improvement in minority-carrier lifetime for argon implantation annealed
at 850°C.
6.8.3 Intrinsic Gettering
We can use the bulk silicon substrate to getter if there are SiO^ precipitates and asso-
ciated dislocations in the sample. In this case one starts with oxygen concentrations
close to the solid solubility^^ ( ~ lO'^ / cm-^ ). Upon heat treatment in neutral or oxidiz-
ing ambients at ~1 100°C, the surface regions become denuded of oxygen by the out-

258 VLSI Technology
(r
loV "1
—I
—I I I 1 1
1|
TTTD
BARE Si
o SCREEN OXIDE
8/^„2
~IO°/cm'
ISOLATED
DISLOCATIONS
t--
— ^
A
/
I I I 1 1 1 1 1
1
10^5
DOSE (lONS/cm )
10^6
Fig. 27 Relaxation leakage current as a function of dose for Xe'^'^ implanted into bare silicon and Si02 on
the back of the wafer. "Annealing" was jDcrformed at 1000°C in dry oxygen for 80 minutes. Optimum
gettering is at doses in the mid-lO'^^/cm- dose range. (After Geipel and Tice, Ref. 63.)
diffusion of oxygen. The sample is tiien annealed at ~800°C, where the oxygen in
the interior is super-saturated and the SiO^ precipitates form. These precipitates
"punch out" dislocations to act as sinks for heavy metal impurities, while the surface
regions are denuded of defects. Junction regions near the surface are free of defects,
while the interior of the silicon is filled with gettering sites.
6.8.4 Ambient Gettering
It is possible to clean the furnaces and wafer surfaces of heavy metal contaminants
when oxidation is done in the presence of HCl. The heavy metal chlorides (e.g.,
CuCl) are volatile and are swept away from the wafers and out of the furnace tube.
A shrinkage of stacking faults is also seen^^^ when oxidations are done in the presence
of CI.
6.9 EFFECTS IN VLSI PROCESSING
There are many known effects which may play a role in an emerging VLSI technol-
ogy. After implantation, the Si, Si02, photoresist, or metal target is modified and can
change the behavior of subsequent process steps. We briefly discuss some of these
effects.
High doses of nitrogen considerably decrease the oxidation rate because of the

700 800 900 1000
ANNEALING TEMPERATURE (°C)
Fig. 28 Lifetime versus gettering temperature for argon, BF2, and PH3 diffusion in (100) and(l 1 1) silicon.
The implants were 150 keV, lO'^/cm-; and anneals or diffusions were done for 30 minutes. (After Ryssel
andRuge, Ref. 64.)
formation of "nitride," while damage introduced by B, Ar, As, and Sb can increase
the oxidation rate by various amounts. ^^ These effects may be used to modify oxide
thicknesses on different parts of a VLSI device. In another apphcation, oxides with
surface damage have been used to taper the edge of etched windows, and the surface
region etches more rapidly than the undamaged region.
Implantation into oxides results in broken bonds, with displaced oxygen and sili-
con atoms. After annealing, an implant-species-dependent electron trapping effect is
observed. Understanding^^ of electron trapping effects continues to be important
since scaling to small dimensions brings high electric fields in the drain region of
MOS devices. Some VLSI devices will be operated at the onset of avalanche multi-
plication which might supply electrons to the traps.
When photoresist is used as an implantation mask it is damaged during implanta-
tion. The result is bond-breaking and evaporation of the volatile components such as
hydrogen and nitrogen. A carbon-rich layer is obtained which can be removed with
oxygen plasma, ozone, or an oxidation processes.
Implantation into metal-silicon interfaces leads to interface reactions. For exam-
ple Mo films on silicon were converted to MoSi by a sufficiently high dose of phos-
phorus.^^ The contact resistance was reduced, presumably due to the knock-on effects
at the interface, which have been referred to as ion-beam mixing.

260 VLSI Technology
Some silicide formations result in the segregation of previously implanted
dopants. For example, arsenic is driven ahead of platinum and palladium during PtSi
and Pd2 Si formation. ^^ Segregation behavior can result in lower contact resistance for
VLSI contacts.
Ion implantation is now being used in every doping step of a typical VLSI process.
We can distinguish between low-dose and high-dose applications. Low-dose applica-
tions include: the threshold voltage control for MOS devices, resistors, n-well and p-
well doping for CMOS devices, control of the vertical dimension of the space charge
width, and base doping for bipolar transistors. High-dose applications include self-
aligned source and drain for MOS devices, high-conductance resistors, buried layers,
and emitters for bipolar transistors.
We now look forward to the possible widespread use of shallow junction depths
(—1000 A) in MOS devices where most of the doping is contained in a 200 A-thick
layer. MOS devices with electrical channel lengths as small as 0.5 ixm seem feasible
using the principles we have discussed. The channeling effects and atomic diffusion
must be reproducibly minimized to give shallow and controlled junctions. Preamor-
phizing the silicon eliminates channeling effects on the implanted profile. Impurity
diffusion may be altered and possibly reduced by the interactions of impurities with
point and extended defects.
Devices with ultra-narrow depletion widths of approximately 200 A will show
hot-electron effects. If the electron mean free path (
— 100 A) is of the order of thick-
ness of the depletion widths, ballistic effects set in. Electrons are accelerated through
the thin layers without scattering and can reach high velocities. Various hot-electron
transistor devices have been proposed. These are an extension of the concept that
very shallow implanted layers can lower and narrow the barrier of Schottky devices.
^°
Bipolar VLSI will continue to make use of the Schottky barrier modifications because
logic level differences are directly generated from the Schottky barrier differences.
In addition, high concentrations of impurities confined to very narrow widths can
give low-temperature-coefficient, high- sheet-resistance monolithic resistors. The ion-
ized impurity and lattice scattering temperature dependencies offset each other and
—4 kCl/r sheet resistances with < 300-ppm/°C temperature coefficients are
obtained. Finally, if the depletion layer thickness of a depletion MOS device can be
made thin most of the carriers can be easily controlled by the gate to obtain relatively
high transconductance.^^
Presently the ultimate device dimensions are not known. However, for gate
dimensions of 0.1 x 0.1 ixm and for a 10^^ /cm^ channel doping in an enhancement
MOSFET, we will have statistical doping effects. For a 200 A-thick depletion layer,
the number of atoms under the gate is only 40. The fluctuation, taken to be Vn /N is
approximately 20%.
In the beginning of this chapter, ion implantation was defined in terms of avoid-
ing surface effects. This requires kinetic energy. When it comes to making the shal-

lowest possible junctions, it is not at all obvious that low-energy (~3-keV) implanta-
tion will be more useful or practical than thermal diffusion. The past problems of
thermal diffusion (cleanliness, surface oxides, and control of doping concentration)
are not fundamental. The shallowest junctions are probably obtainable from the use
of thermal, and not kinetic, energies. However, implantation, with its obvious advan-
tages, will continue to play a major role in VLSI in the foreseeable future.
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Implanted Silicon,' ' Appl. Phys. Lett., 14, 313 (1969).
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[43] H. Foell. T. Y. Tan. and W. Krakow, "Undissociated Dislocations and Intermediate Defects," in
J. Narayan and T. Y. Tan, Eds., Defects in Semiconductors. North-Holland, New York, 1981.
Vol. 2,'p. 173.
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38.3148(1967).
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Annealed Ion Implanted B in Si," in Ref. 5e. p. 71 1.
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"Ion Channeling Analysis of Disorder." in J. Narayan and T. Y. Tan. Eds.. Defects in Semiconduc-
tors. North-Holland. New York. 1981. Vol. 2. p. 135.
[47] L. Csepregi. W. K. Chu. H. Muellor. and J. W. Mayer, "Influence of Thermal Histor' on the Resi-
dual Disorder in Implanted- 1 1 1 Silicon." Radiat Eff.. 28. 277 ( 1976).
[48] E. I. Alessandrini. W. K. Chu. and M. R. Poponiak. "TEM Study of the Two Step Annealing of
Arsenic-Implanted. 100) Silicon." J. Vac. Sci. TechnoL. 16, 342 (1979).
[49] T. E. Seidel and A. U. MacRae. "Some Prop)erties of Ion Implanted Boron in Silicon." Trans.
Metall. Sac. AIME. 245, 491 ( 1969).
[50] E. C. Douglas and A. G. F. Dingwall. "Ion Implantation for Threshold Control in COSMOS Cir-
cuits," IEEE Tram. Electron Devices. ED-21. 324 ( 1974).
[51] B. R. Appleton and G. K. Aller. Eds.. Laser arid Electron Beam Interactions with Solids. North-
Holland. New York. 1982.
[52] A. Gat et al.. "Physical and Electrical Properties of Laser-Annealed Ion Implanted Silicon." Appl.
Phys. Lett.. 32. 276 (1978). and A. Gat. "Heat Pulse Annealing of Arsenic-Implanted Silicon with a
CW Arc Lamp." IEEE Electron Device Lett.. EDL-2. p. 85 (1981). and T. O. Sedgwick. "Short
Time Annealing," in C. J. Dell'Oca and W. M. BuUis, Eds.. VLSI Science and Technology,
Vol. 82-7. The ElecL-ochemical Soc.. Pennington. NJ 1982 p. 130.
[53] S. Prussin. "Role of Sequential Annealing. Oxidation and Diffusion Upon Defect Generation in Ion-
Implanted Silicon Surfaces." y. Appl. Phys.. 45. 1635 (1974).
[54] McD. Robinson. G. A. Rozgonyi. T. E. Seidel. and M. H. Read, "Orientation and Implantation
Effects on Stacking Faults During Silicon Buried Layer Processing." J. Electrochem. Soc, 128. 926
(1981).
[55] M. Y. Tsai and B. G. Streetman. "Recrystallization of Implanted Amorphous Silicon Layers, I.
Electrical Properties of Silicon hnplanted with BF;* or Si* + B*." J. Appl. Phys.. 50, 183 ( 1979).
[56] B. L. Crowder, "Influence of Amorphous Phase on Ion Distributions and Annealing Behavior of
Group III and Group V Ions Implanted into Silicon," 7. Electrochem. Soc. 118, 943 ( 1971).
[57] L. C. Kimmerling. "Defect Characterization by Junction Spectroscopy." in J. Narayan and
T. Y. Tan. Eds.. Defects in Semiconductors. North-Holland. New York, 1981, Vol. 2, p. 85.
[58] K. A. Pickar and J. V. Dalton. "Lifetime Effects in Ion Implanted Silicon." in Ref. 5a, p. 125.
[59] T. E. Seidel and R. L. Meek. "Ion Implantation Gettering and Phosphorus Diffusion Gettering of Cu
and Au in Silicon." in Ref. 5c. p. 305.
[60] D. Lecrosnier. J. Paugam. F. Richou. G. Pelous. and F. Beniere. "Influence of Phosphorus-Induced
Point Defects on a Gold-Gettering Mechanism in Silicon." J. Appl. Phys.. 51, 1036 (1980).
[61] T. E. Seidel. R. L. Meek, and A. G. CuUis. "Direct Comparison of Ion Damage Gettering and
Phosphorus-Diffusion Gettering of Au in Si." J. Appl. Phys.. 46. 600 ( 1975).
[62] A. G. Culhs. T. E. Seidel. and R. L. Meek. "Comparative Study of Annealed Neon. Argon, and
Kr>'pton Ion Implantation Damage in Silicon," 7. Appl. Phys.. 49, 5188 ( 1978).
[63] H. J. Geipel and W. K. Tice. "Reduction of Leakage by Implantation Gettering in VLSI Circuit,"
IBM J. Res. Dew. 24. 310 ( 1980).
[64] H. Ryssel and 1. Ruge. "New Applications of Ion Implantation in Semiconductor Technology," in
W. A. Kaiser and W. E. Proebster, Eds., Electronics to Microelectronics, North-Holland, New
York. 1980, p. 63.
[65] T. Y. Tan, E. E. Gardner, and W. K. Tice, "Intrinsic Gettering by Oxide Precipitate Induced Dislo-
cations in Czochralski Si." Appl. Phys. Lett., 30. 175 (1977).
[65a] H. Shiraki, "Stacking Fault Generation Suppression and Grown-In Defect Elimination in Dislocation
Free Sihcon Wafers by HCl Oxidation." Jap. Jour. Appl. Phys. 15. 1 ( 1976).
[66] W. J. M. J. Josquin, "The Oxidation Characteristics of Nitrogen Implanted Silicon," in Ref. 12, p.

264 VLSI Technology
1433; and J. F. Gotzlich, et al., "Dopant Dependence of the Oxidation Rate of Ion Implanted Sili-
con," in Ref. 12, p. 1419.
[67] R. F. DeKeersmaecher and D. J. DiMaria. "Electron Trapping and Detrapping Characteristics of
Arsenic-Implanted SiOo Layers," J. Appl. Phys.. 51, 1085 ( 1980).
[68] S. W. Chiang, T. P. Chow, R. F. Reihl, and K. L. Wang, "The Effect of Phosphorus Ion Implanta-
tions on Molybdenum/Silicon Contacts," 7. Appl. Phys., 52, 4027 ( 1981).
[69] M. Wittmer and T. E. Seidel, "The Redistribution of Implanted Doponts After Metal-Silicides For-
mation," J. Appl. Phys.. 49, 5826 (1978).
[70] J. M. Shannon, "Shallow Implanted Layers in Advanced Silicon Devices," in Ref. 13, p. 545.
Additional reading
See J. L. Stone and J. C. Plunkett, "Ion Implantation Processes in Silicon" (Chapter 2) and H. Maes,
W. Vandervorst, and R. van Overstraeten. "Impurity Profile of Implanted Ions in Silicon" (Chapter 8), in
F. F. Y. Wang, Ed., Material Processing Theory arid Practices. Vol. 2: Impurity Doping Processes in Sili-
con, North-Holland, New York, 1981.
PROBLEMS
1 A 10-|xA ion beam has a 10° half-angle divergence as it passes through a square aperture (8 cm x 8 cm),
placed 6 cm away from the target. Using a current meter, how much time is needed to implant lO'^
atoms/cm^ for (a) a singly ionized, monatomic species, (b) a triply ionized diatomic species? Using a
charge integrator (measures It) calibrated for a singly ionized monatomic species, (c) what dose should be
"set" to obtain lO'^ atom/cm" for the triply ionized diatomic species?
2 The drift-space vacuum between a mass-separation magnet and the target is approximately 10"^ Torr.
Consider the possibility of a neutralizing charge exchange reaction
1+ + N2 ^ I^ + N2+
with a cross section of 10"^ cnt/atom. What percent of the ions are charge exchanged in a distance of 1 m?
Take the (probability) fraction of unreacted particles to be exp ( -.x I K) where X is the mean free path.
3 (a) Identify the three minor species peaks in Fig. 3. Use the relative magnetic-field values of 7.7, 9.9,
and 13.3. F2^ is atB = 8.9, and As+ atfl = 12.5. Make a list of the ion species.
(b) Can AsF4"^"'' and F/ be resolved from As"*"?
(c) Discuss beam purity.
(d) Discuss solutions that would improve beam purity.
4 An existing accelerator has a lO-fi, A beam current with a 1-cm- area and deflection plates (x,v scan) that
are separated by 2 cm and have a 2-kV saw-tooth sweep voltage. Consider 10-keV As^'' as the ion of
interest. The ion beam's charge density can cause a drop in the sweeping electric field.
(aj What is the magnitude of the drop in the sweeping electric field at the center of the beam?
(b) Should this machine be retrofitted with a 1 .0-mA beam source? Assume no geometry changes.
(c) Discuss alternatives for scanning high beam currents.
5 (a) Using Fig. 7, approximate {dE Idx ) total as a constant and calculate the range R. Compare at 30 and
300 keV for As, P, and B with R^ values from Fig. 8.
(b) Calculate the sheet resistance for 30-keV lO'^ As^'' atoms/cm- and lO'^ B¥f atoms/cm-. Assume
a fuUy active Gaussian nondiffused dopant profile. The profile can be approximated by equally spaced
strips of constant doping and mobility.

6 (a) Plot the vertical and lateral dopant profiles at .v = /?p , for lO'^ As atoms /cm- and 60 keV. Use Gaus-
sian and erfc distributions, respectively. Assume a ver^ thick sharp vertical mask edge.
(b) Show that the vertical junction depth is
— Rp I A /?p
2 In
V277 i^RpHB
where n^ is the background dopant concentration; assume ng = lO'^/cm^ in this problem.
Ic) Plot the ertical profiles for an anneal of 850 and 1000°C for 30 minutes.
D =5 X 10"'^ cm-/ s and 8 x 10"'^ cm-/ s, respectively, and assume Eq. (26) is valid.
(d) Show that a mask of thickness d has a transmission factor
Use
— erfc
Rn
V2 1R„
where (Jjt is the number of ions/cm- that penetrate the mask. How thick must an amorphous polysilicon
mask be to give T = lO"'* for 150-keV boron?
(e) Assume a 150-keV B ion beam is perfectly ahgned with a(lOO) grain of a crystalhzed polysilicon
mask. How thick must the polycrystal be to give T = lO"'*? Use ^Rp ~ 800 A and Fig. 1 lb.
7 TEM studies show that a single ion damage track has a 30 k diameter. Using the range and
{dE I dx )nuciear values of 30-keV As^- ion comment on the likelihood that the ion's damage is amorphous.
8 Assume 100-keV lO'^ P^' atoms/cm^ are uniformly implanted across a nonuniform thermally clamped
silicon target. After implantation the colder end is amorphous, and exhibits higher reflectance, and colors
appear between the amorphous and the other end. Approximately what is the electrically activity fraction
after 30-minute anneals at 600, 900, and 1 100°C at both the cold and hot ends.
9 {a) We are interested in producing shallow, defect-free junctions. Discuss the following: channeling tails,
solid phase epitaxy, thermal cycles, and ambients.
ih) We are interested in producing shallow junctions with no defects in the space charge region but
extended defects near the surface. Discuss the same items listed in 9(aJ. Recommend two processes each
ioxia) andffej.

CHAPTER
SEVEN
LITHOGRAPHY
D. A. McGILLIS
7.1 INTRODUCTION
Lithography, as used in the manufacture of ICs, is the process of transferring
geometric shapes on a mask to the surface of a siHcon wafer. These shapes make up
the parts of the circuit, such as gate electrodes, contact windows, metal interconnec-
tions, and so on. Although most lithography techniques used today were developed in
the past 20 years, the process was actually invented in 1798; in this first process, the
pattern, or image, was transferred from a stone plate (lithos).^
After a test circuit or computer simulation is completed, the first step in fabricat-
ing an IC is to generate the pattern of geometric shapes. A composite drawing of the
circuit is broken into levels for subsequent IC processing: gate electrodes on one
level, contact windows on another, and so on. These are called masking levels.
Interactive graphic displays and digitizers convert the geometrical layout to digital
data, which is used to drive a computer-controlled pattern generator. The pattern gen-
erator is often an electron beam machine. It can transfer the design features directly
to the surface of a silicon wafer, but more often it transfers the features to photosensi-
tized glass plates callQd photomasks, or masks.
The final IC is made by sequentially transferring the features from each mask,
level by level, to the surface of the silicon wafer. For example, between each succes-
sive image transfer an ion implant, drive-in, oxidation, or metallization operation
may take place.
In the IC lithographic process, a photosensitive polymer film is applied to the sil-
icon wafer, dried, and then exposed with the proper geometrical patterns through a
photomask to ultraviolet (UV) light or other radiation. After exposure, the wafer is
soaked in a solution that develops the images in the photosensitive material. Depend-
ing on the type of polymer used, either exposed or nonexposed areas of film are
removed in the developing process. The wafer is then placed in an ambient that
267

268 VLSI Technology
etches surface areas not protected by polymer patterns. Because the polymeric
materials resist the etching process, they are called resists; if light is used to expose
the IC pattern, they are called photoresists. Resists are made that are sensitive to UV
light, electron beams, x-rays, or ion beams. The type of resist used in VLSI lithogra-
phy depends on the type of exposure tool used to expose the silicon wafer.
Exposure tools do several jobs. First, they rigidly hold the wafer and mask in
place after the mask pattern is aligned to a previous pattern already processed into the
wafer. Since they provide the mechanical motion needed to make this alignment,
exposure tools are sometimes called aligners, as are the people who operate them.
Second, they provide a source of exposing radiation for the resist. Some exposure
tools, such as the e-beam machine, provide a third function; they allow the silicon
wafer to be exposed directly without requiring a mask. Exposure tool performance
can be evaluated by three parameters: resolution, registration, and throughput. Reso-
lution is defined in terms of the minimum feature that can be repeatedly exposed and
developed in at least 1 fim of resist.^ Registration is a measure of how closely succes-
sive mask levels can be overlaid, and throughput is defined as the number of silicon
wafers that can be exposed per hour.
The majority of VLSI exposure tools used in IC production are optical systems
that use UV light. They are capable of approximately l-fxm resolution, ±0.5-|jLm
(3o-) registration, and up to 100 exposures per hour. Electron-beam exposure systems
can produce IC features with resolution less than approximately 0.5 (xm with ±0.2-
|jLm (3o-) registration. The e-beam systems are primarily used to produce photomasks;
relatively few are dedicated to direct wafer exposure. X-ray lithographic systems
have approximately 0.5-|jLm resolution and ±0.5-|jLm (3a) registration but are not yet
used to produce ICs in volume.
7.2 THE LITHOGRAPfflC PROCESS
7.2.1 Masks
The first step in generating masks for IC fabrication is to draw a large-scale composite
of the set of masks, typically lOOx to 2000 x the final size.^ The composite layout is
then converted into a set of oversized artwork with a drawing for each masking level.
The artwork is photographically reduced to a 10 x glass reticle. The final mask is
made from the 10 x reticle using another photoreduction system that reduces the
image to 1 x . This system exposes a site on the final photosensitive glass mask,
mechanically moves to an adjacent site, exposes the mask again, and so on in step-
and-repeat fashion. Each site contains a complete circuit pattern for that masking
level. As many identical IC chips, or dice, are put on the mask as will ultimately fit
on the silicon wafer. Figure 1 shows a mask on which IC patterns have been arrayed.
The mask contains a few secondary chip sites which will produce test circuits that can
be used to monitor the complete IC fabrication process or to test primary circuit
design modifications.

Lithography 269
MASK AS SEEN BY NAKED EYE
^^^ MAGNIFIED BY 40X
SECONDARY CHIP SITE
MAGNIFIED BY 400X
PRIMARY CHIP SITE
DEVICE FEATURE
Fig. 1 A glass IC photomask.
The oversized artwork approach to mask making is relatively simple, but not
practical when applied to VLSI circuits. Considerable effort has been invested in the
development of interactive graphics systems with which designers can completely
describe the circuit layout electrically. These are called computer-aided design
(CAD) systems. Geometric patterns are displayed on a cathode ray tube (CRT) and
positioned on the screen by using a light pen or joystick to form the desired circuit
shapes. The output of the CAD system is digital data, stored on magnetic tape, which
is used to drive a 1 x or 10 x pattern generator.
Masks are made from glass emulsion plates like the Kodak high-resolution plate
(HRP). or glass covered with a hard surface material. Emulsion masks are the least
expensive, but they are usually only used with feature sizes in the 5-|JLm region. All
e-beam generated masks are made with hard-surface materials such as chromium,
chromium oxide, iron oxide, or silicon. These masks are m-ore expensive than emul-
sion but features in the l-fxm region can be defined on them.
7.2.2 The Transfer Process
The purpose of the lithographic process is to transfer the mask features to the surface
of the silicon wafer (Fig. 2). Figure 3 shows an overview of a typical transfer pro-
cess."^ The silicon wafer is first oxidized to form a Si02 layer on the surface; the layer
is usually 1(XX) to 10,000 A thick. Resist is then applied to form a uniform film about
-xm thick. After coating and drying, the resist is exposed to UV light through a
photomask and developed in a solution that, in this case, dissolves the resist that was
not exposed. The wafer is then put in an ambient that etches the exposed Si02 but
does not attack the resist. Buffered hydrofluoric acid (BHF) is a typical Si02 etchant.

270 VLSI Technology
UNPATTERNED WAFER
MASK / v
n^xj
IDENTICAL PATTERN
PRINTED ONTO WAFER
IDENTICAL PATTERNS
ON MASK AND WAFER
Fig. 2 The transfer of IC patterns from a mask to a silicon wafer.
Finally the resist is stripped, leaving behind a Si02 image which then becomes a mask
for subsequent processing. For example, an ion implant would dope the exposed sili-
con, but not the silicon covered by oxide. After the SiO^ is stripped, the silicon sur-
face is left with a dopant pattern that duplicates the design pattern on the photomask.
The complete circuit is built up by aligning the next photomask in the sequence to the
pattern in the silicon and repeating the lithographic transfer process. VLSI circuits
may require from 5 to 1 1 separate masks and lithographic transfer steps to fabricate a
functional device.
SiO DEVELOPED IMAGE
^
PHOTORESIST
UV RADIATION
I I I I I /—PHOTOMASK
z^m
PHOTORESIST REMOVED
Fig. 3 Details of the lithographic transfer process. {After Till atulLwcon. Ref. 4.)

Lithography 271
Ol ITR n 1 M ft
WAFERS ^- INSPECT
AND
MEASURE
,
-
'
1,
POST BAKE
OVEN
ETCH .
'
DEVELOP
RINSE AND DRY
STRIP
RESIST
1
'
MASK *
PRINTER
ALIGN
EXPOSE
DEPOSIT
OR GROW
NEW LAYER
M
PRE-BAKE
OVEN

INCOMING
WAFERS J
M
L APPLY
PHOTORESIST
1
-
PHO TORESIST ROOM
Fig. 4 Row of silicon wafers through the lithographic processing area of an IC fabrication facility.
The complete lithographic process must be as free of defects as possible. If 10%
of the chip sites become defective during each transfer process (a 90% yield), after 1
1
lithographic operations only 31% of the chips would work. Since defects can be
introduced at all the other processing steps as well, the chip yield can easily fall to
zero unless close attention is paid to limiting defects.^
Figure 4 shows the steps in a photolithographic process and traces the flow of sili-
con wafers into and out of a lithographic processing area. The photoresist room is
typically illuminated with yellow light since photoresists are not sensitive to
wavelengths greater than about 5000 A. The first step is to apply the photoresist. The
resist is usually spun on the wafer. The wafer is held on a vacuum spindle, and a few
drops of the liquid resist are spread over its surface. The wafer is then accelerated up
to a constant rotational speed, which is held for about 30 s. The thickness of the
resulting resist film is proportional to the percent solids in the resist and inversely pro-
portional to the square root of the spinspeed.^ After spinning, the wafer is given a
preexposure bake to remove the resist solvent and increase the resist adhesion to the
wafer. The wafer and the appropriate mask pattern are then exposed to UV light.
Before exposure the mask pattern must first be aligned to existing patterns previously
etched into the wafer. The images are developed, rinsed of developer solution, and
dried. A postdevelopment bake may be required to give the remaining resist images

272 VLSI Technology
the adhesion necessary to withstand the subsequent etching process.^ The wafers are
then inspected for quahty and the resist images are measured. If the quality is poor or
the feature sizes are not within a specified range, the resist may be stripped and the
complete photoresist process repeated. Acceptable wafers go on to be etched, resist-
stripped, and cleaned, and then given further IC processing. The entire photoresist
process may take a few hours to complete and is automated as much as possible.
7.2.3 Resists
Resists may be either negative or positive. Negative resists become less soluble in
developer when they are exposed to radiation (as in Fig. 3), and positive resists
become more soluble after exposure. Figure 5a shows typical negative and positive
resist exposure response curves. At low-exposure energies the negative resist remains
completely soluble in the developer solution. As the exposure is increased above a
threshold energy Ej, more of the resist film remains after development. At exposures
two or three times the threshold energy, very little of the resist film is dissolved. For
positive resists, the resist solubility in its devt loper is finite even at zero-exposure
energy. The solubility gradually increases unti , at some threshold, it becomes com-
pletely soluble. Response curves such as these are affected by all the resist-
processing variables: initial resist thickness, spectral distribution of the exposure radi-
ation, prebake conditions, developer chemistry, developing time, and so on. These
LOG EXPOSURE ENERGY (mj/cm^)
(a)
EXPOSURE RADIATION
MM! I M M
VA
NEGATIVE RESIST POSITIVE RESIST
(b)
Fig. 5 (a) Positive and negative resist exposure characteristics, (b) Resist images after development.

Lithography 273
curves can therefore be used to characterize the complete photoresist process 7 As
shown in Fig. 5a, positive resists usually require more exposure energy (longer expo-
sure times) than negative resists to form resist images. Exposure tool throughput is
therefore less when positive resists are used.
In Fig. 5b, typical resist image cross sections are drawn, showing the relationship
between the edges of a photomask image and the corresponding edges of the resist
images after development. Overexposure tends to reduce the resist image size rela-
tive to the mask size in both cases, but in an opposite sense. The area free of resist
and consequently the area that will be etched into the silicon wafer decreases as nega-
tive resist is exposed longer, but the area free of resist increases as positive resist is
given a longer exposure. This effect in optical lithography is explained by the leak-
age of light under the opaque mask features caused by light diffraction (see Sec. 7.3.3
for a discussion). The object of the lithographic process is to faithfully replicate the
mask feature dimension in the corresponding resist images and to ultimately transfer
those images into the silicon. One of the major challenges faced by lithographic
engineers is to control images to the tight tolerances required in VLSI lithography,
typically less than about 10% of the nominal linewidth (e.g., ±0.2 |xm for 2-jjLm
lines).
7.2.4 Tolerances
Features on successive masking levels bear a spatial relationship to each other: metal-
lization patterns should fully cover contact windows, emitters should lie wholly
within base features, and so on. Figure 6 gives an example where a device feature on
masking level 2 is designed to nest into a feature on masking level 1 with the restric-
tion that an edge of level 1 should never touch an edge of level 2. In the circuit lay-
out, a nesting tolerance must be included between the edges of level 1 and level 2
features. This tolerance is one of the design rules used to lay out the circuit.
The magnitude of the nesting tolerance is dictated by three factors. First, the
location of device feature edges on the silicon wafer may not be exactly as specified
in the original circuit layout. The size of mask features can vary from chip to chip on
NESTING
tolerance"
t—-f
I
^ MASKING LEVEL 1 FEATURE
•1 EDGE 1 UNCERTAINTY
H^
OVERLAY UNCERTAINTY
EDGE 2 UNCERTAINTY
MASKING LEVEL 2 FEATURE
Fig. 6 Components of the nesting tolerance required between two mask levels that are registered to one
another.

274 VLSI Technology
the mask because of improper exposure, and other factors. An absolute size variation
of ±0.2 fxm across a 125-mm square mask is not uncommon. When these variable
size features are lithographically transferred to a silicon wafer more deviation from
the original layout may occur. The resist image can deviate from the mask image
because of variations in any or all of the lithographic processing variables, such as
resist thickness, baking temperature, exposure, and development conditions. The
etching process that finally transfers the resist image into, for example, a Si02 layer
can also vary the etched image size from wafer to wafer and from day to day. An
absolute variation of the final etched image of ±0.4 fxm over a year of production is
easily possible.
The second component of the nesting tolerance is the uncertainty involved in
aligning the images on mask 2 to the previously etched images from mask 1 . The
mask-making equipment may not produce a set of masks that perfectly overlay, and
the exposure machines used to align the mask patterns to the wafer patterns may have
limited registration capability. The human factor involved in manually aligning one
pattern to another can easily lead to ±0.5-fxm uncertainties. Automatic alignment
reduces the error, but does not eliminate it. The third factor is the broadening of the
dopant profiles in the silicon caused by, for example, lateral diffusion.
An estimate of the nesting tolerance T can be made if the distributions of etched
feature sizes {(jfi
for level 1, ct/2 for level 2) and registration (a,) are known (ignor-
ing the profile factor). Assuming that Gf^, Ufi, and ct,. are independent random vari-
ables and have normal distributions,
'/2
a-/i
2
2
+
0-/2
2
2 "
r = 3 -^^ + ^ + ct/ (1)
With this tolerance the probability that the edge of an etched feature from level 1 will
touch a feature from masking level 2 is approximately only 0.1%. Typical values for
a well-controlled VLSI production lithographic process are O/^i = Ufi = ±0.15 |xm
and Ur = ±0.15 ixm. Using these in Eq. 1, we find T s ± 0.6 fxm. Both the
minimum size feature that can be lithographically transferred and the nesfing toler-
ance determine how tightly devices can be packed on a VLSI circuit.
An often forgotten part of lithography is the measurement technique used to
determine that the size of the feature transferred to the silicon wafer is really the size
that the circuit designer wanted. Current research at the National Bureau of Standards
is directed toward the characterization of feature sizes for both photomasks and IC
devices using optical and scanning electron microscope (SEM) techniques.^' ^ It is
unfortunately quite common to find that two measurements of the same IC device
feature in two different fabrication facilities may differ by as much as 0.5 fxm.
7.3 OPTICAL LITHOGRAPHY
7.3.1 Types of Optical Lithography
The three primary optical exposure methods are contact, proximity, and projection.
They are illustrated in Fig. 7.

LiTHOGRAPm- 275
CONTACT PROXIMITY PROJECTION
GAP
y^
-/-
•/-
(a) (b) (c)
Fig. 7 Schematics of three optical lithographic techniques, (a) Contact, (b) Proximity, (c) Projection in
which the mask and wafer are moved synchronously.
In contact printing, shown in Fig. 7a, a resist-coated silicon wafer is brought into
physical contact with the glass photomask. The wafer is held on a vacuum chuck, and
the whole assembly rises until the wafer and mask contact each other with a few kilo-
grams of force. To align the photomask pattern to a previously etched silicon pattern,
the mask and wafer are separated by about 25 fxm, and a high-powered pair of objec-
tives are brought in behind the mask to view both the mask and wafer patterns at two
positions simultaneously. The objectives are connected to a split-field microscope so
that the right eye sees a spot on the right side of the mask and wafer, and the left eye
sees a spot on the left. The mask and wafer are aligned by mechanically translating
and rotating the vacuum chuck assembly until the patterns on the mask and wafer are
aligned. At this point, the wafer is brought into contact with the mask and reexam-
ined for alignment. When the expose button on the machine is pushed, the split-field
microscope is automatically withdrawn and a collimated beam of UV light illuminates
the entire mask for a fixed exposure time. The exposure intensity (in mW/cm"-) at the
wafer surface times the exposure time (in seconds) gives the exposure energy
(mJ/cm"), or dose, received by the resist.
Because of the intimate contact between resist and mask, very high resolution is
possible in contact printing. Printing l-fjim features in 0.5 |Jim of positive resist is
relatively easy. The problem in contact printing is dirt. A piece of dirt, such as a
speck of Si dust, on the silicon wafer can damage the mask surface when the mask is
forced into contact with the wafer. This damaged site then prints as a defective pat-
tern on all subsequent wafers used with that mask. Each additional wafer may add its
own damage to the mask as well. If the IC fabrication process or environment is not
scrupulously clean, very few defect-free IC chips will be printed. The defect density
(number of defects per centimeter squared) must be much less than one for each litho-
graphic transfer process to realize high VLSI chip yields.^
The proximity exposure method is very similar to contact printing except that a
small gap, 10 to 25 xxa wide, is maintained between the wafer and mask during expo-
sure. This gap minimizes (but may not eliminate) mask damage. Proximity printers
operate in the Fresnel diffraction region, where resolution is proportional to {kg)'-.

276 VLSI Technology
where A. is the exposure wavelength and g is the gap between the mask and the wafer7
Approximately 2- to 4-(jLm resolution is possible with proximity printing.
The third exposure method, projection printing, avoids mask damage entirely.
An image of the patterns on the mask is projected onto the resist-coated wafer, which
is many centimeters away. To achieve high resolution, only a small portion of the
mask is imaged. This small image field is scanned or stepped over the surface of the
wafer. In scanning projection printers, the mask and wafer are moved synchronously.
This technique achieves resolution of about 1.5-|xm lines and spaces. Projection
printers that step the mask image over the wafer surface are called direct-step-on-
wafer or step-and-repeat systems. With these printers, the mask contains the pattern
of one large chip or a group of small chips which are enlarged up to lOx . The image
of this pattern, or reticle, is demagnified and projected onto the wafer. After the
exposure of one chip site, the wafer is moved or stepped on an interferometrically
controlled XY table to the next chip site, and the process is repeated. Step-and-repeat
reduction projection printers are capable of approximately l-|JLm resolution.'*^
The optical elements in most modem projection printers are so perfect that their
imaging characteristics are dominated by diffraction effects and not by lens aberra-
tions. These printers are said to be diffraction limited systems. The resolution of a
diffraction-limited projection printer is roughly 0.5 (A./NA), where NA is the numeri-
cal aperture of the projection optics and is the exposure wavelength.'^ Projection
printers have a limited depth of focus over which image quality is not degraded. The
depth of focus is approximately ±X/2(NA)-^. High resolution (large NA) is achieved
at the expense of depth of focus. For example, a projection system with NA = 0.17
and an exposure wavelength of 4000 A will have a resolution limit of about 1.2 (xm
and a depth of focus approximately ±7 xm, about the thickness of a red blood cell.
7.3.2 Optical Resists
Negative resist is a cyclized polyisoprene polymer material combined with a pho-
tosensitive compound." The sensitizer, or photoinitiator, becomes activated by the
absorption of energy in the 2000- to 4500-A range. Once activated the sensitizer
transfers energy to the polymer molecules, which promotes crosslinking. The result-
ant molecular weight increase leads to insolubility in the developer system.
Numerous insolubilizing reactions occur for each photon absorbed. Oxygen tends to
interfere with the polymerization reactions, and so nitrogen is often directed at the
negative resist surface during exposure. During development of the negative resist,
the film swells, and the unexposed low molecular weight material is dissolved and
rinsed away. It is this swelling action that limits the resolution of negative resists. As
a rule of thumb, the minimum resolvable feature is about three times the negative
resist film thickness.
Optical positive resist systems also contain a base resin material and a photosen-
sitizer, but are totally different from negative resists in their response to exposure
radiation. The sensitizer is insoluble in the aqueous developer solution and therefore
prevents the dissolution of the base resin. In the exposed pattern areas, however, the
sensitizer absorbs radiation and becomes soluble in an aqueous base.'" The solubility

Lithography 277
differential leads to the development of images in positive resist. Unlike negative
resist, the developer does not permeate the whole resist film; the film does not swell.
Consequently, positive resists exhibit higher resolution capability.
Negative resists usually have poorer resolution capability than positive resists,
but they are very sensitive and permit a large number of wafers to be exposed in an
hour. This throughput can significantly reduce the cost of the ICs being made. Posi-
tive resists can be many times slower, resulting in lower throughputs and higher costs,
but they offer higher resolution. Therefore, there is a tradeoff between resolution and
throughput.
7.3.3 Diffraction
When exposure radiation passes through a photomask close to the edge of an opaque
mask feature, the propagation is not rectilinear. Fringes are observed near the edge of
the geometric shadow, and some light penetrates into the shadow region. Phenomena
of this type are called diffraction. The theory involved in deriving the intensity distri-
bution in the diffraction pattern can be found in several references.''' Figure 8 shows
typical diffraction patterns for contact, proximity, and projection printing. Since the
energy distribution incident on the photoresist film equals the intensity distribution
times the exposure time, the edge of the resist image is defined by the edges of the
diffraction pattern at the position where the exposure energy equals the threshold
energy for the resist (see Fig. 5). By changing either the exposure time or the diffrac-
tion pattern, the resist image can be made to grow or shrink with respect to the
corresponding mask image. These changes are often not intentional.
True contact printing is performed in the geometric shadow region of the mask,
which extends to a gap distance less than the wavelength of light (X) used for the
PROJECTION
Fig. 8 Typical optical diffraction patterns from a mask feature in contact, proximity, and projection lithog-
raphy. (After Skinner, Ref. 14.)

278 VLSI Technology
exposure. The contact between mask and wafer is rarely close enough for the wafer
to actually be in this region. Proximity printing is performed in the Fresnel or near-
field diffraction region, which extends out to about W-/ k micrometers from the
mask, where W is the mask feature width. ''^
Variations in the distance between mask
and wafer cause the near-field diffraction patterns of the mask images to change signi-
ficantly. This in turn causes wide variations in resist image size.
Projection printing is carried out in the Fraunhoffer or far- field diffraction region.
The intensity distributions in projection printing diffraction patterns may be altered by
changing the system focus by as little as ±2 |xm.'"^ Since silicon wafers can easily
have a surface ripple that is greater than 6 ixm peak to valley, most step-and-repeat
projection systems have automatic focusing at each chip site.
7.3.4 Modulation Transfer Function
Optical lithographic exposure systems are characterized by their modulation transfer
function (MTF). The quality of the image presented to the resist with respect to the
mask image is determined by the MTF of the exposure tool. In principle, this MTF is
measured by imaging sinusoidal grating masks characterized by spatial frequencies v,
defined as the inverse of the grating pitch. The modulation of the mask is a function
of V and is defined as
' m3v *
min
^^mask = 7 —} (2)
' max ' min
where /max ^nd /jnin are the local maximum and minimum intensities emerging from
the mask. If the corresponding modulation of the image presented to the resist film is
also measured, the MTF of the exposure tool is
MTF(v) = ^ '
''
; (3)
The ratio Im^/Imn is called the contrast C. By plotting the MTF as a function of the
spatial frequency, the lithographic performance of the exposure tool can be character-
ized.
'^
The degree of coherence of the light illuminating the photomask influences the
image transfer capabilities of the exposure tool. The degree of optical coherence for
1:1 scanning projection systems can be measured by the ratio'^
numerical aperture of illuminator optics
numerical aperture of projection optics
A small value of s indicates that the angular range of lightwaves incident on the mask
is small so that the illumination is highly coherent. A large value of s indicates a
large angular range of incident waves which overfill the projection optics. These
waves provide what is called incoherent illumination.
The MTF curves in Fig. 9 represent an idealized optical exposure system that is
in perfect focus. The curves closely agree with the values measured on existing opti-
cal lithographic tools. The MTF values are plotted for various degrees of illumination

Lithography 279
0.2 0.4 0.6 0.8 1.0
NORMALIZED SPATIAL FREQUENCY = vi
Fig. 9 MTF of an ideal imaging system as a function of illumination coherence. (After King, Ref. 16.)
coherence: from ^ = ^ for completely incoherent illumination, to 5 = for com-
pletely coherent illumination. The abscissa is in normalized spatial frequency units,
vf, where 1/2/ equals the numerical aperture of the projection optics. A coherent
optical system images all sinusoidal grating masks equally well until the pitch
becomes less than 2X/. After that point, no image is formed at all. The figure shows
that completely incoherent optical systems can image gratings that are half the pitch
of gratings imaged by the coherent system, but the image contrast falls monotonically
as the spatial frequency is increased. To form useful resist images, most optical
resists require a contrast corresponding to an MTF that is approximately 0.6. For this
reason, optical exposure tools use partially coherent illumination. < 5 < ^c, to
increase the useful image resolution while avoiding the image "ringing" that occurs
with completely coherent illumination. Within the range 0.5 < 5 < 0.9, tradeoffs can
be made between feature size control and image sharpness. Photolithography is
optimum when the size of the developed resist images are equal to or slightly larger
than the corresponding mask images.'''
'^
7.3.5 Standing Waves
In addition to diffraction effects and exposure tool MTF, light wave constructive and
destructive interference within the photoresist film is another optical effect that signi-
ficantly influences photoresist images.''' This interference is illustrated in Fig. 10.
Figure 10a shows monochromatic light with wavelength X entering a photoresist film
from the left (ray 1), passing through the resist and the underlying Si02 film (ray 2),
and being reflected from the silicon substrate (ray 3). The reflected light (ray 3)
passes through the resist again and exits into the air. A small percentage of the light
(ray 4) is reflected at the resist-air interface and the process is repeated. Figure 10b
shows the amplitudes of the incident wave (^^2 and the reflected wave §3. A phase
change of it is assumed during the reflection at the silicon surface. Adding waves ^2
and §3, the result is a standing wave of light intensity in the resist film as shown in
Fig. 10c. The standing wave contains antinodes of maximum intensity and nodes of
minimum intensity occurring periodically throughout the film. These standing waves
can play an important role in determining the size of a developed photoresist image.
The solubility of positive resist in developer is a function of the amount of sensi-
tizer in the resist. The sensitizer's rate of destruction is proportional to the local
intensity distribution in the resist.'^ If the intensity distribution is similar to that

280 VLSI Technology
REFLECTING SURFACE
4l2
2I2
1
K
/
1
/
1
A
1
/
~ /~ ^^ /TN. JS. / (n
/ / / /
- '?/ / 1 / /
Lm / / 1 /
/ y J
J /
X = d. X = d
Fig. 10 Standing light waves in a resist film caused by interference between the incident and reflected light.
(After Cuthbert, Ref. 17.)
shown in Fig. 10c, we would expect positive resist development rates to speed up and
slow down as regions of maximum and minimum intensity are reached in the film as
the development process proceeds. This is the case shown in Fig. 1 1 , which plots the
thickness of a positive photoresist film as a function of time in the developer solution.
The resist develops slowly in regions of low exposure and rapidly in regions of high
exposure, creating the steplike effect seen in the figure.
7.3.6 Summary
Optical lithographic processes and equipment exist today that will produce VLSI cir-
cuits with minimum features in the 1- to 1.5-|JLm range. The major problem areas
being addressed by exposure tool manufactures are level-to-level registration and
machine throughput. Photoresist suppliers are developing resist systems with
increased photospeed and the ruggedness to withstand today's plasma etching
environments. Research and development laboratories are devising multilevel resist
schemes (see Sec. 7.6.2) which may push practical optical lithography to the 0.5-|JLm
level. All of this activity will probably keep optical lithography the dominant tech-
nology of the 1980s for defining VLSI patterns on a production scale.

Lithography 281
-J 6000
CO
2 5000
z
^4000
1-
^ 3000
CO
u
cc
g2000
o
I
°-
1000
n
^
A

V
^
v^
V
100 200 300 400 500
DEVELOPMENT TIME (SECONDS)
Fig. 11 Measured thickness versus time, during development of a positive resist film on a silicon wafer.
(After Konnerth and Dill, Ref. 18.)
lA ELECTRON BEAM LITHOGRAPHY
7.4.1 Overview
Electron-beam fabrication of ICs offers several advantages for lithographic pattern
transfer: resist geometries smaller than 1 |jLm can be generated, wafers can be pat-
terned directly without a mask, and the technique can be highly automated. In addi-
tion, an electron beam has a much greater depth of focus than an optical lithographic
system. An electron beam can be used to detect features on a silicon wafer. This
capability can lead to extremely accurate level-to-level registration. The problem
with e-beam lithographic machines is that they are slow. Their throughput is approxi-
mately only five wafers per hour at less than l-|xm resolution. These throughputs do
not economically compete with optical machine throughputs of 40 wafers per hour at
1 .5- (Jim resolution.
To write submicrometer patterns into a resist, the e-beam must be focused to a
diameter of 0.01 to 0.5 fxm. The current density in the focused spot should also be
high, to minimize resist exposure times. Most thermionic electron guns have current
densities of a few amperes per centimeter squared from a cathode that is 10 to 100 fxm
in diameter.'^ Therefore, electron-optical demagnifying lenses are required to reduce
the e-beam diameter by as much as 10^. The focused beam must be capable of being
directed to any point in the scan field under the control of pattern generator data. This
requires beam deflection and blanking systems that can operate at megahertz rates
under computer control. Figure 12 gives a schematic of an e-beam lithography
machine. Since the beam scan is restricted by lens aberrations to usually less than 1
cm, an interferometrically controlled XY table is used to position the substrate to be
patterned under the e-beam. Registration to a previously defined pattern may be
accomplished at each chip site by scanning the e-beam across reference marks etched
in the substrate and detecting the secondary and backscattered electrons. These sig-

282 VLSI Technology
XY MASK
DATA
COMPUTER
CONTROL
TABLE
POSITION
MONITOR
VVVVVV^^^'.
ELECTRON GUN
BEAM BLANKING
DEFLECTION COILS, LENSES
VACUUM CHAMBER
ELECTRON RESIST
METAL FILM
SUBSTRATE
TABLE
MECHANICAL
DRIVE
Fig. 12 Schematic of an electron-beam machine.
nals are used to automatically position the substrate under the beam. Alignment accu-
racy of ±0.2 |jLm (3cr) is reported.
^^
Electron-beam lithography machines are usually designed for optimum perform-
ance in research and development, in the production of photomasks, or in the direct
writing of silicon wafers. Machines used in research and development must provide
the smallest possible focused spot so that the highest resolution can be obtained.
Beam diameters as small as 5 A have been used to etch 13-A wide lines in NaCl crys-
tals. ^^ Device throughput in these machines is not important. A machine intended for
the production of photomasks or reticles with features of 2 to 4 |jLm can have a rela-
tively large beam diameter (0.25 to 1 fim) and modest throughput. Satisfactory
throughput may be one mask per hour. However, a machine designed for the produc-
tion of IC devices must have the highest possible throughput and, therefore, the larg-
est beam diameter consistent with the minimum device dimensions. As a rule of
thumb, the minimum device feature is about 4x the beam diameter, and the field that
can be directly accessed by the e-beam without XY stage motion is about 2000 x the
minimum device feature. In other words, the smaller the device feature, the more XY
stage motion required. More stage motion, of course, slows down production. Once
again a tradeoff must be made: smaller features for wafer throughput.
7.4.2 Electron Resists
A radiation sensitive resist is one in which chemical or physical changes are induced
by ionizing radiation, which allows the resist to be patterned. -^^
A molecule of a poly-
mer electron resist consists primarily of monomer units that have been polymerized

Lithography 283
into a backbone chain. Irradiation with electrons leads to two generic types of
interactions: chemical bond breaking and radiation-induced polymer cross-linking.
In chemical bond breaking, or chain scission, the molecular weight is reduced in
the irradiated area. If the average molecular weight is reduced enough, the irradiated
material can be dissolved in a solvent that does not attack high molecular weight
material. Polymers that undergo chain scission are called positive electron resists.
Common positive resists are poly(methyl methacrylate), called PMMA, and
poly(butene-l sulfone), called PBS. A typical developer is a 1:1 mixture of methyl
isobutyl ketone (MIBK) with isopropyl alcohol.
The second polymer-electron interaction is radiation-induced polymer cross-
linking. The cross-linking events cause new bonds to form between adjacent chains,
which creates a complex three-dimensional structure with higher molecular weight
than the surrounding nonirradiated area. Polymers in which cross-linking events
dominate are called negative electron resists. Again, development proceeds by the
dissolution of the low molecular weight material. COP, poly (glycidylmethacrylate-
co-ethyl acrylate), is a common negative electron resist. Swelling during develop-
ment limits most negative electron resists to resolutions of about 1 |jLm. Positive
resists have resolutions that are less than 0.1 ixm.
Figure 13 shows the characteristic response curves of typical positive and nega-
tive electron resists. The curves that represent the remaining-resist thickness as a
function of exposure dose are similar to curves representing optical resist characteris-
tics (Fig. 5). The electron resist sensitivity S for positive and negative resists are
defined as the electron dose required per centimeter squared to ensure complete posi-
tive resist development or to correspond to a 50% remaining thickness in the case of
negative resist. ^^ This definition makes the sensitivity a function of all the resist pro-
cessing variables, such as thickness, developer strength, and so on. The figure shows
that the positive resist PMMA is about three orders of magnitude less sensitive than
the negative resist COP and would therefore require an exposure time about 1000
times longer to form useful resist images. Generally, slow resists have higher resolu-
tion than fast resists. This sensitivity-resolution tradeoff can be outlined as follows.
^^
First, imagine that the substrate to be exposed by the electron beam is subdivided
into a grid of addressable locations. Each element in this grid is called a pixel. A
pixel represents the minimum resolution element that can be defined by the complete
presence or absence of charge. Pixels are combined to form pattern shapes. The
minimum discernible pattern is one pixel exposed and one pixel not exposed. If the
1 Or
ELECTRON DOSE (C/cm )
Fig. 13 Typical exposure characteristics curves for a positive and negative electron-beam resist. (Afier
Greeneich, Ref. 23.)

284 VLSI Technology
side of a pixel is 0.5 fxm, a 125-mm diameter silicon wafer would contain about 5 x
10^° pixels. To form a useful image in the resist some minimum total number of elec-
trons A^,„ must strike each exposed pixel. For a given resist sensitivity 5, this
minimum is
N,„ =
SLr
(4)
where Lp is the minimum pixel dimension, q is the electron charge, and S is the
required dose in coulombs per centimeter squared.
Electron emission from the cathode of an electron gun is a random process, and
the number of electrons striking a given pixel element in a time T varies statistically.
One can show"-^ that the probability of a pixel not receiving A^,„ electrons is approxi-
mately 10"'^ if A^,„ = 200 electrons; this probability is sufficiently small that 5 x 10'°
pixels can probably be exposed without error. With A^^ = 200, Eq. 4 becomes
^P
= 200^
S
'/:
(5)
which is plotted in Fig. 14. The shaded area contains combinations of pixel size and
resist sensitivity that produce unacceptably high probabilities of exposure error.
Equation 4 shows the basic resist-sensitivity resolution tradeoff; the product of sensi-
tivity and pixel size is a constant fixed by N,„
.
Figure 14 compares data on sensitivity and resolution for several electron resists.
The data is representative of the best combination of resolution and sensitivity for the
indicated resists, as the result of a single line scan under typical IC exposure condi-
tions. The broken line represents the present state of the art in electron resists.
^-^
7.4.3 Electron Scattering and Proximity Effects
When an electron beam penetrates both a resist and the IC substrate beneath it, the
electrons scatter elastically and inelastically. Inelastic collisions with resist and sub-
10.0 r
PRESENT STATE-OF-THE-ART
ELECTRON DOSE (C/cm'^)
Fig. 14 Minimum pixel size (resolution) as a function of resist sensitivity. Typical resist sensitivity-
resolution data shows current state of the art for e-beam lithography. (After Greeneich, Ref. 23.)

LiTHOGR.'pm' 285
ELECTRON BEAM
Fig. 15 Electron scattering effects in a resist-coated substrate. (After Greeneich, Ref. 23.)
strate atoms result in energy loss; elastic collisions cause a change in the direction of
the electrons. Consequently, the incident electrons spread out as they penetrate a
resist-coated wafer until either all their energy is lost or they leave the material as a
result of backscattering collisions.
Electrons that are backscattered from the substrate and return to the resist deposit
energy several micrometers from the center of the exposing beam. Since the resist
integrates the energy contributions from all surrounding areas, the exposure dose in
one pixel is affected by the exposure in neighboring pixels. This behavior is called
the proximiTy effect. Figure 15 gives a specific example. The line patterns indicated
by the shaded areas are to be written by the incident electron beam that is scanned
along the length of the three lines. As the electrons penetrate the resist, scattering
broadens the incident energy distribution. Consequently, the developed resist images
are wider than would be expected from the size of the incident beam. Scattering
places a limit on the minimum resist linewidth. Since backscattered electrons may
travel relatively large distances before reentering the resist film, a fraction of them
contribute to the exposure of resist patterns lying adjacent to the one being written. In
other words, the total energy absorbed depends on the proximity of neighboring
exposed areas.
In the center of a large exposed area, such as at point A in Fig. 16. there are expo-
sure contributions from all the surrounding incident electrons. Point B, however,
receives only half the energy of point A, and point C at the feature comer receives
only one-fourth the dose of point A. The resist image is usually developed to a point
where the width of the feature corresponds to the design width, that is, point B. The
shaded area in the figure represents the developed image. Because of proximity
effects, the comers are not developed out to their design location. This phenomenon
is called the intraproximiry' effect. The intraproximity effect also causes large and
small features to print differently. The long narrow line in the figure is smaller than
its design value because the exposure dose and development conditions were opti-
mized to produce the required edge at point B. Cooperative effects can also be seen;
backscattered electrons travel large distances so pattems relatively close to each other
are affected by the neighboring exposure. These are called interproximity effects.
To correct for proximity effects, pattems can be divided into smaller shapes. The

286 VLSI Technology
n
mI
I'
ill
h!
Fi
Fig. 16 Inter and intra proximity effects in e-beam exposure caused by electron scattering. (After
Greeneich, Ref. 23.)
incident dose in each subshape is then adjusted so that the average dose in each pat-
tern is correct.
"^"^
A drawback is that this procedure may decrease the e-beam machine
throughput because of the increased computer time required to partition and print the
subdivided resist patterns.
7.4.4 Operating Strategies
To obtain a minimum-size resist image with good size control (better than ±10%)
usually requires several passes of the electron beam. Typically, four or more passes
of a Gaussian-shaped beam spaced at the beam half-width are used to write a
minimum size resist feature. Two major strategies are used to write e-beam patterns:
vector and raster scan.'^
In a typical vector-scan system, the digital data that specifies the feature size and
location is used to direct the e-beam to the proper circuit location, turn the beam on,
fill in the pattern shape by rastering the beam back and forth within the feature shape,
turn the beam off and vector the beam to the next feature location, and then repeat the
process. When the available scan field has been written, an XY table moves a new
scan field under the beam. This method is particularly attractive when only a few pat-
terns must be written and they are all the same size, for example, at a contact window
level; otherwise, it may take several hours to expose a 125-mm silicon wafer.
In a raster-scan system, the electron beam scans continuously back and forth over
a small field of view (typically 256 fxm) while the XY table scans at a right angle to
the beam scan. The beam is turned on and off to write the pattern. After the first
stripe of a circuit pattern is written over the whole substrate, the XY table returns to
the beginning and scans the next stripe. Systems of this type can use less complicated
electron optics than vector scan machines but the XY table control must be precise.
The raster-scan system is used primarily to make photomasks and can write a 125-mm
mask in about one hour.
A third approach to writing an electron-beam pattern uses a variable-shaped elec-
tron beam in a vector scanning mode. A shaped aperture is illuminated by the elec-
tron beam and imaged onto a second shaped aperture. By deflecting the image of the

Lithography 287
first with respect to the second, a variable shaped beam can be formed and vectored to
the proper circuit locations. Machine throughput can be increased substantially by
this technique; a 125-mm wafer can be written in several minutes.
7.4.5 Limitations and Trends
Direct writing electron beam lithography is attractive because an e-beam system is
capable of submicrometer resolution and has the best level-to-level registration capa-
bility of the major lithographic techniques. An e-beam system has the advantage of
flexibility. Customized VLSI designs can be fabricated without first going through a
mask-making process that is prone to errors and defects. The challenge of e-beam
lithography is using the existing submicron capability at an economically justified
throughput. Proximity effects can be corrected, but often at the cost of lower
throughput resulting from increased computation time. High resolution is possible, but
at the cost of lower resist sensitivity and lower throughput. To achieve both high
throughput and high resolution, brighter, higher current sources must be developed.
7.5 X-RAY LITHOGRAPHY
7.5.1 General Principles
X-ray lithography is an extension of optical proximity printing in which the exposing
wavelength is in the 4- to 50-A range. The short wavelength of x-rays reduces diffrac-
tion effects while still using a noncontact exposure system. Because x-ray optical ele-
ments are not yet available, x-ray lithography is limited to shadow printing. An x-ray
lithography system is illustrated in Fig. 17. In this system*^^ a 25-kV, 4- to 6-kW elec-
tron beam generated by a ring electron gun is focused on a water-cooled Pd target. As
a result, 4.37-a x-rays are emitted and pass through a beryllium window into an expo-
sure chamber filled with helium. (The helium prevents air from absorbing the
x-rays.) A mask, with x-ray absorbing patterns, and a wafer coated with an x-ray sen-
sitive resist are mounted on a movable stage that contains a vacuum chuck to hold the
wafer flat. The mask and wafer are separated by about 40 [xm. After the mask is
aligned with the wafer, the stage is moved into the exposure position where the x-rays
cast a shadow of the mask patterns onto the x-ray resist. The full wafer is exposed in
about 1 min.
The primary reason for developing x-ray lithography is the possibility of achiev-
ing high resolution and high throughput at the same time. There are other benefits as
well. The low energy of soft x-rays reduces scattering effects in both the resist and
substrate; no proximity corrections have to be made. Since x-rays are not appreciably
absorbed by dirt with low atomic number, dirt on the mask does not print as a defec-
tive pattern in the resist. And finally, because of the low absorption in x-ray resists, a
thick resist can be uniformly exposed throughout the entire thickness, resulting in
straight-walled resist images exactly replicating the mask patterns.
Geometrical effects, however, can limit the resolution of x-ray lithography.-^

288 VLSI Technology
COOLING WATER
VACUUM
Pd TARGET
Be WINDOW
Fig. 17 Schematic of an x-ray exposure system. (After Maydan, Ref. 25.)
Figure 18 shows the general outline of an x-ray exposure system. A point source of
x-rays of diameter (}> is at a distance L from the x-ray mask, which in turn is separated
a distance g from the resist-coated wafer. The extended point source introduces a
penumbral blur 8 on the position of the resist image edge
5 = (b
L
(6)
For typical values of cj) = 3 mm, ^ = 40 ixm, and L = 50 cm, the penumbral blur can
be on the order of 0.2 |xm.
Another geometrical effect shown in Fig. 18 is the lateral magnification error,
which is caused by the x-ray divergence from the point source and the finite mask to
wafer separation. The projected images of the mask are shifted laterally by an
amount d, given by
d ^ rj- (7)
where r is the radial distance measured from the center of the wafer. The error is zero
at the center of the wafer, but it increases linearly across the wafer. This run-out error
can be as large as 5 xm at the edge of 1 25-mm wafer using the values g — 40 |xm and
L = 50 cm. In principle the error can be compensated for during the mask-making

Lithography 289
X-RAY
SOURCE
WAFER
Fig. 18 Geometrical effects in x-ray lithography. (After Fay, Ref. 26.)
process. Variations in the mask-to-wafer gap, however, either across the wafer or
from mask level to mask level, can introduce significant run-out error. Gap adjust-
ment before each exposure may be required.
7.5.2 X-ray Resists
X-rays with wavelengths between 1 and 50 A (photon energies between 10 and 0.25
keV) suffer negligible scattering as they go through resist materials. An x-ray moves
in a straight line until it is captured by an atom, which ejects a photoelectron. The
energy of the photoelectron equals the x-ray photon energy minus the few electron
volts of binding energy necessary to remove the electron from its atomic shell out to
infinity. The photoelectron 's most probable direction is normal to the x-ray photon
direction, that is, in the plane of the resist.^" The excited atom returns to its ground
state by emitting a fluorescent x-ray or an Auger electron. The x-ray fluorescence is
absorbed by another atom, and the process repeats. Since all the processes end with
the emission of electrons, x-ray absorption in the resist material can be thought of as
releasing a swarm of secondary electrons. These electrons expose the resist by either
inducing chain scission or cross-linking, depending on the type of resist. All e-beam
resists are also x-ray resists.
Table 1 summarizes x-ray resist sensitivities, as previously defined in Fig. 13,
for the electron beam resists COP, PBS, and PMMA. Since the flux incident on the
resist from a point source x-ray exposure tool may only be between 1 and 10
mJ/cm*^min, the sensitivity of these resists is not adequate to achieve the goal of high
resolution and high throughput.^''

290 VLSI Technology
Table 1 Properties of a few x-ray resists!
Resist Tone
Major Abs
elements K
Sensitivity
(mJ/cnr)
Resolution
(|jLm)
COP
PBS
PMMA
(-)
( + )
( + )
S
4.37APdi„
4.37APd^„
8.34AA1,„
175
94
600-1000
1.0
0.5
<0.1
tAfterTaylor, Ref. 27.
One way higher resist sensitivity can be accomphshed is by increasing the x-ray
absorption in the resist. The absorption of x-rays can be described by the equation
I = Iq exp (—ar) (8)
where t is the thickness of the resist, a is the linear absorption coefficient, and /q and
/ are the intensities before and after absorption, respectively. Figure 19 shows
absorption coefficients for a few selected materials"^ in the wavelength range of
interest. The absorption can be increased by increasing the absorption coefficient,
which is related to the x-ray atomic absorption cross sections of the elements in the
resist. The cross section for x-ray capture by electrons in a given atomic shell varies
with the x-ray wavelength and shows large increases at certain critical wavelengths.
The critical wavelengths correspond to x-ray energies that are just sufficient to
remove electrons from their atomic shells, K, L], and so on. For example,
wavelengths slightly longer than kj^ can no longer be captured by K-shell electrons;
therefore the cross section drops abruptly at that point. Materials are most transparent
Fig. 19 Absorption coefficients of PMMA, Be, Si, and Au in the x-ray wavelength range used in x-ray
lithography. (After Spiller and Feder, Ref. 28.)

Lithography 291
to x-rays whose wavelength is just slightly longer than a critical wavelength, and
materials have the greatest absorption when the x-ray wavelength is slightly shorter
than a critical wavelength. -~ Therefore, x-ray resist sensitivity can be increased by
including in the resist elements whose absorption edges are in near resonance with the
exposure wavelength. Chlorine has a K edge at 4.40 A and consequently strongly
absorbs the 4.37-A PdLa wavelength. Negative x-ray resists with sensitivities below
10 mJ/cm- have been made by incorporating CI into the resist polymer.
^^
Although sensitive and capable of high throughputs, negative resists have limited
resolution because they swell and contract during the wet chemical development proc-
ess. Dry development by plasma processing avoids the swelling problem. Several
types of plasma developable negative x-ray resists have been described recently. All
contain an absorbing polymer host and a polymerizable monomer guest, which is
locked into the host by incident x-ray radiation. Negative x-ray resists have been
made by incorporating silicon-containing organometallic monomers with a chlori-
nated polymer absorber. These resists can be fully exposed in about 1 min and can be
developed in an O2 plasma. The resist resolution is less than 0.5 |xm.^^ Figure 20
shows a plasma-developed x-ray resist process. The resist consists of a host polymer
RESIST OF POLYMER P
AND ORGANOMETALLIC
MONOMER rm —
SUBSTRATE
1. EXPOSURE
P P P p rm P
rm ""rm P rn
P P /P I
Ps P P
rm rm-rm rm P
P P P P P
VACUUM BAKE
2. FIXING

P P rm P P
P P/P I P^ P P
rm — rm rm P
P P P P P— P
O2 PLASMA 3. DEVELOPMENT
MO LAYER
Fig. 20 Schematic of plasma-developed x-ray resist. (After Taylor. Wolf, and Moran, Ref. 29.)

292 VLSI Technology
P and an organometallic monomer rm, where r is the organic component and m is the
metal component of the monomer guest. Radiation incident on the resist polymerizes
the monomer and host polymer, locking in the organometallic. After exposure, the
resist film is baked in a vacuum to drive off the unpolymerized monomer. The resist
images are then developed out using an O2 plasma. The underlying assumption is that
the organometallic monomer is converted to a metallic oxide MO, which protects the
remaining resist from attack by the O2 plasma. This protective layer then enhances
the difference in plasma removal rates between the exposed and unexposed resist,
and, therefore an image is developed. These resist systems are still the subject of
active research programs.
7.5.3 X-ray Masks
An x-ray mask consists of a patterned metal x-ray absorber on a thin membrane that
transmits x-rays. The thickness of the absorbing material is determined by the x-ray
wavelength of interest, the absorption coefficient of the material, and the contrast
required by the resist to form an image. Gold is currently the most widely used
absorbing material. The mask patterns are usually generated using e-beam lithogra-
phy combined with dry etching techniques. To maintain high resolution and good
feature size control, vertical walls are required on the absorbing gold patterns. These
properties are most easily achieved with thin gold, which can be used at the longer
exposure wavelengths.
The membrane that forms the mask substrate must be highly transparent to x-rays
so that exposure times are minimized. It should be dimensionally stable, rugged
enough to be handled frequently in production use, and, if optical alignment tech-
niques are to be used, transparent to visible light. Many membrane materials, -^"^
such
as polyimide. Si, SiC, Si3N4, AI2O3, and sandwich structures of Si3N4/Si02/Si3N4,
have been used.
Figure 2 1 shows an x-ray mask structure that has been used successfully to make
IC devices. It is a sandwich of boron nitride and polyimide, with 0.6-(jLm thick gold
patterns that absorb the x-rays. The exposure wavelength used with this mask is the
4. 37-A PdLa characteristic line. The mask is made by first depositing a 6-fxm film of
boron nitride on a silicon wafer. After deposition, a 6-|xm polyimide film is spun on
top of the boron nitride to give additional strength. After the polyimide layer is
GOLD
(0.6/im)
PROTECTIVE
COATING
///////////////b°>^'on-n,tr,de7///////777^
POLYIMIDE
PYREX
Fig. 21 An x-ray mask. (After Maydan. Fef. 25.)

Lithography 293
cured, a thin Ta layer is deposited on the membrane, followed by 0.6 fxm of gold
which is then covered by another thin Ta layer. Electron beam resist is applied to the
structure and patterned using e-beam lithography. The resist images are transferred to
the top Ta layer, which subsequently acts as a masking layer for the gold etching pro-
cess. After gold patterning, the Ta films are stripped and another polyimide protec-
tive coating is applied. The patterned wafer is then bonded to a pyrex ring and the sil-
icon is etched from the back, leaving the membrane structure shown in Fig. 21
.
X-ray mask making is not yet a fully developed technology. The following prob-
lems remain to be solved: improving the long-term dimensional stability of the mask,
eliminating the resolution degrading effects of sloped pattern edges, and reducing the
mask defect density. The viability of submicrometer x-ray lithography depends on
solving these problems.
^^'
7.5.4 X-ray Sources
The simplest x-ray source"^' ^~
is the x-ray tube. This device focuses electrons in the
keV energy range on a metal target. Here they excite an x-ray spectrum of discrete
lines characteristic of the target metal and a continuous background spectrum of much
lower intensity. The efficiency is usually less than one percent. Most of the e-beam
energy is dissipated ar heat within the target. For reasons already discussed, an
extended point source of x-rays can cause considerable image edge blur due to
penumbra effects. To minimize the blur the electron beam is focused to a spot a few
square millimeters in diameter. Even with forced cooling of the target, the
maximum-allowable thermal load is only on the order of 2 kW/mm", so that the x-ray
flux incident on a resist-coated wafer is low, usually less than 0.1 mW/cm^.
Another source of x-rays, however, provides an almost collimated beam (so there
are no geometrical effects), a wide continuum of x-ray wavelengths, and flux densi-
ties in excess of 100 mW/cm- at the wafer plane. This x-ray source, called synchro-
tron radiation, is the electromagnetic radiation emitted by electrons in response to the
radial acceleration that keeps them in orbit in storage rings or synchrotrons. In a syn-
chrotron, bunches of electrons are continuously injected into a ring, raised in energy,
and then removed, usually at a 50- to 60-Hz rate. In a storage ring, a single bunch of
electrons is injected, raised in energy, and kept stable for several hours. Synchrotron
radiation is rich in the long x-ray wavelengths between 10 and 50 A, which are
strongly absorbed by thin absorber patterns on masks and are therefore ideal for high-
resolution x-ray lithography. The obvious drawback is cost.
Other x-ray sources rely on the generation of a dense plasma in a small volume to
provide bursts of intense x-rays. These sources include laser focus, plasma focus, and
vacuum spark techniques. It is too early to tell if any of these methods of x-ray pro-
duction will fmd practical applications.
7.5.5 Summary
In principle, x-ray lithography offers the best conditions for achieving submicrometer
resolution with high wafer throughput. Full wafers can be exposed in about 1 min
using existing resists and x-ray sources, with resolution better than 0.5 ^xm. Step-

294 VLSI Technology
and-repeat exposure methods, using the intense coUimated x-rays from a storage ring,
may be feasible in the future. Automatic ahgnment techniques must be perfected,
however, and mask fabrication must be improved before x-ray Hthography becomes a
production process.
7.6 OTHER LITHOGRAPHIC TECHNIQUES
7.6.1 Deep-UV Lithography
Standard photohthography is normally carried out in the 3100- to 4500-A spectral
region, with practical resolution about 1 to 1 .5 ixm. Resolution can be increased by
reducing the wavelength of the exposure radiation to the 2000- to 3000-A spectral
region, called "deep UV."'-^ Using conventional optical lithographic equipment that
has been modified to operate at shorter wavelengths, and using mask substrates made
of quartz instead of glass, resist images on the order of 0.5 |JLm have been printed.'^
The major advantage of the technique lies in the use of established e-beam mask-
making technology.
Commercial deep-UV exposure sources are available. The xenon-mercury lamp
is rich in deep UV output but has lower intensity than a standard mercury lamp. Mer-
cury arc lamps doped with zinc or cadmium, or deuterium lamps can also be used as
exposure sources.
Whether deep-UV lithography can be practical depends on the availability of a
suitable photoresist. The match between the output spectrum of the exposure tool and
the absorption spectrum of the resist determines the throughput capability of the tech-
nique. To achieve straight- walled resist image profiles, the resist must absorb only a
small percentage of the incident radiation, usually less than 20%. On the other hand,
too little absorption significantly increases exposure time. In general, any e-beam
resist is a candidate for a deep UV-resist. Figure 22 shows the spectral transmission
of 0.8 fxm of PMMA for unexposed resist and at 2-min exposure intervals.'^ The
resist exhibits a photo-dyeing effect, that is, the absorption increases with exposure.
Because of the low absorption, PMMA forms straight- walled resist images. How-
ever, since the match is poor between the PMMA absorption spectrum and the output
of a xenon-mercury lamp, for example, exposure times with this source are high—on
the order of 10 min.
Given the availability of deep-UV exposure tools and more sensitive resists, deep
UV optical lithography may soon become the dominant technology for VLSI produc-
tion in the 1-fxm design-rule region.
^^
7.6.2 Multilevel Resists
To develop a high-resolution straight-walled resist image, the resist must receive a
uniform exposure dose throughout the depth of the resist film. Using thin resist films,
usually less than 0.3 |JLm, greatly increases the useful resolution of an exposure tool
and significantly improves feature size control. ^^ However, a resist film must be thick

Lithography 295
2500 3000 3500^ 4000
WAVELENGTH (A)
4500
Fig. 22 Transmission spectrum of 0.8 xm of PMMA in the deep UV exposure region. (After Lin et al.
Ref. 13.)
enough to cover the previously patterned device topography on a silicon wafer. Oxide
or metal steps that are approximately 1 |xm high on a VLSI device are not unusual.
To adequately cover such a step the resist should be at least 1 |JLm thick, preferably
thicker. Once such a step is covered, the resist film is not only much thicker than
desired for high resolution but is also nonuniform in thickness across the step. The
realization that very thin resist films lead to improved resolution, but that thick films
are required for IC fabrication, led to the development of resist systems composed of
multiple layers.
Multiple layer systems can be divided into two categories; those in which at least
two layers are used as resists and both are exposed and developed, and those in which
only the top layer is used as a resist and the other layers are removed using the top
resist as a mask. In both categories, the bottom layer is usually very thick, typically
two to four times the maximum step height on the IC device. This layer, if thick
enough, will not only cover all the device topography, but will also form a flat sur-
face. A very thin resist imaging layer is then spun on top of the planarizing layer.
Figure 23 shows a schematic of a multilevel resist system. Device steps are covered
and planarized by a thick layer of polymer, which may or may not be photosensitive.
In the top figure a thin layer of isolation material such as Si02 or Si3N4 separates the
thin imaging resist from the bottom material. Images are formed in the resist using
optical, e-beam, or x-ray lithography. Since the resist is thin, the highest resolution
capability of the exposure technique can be achieved. The top masking layer con-
forms to the bottom layer and is portable with the wafer, so it is caW^d a portable con-

296 VLSI Technology
TOP RESIST LAYER
ISOLATION LAYER ZL
DEEP-UV
BLANKET EXPOSUE
UHIU
PLANARIZING LAYER
TOPOGRAPHIC FEATURE
ISOLATION LAYER
NOT USED
I t^3 CZl^Sl
CAPPED UNCAPPED
WET-ETCH PCM EXPOSURE PCM EXPOSURE PCM RIE PCM
Fig. 23 Schematicof a multilevel resist system. (After Lin, etai. Ref. 35.)
formable mask (PCM).-^^ The resist image is etched into the isolation layer and then
removed (see Fig. 23, top). The isolation layer acts as a mask to transfer the image
into the thick bottom layer using wet chemical isotropic etching or dry anisotropic
plasma reactive-ion etching (RIE). The image transferred to the thick material then
acts as a mask to pattern the IC device. When three levels are involved in the pattern
transfer process, it is called a trilevel resist process. In the middle of Fig. 23 the
intermediate isolation layer has been omitted. The thin resist is applied directly on
top of the thick layer. If the bottom thick material is deep-UV sensitive, for example
PMMA, and the top resist is an optical positive resist that strongly absorbs in the deep
UV, the top resist can act as a PCM for the exposure of the PMMA. The top resist
layer may or may not be developed off during the development of the PMMA,
depending on the choice of developing conditions.'*''
Processing a multilevel resist system is much more complex than a single-layer
image-transfer process. The resolution and feature size control given by a multilevel
process is, however, far superior. In optical lithography, standing-wave effects are
eliminated by using a multilevel resist, and in e-beam lithography, backscattering
from the substrate is minimal.
7.6.3 Inorganic Resists
Germanium selenide (GeSe) glass films can act as photoresists.^^ These glasses dis-
solve easily in an alkaline solution but when doped with silver, they become almost
insoluble. By coating a GeSe glass film with silver and exposing the film to UV light
from an optical exposure tool, light-induced silver migration called photodoping
occurs in the exposed regions. Figure 24 illustrates the process of forming an image
in the GeSe inorganic resist. A thin (approximately 0.2-(Jim) film of GeSe is evap-
orated onto a substrate and then dipped into an aqueous AgN03 solution to form a
layer of silver on the surface a few hundred angstroms thick. After exposure to UV
light through a photomask, the unphotodoped silver in the unexposed regions is

Lithography 297
^^- GeSe
777?//////////////
GeSeFILM DEPOSITION —S1O2
ss
1
NEGATIVE PROCE
7////////////////,
DIPPING INTO AgN03
SOLUTION
^
w//miw///xii
EXPOSURE
ETCHING BY ACID
m777^^77m
SOLUTION
P ym m
ETCHING BY ALKALINE
SOLUTION
SUBSTRATE (SiOa ,Si3N4,-)
f
m H
ETCHING
n t I n
GeSe FILM REMOVAL
Fig. 24 {After Yoshikawa etal., Ref. 36.)
removed in a HNO3 -HCl—H2O solution. The GeSe not made insoluble by photo-
doping is etched in an alkaline aqueous solution of NH4OH. KOH, or NaOH.
Most polymer optical resists require an image contrast corresponding to a modu-
lation transfer function (MTF) of approximately 0.6 to form useful images. The GeSe
inorganic resist requires only an MTF of approximately 0.2 to form an image. ^^ The
consequence of this low-contrast requirement can be seen by referring to Fig. 9; as the
MTF threshold is lowered, a greater spatial frequency can be resolved. This means
that optical-projection exposure equipment that can. for example, resolve l-jjim
features in a standard polymer photoresist, can resolve much smaller features in a
GeSe resist. In fact, 0.5-|JLm lines and spaces have been printed in GeSe using com-
mercial step-and-repeat optical exposure equipment.
-^^
Additional research is needed before inorganic resists become practical. If these
resists can be used in a multilevel resist system, however, existing optical litho-
graphic equipment may be able to produce submicrometer VLSI devices.
7.6.4 Ion Beam Lithography
Ions, because of their mass, scatter much less than electrons. Ion-beam lithography^^
inherently has higher resolution capabilities than e-beam lithography because of the
absence of proximity effects. Ion beams, like e-beams, can be used as a focused

298 VLSI Technology
beam for direct writing in resists (see Chap. 10). Conventional resists can be used in
ion-beam lithography, but new possibilities exist. Virtually any polymer can be used
as a negative resist by implanting ions such that after reactive-ion etching the resist in
a suitable plasma, the implanted ions form nonvolatile compounds. The unimplanted
regions are etched away. GeSe inorganic resist can also be used with ion beams.
Ion-beam lithography is still in its infancy. Direct writing appears to be too slow
to be economically attractive, but it may be useful in the future for making step-and-
repeat 1:1 reticles for x-ray lithography.
All of the major lithographic technologies (optical, e-beam, and x-ray) are capable of
producing the 1- to 2-|jLm feature sizes required for state-of-the-art VLSI device fabri-
cation. Only optical and e-beam lithographic processes are used in VLSI production
today; and the overwhelming majority of the processes are optical. Each technique
has its limitations: diffraction effects in optical lithography, proximity effects in
e-beam lithography, and mask fabrication in x-ray lithography. Electron-beam expo-
sure systems are capable of defining submicrometer geometries today but with very
low wafer throughput. Multilevel and inorganic resist systems may push optical
lithography into the submicrometer region in the near future. Any one of the three
lithographies can be used to do research in submicrometer devices.
Three criteria dictate the viability of a production lithographic process: resolu-
tion, registration capability, and throughput. Adequate resolution is available for
VLSI ICs, but the required overlay registration can only be achieved at the expense of
throughput. Figure 25 shows the estimated resolution for all modem exposure sys-
tems as a function of 125-mm wafer throughput. -^^
The outlined areas represent the
maximum resolution expected. The "usable" resolution is defined as 2.5 times the
machine-overlay registration capability (3a). Optical step-and-repeat lithography and
1:1 projection lithography is expected to dominate VLSI production in the 1980s.
Electron beam systems, with their excellent overlay capability but poor throughput,
will continue to be important for specialized direct-write applications. As step-and-
repeat x-ray systems become available and mask fabrication improves, x-ray lithogra-
phy may fill the gap between e-beam and optical lithography.
2° I" '^^e-BEAM
*
5 18 11
o SCANNING
PROJECTION
*- t- i Z_ 'USABLE
jtr;;::.-^.-^ Z_ 'USABLE' RESOLUTION
/ y 2 5 X OVERLAY REGISTRATION
2 4 t^' /
^ '
^X-RAY HIGH PRECISION
^ STEPPING
I I I I 1 I 1 I I
20 40 60 80 100
WAFER EXPOSURES PER HOUR
Fig. 25 Resolution capability versus throughput of 125-mm wafers for e-beam, x-ray. and optical projec-
tion exposure equipment. (After Eklutid and Landrum, Ref. 39.)

Lithography 299
REFERENCES
M. Hepher. "The Photoresist Story," J. Photog. Sci.. 12. 181 (1964).
M. Hatzakis, "Lithographic Processes in VLSI Circuit Fabrication," in Scanning Electron Microscopy
Meeting, 1979, Washington, D.C., pt 1, pp. 275-284.
R. A. Colclaser, Microelectronics: Processing and Device Design. Wiley, New York, 1980.
W. C. Till and J. T. Luxon, Integrated Circuits: Materials, Devices, and Fabrication. Prentice-Hall,
Englewood Cliffs, N.J., 1982.
For a review of IC defect analysis see, for example, A. B. Glaser and G. E. Subak-Sharpe, Integrated
Circuit Engineering, Design. Fabrication, and Applications. Addison-Wesley, Reading, Mass., 1979.
For a discussion of resist processes see, for example, D. J. Elliott, Integrated Circuit Fabrication
Technology. McGraw-Hill, New York, 1982.
D. A. McGillis and D. L. Fehrs, "Photolithographic Linewidth Control," IEEE Trans. Electron De-
vices. ED-22, 471 (1975); D. L. Fehrs, "An Empirical Approach to Projection Lithography," Proc.
Kodak Interface '79. 135 (1979).
W. M. Bullis and D. Nyyssonen, "Optical Linewidth Measurements on Photomasks and Wafers," in
N. Einsprusch (ed.), Microstructure Science and Engineering, vol. 2, Academic, New York, 1981.
S. Jensen, G. Hembree, J. Marchiando, and D. Swyt, "Quantitative Sub-Micrometer Linewidth
Determination Using Electron Microscopy," SPIE Semicon. Microlithog.. 275, 100 (1981).
R. K. Watts and J. H. Bruning, "A Review of Fine-Line Lithographic Techniques: Present and
Future," Solid State Technol., p. 99, May 1981.
M. Long and C. Walker, "Stress Factors in Positive Photoresist," Proc. Kodak Interface '79. 125
(1979).
For other reaction possibilities see also D. W. Frey, J. R. Guild, and E. B. Hryhorenko, "Edge Profile
and Dimensional Control for Positive Photoresist," Proc. Kodak Interface '81 (1981).
See, for example, B. T. Lin, "Optical Methods for Fine Line Lithography," in R. Newman (ed.).
Fine Line Lithography. North-Holland, Amsterdam, 1980.
J. G. Skinner, "Some Relative Merits of Contact, Near-Contact, and Projection Printing," Proc.
Kodak Interface '73. 53 (1973).
C. N. Ahlquist, W. G. Oldham, and P. Schoen, "A Study of a High-Performance Projection Stepper
Lens," Proc. Kodak Interface '79. 94 (1979).
M. C. King, "Principles of Optical Lithography," in N. G. Einspruch (ed.), VLSI Electronics Micro-
structure Science . vol. 1, Academic, New York, 1981.
J. D. Cuthbert, "Optical Projection Printing," Solid State Technol.. p. 59, Aug. 1977.
K. L. Konnerth and F. H. Dill, "In-Situ Measurement of Dielectric Thickness During Etching or
Developing Processes," IEEE Trans. Electron Devices. ED-22, 452 (1975). See, also, the classic
series of papers by F. H. Dill et al..IEEE Trans. Electron Devices. ED-22, 440-464 ( 1975).
D. R. Herriott, "Electron-Beam Lithography Machines," in G. R. Brewer (ed.), Electron-Beam Tech-
nology in Microelectronic Fabrication. Academic, New York, 1980.
P. Shaw, G. Pollack, R. Miller, G. Vamell, W. Lee, R. Loue, S. Wood, and R. Robbins, "E-beam
fabrication of 1.25-(xm4K Static Memory," J. Vac. Sci. Technol.. 19, 905 (1981).
M. Isaacson and A. Murray, "In-situ Vaporization of Very Low Molecular Weight Resists Using 1/2
nm Diameter Electron Beams," J. Vac. Sci. Technol.. 19, 1 1 17 ( 1981 ).
N. D. Winels, "Fundamentals of Electron and X-Ray Lithography," in R. Newman (ed.). Fine Line
Lithography. North-Holland, Amsterdam, 1980.
J. S. Greeneich, "Electron-Beam Processes" in G. R. Brewer (ed.), Electron-Beam Technology in
Microelectronic Fabrication. Academic, New York, 1980.
E. Kratschmer, "Verification of a Proximity Effect Correction Program in Electron- Beam Lithogra-
phy," J. Vac. Sci. Technol., 19, 1264 (1981).
D. Maydan, "X-Ray Lithography for Microfabrication," J. Vac. Sci. Technol., 17, 1 164 (1980).
B. Fay, "X-Ray Techniques and Registration Methods (Micro-Lithography)," in H. Ahmed and W.
C. Nixon (eds.), Microcircuit Engineering. Cambridge University Press, London, 1980.
G. N. Taylor, "X-Ray Resist Materials," Solid State Technol., p. 73, May 1980.
E. Spiller and R. Feder, "X-Ray Lithography," in H. J. Queisser (ed.). X-Ray Optics, Springer-
Veriag, New York, 1977.

300 VLSI Technology
[29] G. N. Taylor, T. M. Wolf, and J. M. Moran, "Organosilicon Monomers for Plasma-Developed X-
Ray Resists," J. Vac. Sci. Technol.. 19, 872 (1981).
[30] R. K. Watts, "X-Ray Lithography," Solid State Technol., p. 68, May 1979.
[31] See, for example, the series of papers by W. D. Buckley et al., 7. Electrochem. Sac, 128, 1 106-1 120
(1981).
[32] A. Heuberger, H. Betz, and S. Pongratz, "Present Status and Problems of X-Ray Lithography," in J.
Truesch (ed.). Advances in Solid State Physics. Plenary Lectures of the German Physical Society,
March, 1980.
[33] E. Chandross, E. Reichmanis, C. Wilkins, Jr., and R. Hartless, "Photoresists for Deep-UV Lithogra-
phy." Solid State Technol.:' p. 81, Aug. 1981.
[34] M. Hatzakis, "Multilayer Resist Systems for Lithography," Solid State Technol., p. 74, Aug. 1981.
[35] B. J. Lin, E. Bassous, V. Chao, and K. Pettillo, "Practicing the Novolac Deep-UV Portable Conform-
able Masking Technique," 7. Vac. Sci. Technol., 19, 1313 ( 1981).
[36] A. Yoshikawa, O. Ochi, H. Nagai, and Y. Mizushima, "A Novel Inorganic Photoresist Utilizing Ag
Photodoping in SeGe Glass Film," Appl. Phys. Lett., 29, 677 ( 1976).
[37] K. L. Tai, R. Vadimsky, C. Kemmerer, J. Wagner, V. Lamberti, and A. Timko, "Submicron Optical
Lithography Using an Inorganic Resist/Polymer Bilevel Scheme," J. Vac. Sci. Technol., 17, 1169
(1980).
[38] W. L. Brown, T. Venkatesan, and A. Wagner, "Ion Beam Lithography," Solid State Technol., p. 60,
Aug. 1981.
[39] M. H. Eklund and G. Landrum, "1982 Forecast on Processing," Semiconductor Int., p. 43, Jan.
1982.
PROBLEMS
1 Suppose that you are required to specify the resist thickness that will be used in a production lithographic
process. The following data is available:
• 1 .5-fjLm minimum features must be printed. Resolution is adequate when the resist thickness t is in the
range 0.5 to 2.0 iJim but feature size control is better for thinner resists.
• Each wafer has 150 chip sites; each chip has a 0.2-cm-^ active area.
• 5 mask levels are required to complete the device.
• 2000 finished wafers must be produced each day (20 h per day = 3 shifts).
• The resist defect density Dq increases as the resist is made thinner, where Dg is the number of defects
per square centimeter, and is approximated by D q = 1 -4 /
~^; t is in micrometers.
• The chip yield (percentage good) can be approximated at each mask level by v = (1 + ^Dga)"'.
where q is the fraction of defects that render a chip inoperable (fatality rate) and a is the active area of
the chip.
• On average, 50% of the defects are fatal defects.
• More time is needed to expose thick resist than to expose thin resist. The exposure tool throughput in
wafers/h is approximated by 125 - 50r for (0.5 « f « 2.0 (xm).
ia) Specify the resist thickness to be used and justify your recommendation with tabular and graphical
data.
(b) If exposure tools cost $350,000 each, what is the difference in equipment cost for a process using
1 ^.m and 1 .5 xm of resist.
2 Referring to Fig. 10, assume that the amplitude of the incident light wave £2 is given by
^^.(.v) = £2 sin iwt - kx + (J))
and the amplitude of the reflected wave £3 is given by
Ei,{x) = E2 sin [wt - k{2d - x) + <i>
+ -n]

Lithography 301
where k = l-nn/X. n is the real part of the film dielectric constant and is assumed equal for photoresist and
SIOt. and is the exposing wavelength.
(a) Referring to Fig. lOr. derive an expression for the standing wave intensity attributable to the
interference between Ei and E i,.
(b) Derive equations that predict the positions of the intensity minima and maxima with respect to the
reflecting surface.
(c) Consider a positive photoresist film on 1250 k of SiOi over a silicon substrate. Discuss the effect
on the resist image that might result from a SIOt thickness change of ±250 A. Assume n = 1.6 and =
3200A.
3 In electron beam lithography the term Gaussian beam diameter (cIq ) describes the diameter of an electron
beam in the absence of system aberrations, that is, a beam distorted only by the thermal velocities of the
electrons. The current density in a Gaussian beam is given hy J = J^ exp [— (r/a)"], where y„ is the peak
current density, r is the radius from the center of the beam, and a is the standard deviation of electron distri-
bution in the beam. Defining dQ = 2a, derive an expression relating d(j to the peak current density y„ and
the total current in the electron beam /.
Answer: I = (-u lAXJ^dQ
4 The maximum current density 7,,, that can be focused toward a spot with a convergence half-angle a is
limited by the transverse thermal emission velocities of the electrons in a Gaussian electron beam. J,„ is
given by the Langmuir limit equation
eVo
^ ^ AT.
where 7,, is the cathode (source) current density, T^ is the temperature corresponding to the electron energy,
k is Boltzmann's constant (1.38 x 10~-^^J/°K), and e is the electronic charge (1.6 x 10"''^ C). For small
convergence angles a, derive an expression that relates the Gaussian beam diameter dQ to the electron
source parameters 7^, , 7"^- , and Vq.
Answer: d^ ^ IkT^J[{TT/4)J^-eVQa-]
5 {a) The brightness fi of a source of electrons is defined as the current density J emitted per unit solid
angle H, that is, B = J /Ci. The units of B are amperes per square centimeter per steradian. Assume that
the current is emitted from (or converges toward) a small area through a cone of included half-angle a and
that a is small. Derive an expression relating the maximum source brightness to the source parameters J^ ,
T^ , and Vq.
Answer: B =J^eVQ/TTkT^
(b) Assuming that brightness is conserved in the electron beam column, show that the Gaussian beam
diameter dQ is related to the source brightness.
Answer: dQ = {2
/
-nXl / a){I / B y~
6 Suppose that an x-ray resist must see a mask modulation greater than or equal to 0.6 in order to form use-
ful resist images. What is the minimum gold thickness required on an x-ray mask to satisfy this requirement
if the exposure wavelength is 4 A ?
Answer: t ^0.31 xm

CHAPTER
EIGHT
DRY ETCHING
C. J. MOGAB
8.1 INTRODUCTION
Resist patterns defined by the lithographic techniques described in Chapter 7 are not
permanent elements of the final device but only replicas of circuit features. To pro-
duce circuit features, these resist patterns must be transferred into the layers compris-
ing the device. One method of transferring the patterns is to selectively remove
unmasked portions of a layer, a process generally known as etching.
As the title of this chapter suggests, "dry etching" methods are particularly suit-
able for VLSI processing. Dry etching is synonymous with plasma-assisted etching^
which denotes several techniques that use plasmas in the form of low-pressure gas-
eous discharges. These techniques are commonly used in VLSI processing because of
their potential for very-high-fidelity transfer of resist patterns.
The earliest application of plasmas to silicon ICs dates back to the late 1960s,
when oxygen plasmas were being explored for the stripping of photoresists." Work on
the use of plasmas for etching silicon was also initiated in the late 1960s and was sig-
naled by a patent^^ detailing the use of CF4-O2 gas mixtures. At that time, there was
no universal endorsement of dry methods which were largely novel replacements for
existing wet chemical techniques.
This early work set the stage for an important period in the evolution of IC tech-
nology. From 1972 to 1974, workers at several major laboratories were heavily
involved in the development of an inorganic passivation layer for MOS devices. The
preferred passivation turned out to be a plasma-deposited silicon nitride layer. While
this material exhibited many desirable characteristics, there was one immediate diffi-
culty. No suitable wet chemical etchant could be found to etch windows in the nitride
in order to expose underlying metallization for subsequent bonding. This problem
303

304 VLSI Technology
was circumvented by the use of CF4-O2 plasma etching.'^ Concurrently, CF4-O2
plasma etching was developed for patterning CVD silicon nitride layers being used as
junction seals/'' These efforts marked the first significant applications of plasma etch-
ing in IC manufacture and the beginning of large-scale efforts to develop plasma etch-
ing techniques.
Not long after this, an awareness of the potential of plasma techniques for highly
anisotropic etching evolved. In particular, there were many observations of a vertical
etch rate that greatly exceeded the lateral etch rate when etching through a layer of
material. As will become apparent, anisotropy is necessary for high-resolution pat-
tern transfer. The significance of etch anisotropy was recognized by researchers who
were hoping to achieve ever larger scales of integration by designing circuits with
ever smaller features. By the mid-1970s, therefore, most major IC manufacturers had
mounted substantial efforts to develop plasma-assisted etching methods. These
methods were no longer seen as merely novel substitutes for wet etching, but rather as
techniques having capabilities uniquely suited to meeting forseeable requirements on
pattern transfer.
8.2 PATTERN TRANSFER
"Pattern transfer" refers to the transfer of a pattern, defined by a masking layer, into
a film or substrate by chemical or physical methods that produce surface relief.
8.2.1 Subtractive and Additive Methods
In the subtractive method of pattern transfer shown in Fig. la, the film is deposited
first, a patterned masking layer is then generated lithographically, and the unmasked
portions of the film are removed by etching. In the additive (or lift-off) method
shown in Fig. lb, the lithographic mask is generated first, the film is then deposited
over the mask and substrate, and those portions of the film over the mask are removed
by selectively dissolving the masking layer in an appropriate liquid so that the overly-
ing film is lifted off and removed.
The subtractive methods collectively known as dry etching are the preferred
means for pattern transfer in VLSI processing today. The lift-off process is capable of
high resolution, but is not as widely applicable as dry etching.
8.2.2 Resolution and Edge Profiles in Subtractive Pattern Transfer
The resolution of an etching process is a measure of the fidelity of pattern transfer,
which can be quantified by two parameters. Bias is the difference in lateral dimen-
sion between the etched image and the mask image, defined as shown in Fig. 2.
Tolerance is a measure of the statistical distribution of bias values that characterizes
the lateral uniformity of etching.

Dry Etching 305
START
yZTZTA
AFTER )MASK
LITHOGRAPHY V/////
DEPOSIT-
ETCH
AFTER
MASK
REMOVAL
(a) (b)
Fig. 1 Schematic illustrations of (a) subtractive and (b) additive methods of pattern transfer.
A zero-bias process produces a vertical edge profile coincident with the edge of
the mask, as shown in Fig. 3a. In this case, there is no etching in the lateral direction
and the pattern is transferred with perfect fidelity. This case represents the extreme of
anisotropic etching. When the vertical and lateral etch rates are equal or, more pre-
cisely, when the etch rate is independent of direction, the edge profile appears as a
quarter-circle after etching has been carried just to completion, as shown in Fig. 3b.
In this case of isotropic etching, the bias is twice the film thickness.
H^H
SPACE
Y///VA
WA
y/////
,
{.•..': A.
df -i— SUE
MASK-
FILM
SUBSTRATE
h—^"1^
^ W//M
A k
-df J
LINE
BIAS = B = df - dpTi
Fig. 2 Etch bias is a measure of the amount by which the etched fikn undercuts the mask at the mask-fibn
interface.

306 VLSI Technology
ANISOTROPIC
(a)
ISOTROPIC
(b)
Fig. 3 Ideal etch profiles for (a) fully anisotropic (Aj- = ) and (b) isotropic {Aj = 0) etching with no mask
erosion.
Any edge profile, corresponding to etching just to completion, which lies
between the extremes depicted in Fig. 3a and 3b results from an etch rate that is aniso-
tropic. We can define the degree of anisotropy Af by
A, = 1 - ^
vv
(1)
where v/ and v. are the lateral and vertical etch rates, respectively. With reference to
a feature etched just to completion, Eq. 1 can be written:
I B I
(2)
A^ = 1
-
2/2'/
where B is the bias and hf is the film thickness. Thus for isotropic etching Af =
while I ^ Af > represents anisotropic etching. In practice the term "anisotropic
etching" is often taken to mean the extreme case, Ay^ = 1 (Fig. 3a).
In early IC fabrication practice, etch bias was usually dealt with by introducing
an appropriate amount of compensation in the masking layer. Consider, for example,
the etching of a pattern consisting of lines and spaces of equal size. To simplify
matters let the film features have a final dimension df and the mask features a dimen-
sion cf^ , as shown in Fig. 4. For a nonzero-bias process, the mask pattern will not
consist of lines and spaces of equal size. Instead the mask is compensated, as shown,
so that the minimum feature / that must be resolved in the mask is
/ = d B
and substituting from Eq. 2
/ = df
2h,
(1 - Af)
(3)
(4)
Equation 4 shows that the minimum lithographic feature is proportional to the desired
feature size with a proportionality factor determined by the degree of etch anisotropy
and the aspect ratio of the etched feature. It is apparent from Eq. 4 that as df tends to
the resolution limit of the lithographic technique employed for generating the masking

Dry Etching 307
Fig. 4 Mask dimensions have been compensated for etch bias to achieve an etched pattern with equisized
hnes and spaces. Edge profile is assumed to be vertical for simplicity.
layer, Aj must tend to unity (except in the case hj « dj , which is not of practical
interest for VLSI). In other words, as features become smaller, for a fixed or nearly
fixed aspect ratio, the margin for compensation diminishes, and a higher degree of
etch anisotropy is required. Such is the case for many of the pattern transfer opera-
tions needed in the fabrication of VLSI devices.
8.2.3 Selectivity and Feature Size Control
In the previous section we Imve focused on the etching of the film, and have impli-
citly treated both the mask and substrate as unetchable. This ideal situation occurs
rarely in actual practice, particularly with dry etching. More often, all of the materi-
als exposed to the etchant have a finite etch rate. Thus, a parameter of considerable
importance in pattern transfer for VLSI is the selectivity of an etching process. Selec-
tivity is defined as the ratio of etch rates between different materials.
Selectivity with respect to the resist mask has an impact on feature size control.
Selectivity with respect to the substrate affects performance and yield. The substrate
may be the silicon substrate or a film grown or deposited in the fabrication of a previ-
ous level of the device.
The selectivity required with respect to the mask is determined by the uniformity
of etch rate for both film and mask, the film thickness uniformity, the extent of
overetching, the mask edge profile, the anisotropy of etch rate for the mask, and the
maximum permissible loss of line width in the etched feature. We can quantify these
contributions with reference to Fig. 5.
Consider the etching of a film with mean thickness hf and with a uniformity
specified by a dimensionless parameter 6, such that hf( + 8) is the maximum thick-
ness, and hf { - 5) is the minimum thickness and 0^5^ 1. Suppose that the
mean etch rate is y and the uniformity of etching is such that the etch rate varies spa-
tially over the range v^ (1 ± ^f) where ^f is a dimensionless parameter
(0 ^ 4)^^ ^ 1). Taking worst-case conditions is the most conservative approach to
deriving the selectivity necessary to assure a loss of linewidth due to resist erosion
(etching) within permissible limits on any portion of any wafer being etched. This
corresponds to using a maximum etch rate for the mask, and assuming that the film
etches at the slowest rate where it is thickest. (The etch rate is defined as the vertical

308 VLSI Technology
Fig. 5 The evolution of an etched feature when the mask has a finite etch rate. The difference between the
intended pattern width and the actual linewidth is W.
depth of etching divided by the time of etching.) In this region of the film the time to
complete etching f^ is:
hf (1 + 8)
t = —
v^ (l-<j>/)
(5)
If A is the fractional overetch time, the time to completion is extended to r,,(l + A),
so that the total etch time r, is:
hf (1 + 8) (1 + A)
t,
= (6)
vy (1 - 4)/)
During this time, the mask is eroded by etching as shown in Fig. 5. If the mask
has maximum vertical and lateral etch velocities v and v/ , respectively, then the edge
of the mask recedes by a maximum amount W /2 given by:
W = [vy cot e + v/ ]t, (7)
where is shown in Fig. 5. Substituting for r, from Eq. 6 we find after rearrange-
ment:
V (1 + 8) (1 + A)
Vf ^ (l-cj)/)
cot e + — (8)
The etch rate of the mask is defined by the vertical etch velocity. In the present case

Dry Etching 309
V,. has been taken as a maximum value, thus providing the most conservative estimate
of the selectivity required for a given value of W.
We can define the mask etch rate in terms of a uniformity parameter cj)^ such that
. = 'm( + (}),„) where v^ is the mean mask etch rate. Then noting that
vy/v. = Sfm is the desired selectivity of the film with respect to the mask, and
v/ /v. = - A^ where A,„ is the degree of etch anisotropy for the mask, Eq. 8 can
be rearranged to yield:
^/- =
i^
^>[^°^ e + (1 - A,„)l (9)
where Uf^ = [H + 8) (1 + A) (1 + (t),„)]/(l -(})/) is the "'uniformity" factor
that accounts for a worst-case coincidence of the various nonuniformities.
It is instructive to consider an example that illustrates the application of Eq. 9.
Suppose that etching is carried out using a process that is fully anisotropic for the film
(Ay = 1). In this case the only linewidth loss results from resist erosion. Further, let
us assume that the etch rate uniformity for both film and mask is 10%, that the film
thickness uniformity is 5%, and that a 20% overetch is used. Then we have:
^f
= <t>,„
= 0.1, 8 = 0.05. and A = 0.2. Substituting these values in Eq. 9 we
find,
Sf„, = 1.54 [cote + (1 - A^)] -^ (10)
Figure 6 shows a plot of this expression for the particular cases 6 = 60° and 90°, and
for isotropic and fully anisotropic etching of the masking layer. For photoresist
masks, the angle is determined by the lithographic method (Secfion 7.3.1) and can
be influenced by post-exposure processing. An angle of 60° is typical for scanning-
type projection printers whereas 6 of about 90° can be achieved with contact printing.
Vertical walled masks (0 = 90°) are also typical of multilevel resist systems (Section
7.6.3). Note that the most favorable case for linewidth control corresponds to aniso-
tropic etching of a vertical-wall mask. This ideal is approached when multilevel
resists are used in conjunction with reacfive ion etching processes (Secfion 8.4).
The selectivity required with respect to etching of the substrate material can be
determined by an approach analogous to the one just used for the mask. Again, tak-
ing the conservative, worst-case view that the fastest etching and thinnest portion of
the film overlays the fastest etching portion of the substrate, we find:
h
Sfs = ir^fs (11)
where h^ is the maximum permissible depth of penetration into the substrate and
'(t)/(2 + A + A8) + 8(2 + A) + A
^fs =
(1 - c})/)
with c})y^, A, and 8 defined as before.
(12)

310 VLSI Technology
25| r
Fig. 6 The selectivity S />„ needed with respect to the mask is plotted as a function of the ratio of film thick-
ness to loss of linewidth for various mask profiles, and for the extremes of isotropic and anisotropic etching
of the mask.
Obviously, if the film thickness and etch rate were perfectly uniform
(8 = cj)y = 0) and no overetching was required (A = 0), selectivity with respect to
the substrate would not be a concern. In actuality, this ideal is rarely encountered in
VLSI. This is true not only for the obvious reason that perfect uniformity is highly
unlikely, but more importantly because (even with perfect uniformity) overetching is
required whenever anisotropic etching is coupled with stepped topography. Figure 7
illustrates the need for overetching. If the etching is anisotropic, then overetching
(i.e., etching beyond the "endpoint" where the slowest etching region of film has
been cleared from the planar surface) is necessary to clear the residual film. From
Fig. 7 it can be seen that for fully anisotropic etching (Af — 1), A = h^/ hj and this
is the minimum possible value of Ufs .
h|+h2
PRIOR TO ETCH
"RESIDUE
ETCHED TO " ENDPOINT"
Fig. 7 If etching is anisotropic, overetching is needed to remove residual material at steps. -4^^ - 1 in the
example shown.

Dry Etching 311
12
Fig. 8 The selectivity needed with respect to the substrate 5^( is plotted as a function of the ratio of film
thickness to the amount of substrate removed for various amounts of overetching.
As an example, pertinent to MOSFET fabrication, consider etching a 0.3-fxm
polysilicon layer that passes over a 0.6-|jLm field oxide step with a 0.05-|JLm sublayer
gate oxide. For these conditions A = 2 (200% overetch!) and the minimum selec-
tivity required for anisotropic etching is 2(0.3/0.05) = 12, if the polysilicon film is
uniform in thickness, etches uniformly, and etching is complete at the instant when
all of the gate oxide has been etched away. The concern with etching beyond this
point should be clear. Because the etch is designed to remove polysilicon, presum-
ably relatively rapidly, continued etching after the gate oxide has been removed
results in substantial etching of the silicon substrate, causing irreparable damage to
the device. Figure 8 illustrates the impact of overetching on selectivity for the partic-
ular case ^f = 0. 1 and 8 = 0.05.
We have seen that selectivity with respect to the mask is needed to enable feature
size control with projection printed resist masks (0 < 90°) and/or when the mask has
a finite etch rate in the lateral dimension. Selectivity with respect to the "substrate"
is needed to prevent unwanted removal of previously processed portions of the de-
vice. Anisotropy is favored for etching fine features, because very little etch bias can

312 VLSI Technology
be tolerated. However, anisotropic etciiing in the presence of stepped topography
necessitates overetching, which increases the selectivity required.
8.3 LOW-PRESSURE GAS DISCHARGES
Plasma-assisted pattern transfer techniques rely on partially ionized gases consisting
of ions, electrons, and neutrons produced by low-pressure (~ 10"'*- to 10''''-torr)
electric discharges. The generic term "plasma-assisted etching" includes ion mil-
ling, sputter etching, reactive ion beam etching, reactive ion etching (also known as
reactive sputter etching), and plasma etching. These techniques, which are described
in Section 8.4, differ in the specifics of discharge conditions, type of gas, and
apparatus; the common thread is the discharge, often referred to simply as the plasma.
8.3.1 Self-Sustained Discharges
When an electric field of sufficient magnitude is applied to a gas, the gas breaks
down. The process begins with the release of an electron by some means such as pho-
toionization or field emission. The released electron is accelerated by the applied
field and gains kinetic energy, but in the course of its travel through the gas, it loses
energy in collisions with gas molecules. There are two types of collisions, elastic and
inelastic. Elastic collisions deplete very little of the electron's energy (fractional loss
~10~^ ), because of the great mass difference between electrons and molecules. Ulti-
mately the electron energy becomes high enough to excite or ionize a molecule by
inelastic collisions. In ionizing collisions the electron loses essentially all of its
energy. Ionization frees another electron which is accelerated by the field, and so the
process continues. If the applied voltage exceeds the breakdown potential, the gas
rapidly becomes ionized throughout its volume.
Electrons released in ionizing collisions and by secondary processes (which will
be discussed later) are lost from the plasma by drift and diffusion to the boundaries,
by recombination with positive ions, and, in certain electronegative gases, by attach-
ment to neutral molecules to form negative ions. The discharge reaches a self-
sustained steady state when electron generation and loss processes balance each other.
Nonionizing, inelastic collisions between electrons and gas molecules or atoms
also occur. Two important types of nonionizing collisions are electronic excitation of
molecules (or atoms) and molecular fragmentation. Electronically excited molecules
and atoms account for much of the luminous glow of the plasma by emitting photons
as they relax to lower-lying electronic states. Molecular fragments are often highly
reactive atoms and free radicals. A free radical is a molecular fragment having an
unpaired electron.
The electron density for the plasmas of interest ranges from 10^ to lO'" cm"~
Considering that the density of gas molecules at 1 torr is about lO'^ cm"^ it can be
seen that these discharges are weakly ionized. This results in a gas temperature near
ambient, despite a mean electron temperature of about 10"* to 10^ K. The relatively
low gas temperature permits the use of thermally sensitive materials, such as organic
resists, for etch masks.

Dry Etching 313
CATHODE FARADAY ANODE
DARK SPACE DARK SPACE DARK SPACE
Fig. 9 Schematic view of a dc glow discharge showing the most prominent regions of the discharge.
In summary, the application of an electric field to a gas results in the conversion
of electrical energy to potential energy of activated gaseous species such as ions,
atoms, and free radicals which can be used to produce etching by physical and chemi-
cal interactions with solid surfaces. The energy is transferred by free electrons collid-
ing inelastically with gas molecules.
8.3.2 Methods for Plasma Production
DC discharge The simplest discharge to produce is the glow discharge, in which a dc
potential is applied between two metal electrodes in a partially evacuated enclosure.
The discharge is visibly nonuniform between the electrodes, and is composed of a
series of luminous light and dark zones, shown schematically in Fig. 9.
Positive ions are accelerated toward the negative electrode (cathode) and, on
impact, cause ejection of secondary electrons. Additionally, if the ions have suffi-
cient energy, they can produce atom displacement in the cathode as well as sputter-
ing^; that is, the ejection of cathode atoms. Secondary electrons are rapidly
accelerated away from the cathode causing a space charge of less mobile positive ions
to form in the region known as the cathode dark space. The dark space has a rela-
tively low conductivity, because it is depleted of the more mobile electrons, and con-
sequently most of the applied voltage drops across it. When the secondary electrons
have been accelerated to a high enough energy, ionization takes place; the point
where ionization begins marks the leading edge of the negative glow. The width of
the negative glow zone reflects the distance over which the accelerated electrons dis-
sipate their energy through inelastic collisions. Upon leaving this zone, most of the
electrons have energies too small to cause further ionization and another relatively
dark region (Faraday dark space) is established. Finally, the positive column is
reached where electrons and ions have equal densities.
Typically, dc glow discharges operate at pressures exceeding 30 x 10"-^ torr and
applied voltages exceeding a few hundred volts. A useful variant of this arrangement
uses a cathode that is heated to produce copious thermionic emission. This ensures an
ample supply of electrons to sustain the plasma and allows operation at lower pres-
sure. At still lower pressures (~10~^ torr ), the mean free path for electrons exceeds
typical dimensions of discharge chambers, and the probability of ionizing collisions is
too small to maintain the discharge unless the electrons are confmed by an external
magnetic field.
^

314 VLSI Technology
The dc glow illustrates three common characteristics of gaseous discharges:
1
.
Because electrons are much more mobile than ions, positive space charge tends
to form adjacent to the negative electrode. In fact, the disparity in mobilities also
causes these "ion sheaths" to form at any surface immersed in the plasma.
2. The ion sheath is a poor conductor compared to regions of higher electron den-
sity; consequently, the largest voltage drops occur across the ion sheaths.
3. The mean electron energy is increased as pressure is reduced or more precisely as
the parameter 6 Ip is increased, where ^'' is the electric field and p is the pres-
sure. Since the electron mean free path is inversely proportional to /?, t'//? is a
measure of the energy imparted to an electron by the field between collisions.
AC discharges If a low-frequency alternating field is applied across the electrodes in
Fig. 9, their polarity changes every half-cycle so that each electrode alternates as the
cathode. The ions and the electrons can both follow the field and establish a glow
discharge identical to that of Fig. 9, except for periodic polarity reversal. As the fre-
quency of the applied field is increased, a point is reached where the ions created dur-
ing breakdown cannot be fully extracted from the gap prior to field reversal. As the
frequency is increased further, a large fraction of the electrons have insufficient time
to drift to the positive electrode during a half-cycle. These electrons then oscillate in
the interelectrode gap and undergo collisions with gas molecules. The lower limit of
frequency for oscillations depends on the electron mobility, the electrode spacing,
and the amplitude of the applied field. The frequency limit is typically in the rf
range.
Three advantages are realized with rf discharges, which make their use
widespread. First, electrons can pick up sufficient energy during their oscillations in
the gap to cause ionization. The discharge can thus be sustained independent of the
yield of secondary electrons from the walls and electrodes. Second, the probability of
ionizing collisions is enhanced by electron oscillations allowing operation at pressures
as low as —10"^ torr. The third advantage is that electrodes within the discharge can
be covered with insulating material. This permits sputter etching and reactive sputter
etching of insulators, and also eliminates problems due to the build-up of insulating
material on metal electrodes that can occur when reactive gases are employed in
plasma etching. The mechanism of insulator sputtering in an rf discharge has been
discussed at length in the literature.^
The potentials that develop at various points in the rf discharge are important in
determining the energies of ions incident on surfaces in the plasma.^ Three potentials
pertinent to various etching techniques are labeled in Fig. 10. V, is the potential at the
surface of the rf-powered electrode measured with respect to ground. Vp is the
plasma potential with respect to ground, and V/ is the potential (relative to ground) of
an electrically floating surface, such as an insulating wall or a substrate isolated from
ground by an insulating film. The potentials across the ion sheaths are: V^ - V, at
the rf-powered electrode, Wp - V/ at the floating surface, and Wp at a grounded sur-
face. The potential of the surface with respect to the plasma determines the maximum
possible energy of ions bombarding that surface.

Dry Etching 315
ION SHEATHS
POWERED ELECTRODE (Vt)
PLASMA (Vp)
FLOATING SURFACE (Vf)
GROUNDED ELECTRODE
+ V
-V
POWERED
ELECTRODE
-Vf
GROUNDED
ELECTRODE
Fig. 10 Schematic view of rf discharge. The potential is shown as a function of position in the discharge
for the case where the area of the powered electrode is much less than the area of all grounded surfaces in
contact with the discharge.
To a first approximation, the rf coupling across the ion sheaths is capacitive with
the area and thickness of a sheath determining the capacitance. For this reason, the
ratio R of the area of the rf-powered electrode to the area of all grounded surfaces in
contact with the plasma is a key parameter in determining how the applied voltage is
distributed among the ion sheaths.^"" The potential Vp — V, increases as R
decreases. As a practical consequence, this relationship means that sputter etching,
which requires relatively large Vp — V,, is most efficient when R is small and the
substrate forms or is attached to the rf-powered electrode (the target).
Under the same conditions the ground-electrode ion sheath has a comparatively
small potential drop Vp across it so little or no sputtering occurs there. In a typical
diode sputtering system, R is about 0.05 and Vp - V, can be in the kilovolt range
when Vp is less than 100 V. Plasma-etching systems tend to be more symmetric
(R ~ 0.5) and are operated at higher pressure (usually in the 0.1- to 1.0-torr range).
Hence the potentials across the ion sheaths, including the powered electrode, are on
the order of Vp . The floating potential, Vf, is usually only a few volts below ground.
Therefore, ions bombarding a floating surface do not usually have energies much
greater than Vp
.

316 VLSI Technology
8.3.3 Physical and Chemical Phenomena in Gas Discharges
In dry etching, the plasma serves as a source of species that produce or in some
manner catalyze etching. The steady-state constitution of any discharge is governed
by the rates of production and loss of the various species.
Production of ions, atoms, and radicals As already noted, electron impact is the
primary mechanism of ion production in noble and molecular gas discharges. In
molecular gases, ionization may be concurrent with fragmentation, in which case dis-
sociative ionization is said to occur. As examples consider:
Simple ionization:
Dissociative ionization:
Ar + f ^ Ar^ + 2e
O2 + ^ -^ 02+ + 2e
^^^^
CF4 + ^ ^ CF3-' + F + Zt- (14)
Dissociative ionization with attachment:
CF4 + e -^CF3+ + F" + ^ (15)
Electron impact can also result in molecular dissociation (fragmentation) without
ionization, which generally requires less energetic electrons. Most atoms, radicals,
and in some cases negative ions are produced by these impact events. As examples,
O2 + e -^ 20 + f'
-^0 + 0" (16)
CF3CI + 6- ^CF3 + CI + ^ (17)
C2F6 + e ^2CF3 + e (18)
The production of atoms and radicals in molecular gas discharges is essential to
etching, because the feed gases themselves are almost always virtually unreactive. As
an example, CF4 is a relatively inert gas that does not react with Si at any temperature
up to the melting point ( 1412°C). However, when a discharge is initiated in CF4, one
of the by-products is atomic fluorine which reacts spontaneously with Si at room tem-
perature to form volatile SiF4. Similarly, O2 does not attack photoresists significantly
at or near room temperature, but the atomic oxygen produced in an Ot discharge
rapidly converts resist to volatile by-products such as CO, CO2, and H2O. The rate of
production of ions, atoms, and radicals depends on discharge parameters such as pres-
sure, power density, frequency, and feed-gas flow rate. However, exact relationships
between discharge parameters and production rates for various species are generally
not known.

Dry Etching 317
Loss mechanisms Electrons are lost from a discharge in ways that have already been
noted: drift, diffusion, recombination, and attachment. In molecular gases the recom-
bination and attachment events can be dissociative. For example,
Dissociative recombination:
^+02^^ 20 (19)
Dissociative attachment:
e + CF4 ^ CF3 + F- (20)
Ions can also drift to the electrodes or diffuse to the walls and be lost.
Atoms and radicals can be lost either by homogeneous reactions or by hetero-
geneous reactions. Homogeneous reactions occur entirely in the gas phase. Hetero-
geneous reactions take place on surfaces. Which type of loss reaction will dominate
for any species depends on many factors such as the pressure, the type of surfaces
present (rough, smooth, reactive, nonreactive. etc.), the surface area to volume ratio
of the discharge, and the particular gas. For example, two oxygen atoms cannot
recombine directly because the energy evolved cannot be dissipated. However, a
third body (e.g., an O2 molecule) can provide the needed energy sink. The rates of
such reactions depend strongly on pressure.
Surfaces can serve as reaction sites regardless of the pressure. All surfaces are
not equally effective with respect to recombination of reactive species, however. As
an example, the recombination of F atoms proceeds much more rapidly on a copper
surface than on an oxidized aluminum surface. The materials used in constructing
reactive etching systems must be chosen carefully to avoid unwanted heterogeneous
reactions.
8.4 PLASMA-ASSISTED ETCfflNG TECHNIQUES
Plasma-assisted etching can take several different forms. The ion etching techniques,
which include sputter etching and ion milling, produce etching solely by physical
sputtering (Section 8.3.2). The reactive techniques, which include plasma etching,
reactive ion etching, and reactive ion beam etching, rely, to various degrees, on both
chemical reactions that form volatile or quasi-volatile compounds and physical effects
such as ion bombardment.
The term "plasma etching" is often taken to represent the pure case of chemical
reaction, where the plasma serves merely as a source of reactive, neutral species that
combine with a solid surface to form a volatile product. There are examples of
plasma etching in VLSI technology where this description is essentially accurate.
However, physical effects such as ion bombardment often play an important role in
plasma etching, much as they do in reactive ion etching. Thus one must be cautious
about the implicit assignment of a "mechanism" to a given etch process based on the
terminology used to describe that process.

318 VLSI Technology
ETCH GAS^ PUMP
GROUND SHIELD
CATHODE
WAFER
Fig. 11 An rf diode system for reactive ion etching. The cathode is the powered electrode, while internal
grounded parts of the system serve as the anode. Note that the area of the cathode is much smaller than the
area of the anode. The plasma is unconfined and fills the entire chamber. The ground shield prevents
sputtering of the enclosed portions of the powered electrode.
It is preferable to distinguish these techniques on an operational rather than a
mechanistic basis. That is, each can be said to occupy a different portion of the
operating parameter space.
8.4.1 Sputter Etching and Ion Beam Milling
Both sputter etching and ion-beam milling use high-energy (> 500-eV) noble gas
ions, such as Ar^, derived from a discharge. Sputter etching is accomplished most
simply in an rf diode system shown schematically in Fig. 11. The material to be
etched is clamped to the powered electrode and bombarded by ions drawn from the
plasma. Recall from Section 8.3.2 that if the ratio of cathode surface to grounded sur-
face is small enough, most of the voltage drop occurs across the ion sheath at the
cathode. The direction of the electric field in the sheath region is normal to the
cathode surface so that, at typical operating pressures (
— 10"-^ to 10"' torr), ions
arrive predominantly at normal incidence and the degree of etch anisotropy is
inherently high.
In ion beam milling, the ion source is usually a magnetically confined dc
discharge that is physically separated from the substrate by a set of grids. The grids
are biased so as to extract an ion beam (typically Ar"*") from the source as shown in
Fig. 12. Ion voltages (energies) exceeding 500 V are required'' for practical beam
current densities (< 1 mA/cm^). Usually the beam is well collimated, so that the
angle of incidence can be controlled by tilting the substrate holder. A hot filament
emitter is placed in the beam path to provide low energy electrons for beam neutrali-
zation.
Although both sputter etching and ion beam milling have the potential for high
resolution, they are not used to any significant extent in VLSI technology. The main
reason for this is that selectivity is insufficient.

Dry Etching 319
NEUTRALIZER
FILAMENT
SUBSTRATE
TABLE
(TILTS,
ROTATES)
^^Ar GAS
PUMP
THERMIONIC
EMITTER
SOLENOID FOR
MAGNETIC
CONFINEMENT
BIASABLE GRIDS FOR
ELECTRON SUPRESSION AND
ION EXTRACTION
Fig. 12 An ion milling system.
8.4.2 Plasma Etching
Molecular gases containing one or more halogen atoms are used for plasma etching
silicon, silicon compounds, and certain metals. These gases are selected because the
fragments they produce in a plasma react with the materials of interest to form vola-
tile compounds at temperatures low enough to be appropriate for pattern transfer.
Parallel-plate systems, such as shown in Fig. 13, are used for high-resolution
etching.'- Such systems have several distinguishing characteristics. First, the elec-
trodes are nearly symmetric (ratio of powered to grounded surfaces tends to be much
nearer to unity than for sputter etching or reactive ion etching systems). The degree
of plasma confinement is relatively high, brought about by electrodes which are
closely spaced and have lateral dimensions nearly equal to those of the vacuum enclo-
sure. Plasma confinement tends to increase the plasma potential. The other distin-
guishing characteristics are that the material to be etched is placed on the grounded
electrode and the operating pressure is relatively high, ranging from 10"' to 10"^' torr.
The possibility of a high plasma potential in plasma etching systems must not be
overiooked.^ Since the substrates are either grounded or floating, the energy of ions
incident on them can be as high or slightly higher than the plasma potential, and can
reach several hundred volts under certain conditions, despite the high operating pres-
sures. When high plasma potentials prevail, the surface reactions involved in the

320 VLSI Technology
RF SIGNAL WAFERS UPPER ELECTRODE
LOWER
ELECTRODE AND
WAFER PLATEN
,^ PLASMA
QOOpBAoOQljaBOOlli
yy////////?
GAS RING
ETCH GAS —I
PYREX
CYLINDER
PUMP
L GAS
Fig. 13 A parallel-plate plasma etching system. The plasma is largely confined to the region between the
powered electrode and the grounded wafer platen. Confinement tends to increase the plasma potential.
etching can be strongly influenced by ion bombardment as discussed in Section 8.5. 1
.
Plasma etching then becomes mechanistically indistinguishable from reactive ion
etching (Section 8.4.3).
Generally only a mechanical pump is needed for plasma etching. Two-stage,
oil-sealed rotary pumps are common, with pumping speeds ranging up to 1500
L/min. Corrosive and/or toxic gases can be formed in the discharge (e.g., CO, COF2,
COCL2, Ft, and CI2) even with relatively inert feed gases, so good safety practice
must be adhered to in venting the pump, changing the pump oil, and routine pump
maintenance.'^
Pressure and feed-gas flow rate should be controlled independently; hence a throttle
valve is required to regulate pumping speed. Flow rate typically ranges from 50 to 5(X)
seem (standard cm^^/min, i.e. , cm^/min at standard temperature and pressure).
RF power is most often delivered to the plasma through an impedance matching
network at 13.56 MHz. (This "ISM" frequency is allotted by the Federal Communi-
cations Commission for industrial, scientific, and medical use.) Recent work on the
influence of frequency, however, has revealed the importance of this parameter in
determining ion energy and has prompted some departures from this standard operat-
ing point. '^ The matching network is used to match the plasma impedance to the out-
put impedance of the rf generator, thus assuring efficient power transfer.
8.4.3 Reactive Ion Etching and Reactive Ion Beam Etching
Reactive ion etching (RIE), also known as reactive sputter etching (RSE), employs
apparatus similar to that for sputter etching (Fig. 11). However, in RIE the noble gas
plasma is replaced by a molecular gas discharge generated in gases identical to those
used for plasma etching. The distinguishing operating conditions are: (1) asymmetric
electrodes (i.e., ratio of cathode area to grounded surface area much less than 1); (2)
substrates placed on the powered electrode; and (3) relatively low operating pressures
ranging from about 10"-^ to 10~' torr. Each condition contributes to providing rela-
tively high-energy ions at the substrate surface during etching (Section 8.3).
The lower operating pressures used in RIE necessitate the use of more complex
vacuum pumps, and lower feed-gas flow rates (—10 to 100 seem). In other respects
these systems are similar to parallel-plate plasma etchers.

Dr^- Etching 321
Reactive ion beam etciiing is the newest of the reactive plasma techniques.'^"' The
equipment and operating parameters are similar to those used in ion milling (Section
8.4.1 and Fig. 12). However, molecular gases identical to those used in plasma and
reactive ion etching replace the noble gases in the ion source.
Although initial results indicate a very high degree of etch anisotropy (Af = 1)
is obtainable, reported selectivities are poor. In light of the considerably greater
equipment complexity and potential drawbacks in connection with ion source mainte-
nance, reactive ion beam etching is unlikely to become a preferred method for VTSI
pattern transfer in the near future.
8.5 CONTROL OF ETCH RATE AND SELECTIVITY
The importance of adequate selectivity in dry etching is discussed in Section 8.2.4.
The etch rate for a given process must be sufficiently reproducible and high enough to
assure its utility for VLSI manufacturing practice. In this section we consider the
major factors governing etch rate and selectivity.
8.5.1 Ion Energy and Angle of Incidence
The influence of ion energy and angle of incidence on sputtering yield, defined as the
number of ejected atoms per incident ion. is of interest, because sputtering and related
effects take place in the reactive plasmas most often used in VLSI. The ion energy
must exceed a threshold value of about 20 eV for sputtering to occur at all, and should
be much higher than this (several hundred eV) to obtain practical sputter etch rates.
The sputtering yield for most materials increases monotonically with ion energy in the
energy range characteristic of dry etching (ion energy < 2 keV), although for ener-
gies exceeding —300 eV the rate of increase diminishes. Typical sputtering yields for
VLSI materials with 500-eV Ar^ range from -0.5 to 1.5. Consequently, selectivity
is inherently poor for ion etching.''
'^
Sputtering yield is sensitive to the angle at which ions impinge on the surface.
Ions arriving with oblique angles of incidence have a higher probability of producing
a substrate atom with velocity vectored away from the surface. In addition, these ions
tend to transfer more of their energy to atoms near the surface which have a higher
probability of escape.
Ions from the plasma collide with surfaces in both plasma and reactive ion etch-
ing. Sputtering can and does result, but under usual operating conditions produces
only a small contribution to the etch rate. Of much greater importance is the effect
that impacting ions can have on chemical reactions occurring at the surface. These
ion-assisted reactions are currently under intensive study. A growing body of experi-
mental evidence indicates that ion-assisted reactions between neutral etchant species
derived from the plasma and solid surfaces play a dominant role in many of the dry
etching processes developed for VLSI.
Figure 14 shows an example of an ion-assisted reaction. In this case separate
beams of Ar^(450 eV) and XeF-. were incident on a Si surface. The etch rates for

322 VLSI Technology
[--xeF2 6as»}-Ar*iON beam +xeF2 Gas
-
ONLY
Ar+ ION BEAM-i-j
ONLY
_ 70n
c
E 60-
Lj so-
ls
-40-
o
M, 30-
1 20-
10-
100 200 300 400 500 600 700 800 900
TIME(S)
Fig. 14 An ion-enhanced reaction. The rate of reaction between XeF^ and Si is increased dramatically
when a 450-eV Ar"^ beam irradiates the Si surface. The Ar"^ beam alone sputter etches the Si at a much
lower rate. (After Coburn and Winters. Ref. 18.)
each beam were measured separately and found to be relatively low. The Ar^ pro-
duces etching by physical sputtering; the XeF2 molecules cause etching by dissociat-
ing on the surface to Xe. which simply desorbs, and two F atoms. The F atoms then
react spontaneously with Si to form volatile silicon fluorides. The measured etch rate
for both beams incident simultaneously was much higher (about eight times) than the
sum of the individual rates, indicating a synergistic effect.
'^
Figure 15 shows another example of an ion-assisted reaction, Ar"^ and CI2 on
Si.''' Unlike F atoms, Ch does not spontaneously etch Si, yet when an Ar"^ beam is
simultaneously incident on the surface. Si is etched with a gas, SiCl4, as the by-
product. The etch rate measurements shown in Figs. 14 and 15 were made by detect-
ing the change in mass of a Si film with a very sensitive quartz crystal microbalance.
The brief transient seen in Fig. 15 when the CI2 gas is admitted (at —220 s)
corresponds to an increase in mass due to initial adsorption of chlorine on Si
.
A number of mechanisms could account for the influence of ion bombardment on
reaction rates :
1
.
Ion bombardment creates damage or defects on the surface which catalyze chem-
isorption or reaction.
2. Ion bombardment directly dissociates reactant molecules (e.g., XeF2 or CI2).
3. Ion bombardment removes involatile residues that would otherwise retard etch-
ing.
The relative importance of these mechanisms and alternatives are still the subject
of study, speculation, and some controversy. For our purposes, it is sufficient to real-
ize that bombardment by energetic ions causes physical processes such as lattice dam-
age, thermal spikes, and molecular dissociation that can greatly enhance or even
enable chemical reactions between neutral etchant species and solid surfaces. In the
first case (XeF2 + Si) the solid can be etched spontaneously (i.e., in the absence of

Dry Etching 323
U— Ar*10N BEAM—4*-
'
ONLY '
Ar*BEAM+Ci2GaS
E 10 h
0<
ttm • • ••••
• •
•
1
•
•
1 1 1 1 1
100 200 • 300 400
TIME (S)
•
•
•
500 600
Fig. 15 An ion-induced reaction. CI2 does not spontaneously etch Si, but etching occurs at a rate much
greater than can be accounted for by sputter etching when the Si surface is irradiated with a 450-eV Ar"^
beam during exposure to CU- (After Coburn and Winters. Ref. 18.)
ion bombardment) by the etchant species (F atoms), but the overall rate of reaction is
accelerated by energetic ion bombardment. In the second case (CI2 + Si) no etching
occurs unless there is energetic ion bombardment. We shall refer to the former case
as an ion-enhanced reaction, and the latter as an ion-induced reaction.
The examples given show that the effect of the ion beam is related to physical
processes, since no mechanism exists for a chemical contribution by noble gas ions.
For 1-keV ions Ar^ is more effective than Ne^ which is more effective than He^ in
assisting the XeF2 + Si and CI2 + Si reactions.'^' -°
The effectiveness of heavier ions
also suggests that physical processes related to momentum transfer are important. But
what about etching in plasmas such as CF4 and related gases used in dry etching? In
these instances the ions themselves contain potential reactants (e.g., CF3^). Work on
etching Si with XcFt under simultaneous ion bombardment reveals essentially no
change in the etch rate when CF3^ replaces Ar"^ as the bombarding ion."^ Thus ener-
getic ions can enhance or induce reactions through physical processes irrespective of
the chemical identity of the ions. In fact, the high etch rates often obtained in dry
etching would be difficult to reconcile with the relatively low ion fluxes arriving at
surfaces immersed in these low-ion-density plasmas, if the etching were attributed
mainly to reaction with ions.
The picture that emerges for etching in reactive plasmas is that reactants, mainly
neutrals, are generated in the plasma, adsorb on the surface, and react to form pro-
ducts that subsequently desorb, with the overall reaction possibly being initiated
and /or accelerated by energetic ions extracted from the plasma. Of course, the extent

324 VLSI Technology
to which the ions increase reaction rates depends on the specific gases, materials, and
operating parameters chosen.
8.5.2 Feed-Gas Composition
Gas composition is a dominant factor in determining etch rate and selectivity for
plasma and reactive ion etching. Table 1 lists some representative gases together with
materials reported to be etched by plasmas generated in these gases. Halogen-
containing gases have been used almost exclusively for etching in VLSI except for
photoresist removal and the patterning of organic layers where O2 plasmas have been
employed. The choice of these gases reflects the fact that the formation of volatile or
quasi-volatile halide compounds from the inorganic materials used in VLSI is both
thermodynamically and kinetically possible at or near room temperature. The
preponderance of halocarbons seen in Table 1 results because they are relatively easy
to handle and have minimal operating hazards.
Multicomponent mixtures are frequently used for reactive etching. These mix-
tures usually take the form of a major component plus one or more additives, which
are introduced to produce a desired effect in connection with etch rate, selectivity,
uniformity, or edge profile. ^'
An example of additive effects on etch rate is the
plasma etching of Si and Si02 with CF4-containing mixtures.
The etch rates of Si and Si02 in a CF4 plasma are relatively low. If O2 is added to
the feed gas, the etch rates of Si and Si02 increase dramatically, as seen in Fig. 16. A
maximum etch rate^- is reached at about 12% O2 for Si and 20% O2 for Si02. The
etch rates decrease with continued addition of O2, more rapidly for Si than for Si02
(Fig. 16). These effects can be explained by considering the plasma and surface
chemistry involved. F atoms are formed by electron impact dissociation of CF4 and
consumed by combination with CF^ radicals (x ^ 3). The rates of these processes in
a pure CF4 plasma are such that the steady-state concentration of F atoms is low, and
since F atoms are the etchant species the etch rates are also low. Added oxygen
results in depletion of CF^ radicals by formation of COF2, CO, and CO2, which
reduces the consumption of F atoms. The net result is an increase in the F atom con-
centration, up to about 23% O2, and a corresponding increase in etch rates. Ulti-
mately the F atom concentration decreases because of dilution.
Table 1 Some gases used in dry etching
for VLSI
Material Gases
Si CF4, CF4+O2. SFg, SFg+Oj, NF3
CI2, CCI4, CCI3F, CCI2F2, CCIF3
Si02, Si3N4 CF4, CF4+H2, C2F6, C3F8, CHF3
Al, Al-Si. CCI4, CCI4+CI2, SiCl4. BCI3,
Al-Cu BCI3+CI2

5000 -
- 280
210
Dry Etching 325
- 350
E
o<
- 140 ^
20 30 40
PERCENT O2 IN CF4
50
Fig. 16 The addition of O2 to a CF4 plasma affects the rate of etching of both Si and Si02.
If oxygen additions affected only the plasma chemistry, one would expect the
maximum etch rates for both Si and Si02 to occur at the O2 concentration which pro-
duces a maximum F atom density. However, as can be seen in Fig. 16, the maxima
for Si and Si02 are not coincident because oxygen is also involved in the surface
chemistry. In the case of Si etching, oxygen tends to chemisorb on the surface,
thereby partially blocking direct access by F atoms. Since this effect increases as
more oxygen is added, the maximum etch rate for Si occurs at an oxygen concentra-
tion much less than 23%. A similar effect is absent for etching Si02, because the sur-
face is, in effect, covered with oxygen to begin with. Thus the maximum etch rate for
Si02 occurs near the oxygen addition producing a maximum F atom concentration.
Oxygen chemisorption also accounts for the more rapid decrease of etch rate for Si
beyond the maximum in Fig. 16. F atoms react much more rapidly with Si than with
Si02, so CF4-O2 plasmas offer high selectivity of Si over Si02.
If H2 is added to a CF4 plasma, quite different effects are noted. ^-^ ^"^
In reactive
ion etching, at relatively low pressure, the etch rate of Si02 is nearly constant for H2
additions up to about 40% while the etch rate for Si decreases monotonically to a
value near zero at ^ 40% H2 as seen in Fig. 17. H2 in amounts exceeding —40%
causes unwanted polymer formation on the Si02. (See Section 8.7.1 for a discussion
of polymer deposition.) Selectivities for Si02:Si of 40:1 are possible with CF4-H2
reactive ion etching. In plasma etching, at higher pressure (~1 torr), the addition of
H2 can both increase the etch rate of Si02 and decrease the etch rate of Si. Again, the
selectivity for Si02:Si can be controlled by adjusting the H2 content of the feed gas.

326 VLSI Technology
Rf POWER- 0.26 W/cm2
PRESSURE-4.7 Pq
FL0WRATE-28sccm
15 20 25 30
PERCENT HgIN CF4
35 40 45
Fig. 17 The addition of H2 to CF4 results in a rapid decrease of the etch rate of Si relative to SiOi. Addi-
tions exceeding —40% cause polymer deposition and cessation of etching. (After Ephrath. Ref. 23).
A generally accepted explanation for these observations is as follows. CF^
(x ^ 3) radicals etch Si02 by an ion-induced reaction, probably involving dissociative
chemisorption, which ultimately results in formation of SiF4. The C derived from
these radicals is removed from the surface by combining with oxygen from the Si02
to form CO, CO2, and possibly COF2 gases. A similar reaction path with Si is una-
vailable, because there is no way to remove the adsorbed C, which blocks etching
(i.e., blocks access to surface sites for F). The role of hydrogen then is twofold. It
combines with F atoms to form stable HF thus removing a potential Si etchant, and,
particularly at higher pressures, it changes the plasma chemistry so that higher con-
centrations of etchant CF^. are produced. The overall effect can be depicted schemati-
cally as:
CF. + e
yH, + F
CF, + ¥ + e
HF
(21)
(22)
and
CF^ + Si02 -^ SiF4 + (CO, CO2, COF2)
CF. + Si ^ C adsorbed on Si
(23)
(24)
To summarize, etch rates and selectivities for Si and Si02 can be controlled in
CF4 reactive plasmas by the addition of oxidizing or reducing components to the feed
gas. With oxidant additions, etching of Si is favored relative to Si02, while reducing
agents favor the inverse selectivity.

Dry Etching 327
8.5.3 Pressure, Power Density, and Frequency
Pressure, power density, and frequency are independent parameters, but in practice,
the individual contributions each makes to an etching process are sometimes difficult
to unravel or predict. However, certain general trends are evident.
Lowering pressure and /or frequency, and increasing power density, increases the
mean electron energy and the energy of ions incident on surfaces. An increase in
power also increases the density of radicals and ions in the plasma. Thus, if etching is
ion-assisted, a decrease in pressure or frequency or an increase in power favors etch
rate anisotropy.
In general, etch rates increase monotonically with power, although at a diminish-
ing rate. Essentially all the applied power is ultimately dissipated as heat, so that at
very high power densities, substrates require heat sinking to avoid deleterious effects
such as photoresist flow and charring or loss of selectivity. Recently, there has been
much interest in very-high-rate etching for single-wafer etching systems"'' that operate
at relatively high pressure and very high power density (several W/cm~).
Very few studies of the variation of etch rate with frequency have been reported.
but it is clear that a main influence of frequency is in its effect on ion energy.
^"^'^^
This is most apparent from observations of etch rate anisotropy that are discussed in
Section 8.6. Frequency has been explored in the range from about 10 kHz to 30
MHz.
8.5.4 Flow Rate
The flow rate of the feed gas determines the maximum possible supply of reactant.
The actual supply depends on the balance between generation and loss of active
species in the plasma, as already discussed. One mechanism by which etchant species
are lost is convective flow. The rate of loss is inversely proportional to the residence
time t,. given by:
t,. - -^ (25)
760F
where p is the pressure in torr and V and F are the plasma volume and flow rate,
respectively, in consistent units. Residence time is a measure of the mean time a
molecule spends in the plasma.
Under usual operating conditions, flow rate has only a small influence on etch
rate. More pronounced effects are seen at the extremes, where either flow rate is so
small that etch rate is limited by the available supply of reactant or flow rate is so high
that convection becomes a major pathway for loss of active species. Whether or not
convective losses are observed depends on the available pumping speed, the particular
gas, and the materials within the reactor. If the active species have an inherently
short lifetime due to other loss processes, then flow rate effects may not be encoun-
tered. This is usually the case when the etchant species is atomic chlorine, for exam-
ple. Etch rates can be affected when species with longer lifetimes, such as F atoms,
are the etchant. Figure 18 shows'^ the reciprocal of etch rate plotted against flow rate
for CF4—Ot etching of SIOt and Si3 N4. The linear dependence shown is consistent
with the inverse dependence of residence time on flow rate.

328 VLSI Technology
100 200 300
FLOW RATE (cm^/min)-
400
Fig. 18 The reciprocal of etch rate R is linear in flow rate for etching in a CF4—4% O2 plasma at 1 .0 torr.
This dependence indicates that the lifetime of the active species is determined by convective losses. (After
Kalter artd Van deVen. Ref. 27.)
8.5.5 Temperature
Temperature influences etch rate in reactive etching primarily through its effect on the
rates of chemical reactions. An Arrhenius dependence [etch rate ~ exp {—Q/kT)
where Q is the activation energy, T is the absolute temperature of the substrate, and k
is Boltzmann's constant] usually prevails with relatively small values of activation
energy (Q ^ 0.5 eV/mole), although exceptions have been noted where the rate
decreases with temperature."^^ The rate decrease may be due to an increase in the rate
of thermal desorption of etchant species from the surface. Selectivity can also be
affected by temperature because the activation energy is material-dependent.
Some means of controlling substrate temperature is desirable for obtaining uni-
form and reproducible etch rates. Heating by the plasma is a major source of tem-
perature rise in thermally isolated wafers. In addition, the heat generated from exo-
thermic reactions that produce etching can be appreciable. Figure 19 illustrates the
effect of the heat of reaction on wafer surface temperature during the stripping of pho-
toresist in a barrel reactor,' where wafers are relatively isolated thermally. The max-
ima in the curves correspond to the times when resist stripping is completed. The
shift in the positions of the maxima with wafer load is due to the loading effect dis-
cussed in the next section.
8.5.6 The Loading Effect
In reactive etching the etch rate is sometimes found to decrease as the amount of etch-
able surface area is increased. This phenomenon is known as the loading effect.
Loading occurs when the active etch species reacts rapidly with the material being
etched, but the species has a long lifetime in the absence of etchable material. Etch-
ing is then the primary loss mechanism for the species, so the greater the area of
material, the more etchant species are consumed. The generation rate of the active

Dry Etching 329
200
^50
UJ
(T
b ioo
50
1 1 1 1 1 1
WAFERS
L /r ^"-C^"- 6 WAFERS
OV£y— 2 WAFERS _^
//^.-•^'^^ WAFER
-
f ^.7/xm AZ1300
f 7.5% C2 Fg -O2
1
150 WATTS
1 1 I
0.5 TORR
1 1 1
-10 -15 20
TIME (min)
25 30
Fig. 19 The variation of wafer temperature with time during plasma stripping of a photoresist layer. The
four sets of data points are for separate runs with only the number of wafers varied. The maxima correspond
closely to the endpoints of stripping.
species is fixed by operating parameters (pressure, power, frequency, etc.) and is
largely independent of the amount of etchable material present. Thus, the average
concentration of active species, as determined by the difference between the rates of
generation and loss, decreases as the etchable surface area increases.
The dependence of etch rate R on etchable surface area O in the simplest case of
a single etchant species takes the form^^
R = (26)
1 + /STPtO
where P is a reaction rate constant, t is the lifetime of the active species in the
absence of etchable material, G is the generation rate of active species, and ^ is a
constant for a given material and reactor geometry.
Equation 26 indicates that no noticeable loading effect will occur so long as
K PtO <^ 1 . This condition can be met by employing plasmas in which the inherent
lifetime (t) of the active species is very small; that is, where loss mechanisms other
than etching dominate.
Figure 20 shows an example^^ of the loading effect for etching polysilicon in
CF4-O2. Notice that the etch rate is independent of area over the range studied at
40°C, but that a strong effect is seen at 140°C. This can be attributed to the Arrhenius
temperature dependence of the rate constant (3 in Eq. 26. The effect would appear at
40°C, of course, if still larger areas were exposed.
The most serious concern caused by the loading effect is with feature size control
when lateral etching occurs. As the endpoint of etching is reached, the surface area
decreases very rapidly and any overetching is carried out at a higher rate than nomi-
nal. This makes linewidth control extremely difficult, since, in effect, accelerated
lateral etching occurs on clearing.

330 VLSI Technology
c
E
(T.
X
o
UJ
10^
_l 1 1 1 1
POLYSILICON
CF4+570 O2
10^ _ . 140°C
-— -B^
103 -
—
o
—
40°C
_^3 Q-i
2
-in
-| 1 1 1 r
1 10 lO'^ 10^ 10^
EXPOSED AREA(mm2)
Fig. 20 The loading effect. The etch rate of Si in a CF4-5% O2 plasma decreases when the surface area of
Si is increased sufficiently and/or the reactivity is increased sufficiently by increasing temperature. For
reference, a single 100 mm-diameter wafer has an area of approximately 7.8 x 10^ mm-. (After Enomoto et
al.,Ref.30.)
The loading effect is macroscopic in the sense that the presence of one wafer in a
reactor influences the etch rate at a second wafer in another part of the reactor. This
implies that transport processes in the plasma are rapid enough that no appreciable
concentration gradients can exist for the etchant species within the bulk of the plasma.
Microscopic loading effects have also been observed, wherein the size and den-
sity of features being etched can influence the etch rate.^' These effects result from
localized concentration gradients of etchant species, which are caused by differing
rates of reaction with mask and substrate materials. For example, the material near
the edge of a masking feature may etch more or less rapidly than the same material
further removed from the edge.
8.6 CONTROL OF EDGE PROFILE
Considerations relevant to feature size control were covered in Sections 8.2.2 and
8.2.3. This section deals with some effects that influence etch profiles and methods
for controlling them.
8.6.1 Mechanisms for Anisotropy in Reactive Etching
When etching occurs by an ion-assisted reaction, etch rate anisotropy can be
expected, because ions are incident normal to the wafer surface. (Normal incidence
occurs in the usual operating modes for reactive etching, with wafers having surface
topography with vertical dimensions much less than typical ion sheath thicknesses.)
Consequently, the bottom surface of an etching feature receives a much greater flux
of energetic ions than the sidewalls, as shown in Fig. 21
.

Dry Etching 331
IONS
MATERIAL TO BE ETCHED
Fig. 21 The sidewalls of etched features are not subject to energetic ion bombardment under typical condi-
tions, since the ions arrive predominantly at normal incidence.
If the etching reaction is ion-induced (Section 8.5.1), there will be no lateral
etching; whereas if it is ion-enhanced, the mask will be undercut by an amount deter-
mined by the spontaneous reaction rate. Figure 22 shows a hypothetical example in
which the degree of anisotropy obtained for the ion-enhanced reaction depends on ion
energy. For a given gas, material, power density, and frequency the reactive ion
etching mode usually provides higher ion energies than the plasma etching mode so
that a higher degree of anisotropy results. Etching of polysilicon in CI2 plasmas illus-
trates the effect of ion energy. When this is done in the RIE mode, nearly ideal aniso-
tropy {Af = 1) results, ^^ whereas plasma etching results in considerable undercut-
ting.^'
A useful approach to minimizing lateral etching with ion-enhanced reactions is to
incorporate a gas additive that provides a recombinant species. ^^'
The function of the
recombinant is either to combine with etchant species on surfaces to produce a vola-
tile product, or to serve as a precursor for the formation of a passivating film. The
detailed mechanisms underlying this approach are not well understood. However, it
is suspected that ion bombardment not only enhances the rate of reaction between
etchant and substrate, but also stimulates desorption of recombinant species, thereby
reducing their concentration on ion-bombarded surfaces. An example will illustrate
these ideas.
When Si is plasma-etched with Cb, undercutting occurs. However, as C2F6 is
added to the feed gas, the degree of undercut diminishes until at sufficiently high
C2F6 concentrations (^ 85%), lateral etching is virtually absent. This effect can be
accounted for by the reactions:
Generation of etchant species:
Ion-enhanced reaction:
e + Cl2 2Cl + e (27)
Si + jcCl SiCL (28)

332 VLSI Technology
-100 -200
BIAS VOLTAGE ON WAFER(VOltS)
Fig. 22 A hypothetical example illustrates the variation of etch rate and etch profile for ion-enhanced (the
curve labeled Si) and ion-induced (the curve labeled Si02) reactions. The ion energy is assumed to
correspond to the value indicated by the arrow labeled V. . V^ and V. are, respectively, the lateral and verti-
cal etch velocities. (After Coburn and Winters, Ref. 18.)
Generation of recombinant species:
e + Cj^e -^ 2CF3+e
Recombination:
CF3 + CI -^ CF3CI
(29)
(30)
The last reaction is likely to be suppressed by ion bombardment because of dissocia-
tion or desorption of CF3 and /or dissociation of CF3 CI. Thus, if the gas composition
is adjusted properly, one can obtain a situation where the rate of etching exceeds the
rate of recombination on ion-bombarded surfaces, whereas the reverse is true on
sidewalls where ion bombardment is minimal. The degree of anisotropy can be con-
trolled simply by adjusting the feed-gas composition.-^'
8.6.2 Other Effects Influencing Edge Profile
Faceting, trenching, and redeposition are three effects that arise from physical
sputtering and can influence edge profiles in reactive etching. The extent of their
influence depends on sputter yield and ion flux so they often can be completely
suppressed. These effects tend to be more prevalent with reactive ion etching than
with plasma etching, because of the higher ion energies involved.

Dry Etching 333
PHOTORESIST
(a)
(d)
Fig. 23 Faceting results from the dependence of sputter etch rate on the angle of incidence of ions striking
the surface, (a) Prior to etching, (b) initiation of the facet, (c) facet intersects substrate surface, (d) substrate
is exposed and forms its own facet.
Figure 23 shows the phenomenon of faceting. The sputter etch rate depends on
the angle of incidence that arriving ions make with the surface and, for most materi-
als, is a maximum for angles off normal incidence. The facet is inclined to the
incident ions at an angle corresponding to the maximum etch rate. The facet does not
affect the edge profile unless etching proceeds long enough for it to intersect the sur-
face (Fig. 23d).
Trenching, depicted in Fig. 24. results mainly from an enhanced ion flux at the
base of a step due to ion reflection off the side of the step. The etch rate resulting
both from physical sputtering and any ion-assisted reactions increases at the location
of the trench because of the greater ion tlux there.
Physically sputtered material that has not been converted to volatile products con-
denses on any surface it encounters. Sputtered material is ejected from the surface
with approximately a cosine distribution, and therefore a significant fraction can
redeposit on the walls of adjacent masking features. This redeposition changes the
edge profile and the line width. Redeposition is not usually a problem in reactive

334 VLSI Technology
FORWARD
REFLECTION OF IONS
"TRENCHING
INTO SUBSTRATE
Fig. 24 Trench formation arises from an
"
"excess"" flux of ions resulting from reflection off the sidewalL
etching, because it can be avoided by choosing feed gas, plasma parameters, and
masking materials so that only volatile products form.
8.6.3 Endpoint Determination
When lateral etching occurs, linewidth and edge profile can be controlled, to a certain
extent, by minimizing the amount of overetching. As noted in Section 8.2.4,
overetching is almost always required to compensate for nonuniformities, and for pat-
terning stepped surfaces when Af > 0. Various methods of detecting the endpoint of
etching have been used.^-^' ^^
They include: ( 1 ) direct visual observation of the etched
layer; (2) monitoring of optical reflections from the etched layer; (3) detection of
changes in the concentration of etchant species in the plasma by emission spectro-
scopy; (4) detection of etch products by emission spectroscopy or mass spectrometry;
and (5) detection of changes in plasma impedance. Methods (1) and (2) are indepen-
dent of the area of material being etched, but are not suited to dealing with nonuni-
form batch etching. Methods (3), (4), and (5) require a minimum area of material,
determined by etch rate and detector sensitivity, and tend to average over nonunifor-
mities. In addition, method (3) requires a loading effect.
Endpoint detection, used with etching processes that have litUe or no anisotropy,
is seldom a suitable substitute for highly anisotropic and selective etching in VLSI
applications with stringent requirements for linewidth control. However, endpoint
detection is a useful adjunct to any etching process for overall process control and
process diagnostics. Endpoint detection permits compensation for variations in etch
rate that result from fluctuations in material composition or thickness, or from
changes in operating parameters.
8.7 SIDE EFFECTS
Etching with reactive plasmas is not without side effects, which are mostly unwanted.
Several of the more important ones are discussed briefly in this section.

Dry Etching 335
8.7.1 Polymer Deposition
Discharges in halocarbon gases produce unsaturated (halogen-deficient) fragments
that can react rapidly on surfaces to produce polymeric films. An example is the reac-
tion of CFt radicals to produce fluorocarbon films. Obviously, such films impede
etching if they form on the material to be etched, and so are undesirable. On the other
hand, if polymer films can be made to form selectively on the mask or substrate, then
very high selectivity is possible.
An excess of unsaturates, low ion energy, and reducing conditions generally
favor film deposition. Thus, for certain gases such as CHF3, films may form on
grounded and floating surfaces, but not form simultaneously on rf-powered surfaces
that are subject to higher-energy ion bombardment. Similarly, films may form on a Si
surface but not on an Si02 surface, because the oxygen released during etching of the
latter surface reacts with the unsaturated species to form volatile products.
Polymer film deposited on reactor surfaces can cause problems with adsorption of
atmospheric contaminants, particularly water vapor, and with release of gaseous
species during subsequent plasma operations. For example, when an oxidizing
plasma is run in a system coated with fluorocarbon film, a substantial quantity of F
atoms is released in the plasma.
8.7.2 Radiation Damage
The variety of energetic particles (ions, electrons, and photons) present in a plasma
creates a potentially hostile environment for processing VLSI devices. The gate oxide
and the SiO^-Si interface are particularly susceptible to damage by irradiation with
these particles.
^^*"^^
The damage can take several forms: ( 1 ) atomic displacement resulting from ener-
getic ion impact; for reactive etching this is usually limited to a region no more than
100 A below the exposed surface; (2) primary ionization where Si—O bonds are bro-
ken and electron-hole pairs formed; this process is caused mainly by deep UV photons
and soft x-rays; and (3) secondary ionization where electrons created by atom dis-
placement or primary ionization interact with defects in the Si— O network.
Each of these forms of damage produces similar electronic defects—trapped
positive charge and neutral traps. The former defect can cause shifts in threshold and
flat-band voltages, while the latter tends to trap energetic electrons.
If a gate oxide is exposed directly to a reactive etching plasma with energetic ions
(—400 eV), atom displacement damage is not observed, probably because the dam-
aged layer is continuously removed by etching. However, photon damage is mani-
fested as trapped holes and neutral traps. The trapped holes can be removed by an-
nealing at 400°C, whereas removal of the neutral traps requires annealing at 600°C or
more.
When gate oxides are exposed directly to non-reactive plasmas, atom displace-
ment damage is observed. Removing this damage requires annealing at 1000°C.
Fortunately, in actual MOS device fabrication the sensitive gate oxide region of
the device is protected by the gate metallization, typically polysilicon, during plasma

336 VLSI Technology
exposure. Most of the radiation is not energetic enough to penetrate the gate elec-
trode, so damage is confined to the periphery of that electrode. In addition, the pro-
cessing usually includes subsequent high-temperature steps that ensure annealing of
the damage.
The primary concern is with the creation of neutral traps after aluminum metal-
lurgy is in place, for then the required annealing is precluded. Care must be taken to
keep the maximum voltages in a reactive etching system below the thresholds that
correspond to unannealable damage. These voltages depend on the specific device
structure and mask level.
8.7.3 Impurity Contamination
All of the internal surfaces of a reactive etching system are subject to ion bombard-
ment and can be sputtered. Unless the construction materials are properly chosen and
voltages carefully controlled, the sputtered material can deposit on wafer surfaces and
be incorporated in the device being etched. ^^ Heavy metal contamination, which
severely degrades minority-carrier lifetime, has been observed, especially in stainless
steel systems.
-^^
Sputter deposition of nonvolatile materials onto the etching surface impedes or
completely blocks etching. This is one cause of etch "residues." When highly aniso-
tropic etching is done, even very localized contamination of this sort presents a prob-
lem. Polymer films, sometimes only a few monolayers thick, can also cause device
contamination. Usually dry etching must be followed by a wet chemical cleaning
procedure to remove various contaminants, particularly following etching of small
contact windows.
8.9 DRY ETCfflNG PROCESSES FOR VLSI TECHNOLOGY
8.8.1 Silicon Dioxide
Dry etching of Si02 is used mainly for opening contact windows, which usually are
the smallest feature with the highest aspect ratio (film thickness to feature size) on the
device. An aspect ratio of 1:2 is typical. Patterning of contact windows is a severe
test, because the degree of anisotropy and the selectivity required are high.
The oxide is usually a deposited form of Si02 such as phosphosilicate glass
(PSG), which isolates two conductor levels. In etching contact windows to both a
first-level conductor and the Si substrate, the conductor thickness and /or substrate
junction depths determine the required selectivity. Extensive efforts have been made
to develop processes with high selectivity and anisotropy for etching PSG over Si and
polysilicon that can be applied to MOS devices.
Following the suggestion that CF3 radicals might react with Si02 in preference to
Si,-^^ gases such as CF4, C2F6, C3F8, and CHF3 have been used individually or in
combination with H2 (or hydrocarbons such as CH4, C2 H4, and C2 H2) to maximize
the CF3 radical concentration and minimize the F atom concentration (see Section
8.5.2). In fact, CF3 has never been conclusively identified as the etchant species, but

Dry Etching 337
Table 2 Typical etch rates and selectivity for some dry etching processes for VLSI
Etched Material (M) Gas
Etch rate
(A/min) M/resist
Selectivity
M/Si M/SiO.
Al. Al-Si, BCI3 + CI2 500 5
Al-Cu
Polysilicon CI2 500-800 5
Si02 CF4 + H2 500 5
PSG CF4 + H2 800 8
3-5
20
32
20-25
25-30
the weight of evidence suggests that CF^ , with x ^3, is the hkely etchant and that
the reaction is ion-induced. Anisotropy is relatively easily obtained both in RIE and
parallel-plate plasma etching.
The selectivity over Si generally improves as operating parameters, especially
gas composition, are altered to increase the concentration of unsaturated (fluorine-
deficient) species in the plasma. As unsaturates also increase the tendency to polymer
deposition (Section 8.7.1), parameters must be carefully controlled when working at
maximum selectivity. Near the maximum in selectivity, polymer forms on grounded
and floating surfaces, while etching occurs at the cathode in RIE. Additionally, since
the release of oxygen discourages polymerization, Si02 can be etched even while
polymer deposits on adjacent Si. In this extreme, very high selectivity is obtained
(see Fig. 17).
Another means of eliminating F atoms from the discharge to maximize selectivity
is to introduce a large surface area of a material which reacts rapidly with F atoms
such as Si or C. The material can be used as the support electrode for the wafers
being etched.
^^^
Oxide etch rate and selectivity over Si are generally increased by an increase in rf
power, consistent with an ion-induced reaction. Typical values for etch rate and
selectivity are shown in Table 2. At high power densities some heat sinking of sub-
strates is usually required to minimize resist degradation. With good heat sinking the
selectivity with respect to conventional photoresists is excellent.
The SEM micrograph in Fig. 25a illustrates a contact window etched in a
C2F6—CHF3 plasma. The high degree of anisotropy apparent in the figure becomes
increasingly important as design rules shrink, but creates a step coverage problem for
subsequently deposited metallization. Various methods for achieving tapered win-
dows with dry etching have been proposed, but all of them involve tradeoffs either in
selectivity, dimensional control, or process complexity.'^'
'^'
8.8.2 Silicon Nitride
Two more or less distinct types of nitride films are used in VLSI processing. Films
deposited by low-pressure or atmospheric CVD are used as an oxidation and /or diffu-

338 VLSI Technology
(a)
(c) (d)
Fig. 25 SEM micrographs illustrate the results of highly anisotropic etching in reactive plasmas for several
materials used in VLSI technology, (a) A plasma etched contact window in a 2-fxm-thick phosphorous-
dop)ed Si02 layer; the substrate is Si. (b) Plasma etched pattern in a l-|jLm-thick phosphorous-doped
polycrystalline Si film; the substrate is SiOi. (c) l-jjim-wide features created in single-crystal Si by RIE;
note the trenching at the base of the features, (d) Plasma-etched pattern in a 1 .5-|j.m-thick Al—0.7% Cu
film; the substrate is an SiO^ film.
sion mask and do not become a permanent part of the device. As an example in n-
channel MOS fabrication a tliin (
— 1000 A) nitride film is deposited over a thin oxide
(—250 A) on the Si substrate and patterned. A thick oxide (—5000 A) is then grown in
unmasked regions by high-temperature oxidation. Because the nitride is thin and
lateral dimensions relatively coarse, a high degree of anisotropy is not required for
patterning the nitride. CF4-O2 and other plasmas that produce F atoms have been
used in this application. The selectivity with respect to Si02 must be sufficient to
avoid complete loss of the underlying oxide, or else the Si substrate will be substan-
tially etched, since the selectivity of CVD silicon nitride relative to Si is about 1:8 for
F atom plasmas.
Nitride films deposited from SiH4—NH3 or SiH^—N2 plasmas at low substrate
temperatures (^ 350°C) are used for passivation and sometimes as intermediate
dielectrics. In the former application the films are thick (=s 1 .5 ixm), but only coarse
features must be etched in them to expose underlying metallization for bonding. Iso-
tropic etching in CF4—O2 or other F atom source gases is usually employed for pat-
terning. Plasma-deposited nitride, which is really a polymer-like Si—N—H material,
etches much faster than CVD silicon nitride in plasmas containing F atoms. The etch
rate is similar to that for Si.

Dry Etching 339
When plasma-deposited silicon nitride film is used as an intermediate dielectric,
the same considerations for etching windows apply as with SiO^, and the same gases
and process conditions are employed, although with somewhat lower etch rates than
for Si02.
8.8.3 Polysilicon and Refractory-Metal Silicides
A high degree of anisotropy is required for etching polysilicon or polycide'*^ gates. (A
polycide is a composite layer consisting of a layer of metal silicide over a layer of
polysilicon.) The gate length is a critical, fine line dimension that fixes the device
channel length in the self-aligned gate technology. For example, if the etch profile is
tapered rather than vertical, then portions of the gate will not be thick enough to be
effective in masking the source and drain dopant implant. The resultant substrate
doping profile depends on the amount of taper which, if uncontrolled, results in a
variable channel length.
Similarly, the selectivity with respect to Si02 must be high, because the thin gate ox-
ide (250 to 500 a) exposed at the completion of etching overlays shallow (~2500-A)
source and drain junctions in the Si substrate. Also, if polysilicon or polycide runners
cross field oxide steps, the runners will have a greater vertical thickness at the steps.
This additional thickness requires overetching if the etching is anisotropic (Section
8.2.4).
Gases and gas mixtures containing chlorine have predominated for anisotropic
etching of polysilicon. CIt and ClT-Ar plasmas have been used for reactive ion etch-
ing with Af = 1 for undoped material. Heavily doped (> 10*^° cm~^^) n-type material
is undercut for identical conditions. ^^ For plasma etching conditions, both doped and
undoped materials etch laterally in CU plasma, and the etch rate for heavily doped n-
type poly-Si is more than an order of magnitude higher than for undoped or p-type
polysilicon. The influence of doping has been explained on the assumption that CI
atoms are the etchant species, and that n-type doping, by raising the Fermi level,
reduces the energy barrier for electron transfer to a bound CI atom.^' Etching can be
made highly anisotropic (Af = 1) by use of a gas additive containing a recombinant,
as discussed in Section 8.6. 1 . Examples of additives that have been used are CCI4 in
RIE and Ct F^ in plasma etching.
Bromine containing analogs of the chlorinated gases can also be used for aniso-
tropic etching of polysilicon. The selectivity with respect to Si02 for both CI and Br
containing plasmas is generally good. Loading effects also tend to be minimal or
absent with CI and Br containing gases. Figure 25b and c illustrates anisotropic etch-
ing of patterns in polysilicon and single-crystal silicon, respectively.
Fluorinated gas plasmas generally etch polysilicon isotropically, with a strong
loading effect. However, gases such as CF4, CF4-O2, and SF6 have been reported to
etch polysilicon anisotropically under conditions that produce high-energy ion bom-
bardment of the surface, such as low frequency and low pressures.
'^^"'^^
Comparatively little information has been published on dry etching processes for
refractory-metal silicides. Both isotropic and anisotropic etching have been reported
for CF4-O2 plasmas."^-
^''
Isotropic profiles have been observed with plasma etching,

340 VLSI Technology
and anisotropic profiles iiave been observed with reactive ion etching. Reactive ion
etching with SF6 has also been reported to provide a high degree of etch anisotropy,
but with low selectivity (^4:1) relative to SiO^.'^''' Much better selectivity is required
for two-level polysilicon or polycide structures, when the layers pass over field oxide
steps.
A single-step process for anisotropic dry etching of polycides has not been
reported. Three problems are encountered in this application. (1) The etch rate aniso-
tropy is insufficient for one or both layers. (2) Polysilicon etches faster than the sili-
cide, leading to undercutting that causes loss of adherence of the silicide or subse-
quent step coverage problems. (3) Selectivity with respect to the underlying gate
oxide is insufficient.
Multi-step processes have been designed to circumvent these problems.
'^^'^^
For
example, a two-step process, for l-|jLm MOSFETs,'^^ consists of a reactive ion etch
step to define the silicide and part of the polysilicon layer. This step is followed by an
isotropic plasma etch with good selectivity over oxide to clear "extra'' material from
vertical steps (see Fig. 7).
8.8.4 Aluminum (Al-Si, Al-Cu)
Chlorine-containing gases, such as CCI4, BCI3 and SiCU, or mixtures of these gases
with CI2 have been favored for etching aluminum alloys (Al-Si, Al—Cu) used in
VLSI.'^^ A freshly exposed aluminum surface, uncovered by AI2O3, reacts spontane-
ously with CI or CI2 to form quasi-volatile AICI3 even in the absence of a plasma.
However, aluminum is usually covered by a thin (~30-A), layer of native oxide that
does not react with CI or CI2.
The native oxide must be removed by sputtering or chemical reduction before
etching can proceed. Gases such as BCI3 and CCI4, when dissociated in a plasma,
produce fragments capable of reducing the thin oxide layer. This step in the etching
is observable as an induction period. Part of the irreproducibility initially reported for
aluminum etching is related to the deleterious effect of residual gases, particularly
water vapor, on the duration of the induction period. Water vapor can prolong initia-
tion of etching by reacting with or scavenging oxide-reducing species and by reacting
with aluminum to reform the oxide.
Further difficulty with residual water vapor is related to the quasi-volatility of the
etch product (AICI3), which can redeposit on etch system walls and adsorb consider-
able moisture on exposure to atmosphere. Upon initiation of a plasma, desorption of
water vapor interferes with etching. Some commercial etching systems have vacuum
load-locks to avoid this problem.
Anisotropic etching can be achieved in either the RIB or plasma etching mode of
operation, particularly if a recombinant gas mixture such as CCI4—Cb or BCI3— CI2 is
used. BCI3 offers an advantage over CCI4, in that polymer deposition does not occur
over a wide range of operating parameters.
Evidence indicates that the reaction of CI atoms with aluminum is unaffected by
ion bombardment.^' If this is the case, anisotropy is attributable to the influence of
ions on rates of recombination-type reactions. There is some evidence that with CCI4

Dry Etching 341
a non-reactive layer forms on sidewalls and blocks etching there, but is removed by
ion bombardment elsewhere.''*
Al-Si alloys, containing up to several percent Si, are readily etched in chlorine
containing gases, as silicon forms volatile chlorides. However, Al—Cu alloys (^ 4%
Cu). used to suppress electromigration. present a more difficult problem, because
copper forms no volatile halides. Cu containing residues often result after reactive
etching of these alloys, unless ion energies are sufficient to remove them by sputter-
ing. Wet chemical procedures have been used to remove such residues.
Selectivity with respect to Si02 is sufficient for VLSI devices even when alumi-
num passes over steps. However, selectivity with respect to silicon (or polysilicon) is
generally poor with chlorine containing gases. Consequently, conductors must over-
lap contact windows and this restricts the density of conductor lines. Table 2 indi-
cates etch rates and selectivity typical of reactive etching of aluminum, and Fig. 25d
illustrates a typical edge profile.
Another problem that has plagued the development of aluminum dry etching is
post-etch corrosion, which results when atmospheric moisture hydrolyzes chlorine
containing residues on the wafer to form HCl. Much of the residue is associated with
the photoresist, making it desirable to remove this material as soon after etching as
possible, preferably in-situ. However even this precaution may be insufficient to pro-
tect fine line patterns. A more expedient approach is to follow etching by exposure
to a tluorocarbon plasma, which converts chloride residues to unreactive fluorides.
Al—Cu alloys are especially susceptible to post-etch corrosion, because the enrich-
ment of the involatile Cu component in the surface region causes copper chlorides to
form.^'^
VLSI processing requires methods for transferring circuit features from resist masks,
defined by lithography, into active circuit materials, with a high degree of dimen-
sional accuracy. Dry etching techniques that use low-pressure gas discharges (plas-
mas) can produce highly directional etching to meet the requirements for dimensional
accuracy.
Etching processes used for pattern transfer in VLSI must be highly selective.
Ideally, neither the resist mask nor previously processed portions of a circuit should
be removed during etching. The requirements for selectivity are best met by plasma-
assisted etching techniques that use gases containing reactive constituents. Fragmen-
tation of these gases in a plasma produces species that can chemically combine with
the material to be etched to form a volatile product.
Reactive ion etching and plasma etching in parallel-plate systems are the dom-
inant techniques for VLSI dry etching. The superior control of circuit dimensions
achieved with these methods results from etch rate anisotropy. Anistropy occurs
when chemical reactions between neutral species, generated in the plasma, and the
surface being etched are influenced by directional energetic particle bombardment.
The energetic particles are usually positive ions drawn from the plasma by an imposed
electric field.

342 VLSI Technology
Etch rate, selectivity, and anisotropy are determined by various parameters
including gas composition, gas pressure, wafer temperature, and the operating fre-
quency and power density of the plasma. These parameters must be carefully con-
trolled to avoid unwanted effects such as polymer deposition and radiation damage.
Plasma processes have been developed for etching most of the materials used in
VLSI technology. However, improvements in selectivity, edge profile control, repro-
ducibility, overall process control, automation, and throughput are needed.
Better selectivity and profile control will be particularly important to efforts to
further reduce the size of circuit features. Future work will lead to increased etch
rates. Faster etching will shift the focus in dry etching equipment to single- wafer sys-
tems, with cassette to cassette, fully automated wafer processing.
The future will also see dry etching extended to new materials and devices, and
significant advances in our understanding of the complex physics and chemistry
underlying dry etching processes.
REFERENCES
[1] C. M. Melliar-Smith and C. J. Mogab, "Plasma-Assisted Etching Techniques for Pattern Delinea-
tion," in J. L. Vossen and W. Kern. Eds., Thm Film Processes. Academic, New York, 1979.
[2] S. M. Irving, "A Plasma Oxidation Process for Removing Photoresist Films," Solid State Technol.,
14(6), 47 (1971).
[3] S. M. Irving, K. E. Lemons, and G. E. Bobos, "Gas Plasma Vapor Etching Process," U.S. Patent
3,615,956. (Filed March 27, 1969; patented Oct. 26. 1971.)
[4] T. C. Penn, "Forecast of VLSI Processing —A Historical Review of the First Dry-Processed IC",
IEEE Trans. Electron Devices, ED-26, 640 (1979).
[5] D. L. Tolliver, "Plasma Processing in Microelectronics —Past, Present, and Future," Solid State
Technol., 25, 99 (9S0).
[6] G. K. Wehner and G. S. Anderson, "The Nature of Physical Sputtering," in L. I. Maissel and R.
Glang, Eds.. Handbook of Thin Film Technology. McGraw-Hill, New York, 1970.
[7] D. Bollinger and R. Fink, "A New Production Technique; Ion Milling," Solid State Technol.. 25. 79
(1980).
[8] B. Chapman, Glow Discharge Processes. Wiley, New York, 1980.
[9] J. L. Vossen, "Glow Discharge Phenomena in Plasma Etching and Deposition," J. Electrochem.
Soc, 126,319(1979).
[10] H. R. Koenig and L. I. Maissel, "Applications of RF Discharges to Sputtering," IBM J . Res. Dev.,
14, 168(1970).
[11] J. W. Cobum and E. Kay, "Positive-Ion Bombardment of Substrates in RF Diode Glow Discharge
Sputtering," y. Appl. Phys.. 43, 4965 ( 1972).
[12] A. R. Reinberg, "Dry Processing for Fabrication of VLSI Devices," in N. G. Einspruch, Ed.. VLSI
Electronics. Academic, New York, 1981, Vol. 2.
[13] D. B. Eraser et al. Pumping Hazardous Gases. American Vacuum Society. New York, 1980.
[14] R. H. Bruce, "Anisotropy Control in Dry Etching," Solid State Technol.. 24, 64 (1981).
[15] D. F. Downey, W. R. Bottoms, and P. R. Hanley, "Introduction to Reactive Ion Beam Etching,"
Solid State Technol.. 26, 121 (1981).
[16] C. M. Melliar-Smith. "Ion Etching for Pattern Delineation," J. Vac. Sci. Technol.. 13, 1008 (1976).
[17] J. W. Cobum and H. F. Winters, "Ion- and Electron-Assisted Gas-Surface Chemistry —An Important
Effect m Plasma Etching," 7. Appl. Phys., 50, 3189 (1979).
[18] J. W. Cobum and H. F. Winters, "Plasma Etching—A Discussion of Mechanisms," J. Vac. Sci.
Technol., 16,391(1979).

Dry Etching 343
U. Gerlach-Meyer. "Ion Enhanced Gas-Surface Reactions: a Kinetic Model for the Etching Mechan-
ism.
"
5i///. Sd'. 103.524(1981).
U. Gerlach-Meyer, J. W. Cobum. and E. Kay. "" Ion-Enhanced Gas-Surface Chemistry: The Influence
of the Mass of the Incident Ion." Surf. Sci.. 103, 177 ( 1981).
D. L. Flamm and V. M. Donnelly, "The Design of Plasma Etchants," Plasma Chemistry and Plasma
Processing. 1,317(1981).
C. J. Mogab. A. C. Adams, and D. L. Flamm, "Plasma Etching of Si and SiO^—The Effect of Oxy-
gen Additions to a CF4 Plasma." J. Appl. Phys.. 49. 3769 ( 1978).
L. M. Ephrath, "Selective Etching of Silicon Dioxide Using Reactive Ion Etching with CF4/H2,"
J. Electrochem. Soc, 126. 1419 (1979).
K. Hirata. Y. Ozaki. M. Oda. and M. Kimizuka. "Dr)- Etching Technology for l-|j.m VLSI Fabrica-
tion." IEEE Tram. Electron Devices. ED-28. 1323 ( 1981 ).
R. F. Reichelderfer. "Single Wafer Plasma Etching." Solid State TechnoL. 25 160 ( 1982).
J. Taillet. "Plasma Physics: Ion Energ>' in RF Plasma Etching." 7. Physique. 1 1 . L-223 ( 1979).
H. Kalter and E. P. G. T. Van deVen. "Plasma Etching in IC Technology." Philips Tech. Rev.. 38.
200(1978 79).
G. C. Schwartz and P. M. Schaible, "Reactive Ion Etching of Silicon," J. Vac. Sci. TechnoL. 16. 410
(1979).
C. J. Mogab. "The Loading Effect in Plasma Etching." 7. Electrochem. Soc. 124. 1262 (1977).
T. Enomoto, M. Denda, A. Yasuoka. and H. Nakato, "Loading Effect and Temperature Dependence
of Etch Rate in CF4 Plasma," Jpn. J. Appl. Phys.. 18. 155 (1979).
C. J. Mogab and H. J. Levinstein. "Anisotropic Plasma Etching of Polycr'stalline Silicon." J. Vac.
Sci. TechnoL. 17,721 (1980).
J. E. Greene. "Optical Spectroscopy for Diagnostics and Process Control During Glow Discharge
Etching and Sputter Deposition," J. Vac. Sci. TechnoL. 15, 1718 ( 1978).
P. J. Marcoux and P. D. Foo, "Methods of End Point Determination for Plasma Etching," Solid State
TechnoL. 24. 115(1981).
R. A. Gdula, "The Effects of Processing on Radiation Damage in Si02," IEEE Trans. Electron De-
vices, ED-26, 644 ( 1979).
L. M. Ephrath and D. J. DiMaria. "Review of RIE Induced Radiation Damage in Silicon Dioxide,"
Solid State TechnoL , 24. 1 82 ( 1 98 1 )
.
S. P. Murarka and C. J. Mogab, "Contamination of Silicon and Oxidized Silicon Wafers During
Plasma Etching," i. Electron. Mater.. 8, 763 ( 1979).
K. Hirata, Y. Ozaki, M. Oda, and M. Kimizuka. "Dr Etching Technology for l-|xm VLSI Fabrica-
tion," IEEE Trans. Electron Devices. ED-28, 1323 ( 1981).
R. A. H. Heinecke, "Control of Relative Etch Rates of SiO^ and Si in Plasma Etching." Solid State
Electron.. 19. 1039(1976).
S. Matsuo. "Selective Etching of SiO^ Relative to Si by Plasma Reactive Spuner Etching." J. Vac.
Sci. TechnoL. 17.587(1980).
J. A. Bondur and R. G. Frieser. "Shaping of Profiles in SiO; by Plasma Etching." in R. G. Frieser
andC. J. Mogab. Eds., Plasma Processing. Electrochem. Soc.. Pennington, New Jersey, 1981.
L. B. Rothman. J. L. Mauer IV, G. C. Schwartz, and J. S. Logan. "Process for Forming Taf»ered
Vias in SiO^ by Reactive Ion Etching." in R. G. Frieser and C. J. Mogab. Eds.. Plasma Processing,
Electrochem. Soc., Pennington. New Jersey, 1981.
S. P. Murarka, "Refracton,' Sihcides for Integrated Circuits," 7. Vac. Sci. TechnoL. 17, 775 1( 1980).
P. D. Pany and A. F. Rodde, "Anisotropic Plasma Etching of Semiconductor Materials," Solid State
TechnoL. 22, 125(1979).
H. Mader, "Anisotropic Plasma Etching of Polysilicon with CF4," in R. G. Frieser and C. J. Mogab,
Eds., Plastna Processing. Electrochem. Soc., Pennington. New Jersey. 1981.
W. Beinvogl and B. Hasler. "Anisotropic Etching of Polysilicon and Metal Silicides in Fluorine Con-
taining Plasma," Proc. 4th Int. Sy/np. on Si Materials and TechnoL, 81-5. 648 ( 1981 ).
B. L. Crowder and S. Zirinsk)'. "lixrn MOSFET VLSI Technology: Part VU—Metal Silicide Inter-
connection Technology—A Future Perspective." IEEE Trans. Electron Devices. ED-26. 369 (1979).

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[47] T. P. Chow and A. J. Steckl, "Plasma Etching Characteristics of Sputtered MoSi2 Films," Appl.
PhyS.Lett.. 31. 466 {9m.
[48] E. C. Whitcomb and A. B. Jones, "Reactive Ion Etching of Submicron MoSiT/Poly-Si Gates for
CMOS/SOS Devices," Solid State TechnoL. 25, 121 (1981).
[49] D. W. Hess, "Plasma Etching of Aluminum." Solid State TechnoL. 24, 189 (1981).
[50] W. Y. Lee, J. M. Eldridge, and G. C. Schwartz, "Reactive ion Etching Induced Corrosion of Al and
Al-Cu Films," y. Appl. Phys., 52, 2994 (1981).
PROBLEMS
1 Assuming a mask that cannot erode, sketch the edge profile of an isotropically etched feature in a film of
thickness hj on an unetchable substrate for (a) etching just to completion, ib) 100% overetch, and (f ) 200%
overetch. What shape does the profile tend toward as overetching proceeds? Comment on the advisability
of estimating the degree of anisotropy of etching from scanning electron micrographs of edge profiles taken
after removal of the masking layer.
2 By tracing the trajectory during etching of a point on the beveled edge of the mask in Fig. 5, arrive at
Eq. 7.
3 Show that Eq. 12 results when the thinnest and fastest etching portion of the film is assumed to be over
the fastest etching portion of the substrate.
4 Polysilicon lines 0.5 ixm thick pass over a field oxide step 1 . 1 [xm high and across a gate oxide 0.05 iJim
thick. Calculate the selectivities required with respect to mask and gate oxide if the polysilicon is etched
with a process having 10% etch rate uniformity, Af = 1 .0, and A,„ = 0.5. Assume 5% polysilicon thick-
ness uniformity, 5% mask etch rate uniformity, a mask edge profile of 60°, and that linewidth must be con-
trolled to 0.2 |jLm.
5 Consider a discharge in CF4. Assume that electrons and gas molecules can be treated as hard spheres with
masses m and M, respectively. Calculate the maximum fractional loss of kinetic energy for an electron strik-
ing a CF4 molecule. Consider the CF4 molecule initially at rest, and the collision to be elastic. Repeat the
calculation for an inelastic collision where the potential energy of the CF4 molecule increases by the max-
imum amount possible.
6 A CF4—Ot rf plasma is operated at 300 W, and 0.5 torr, with a feed-gas flow rate of 100 cm- /min (STP).
The plasma occupies a volume of 4000 cm^^. Under these conditions atomic fluorine is generated at a rate of
10'^ cm"^ — s~' in the plasma. The combined effect of loss mechanisms for F atoms results in a rate of
loss proportional to the F atom concentration. In steady state, this concentration is measured as
3 X lO'^cm"^. What is the mean lifetime of F atoms for these conditions? How does it compare to the
residence time of an average molecule in the plasma? How would the etch rate of Si be affected if the flow
rate were increased tenfold while holding other parameters constant?
7 What is the function of the ground shield shown in Fig. 11? What limitation is there on the spacing
between the ground shield and the powered electrode?
8 What are the major distinctions between reactive ion etching and parallel-plate plasma etching? Compare
the advantages and limitations of these techniques.
9 Would you expect the rate of an ion-assisted reaction between neutral species and a solid surface to be
independent of the angle of incidence of the ion beam? Why? What do you expect would happen to the
reaction rate as the ion energy was increased continuously beyond 5 keV?
10 The enthalpy of the exothermic reaction
Si + 4F ^ SiF4
is 370 kcal/g-mole at 25°C. At what rate is heat generated when a 100-mm-diameter, 0.5-mm-thick Si wafer
is etched on one face at a rate of 1 .0 p-m/min in an F generating plasma? Suppose that the wafer is thermally
isolated during etching. By how much will its temperature rise if 5.0 jxm are etched away?

Dr- Etchixg 345
11 Explain why the peaks of the cunes m Fig. 19 are shifted in time relative to each other. Plot the peak
positions (time coordinate) against the number of wafers. What functional form do ou get? Show that this
form is expected when a loading effect exists and the actixation energy for the reaction is negligible. What
conclusion can be drawn from the fact that peak wafer temperature depends on the number of wafers?
12 Explain wh>' endpwint detection b' monitoring of reactant species requires a loading effect.

CHAPTER
NINE
METALLIZATION
D. B. ERASER
9.1 INTRODUCTION
Metallization is perhaps best defined operationally by giving an example. Figure 1
shows a schematic view of a conventional MOSFET with an n^ source and drain
implanted in a p-type substrate. The source and drain are contacted through windows
by metal (e.g., Al) and connected to a power supply. Current flows between the
source and drain when a threshold voltage Vj is applied to the gate electrode. This
voltage creates a field across the gate oxide, which causes the adjacent p substrate to
invert to n-type, thus creating a conductive n channel between the source and drain.
The gate electrode, usually conductive polysilicon, is connected by metal to a signal
voltage. Thus, the metallization requires low-resistance interconnections, and the
formation of low-resistance contacts to n"*", p"^, and polysilicon layers. Also, the
structures should be stable under use —that is, metal adherence, electromigration
(material transport in conductors carrying high currents), and corrosion should not
significantly reduce reliability —and, finally, the structure should be easily patterned
by a straightforward process.^
Most silicon MOS and bipolar integrated circuits now manufactured are metal-
lized with Al or one of its alloys. Because Al has a low-room-temperature resistivity
of approximately 2.7 ixO-cm, and that of its alloys may be 307c greater, these metals
satisfy the requirements of low resistance. Al and its alloys adhere well to thermally
grown Si02 and to deposited silicate glasses (because the heat of formation of AI2 O3
is higher than that of Si02). Despite these advantages, the use of Al in VLSI applica-
tions where junctions are shallow often encounters problems with electromigration
and corrosion. However, as will be shown, viable solutions exist. Electromigration
can be reduced by control of the deposited film characteristics and corrosion can be
minimized by careful processing and packaging techniques.
347

348 VLSI Technology
METAL CONTACTS
GATE
ELECTRODE
DEPOSITED
DIELECTRIC
Fig. 1 Schematic view of a MOSFET cross section. The areas of concern (in this chapter) are the gate elec-
trode and metal regions.
Other metallization structures have been used but their complex processing
makes them undesirable for VLSI. Among these structures" are Ti-Pd-Au and Ti-Pt-
Au. The Ti-Pt combination is currently used as the first-level conductor in a two-
level metal device structure for LSI applications with Ti-Pt-Au as the second-level
metal layer.
^
The MOSFET gate electrode and interconnect structures are another category of
metallization structures. The reason for the metallization designation is that the
refractory metals and refractory metal silicides that are used to augment or replace the
polysilicon are generally deposited by physical vapor deposition processes. These
processes are similar to those used to deposit Al and its alloys. These refractory
materials are necessary, since the nominal SOO-fxd-cm resistivity of n"^ polysilicon is
too high for VLSI applications when the device channel lengths are 1 .5 ixm or less
and where a single chip may have more than 100,000 devices.
9.1.1 Contacts
In general the contact between the metallization and the substrate may be character-
ized as rectifying or ohmic. When devices require diode characteristics in the con-
tact, a barrier must be used. Otherwise, the goal is to achieve low resistance. A fig-
ure of merit, the specific contact resistance R^ , is useful in characterizing ohmic con-
tacts:'^
Rr =
dJ
dV
(1)
v=o
For low doping in the semiconductor, the metal specific contact resistance can be
represented by
Rr =
qA*T
exp
kT
(2)

Metallization 349
In Eq. 2 A* is the Richardson's constant given by A* = 4TTqm*k'^/ h^ where q is the
charge, m* is the effective mass of the charge carrier (e.g., electron), k is
Boltzmann's constant, /i is Planck's constant, and <^b is the barrier height. Equa-
tion 2 leads to the conclusion that low-resistance contacts are obtained with low bar-
rier heights, since thermionic emission over the barrier dominates the charge tran-
sport. At higher doping levels the barrier width decreases, tunneling becomes impor-
tant, and the specific contact resistance may be written as
Re ~ exp
47T le,m
h
4>f
(3)
where e^ is the dielectric permittivity of silicon and A^^ is the doping concentration.
Roughly, for Nq ^ 10'^ cm~" R^ will be dominated by tunneling and will decrease
rapidly as the doping level goes above lO'^ cm~^. ForN^ ^ lO'^ cm~ thermionic
emission dominates R^ which is then independent of the doping level. Calculated and
experimental values for R^ are shown in Fig. 2. For low-barrier contacts on highly
ND(cm-^ )
10^
,0^° ic" io'« lo'^
1
300K
1 1 1
THEORY
I05 PtSi -
Af -Si
Si
D
^^^.
1
10^ -
y
'^^oesv -
/
/
D
o
^0-'
r
^
D
a
60
-
10-^
-
i / 0.40
-
10-^
-/ -
in-^ // 1 1
H 1
10 30
dO'^'cm'
Nd
Fig. 2 Theoretical and measured values of specific contact resistance as a function of donor concentration
and barrier height. {After Sze. Ref. 4.)

350 VLSI Technology
Table 1 Schottky barrier height ^g
Contact <i>B (V) for ^^ (V) for
material n-type Si p-type Si
Al 0.72 0.58
Cr 0.61 0.50
Mo 0.68 0.42
Ni 0.61 0.51
Pt 0.90
Ti 0.50 0.61
W 0.67 0.45
CoSi 0.68
CoSi2 0.64
IrSi 0.93
NijSi 0.7-0.75
NiSi 0.66-0.75
NiSi2 0.7
PtSi 0.84
PdjSi 0.72-0.75
TaSi2 0.59
TiSi2 0.60
WSij 0.65
doped substrates, /?^. ~ 10 ^ fl-cm" may be used as a target value. Table 1 lists a
number of (})5 values."^
9.1.2 Fundamentals of Physical Vapor Deposition
5
VLSI metallization is currently done in vacuum chambers.^ Figure 3 shows a
schematic view of a system. The chamber shown is a bell jar, a stainless-steel
cylindrical vessel closed at the top and sealed at the base by a gasket. Beginning at
atmospheric pressure the chamber is evacuated by a roughing pump, such as a
mechanical rotary-vane pump or a combination mechanical pump and liquid-
nitrogen-cooled molecular sieve system. The rotary-vane pump can reduce the sys-
tem pressure to about 20 Pa, and the combination pump system can achieve about
0.5 Pa. At the appropriate pressure, the chamber is opened to a high-vacuum pump-
ing system that continues to reduce the pressure of the process chamber. The high-
vacuum pumping system may consist of a liquid-nitrogen-cooled trap and an oil diffu-
sion pump, a trap and a turbomolecular pump, or a trap and a closed cycle helium
refrigerator cryopump. In a low-throughput system, a trap, a titanium sublimation
pump, and an ion pump could also be used. The choice of pumping system depends
on required pumping speed, ultimate pressure attainable (in a reasonable time),
desired film quality, method of film deposition, and expense. Traditional systems
have used oil diffusion pumps but fear of contaminating the films with oil has led to
the use of turbomolecular and cryopumps. The cryopump acts as a trap and must be

Metallization 351
PROCESS
CHAMBER
SUBSTRATES^'
SOURCE
BACKFILL OR
SPUTTER GAS
BASE PLATE
L THROTTLE
VALVE
ROUGHING PUMP
Fig. 3 Schematic view of a high-vacuum chamber with substrates mounted in a planetary substrate support
above the source. Gages are not shown for simplicity.
regenerated periodically; the turbomolecular and diffusion pumps act as transfer
pumps, expelling their gas to a forepump.
The high-vacuum pumping system brings the chamber to a low pressure which is
tolerable for the deposition process. This low pressure is considered the "working"
or base pressure. As an example, the desired base pressure may be 6.6 x 10~^ Pa
(5 X 10"'' torr) for an aluminum evaporation system, but when auxiliary heaters are
turned on the chamber pressure may rise by an order of magnitude or more. The pres-
sure may rise still further when the evaporation source is heated. To reduce the time
required for the deposition process including the pump-down period, system cleanli-
ness is an absolute necessity on several levels. All components in the chamber are
chemically cleaned and dried. Generally, warm water circulates in the coolant chan-
nels of the vacuum chamber to reduce the adsorption of water vapor on the freshly
coated interior when it is opened to the atmosphere. Any interior film buildup is
removed frequently to avoid a major source of trapped atmospheric gas. Freedom
from sodium contamination is vital when coating MOS devices.^ This requirement
involves cleaning the substrates to be coated in HF solutions, avoiding skin contact
with any interior portion of the coating system, and using pure-metal sources.
Sputter deposition demands similar precautions. The system operates with about
1 Pa of argon pressure during the film deposition. Despite the relatively high system
pressure, sputtering is as demanding a process as evaporation because other gases,
such as water vapor and oxygen, may be detrimental to film quality if present at back-
ground pressures of about 10"- Pa. The purity of the argon sputtering gas is also a
factor. Thus, to maintain purity, the lines connecting the gas source to the sputter
chamber should be clean and vacuum tight. For sputtering, the throttle valve should
be placed between the trap and the high-vacuum pumping system. The argon gas
pressure can then be maintained by reducing the effective pumping speed of the high-
vacuum pump, while the full pumping speed of the trap for water vapor is utilized.
Assuming a vacuum station of volume V has no leaks, and is equipped with
pumps of adequate capacity and that the ultimate limitation is set by outgassing of

352 VLSI Technology
water vapor, the chamber pressure P at any time t after pump down has been initiated
is given by the approximate relation^
P = Pq exp
-St
+ ^ (4)
where Pq'i?, the initial pressure, S is the pumping speed, and Q is the rate of outgass-
ing within the system. After the first hour of pumping the second term dominates and
P = Q/S where Q is the outgassing rate after approximately 1 hour. Note that Q
is a slowly varying function of time, since the source of outgassing, in principle, will
eventually be depleted. This characteristic of vacuum systems has led to the introduc-
tion of "load-lock" systems, where the substrates are introduced into the process
chamber through a lock chamber that cycles between atmospheric pressure and some
reduced pressure. At the reduced pressure the substrates are transferred from the lock
into the process chamber, and only the substrates have to be outgassed rather than the
whole chamber interior. After completion of the process the substrates are transferred
through the same or another lock and brought out of the system. Use of such systems
in production facilities is growing because the number of wafers processed per day
can exceed what can be processed in a simple chamber (when silicon wafers 100 mm
and larger in diameter are used). We used the term "process" in the above descrip-
tion because, in addition to film deposition, reactive sputter etching and plasma etch-
ing are also performed in load-lock systems.
9.1.3 Thickness Measurement and Monitoring
In VLSI applications control of conductive film thickness is essential, because a film
thinner than desired can cause excess current density and failure during operation.
Conversely, excessive thickness can lead to difficuhies in etching. The use of thick-
ness monitors is common in evaporation deposition, and in magnetron sputter deposi-
tion where planetary systems support the substrates. In some magnetron deposition
processes, the film is deposited without monitoring during the deposition, but is
checked after the deposition.
The most common thickness monitor is a resonator plate made from a quartz cry-
stal. The plate is oriented relative to the major crystal axes, so that its resonance fre-
quency is relatively insensitive to small temperature changes.^ The acoustic
impedance and the additional mass of any film deposited on the resonator cause a fre-
quency change that can be measured accurately. After calibrating the monitor in the
deposition system, it may be used to control the deposition rate as well as the final
thickness of the deposited film. The resonator crystal has a finite useful life and must
be replaced; however, no recalibration is necessary if the deposition system has not
been modified. The resonator has a finite useful life because A/ ^^ AM holds true
for A/ //o ^ 0.05, where A/ is the resonator frequency change, AM is the addi-
tional deposited mass, and/o is the initial resonator frequency.
We can calibrate such systems and measure unmonitored film thickness in at least
two different ways. The simplest is to use a microbalance and weigh the substrate

Metallization 353
before and after film deposition. The film is assumed to have bulk density p^,, so that
the increase in mass A m is related to the film thickness t by
Volume = —— = At (5)
Pd
and
Am ,- .
t
= (5a)
where A is the area of the film.
Another technique uses a surface profile measuring device. A fine stylus, usually
diamond, is drawn over the surface of the substrate and encounters a step where the
film has been etched or masked during deposition. The entire height of the step is
detected by differential capacitance or inductance measurements. Calibration is
maintained by using standard film samples which can be checked periodically. Films
as thin as 100 A or less can be measured by such devices. Other techniques for
measuring conductor film thickness include optical interference techniques and eddy
current measurements.
9.1.4 Application of Kinetic Theory of Gases
The kinetic theory of gases yields two concepts that are useful in physical vapor depo-
sition. The first is the concept of rate of bombardment by gas molecules of the
exposed surfaces in the chamber.
N = {ImnkTr^-p (6)
where N is the bombardment rate in molecules cm~^-s"' for a gas of molecular mass
m at temperature T in kelvins and pressure /?. Equation 6 may be rewritten as
A^ = 6.4 X 10'*^ {MT)-% (7)
where M is the gram-molecular mass and/? is in Pa. Possible effects of residual gas or
gas added intentionally during the deposition of films can be estimated using the bom-
bardment rate. The second useful concept is that of mean free path X where
X = —
^
(8)
P 1TCT"V2
and where ct is the diameter of a gas molecule. For residual gases, such as He, O2,
N2, and H2O, found frequently in vacuum chambers, the value of a ranges^ from 2 to
5 A. Thus for air at constant pressure the product
p = constant — 0.7 cm-Pa (9)
Because the collision process is statistical , the fraction of total molecules n not
suffering a collision while traveling a distance d is
n /no = Qxp(-d /) (10)

354 VLSI Technology
For a distance d = K, only 37% of the tiQ molecules do not undergo collision. These
concepts are useful in sputtering applications where Ar pressures of about 1 Pa are
frequently used, and ~ 0.7 cm may be expected. The implication for sputter depo-
sition is that the sputtered vapor may undergo considerable kinetic scatter prior to
reaching the substrate. In contrast, in evaporation processes with chamber pressure
P ^ 10~" Pa, residual gas molecules would have X ~ 1 m, thus validating the
assumption that evaporated vapor travels in straight lines from the source to the sub-
strate. The assumption of straight-line travel is basic to treatments of film step cover-
age on substrates.
9.2 METHODS OF PHYSICAL VAPOR DEPOSITION
The rate of evaporation of metal from a melt is estimated by use of the Hertz-
Knudsen^ equation:
A^, = (2iT mkT)-%, (11)
where A^^ is the number of molecules per unit area per time, m is the molecular
(atomic) mass, k is Boltzmann's constant, T is the surface temperature in kelvins, and
Pg is the equilibrium vapor pressure of the evaporant. This vapor pressure may be
written as a rate of mass loss per unit area from the source
M
T
R = 4.43 X 10"4 g/cm^-s (12)
where M is the gram-molecular mass andp^ is in Pa. For example, p^ (Al) ~ 1 .5 Pa
at 1500 K.
The total loss Rj per unit time from the source may be found by integrating over
the source area:
Rt = J R dA, (13)
The flux of material to the receiving substrate is dependent on the cosine of the angle,
4), between the normal to the source surface and the direction of the receiving surface
a distance r away. If 6 is an angle between the receiving surface normal and the
direction back to the source, then
n
D = —^ cos ct) cos e (14)
where D is the deposition rate in g/cm^-s.
The deposition rate at various points on a substrate plane above a point or area
source may be found from Eq. 14. For example,
-2
-^ = + ^ (15)
L
2"
1 +
H

Metallization 355
RECEIVER
SOURCE
Fig. 4 Idealized view of vapor source and film gathering surface mounted on a sphere of radius Kq.
for a small area source and
D
Do
r
2
~
1 +
H
(16)
for a point source where Do is the rate directly above and H away from the source and
D is the rate at a point L away from the center of the substrate plane.
When the receiving surface is spherical and has a radius kq, and the source is on
the surface (see Fig. 4), then
cos 6 = cos 6 =
^'o
and Eq. 14 is written
D =
Ri
4iTr
(17)
(18)
Therefore the deposition rate is the same for all points on the spherical surface, which
is the principle behind the planetary (rotating spherical sections) substrate supporting
systems used in deposition chambers.
In chronological order, the method of deposition of Al and (to some extent) its
alloys has proceeded through: (1) resistance-heated evaporation, (2) electron-beam
evaporation, (3) inductively heated evaporation, (4) magnetron sputter deposition,
and (5) chemical vapor deposition. Each technique has advantages and disadvantages
that must be carefully considered before deciding which may be used in a given appli-
cation.
9.2.1 Resistance-Heated Evaporation
Figure 5 shows a refractory metal filament (e.g., W) with small pieces of the Al to be
evaporated shown suspended from the filament coils. Other, more complex source
structures may also be formed from sheets of the refractory metal. The resistance-
heated approach is attractive because it is simple, inexpensive, and produces no ioniz-

356 VLSI Technology
W HEATER
t
.At
Fig. 5 Refractory wire coil W acting as a support and heat source for the vacuum evaporation of Al.
ing radiation. Its disadvantages are the possibility of contamination from the heater,
the small charge which limits ultimate film thickness, short filament life, and, unless
flash evaporation techniques'^ are used, the difficulty in preserving alloy composition
in the film. Flash evaporation employs a heated surface onto which particles of the
alloy to be vaporized are dropped. The heating is rapid and all constituents are trans-
ported to the substrate. Despite its disadvantages, filament evaporation continues to
be used for deposition of Al electrodes that are used in the evaluation of test capaci-
tors for furnace qualification and in experiments. A large array of charged filaments
can be used to approximate a large area source. The large area source gives better
metal film step coverage than a single source. When a number of substrates are to be
coated simultaneously, a planetary system may be used to provide uniform film thick-
ness. Other metals, such as Au and Pd, may be conveniently evaporated by this
method.
9.2.2 Electron-Beam Evaporation
Figure 6 shows a schematic view of an e-beam evaporation source. A hot filament
supplies current of the order of 1 A to the beam and the electrons are accelerated
through (typically) 10 kV, and strike the surface to be evaporated. Using a magnetic
field to curve the path of the e-beam permits screening of the hot filament so that
impurities from the filament cannot reach the substrates. Scanning the e-beam over
the surface of the melt prevents the nonuniform deposition that would otherwise occur
by the formation of a cavity in the molten source. By using a large source, thick-film
deposition may be performed without breaking the vacuum and recharging the source.
The large source also permits moving the substrates farther away from the source such
as in a planetary system. With a number of sources in one chamber, the system can
deposit films sequentially without breaking the vacuum. Coevaporation to form alloy
films may also be performed with multiple sources. Because of the high power avail-
able in the e-beam very high film deposition rates can be attained. Depending on
source-to- substrate distance, rates as high as 0.5 fxm/min are common. The use of
excessive power, however, can lead to deposition on the substrates of metal droplets
that have been blown out of the source by expanding metal vapor.
In addition to Al and its alloys, other elements (Si, Pd, Au, Ti, Mo, Pt, and W)
and dielectrics such as AI2O3 may be evaporated by the e-beam process. Generally
Al and its alloys are evaporated from a charge sitting directly in the water-cooled

Metallization 357
e BEAM
WATER COOLED
Cu HEARTH
Fig. 6 Electron-beam evaporation system. Note that a magnetic field causes the electrons to follow a
curxed path so that the substrates are protected from the hot filament.
copper hearth of the e-beam source. Heat transfer to the coohng water is reduced if a
crucible hner (e.g., boron nitride) is used to contain the source. However, the hner
may contaminate the deposited films. Contamination from Cu may also occur when
no liner is used, if the Al meh wets the copper hearth and begins dissolving it.
At voltages of the order of 10 kV, the characteristic Al K-shell x-rays, along with
a continuum, are generated by the e-beam. This ionizing radiation penetrates the sur-
face layers of the silicon substrates and causes "damage" which changes the MOS
capacitor characteristics. The silicon then requires subsequent annealing.
9.2.3 Inductively Heated Sources
Figure 7 schematically shows an evaporation source that is heated by rf induction.
The crucible is generally made of BN. This process also achieves high deposition
rates. Its advantage over the e-beam source is the absence of ionizing radiation. Like
e-beam evaporation excessive material heating by rf induction can also cause molten
drops to be transported to the substrates. Another disadvantage of this process is the
mandator}' use of the crucible. As in the e-beam method, dilute Al alloys may be
deposited, as well as other metals compatible with the crucible. Note a lower tem-
perature sinter can be used to form the contacts of the Al film to the substrate,
because of the absence of ionizing radiation during the deposition process. This point
will be discussed later when contact problems are described (Section 9.4. 1 ).
a£ CHARGE
rf COIL (WATER COOLED)
Fig. 7 Inductively heated evaporation source. The molten Al charge is contained by the dielectric BN
crucible.

358 VLSI Technology
9.2.4 Sputter Deposition
Conventional sputtering" has found wide application in IC processing. Metals such
as Ti, Pt, Au, Mo, W, Ni, and Co are readily sputtered using either a dc or rf
discharge in a diode system. Sputtering is a physical phenomenon involving the
acceleration of ions, usually Ar"^, through a potential gradient, and the bombardment
by these ions of a "target" or cathode. Through momentum transfer, atoms near the
surface of the target material become volatile and are transported as a vapor to the
substrates. At the substrates, the film grows through deposition. The sputtering of
dielectrics, such as AI2O3 or Si02 requires the use of an rf power source, while con-
ductors may be sputtered with either power source. Al is difficult to sputter by con-
ventional means because residual oxidants form a stable oxide on its surface during
sputtering. A high electron density is required in the discharge to increase the ion
current density at the target surface and thus prevent the oxide from forming. The
high density may be achieved by introducing an auxiliary discharge, as in triode
sputtering," or through the use of magnetic fields to capture the electrons and
increase their ionizing efficiency, as is done in magnetron sputtering.'^'
'' '"^
Ion beam sputtering'"* has also been used to sputter both metals and insulators.
The flux of energy to the target can be modified through independent variation of ion
current and energy. Furthermore, the target is in a lower pressure chamber than in
other sputter processes, so that more of the sputtered material is transferred to the sub-
strate and less background gas is incorporated in the deposited film. No ion beam
sputter deposition system has yet been developed for the metallization of large
numbers of silicon wafers.
Some characteristics of sputter deposition are: (1) the ability to deposit alloy
films with composition similar to that of the target, (2) the incorporation of Ar (—2%)
and background gas (~1%) in the film, and (3) in conventional diode systems, con-
siderable heating of the substrates ('-350°C) by the secondary electrons emitted by
the target. Often rf energy may be applied to the substrates which causes them to be
bombarded by ions. If the rf is applied prior to metal deposition, the process is
termed "sputter etching."'^ Sputter etching may clear residual films from window
areas and enhance the contact between the metal and exposed areas. If the rf energy
is applied during film deposition, it is a bias-sputter deposition,''' and may enhance
the step coverage of the film or reduce the severity of the surface topography. Bias-
sputter deposition of Si02 produces planar Si wafer surfaces prior to metal deposi-
tion.'^
9.2.5 Magnetron Sputter Deposition
When magnetron sputter deposition'-'
'^^' '"^
was introduced, high-rate sputter deposi-
tion of Al and its alloys found practical application. The reason appears to be the
much higher current density that occurs at the magnetron target surface during opera-
tion. Introducing a magnetic field converts the sputtering device from a high-
impedance to a low-impedance structure. Two versions are available in large-scale
film coating machines.

Metallization 359
CATHODE
ANODE
Fig. 8 Cross section of a conical magnetron. The magnetic field, 9j , is provided by permanent magnets
and is perpendicular to the electric field, t:^ , near the cathode. The anode is usually biased positively (20 to
40 V) relative to ground.
The first version, shown in Fig. 8. is the conical magnetron or S-Gun. The incor-
poration of a concentric anode and the circular symmetry are unique to this structure.
The conical magnetron has a sputtered flux that is less than that found for the cosine
distribution, and. if many substrates are to be coated simultaneously, planetary sys-
tems similar to those used with evaporation sources may be used.
Figure 9 shows the other source, a planar magnetron. It can be made in varying
lengths so that large substrate areas can be coated. Usually, this magnetron is used
with substrates translated in a plane before the magnetron. The magnetron also can be
mounted in systems equipped with planetary' substrate holders.
Both magnetrons operate at voltages an order of magnitude or more below the
e-beam source voltage, and thus generate less penetrating radiation. Deposition rates
depend on the source-to-substrate distance, and can be as high as 1 |jLm/min for Al
and its alloys.
9.2.6 Chemical Vapor Deposition
The attractiveness of chemical vapor deposition (CVD)'^-'^ for metallization stems
from the conformal nature of the coating (i.e., good step coverage), the ability to coat
large numbers of substrates at a time, and the relatively simple equipment required.
1 i^'
A
' a
s
/
N S
*
CATHODE
MAGNET
MAXIMUM
EROSION
Fig. 9 Cross section of a planar magnetron. The magnets may be permanent or electromagnets. The anode
is a separate entity, usualh' nearby, and biased positively relative to ground.

360 VLSI Technology
Unlike physical vapor deposition, which suffers from shadowing effects and imper-
fect step coverage, low-pressure CVD can yield conformal film coverage over a wide
range of step profiles, and often yields lower bulk electrical resistivity.
The major effort in depositing metal for ICs by CVD has been in W deposition.
Processes for W deposition have been developed with preferential deposition on sili-
con but not oxide. '^'
The W is attractive because of its low electrical resistivity (5.3
ixll-cm) and its refractory nature. Both pyrolytic and reduction reactions have been
used. For example, WF6 may produce W films by:
WF6 + thermal energy ^ W + 3F2 (19)
or
WFe + 3H2 -> W + 6HF (20)
or
WFg + plasma or optical energy -^ W -I- 3F2 (21)
Temperatures may range from 60 to 800°C in the various reactors. The use of WF^
may cause loss of oxide during deposition, and WCl6 may find application where the
fluoride is not suitable, although the chloride requires higher temperatures.
Figure 10 shows a schematic view of a CVD reactor. The reactor tube is sur-
rounded by a furnace and is considered a "hot wall" system. Using rf induction heat-
ing of a susceptor on which the substrates are positioned and cooling the reactor
vessel walls constitutes a "cold wall" system. Arguments for either system have
been based on efficiency of gas usage and particulate contamination.
In addition to W, other metals such as Mo, Ta, Ti, and Al are of interest for
VLSI applications. Reactions such as^^
800°C
2M0CI5 + 5H2 -^ 2Mo + lOHCl (22)
600°C
2TaCl5 + 5H2 -^ 2Ta + lOHCl (23)
600°C
2TiCl5 + 5H2 -^ 2Ti + lOHCl (24)
and using metal organic compounds such as tri-isobutyl aluminum
150°C
[(CH3)2CH-CH2]3A1 -> t(CH3)2CH-CH2]2AlH
+ (CH3)2C=CH2 (25)
followed by
250°C
[(CH3)2CH-CH2]2A1H ^ Al + hUj
+ 2(CH3)2C=CH2 (26)

Metallization 361
TO EXHAUST
REACTOR
Fig. 10 Highly simplified view of a low-pressure CVD reactor system. To obtain enhanced reactions, the
furnace could be augmented by a plasma source, intense hght source, or other energy source.
are typical. The CVD deposition of Al films suitable for VLSI has yet to be demon-
strated, although the other metals have been successfully deposited. The deposition
of the refractory metal may be a preliminary step in forming the silicide, as demon-
strated by WSii films formed on polysilicon.^-^
9.3 PROBLEMS ENCOUNTERED IN METALLIZATION
Assume that an Al-based metallization is to be used. Questions remain about which
alloy, what method of deposition, and what etching process should be employed. The
answers are not simple since device performance, economics, and reliability will be
factors that must be considered in each case.
9.3.1 Description
Step coverage presents a problem in metallization, because metal is deposited well
into the process sequence. At this point the wafer has already had many steps gen-
erated in it. Metal alloy composition is another problem, because an excess of a con-
stituent may cause device malfunction. A related problem is obtaining a low contact
resistance. Particulates generated within the deposition chamber can severely limit
the yields in the narrow linewidths associated with VLSI. Hillock (small, elevated
areas) formation dependent on alloy composition and thermal history can change the
specular nature of the film reflectivity and introduce difficulties in lithography and
subsequent film coverage. Etching the metal layer has been a problem, because con-
ventional wet etching cannot be used in VLSI. Figure 1 1 schematically shows an

362 VLSI Technology
^RESIST
Fig. 11 Schematic view of a cross section of wet-etched Al beneath a resist mask. The solid profile is the
expected boundary if etching is sufficient just to clear the surface. The broken line is the boundary for an
overetch of 15 to 20%.
example of the results of isotropic etching. Because metal is attacked beneath the
etch mask, compensation must be made for the linewidth lost in transferring the litho-
graphic pattern to the etched metal. As lateral dimensions decrease and lines get
closer together, compensation becomes physically impossible; anisotropic etching of
the metal is therefore necessary.
9.3.2 Solutions
Solutions to the step coverage problem have been approached in several ways. First,
raising the temperature of the substrate during film deposition (~300°C) creates
greater surface mobility of the deposited material, thus reducing the severity of cracks
that exist in comer regions. Next, orientation of the substrate relative to the source
can be optimized.^'*' ^^
Optimization is especially important since shadowing occurs in
the deposition process when using a point source such as an e-beam or an inductively
heated melt. Computer simulation has been useful in modifying the supporting plane-
tary system.
Since most planetary systems do not use rotation of the individual substrate about
its own axis, orientation within the planet is significant in reducing step coverage
problems.^"* Step edges that are parallel to the planet radius are coated symmetrically.
Steps with edges placed perpendicular to the planet radius tend to be coated asym-
metrically, and also tend more to exhibit cracks (Fig. 12).
If small contact windows are to be coated, the course of action may be different
than outlined above. For VLSI, a plane surface may be approximated by depositing
the interlevel dielectric by bias-sputter deposition (see Section 9.2.4) or by using
planarization.^^ Planarization is a low-temperature process that reduces surface
features. A thick resist layer is applied to the dielectric, and a plasma-etch process is
used that attacks the dielectric and the resist at equal rates. To accommodate this pro-
cess a thicker than normal (usually by a factor of 2) intermediate dielectric layer is
needed. The extensive heat treatment that normally would be used to make the
dielectric flow, thus reducing the severity of the step contours, cannot be tolerated in
VLSI where implanted dopants are not permitted to diffuse extensively. Contact-
window step coverage remains a problem even on planar surfaces, because extensive
taper etching of the window edge would consume excessive area.

.— "^
J= ii -c
o
C
'o
a.
1^
1
5 ;/: -
c 11)
"^
H
OJ
3 i
CJJ
OJJ «3
^
O
E
o 5 ^
^ 2 ^
*^ "^ 2
-a ^ § -
c S <u
Q. (L) a
c -S
c -s
a D.
2 o o :S
^ o
= 323
C -o
o o
DU 0)
R X3
15 ^^ a X) ^-
^ y :;5 1?
OX) (u
363

364 VLSI Technology
The use of sources that have larger areas than point sources, such as magnetrons,
reheves many of the step coverage problems. If the substrates are relatively distant
(20 to 30 cm) from the source, such as planetary-mounted wafers, the directionality of
the sputtered metal vapor becomes more random. Randomness occurs because at
pressures of about 0.5 Pa the mean-free path of the Ar atoms is of the order of 1 cm.
Thus the metal vapor incident on the planetary-mounted substrate during magnetron
sputtering is more random in direction than evaporated vapor but the vapor is
"colder" because it transfers energy to the Ar gas. The vapor's lower energy, which
is characteristic of the incident vapor, leads to less movement of the deposited species
on the substrate surface. Decreased movement can limit the grain growth and the
development of ordered (fiber texture) structures. The substrates can be relatively
close and stationary, or they can move slowly before a large-area magnetron. This
proximity to the source permits high deposition rates with material that has undergone
an order of magnitude less travel through the Ar. Significantly more heating of the
substrate can be achieved, resulting in improved step coverage. Sidewall and flat-
surface film thickness ratios ranging from 50 to 100% have been obtained on steps.
In windows this ratio is dependent on the aspect ratio (depth/width).
Alloy films may be deposited by single- or multiple-source evaporation.
Electron-beam evaporation from Al-2% Cu, for example, yields a deposited film of
Al-0.5% Cu. Silicon is usually added by co-evaporation, and thus requires control of
evaporation from more than one source. The degree of control of alloy composition is
critical, because the commonly used postmetallization 450°C sinter of Al alloys can
remove Si by dissolution (see Figs. 13 and 14) from the substrate, if the alloy lacks
sufficient Si. Redeposition of previously dissolved Si in windows occurs upon cool-
ing if excess Si is present. The magnetron sputter sources offer the opportunity to use
complex alloy sources for film deposition. In some early studies all constituents of
commercial alloy targets were found in approximately the same concentration in the
deposited films. The choice of alloy composition may be directed by the need to
preserve a specular, hillock-free surface.
Particulate contamination during the metallization process can create defects.
When the chamber containing the substrates is evacuated the gas flow may be tur-
bulent,^ and particles may be stirred up and deposited on the substrates. This condi-
tion can be minimized by using controlled throttling during the pump down. Also
during venting, when substrates are to be removed, turbulence should be avoided in
the chamber. Moving components which may have previously deposited layers that
can flake are also another source of particulates. System cleanliness and minimizing
film buildup on rolling or sliding surfaces are essential.
VISI requires anisotropic etching of metal layers. Both plasma etching and reac-
tive sputter etching have been developed enough that commercial equipment is avail-
able. Another approach, which may be attractive if an unusual alloy is used, is lift-
off.^^' ^^
In lift-off the inverse pattern is formed by lithography and metal is deposited
on the masked substrate. Then the desired pattern is revealed by lifting the mask and
undesired metal (Fig. 15). The lifting is accomplished by using solvents that attack
the lithographic pattern, thus undercutting the overlayer of metal. When the metal is
deposited through apertures in the lithographic mask, it sits directly on the substrate,

Metallization 365
SiO;
Fig. 13 A schematic view of an Al film contacting a large window (
— 10 x 10 xnr). Note the Al spikes
(pits) in the silicon and the precipitated silicon.
Si PRECIPITATE
Ai SPIKE (PIT)
Fig. 14 A schematic view of a VLSI Al contact to a window (
— 1.5 x 1.5 |xm-). Note that the pit in the
silicon can fill the window and that it may have a thin covering of precipitated silicon.
EVAPORATED
LAYER
MASK
SPUTTERED LAYER
MASK
BREAK
(b)
Fig. 15 Views of lift-off cross sections for (a) evaporated metal and (b) sputtered metal. Note the high-
shadowing features used in evaporation and the undercut masks used in sputtering. These different features
are necessary because the two deposition processes have different step coverages.

366 VLSI Technology
and thus remains after lifting. Unless thermally stable materials are used to form the
mask layer, constraints on substrate temperature during film deposition may be
imposed which would limit the usefulness of the metal layer. The masking layer
should also withstand predeposition cleaning.
As well as being affected by the purity of the source material, the microstructure
and purity of the film deposited in a vacuum chamber may be affected by how the
system is pumped, the base pressure, and the rate of deposition. For example, if a
chamber is evacuated to a base pressure of 10"^ Pa (7.5 x 10"^ torr), the residual
gas (if there are no air leaks) is primarily water vapor. From the kinetic theory of
gases
TV = 6.4 X 10'^ (Tr^-P (27)
where A^ is the bombardment rate of H2O molecules (in cm~^-s~^), T is the absolute
temperature, and P is the pressure in Pa. At T = 300 K and 10~" Pa, A^ is signifi-
cant, because it approximates the rate of arrival of Al at the substrate for a deposition
rate of 50 A/s. Al films normally have less than 50% O content (usually < 0.1%);
thus the probability of the H2O molecule relinquishing the O atom to the metal film is
significantly less than 1. Nevertheless, a low-background pressure prior to initiating
film deposition minimizes incorporation of oxygen.
Similarly, the base pressure prior to sputter deposition should be low. The addi-
tion of Ar, along with any impurities it contains, to the ambient for sputter deposition
also increases the impurity content of the film. The type of pumps used to evacuate
the deposition chamber and the traps are important considerations. Oil contamination
from mechanical and diffusion pumps may be minimized by controlling the pump
down sequence and using cryotraps. Closed-cycle helium cryopumps and turbo-
molecular pumps are frequently used in evaporation and sputter deposition equip-
ment. These pumps are primarily used to avoid oil contamination, and also to reduce
the operating costs incurred by continuous use of liquid nitrogen in cold traps.
^
Of course, the Si substrates should be cleaned before being placed in the metalli-
zation chamber. Most common cleaning techniques involve the use of buffered HF or
HF solutions. These solutions remove thin residual oxides from Si and polycrystalline
Si, as well as remove some oxide from the intermediate dielectric. Surface contam-
inants containing sodium are removed along with the surface layers. Extensive deion-
ized water rinses follow the aggressive cleaning to remove the fluoride. Spin drying
in a warm, dry nitrogen flow removes the water. The substrates are loaded shortly
after drying to avoid recontamination. The small amount of Si02 (^ 20 A) resulting
from the deionized water rinse and exposure to air offers no significant barrier to the
Al metal film when sintering is performed at 300°C and above. No barrier exists
because of the high energy of formation of the AI2O3 (400 kcal/mol)"^^ relative to that
of Si02 (205 kcal/mol).^^ These energy values permit the contacting Al to reduce the
thin Si02 layer.
The quality of the metal films deposited in a system should be checked frequently
by evaluating the C-V characteristics of a gate oxide-type Si02 layer (which comes
from a furnace known to produce clean oxides). These checks should be made if the
system is cleaned, a new source is installed, the system has had questionable test
results, or unusual substrate material has been processed.

Metallization 367
9.4 METALLIZATION FAILURE
As device structures diminish in size, the migration of Al into the Si substrate at con-
tact windows will cause failure. This migration may occur during the fabrication pro-
cess or in subsequent device operation. In addition, migration of Al in the metal lines
during device operation may result in failure through open circuits. As VLSI emerges
the pursuit of solutions to these failure mechanisms is an area of intense activity.
9.4.1 Junction Spiking
Junction spiking is a penetration of a p-n junction interface by a conductive projec-
tion. Although the problem of penetration of the Si substrate by Al "spikes," caused
by the local dissolution of Si, can occur generally in IC processing, the problem is
compounded in VLSI (see Figs. 13 and 14). In VLSI the junctions are shallow, typi-
cally of the order of 0.3 |xm deep, and the contact windows are small. This combina-
tion is formidable since the Si that satisfies the solubility requirements of the Al is
only accessed through small area contacts, which increase the depth of the spike.
The problem of junction spiking may be solved by depositing Al with Si added.
The amount of Si required should be determined by the maximum process tempera-
ture and the Al-Si phase diagram (see Fig. 16). For example, heating the substrate to
450°C should require that the Al contain 0.5 wt. % Si. However, in practice slightly
more than 1 wt. % Si is required. If the Al contacts are all to p"^ Si, this method of
700
600
500
400
300
200
100
05 10 15
At-% Si
Fig. 16 A portion of the Al-Si phase diagram. (After Hansen, Ref. 58.)

368 VLSI Technology
solving the spiking problem is acceptable. However, another problem may be evident
if n"^ Si must be contacted. Because of the excess Si present in the Al, some precipi-
tation of Si occurs in the contact window and will form a nonohmic contact to n^ Si,
because the recrystallized Si precipitate contains Al (which is a p dopant). ^^ Another
method of satisfying the Si requirements of the Al film is to deposit the film on a layer
of polysilicon. The polysilicon may be doped p"^ or n"^ by in-situ or post-deposition
doping. If the polysilicon is deposited by CVD methods, a conformal coating exists
in the windows. The solubility requirements of the Al are satisfied locally since the
polysilicon is present beneath the Al at all points.
A structure that will work equally well for both n^ and p^ contacts is required
An elegant structure involving multiple layers has been proposed. ^° Figure 17 shows
this structure. The bottom layer in the window is a silicide formed by reacting a noble
or near-noble metal with the substrate. Covering the silicide is a barrier layer that
prevents the top layer (Al) from reacting with the silicide. The contact structure may
be formed by depositing a single layer consisting of a mixture of a refractory and a
noble metal. By controlling the deposition temperature and restricting the process
temperature, only the noble metal silicide forms at the contact to the silicon, while
above the contact the remaining film acts as a barrier to the Al layer. The combina-
tion of refractory and noble metals in a single layer makes etching a formidable task
so that lift-off patterning becomes a viable solution to the problem. These combina-
tion structures have been evaluated for Al-Pd go W 20 -Si and Al-Pt loCrgo-Si, and
found to be stable^*^ for normal contact sintering at 450°C.
Another method for forming shallow contacts is to deposit a mixture of metal and
Si such that some Si is consumed in the contact window, although not as much as if
the metal alone were deposited. These structures have been used for Schottky barrier
contacts where Pd-Si and Pt-Si mixtures were deposited and subsequently reacted to
form Pd2Si and PtSi contacts. ^° Similar shallow silicide contacts should be feasible
using other silicide systems for non-Schottky contacts to VLSI structures. Of course,
the need for a barrier on the silicides still exists if reactions with Al are possible.
Epitaxial Si layers in contact windows may be able to supply the needed barrier.
One approach is to use molecular beam epitaxy (MBE), a low-temperature process,
and grow a Si plug in the window. This Si plug would raise the contact interface
away from the junction, and also alleviate metal step coverage at the window.
REFRACTORY- NOBLE METAL
(PSEUDO ALLOY)
Si02
Fig. 17 Idealized cross-sectional view of a barrier-noble silicide contact to silicon.

Metallization 369
Another technique is to use solid phase epitaxy where an upward diffusing silicide
(TiSi2 ) layer^' passes through a covering polysihcon layer and converts it to an epi-
taxial crystalline plug. Again this results in the Al contact being moved away from
the junction.
Diffusion barriers may be considered essential to incorporation of stable contacts
in VLSI structures. In the preceding paragraphs, reference was made to a barrier
layer (refractory metal) on a silicide layer. Such layers are generally polycrystalline
and therefore have different diffusion characteristics than bulk materials have at low
temperature. The rapid diffusion of material through grain boundary regions requires
that impurities be incorporated to passivate the grain boundaries. As an example, Mo
or Ti-W films may be improved by the addition of O or N at levels of 10"-^ wt.% or
less. These are examples of "stuffed barriers, "^^ since they inhibit rapid diffusion
along grain boundaries.
Passive compounds such as nitrides are also attractive as barriers, because they
may be deposited by reactive sputter deposition using metal targets. However,
because of possible reactions between Al and TiN at ~500°C, the use of another layer
such as Ti between the nitride and the Al is necessary if high-temperature processing
will be used.-^-^ Sufficient Ti must be present to satisfy the Al in forming Al3Ti, other-
wise Al will get through the TiN and react with the Si substrate. For structures that
will be heated to 450°C, Ta may be a preferable metal since it too forms a nitride,
TaN. It has been observed that Ta metal between Al and TaN has been found supe-
rior to the Ti-based structure. ^-^
Using one metal to form both the nitride and metal
layer is attractive, because the layers can be deposited sequentially.
Refractory metals deposited directly on the Si exposed in the windows may be
considered. Ta reacts with Si only at temperatures above 6(X)°C, and may form a
Al3Ta layer with Al above 450°C. Provided sufficient Ta is deposited, Al spiking
should be prevented. Sputter-deposited Ti-W (10 to 90 wt.%) has been evaluated as a
barrier layer between Al and Si, as well as between Al and Pt-Si.-^'^ Contacts were
stable after heating to 550°C. The use of the Ti-W beneath the Al caused a 10%
increase in the resistivity, because either Ti or W diffused into the Al layer.^^
9.4.2 Electromigration
A prime consideration in device reliability is the electromigration resistance of the
metallization. Electromigration is observed as a material transport of the conductive
material. It occurs by the transfer of momentum from the electrons, moving under the
influence of the electric field applied along the conductor, to the positive metal ions.^^
Hence, after conductor failure, a void or break in the conductor is observed and
nearby a hillock or other evidence of material accumulation in the direction of the
anode (Figs. 18 and 19) is found.
-^^
Figure 18 shows SEM views of S-Gun sputter-deposited Al-0.5 wt. % Cu and In-
Source-evaporated Al-0.5 wt. % Cu failures. Melting is evident in both cases but
view (b) also clearly displays hillock formation in the direction of the electron flow.
Figure 19 shows an SEM view of failure of e-beam-evaporated Al on polysilicon. In

370 VLSI Technology
(3) (b)
Fig. 18 SEM micrographs of electromigration failure, (a) S-Gun magnetron-deposited Al-0.5 wt. % Cu
and (b) In-Source-evaporated Al-0.5 wt. % Cu. (After Vaidya, Fraser, aiidSinha, Ref. 36.)
view (a) catastrophic melting and balling of the Al is evident. View (b) shows the
area after etching the Al to reveal the polysilicon runners and the Si precipitates. The
arrows indicate the direction of the electron flow.
Electromigration resistance of Al film conductors can be increased by several
techniques. These techniques include alloying with Cu, incorporation of discrete
layers such as Ti, encapsulating the conductor in a dielectric, or incorporating oxygen
during film deposition. ^^ The mean-time-to-failure (MTF) of the conductor can be
related to the current density J in the conductor and an activation energy Q by
MTF ^ J'^ Qxp[Q/kT] (28)
for 10-^ ^ y ^ 2 X 10^ (A/cm-). Experimentally, a value of Q -- 0.5 eV is
obtained, and taken to indicate that low-temperature grain boundary diffusion is the
5 Aim
Fig. 19 SEM view of an electromigration failure of e-beam-evaporated Al on polysilicon. (a) Metal is on
the polysilicon. (b) Al is etched to reveal the polysilicon (After Vaidya. Fraser. andSinlm. Ref. 36.)

Metallization 371
10^
MEDIAN GRAIN SIZE, s(^m)
0.
e 10
5 _
—I
—I
—
r
a10.5%Cu
w = 2 /i.m
T=80°C o
J = Ix IO^A cm-2
I I r
100 1000
_s
rr* '°^
( III)
(200)
Fig. 20 Plot of median conductor lifetimt , t^i^^, versus median grain size of AJ-0.5 wt. % Cu (denoted by
triangles) and t^Qcj^ versus an empirical parameter (denoted by circles). (After Vaidya, Fraser, and Sinha,
Ref. 36.)
primary vehicle of material transport, since Q ~ 1.4 eV would characterize the self-
diffusion of Al in bulk crystalline material. Experiments have also related the MTF to
grain size in the metal film, distribution of grain size, and the degree to which the
conductor exhibits fiber texture ((1 1 1)). Figure 20 shows the relationship between two
parameters and the time for 50% (f 50% ) of the conductors to fail.
36
,//r
(111)/'' (200)
One parameter is
. Here ct^ is a
the median grain size s and the other is 5 / cr^ x lo|
measure of the distribution in grain sizes, /(hd is the intensity of the (1 1 1) reflection,
and 7(200) is the intensity of the (200) reflection obtained from x-ray diffractometer
measurements of the films. The latter parameter is strongly dependent on the method
of film deposition. Figure 21 shows how e-beam-evaporated films have demonstrated
superior lifetimes compared to In-Source and S-Gun magnetron-sputtered films. Infe-
rior lifetimes may be due both to the 2 wt. % Si and to the lower surface mobility of
the incident metal vapor atoms during sputter deposition when the substrates are many
free path lengths from the sputter source (see Section 9.1.4). Sputter deposition is to
be contrasted with an evaporation deposition where the vapor travels in straight lines
to the substrates and loses virtually no energy in transit. A recent discovery, -^^
signifi-
cant to VLSI, is that decreasing linewidth (below 2 |jLm) results in increased MTF for
e-beam-deposited Al-0.5% Cu (Fig. 21).^^ This discovery is related to the fact that
when linewidth shrinks sufficiently, the metal line is composed of single-crystal seg-
ments.

372 VLSI Technology
^8
10^
_ 10
X
o
I-
UJ
uj 10^
10^ Acm-2
80°C
E-GUN Ai-0.57oCu
I 2 34 5 67
LINEWIDTH (^m)
Fig. 21 Median conductor lifetime versus linewidth for Al alloys deposited in three different ways (After
Vaidya, Fraser, andSinha, Ref. 36.)
Attempts have been made to eliminate contact spiking by combining Al metal
films with n^ doped polysilicon. Polysilicon was used for two reasons: first, to pro-
vide Si that satisfies the solubility requirements of the Al, and second to provide a
conformal conductive layer beneath the Al at steps. The first requirement was satis-
fied, but the second requirement was not completely met. Si was found to move in
the Al grain boundaries and failure due to electromigration occurred predominantly at
steps where the evaporated Al was thinned. ^^ Failure rapidly followed the loss of con-
tinuity in the metal film, due to electromigration of the Si resulting in local heating
and melting (see Fig. 19).
Note also that merely using an Al-(l-3%) Si alloy does not necessarily protect
the junctions. ^^ For example, a circuit under test and locally operating below 250°C
will show Si electromigrating within the metal and pits forming at the cathode, while
Si (p^) will be deposited at the anode. Perhaps, the use of refractory layers
sandwiched between Al and the underlying polysilicon would perform the task of iso-
lating the interactive layers while also providing a shunt if the Al were to form an
open circuit.
9.5 SILICIDES FOR GATES AND INTERCONNECTIONS
9.5.1 Application Requirements
The general requirements for gates and interconnects are that the film material have
p < 60 ixH-cm, be stable throughout the remaining process steps, and be reliable.
Refractory metals such as W and Mo and the silicides TiSi2, WSi2, MoSi2, and TaSi2

Metallization 373
10"
10
10" I I I
L
02 0.4 12 4
DESIGN RULE (^m)
10
Fig. 22 RC time constant per unit length for three conductive materials as a function of feature size. Also
shown is delay p»er stage of ring oscillators as a function feature size. (After Sinha, Ref. 47.)
have been proposed and used as MOSFET gate electrode materials either alone or
with doped polysilicon.
"^"'^^
These disilicides are stable in contact with the polysili-
con, and, as will be seen, the presence of the polysilicon helps to stabilize the struc-
tures in oxidizing ambients. However, the metals (notably W and Mo), if used
directly on gate oxides, are not stable in oxidizing ambients.
To appreciate the need for higher-conductivity gate and interconnect materials,
consider the fact that RC delay time is a key factor in VLSI or high-speed circuits
."^^
Figure 22 compares the delay per unit length versus linewidth for polysilicon
(30 n/ c), TaSi2 (1.25 H/r:), and Al (.025 H/n). The conductive layers are as-
sumed to be 1 |jLm thick and sandwiched between two 1.5-|jLm-thick Si02 layers.
These facts imply that for a given maximum tolerable delay, a conductor may be
more than an order of magnitude longer if a silicide is used instead of polysilicon. Of
course, the use of an additional metal layer to interconnect short lengths of polysili-
con is an option, but the added process complexity and cost make it less attractive
than using a single-level conductor.
9.5.2 Deposition Techniques
Silicides may be formed in several ways. A metal film may be deposited on polysili-
con, and the structure sintered to obtain the silicide. (1) The silicide film may be
deposited by co-deposition by sputtering'*'^ or evaporating"*^ simultaneously from
metal and silicon sources either onto oxide or polysilicon; (2) sputtering from a single
source, such as a composite or sintered target, onto oxide or polysilicon; or (3) chemi-
cal vapor deposition (either thermally or plasma enhanced) of the silicide on oxide or
polysilicon. The most widely used techniques have been sputter deposition and
e-beam evaporation. Co-deposition by either process permits control of the ratio of

374 VLSI Technology
e
0<
w^
/-TO
80 -
/
60 -
/
40 /
^^Z^
20
/^ 1
p^r
-0 5 Pa
1 1 1
200 400 600 800
TOTAL POWER INPUT (w)
1000
Fig. 23 S-Gun magnetron deposition rates versus power for Ta and Si. The anode was at +40 V relative to
ground.
metal to Si atoms in the deposited layer. As an example. Fig. 23 shows the sputter
deposition rates for Ta and Si, respectively, in a system equipped with 45-cm plane-
tary and S-Gun magnetrons. Figure 24 shows the symmetric placement of sources for
co-deposition. Because of the stability of the sources, co-deposition may be per-
formed by maintaining each source at a predetermined power dissipation. Electron-
beam evaporation may be performed in a similar manner using two independent
sources. However, co-evaporation is likely to be used less often than co- sputtering in
production, because the desired material constituent ratio is more difficult to maintain
in the deposited film.
9.5.3 Properties
Room temperature resistivities of various silicides"^^ on n^ poly Si are given in Table
2. The lowest resistivity is obtained in TiSi2 formed by sintering a metal layer on
polysilicon and should be contrasted with a value 1 .5 to 2 times larger obtained when
METAL SILICON
Fig. 24 Schematic view of magnetrons and a planetary system for co-sputter deposition. Note the sym-
metric placement of the sources, which is necessary to get uniform films.

Metallization 375
Table 2 Silicide resistivities (300 K)
Material Starting form Resistivity dJuH-cm)
TiSi2 Metal/polysilicon
Co-sputtered
13-16
25
ZrSij Metal/polysilicon 35-40
HfSij Metal/polysilicon 45-50
TaSi2 Metal/polysilicon
Co-sputtered
35-45
50-55
MoSij Co-sputtered 100
WSi2 Co-sputtered 70
CoSi2 Metal/polysilicon
Co-sputtered
17-20
25
NiSi2 Metal/polysilicon
Co-sputtered
50
50-60
PtSi Metal/polysilicon 28-35
Pd2Si Metal/polysilicon 30-35
TiSi2 is obtained by co-sputter deposition. This difference is believed to be due to
electron mobility, which may be higher in the silicide formed by sintering the metal
since larger crystals of the silicide are obtained. Figure 25 shows that the reflectivity
from the silicide surface formed by reacting the metal with polysilicon is quite dif-
fuse. Such films are difficult to work with in photolithography and may even disturb
automatic alignment devices. In contrast the co-deposited film reflectivity is more
like that of a metal, and the film merely replicates the underlying polysilicon surface.
Resistivity and reflectivity, however, are not the only parameters that determine
which silicide to use. The stability of the desired phase can be extremely significant.
For example, the existence of eutectics would limit the maximum temperature of the
silicide in contact with Si. Thus, Pd2Si is limited to about 7(X)°C, PtSi to about
SOOT, and NiSis to about 900°C. The other silicides in Table 2 should be stable to
temperatures above 1000°C. Stability in an oxidizing ambient is also important.
Stress, because of its magnitude, is a significant parameter in silicide layers
formed on Si wafers. To a first approximation, the source of the tensile stress
observed in sintered silicide layers appears to be caused by the net volume loss occur-
ring when the volumes of the metal and the Si are combined to form the silicide.
However, temperature-dependent measurements of stress have shown that the tensile
stress in TaSi2 decreases as temperature is increased and that the coefficient of ther-
mal expansion of TaSi2 is approximately 9 x 10~^/C°, while that of Si is approxi-
mately 3 X 0~^/C°^'^ The major portion of the room temperature stress is due to
thermal expansion differences and the relatively high temperature at which the silicide
is formed by sintering. The stress levels may be reduced in the silicides by forming
them at lower temperatures through the introduction of other sources of energy. The

376 VLSI Technology
00 -
^
90 /^ METAL ON Si02
80 - /
/
-
/
70 /y^
//SINTERED COSPUTTERED TaSig
60 -
y ON POLYS 1 LI CON
50
^
40 —
30 ^^^
20 - /""^
10 - /Wintered to on polysilicon
^-^- 1 1 1 1 1
2000 3000 4000 5000 6000 7000 8000 9000
WAVELENGTH (A)
Fig. 25 Reflectivity of three surfaces versus wavelength. Note the low reflectivity of the bottom curve.
significance of stress may be appreciated by examining Fig. 26, where the room tem-
perature stress of a 25(X)-A co- sputter-deposited TaSi^ film is shown as a function of
various MOS process steps. Should the value of stress rise appreciably above ~ 2 x
10^° dyn/cm^, the adherence of the layer would be uncertain and the useful thickness
would also be limited. The preceding discussion illustrates the need for a silicide
layer compatible with the process sequence.
Similarly, Fig. 26 shows the variation in the room temperature sheet resistance of
the same (stress) specimen measured by a four-point probe as a function of the same
process steps. In addition, the silicide may be exposed to chemicals, such as
NH4F/HF solutions that attack silicides. Thus TiSi2 is attractive because of its resis-
tivity, but unattractive because of its susceptibility to attack by HF solutions.
The next requirement is the determination of the work function i^^ of the MOS
electrode material by obtaining ^y^ (= ^m ~ 4>si). where (j)si
~ 4.35 V. The
value of (j)Ms is obtained by making a series of capacitance measurements on oxides
of different thickness and plotting the flatband voltage VpB versus oxide thickness.
^FB - 4>MS
Q/+e,.+eot
c
(29)
where Qj is the fixed charge per unit area, Q,„ is the mobile charge (e.g., Na"^) per
unit area, Qot is the trapped charge per unit area in the oxide, and C is the capaci-
tance. To keep the parameters in the second term common to all the capacitors, a
thick oxide is grown and selectively etched to provide four or more dielectric
thicknesses. With these different thicknesses, one substrate may yield four or more

Metallization 377
10
h

-

2 -
AS DEPOSITED 2500A TaSi2/n* POLY
r
/
^/
/
^

I 4
12
10 </)
08
06
PROCESS STEPS
Fig. 26 Room temperature stress and sheet resistance of TaSii on polysilicon as a function of process steps.
experimental values. As an example the plots for TiSi2/n"^ polysilicon, TaSi2/n"^
polysilicon, and Al/n^ polysilicon are shown in Fig. 21 ^^ The values of ^^ for the
two silicides are 3.30 ± 0.05 V and are very similar to <)m for Al/n"^ polysilicon,
which is 3.25 V. Should the values for the silicides differ from the "standard" Al/n"^
polysilicon, modifications would have to be made in a process sequence (e.g.,
implants to adjust threshold voltage) to incorporate the silicides and still have device
parameters meet specifications.
Also test capacitors must be subjected to temperature-voltage bias stressing in
order to evaluate the stability of the capacitors. Since many of the metals used to
form silicides are not as free from impurities as polysilicon, mobile charge and slow
trapping should be monitored. This is conveniently done by making test capacitors
that have been subjected to the full range of the process sequence. Figure 28 shows
an example of such a test capacitor
.'^^
In this case a TaSi2 / n"^ polysilicon electrode on
a 526-A-thick oxide. The tests involved ± 10 V bias at 250°C which did not shift the
C-V curve and is indicative of no Q,„ contamination. The C-V curve also gives a
fixed charge of Qy^ = 2 x 10'°/ cm"^ which is acceptable.
The refractory metals may exhibit oxidation at lower temperatures than their sili-
cides do. The formation of volatile oxides such as occur with W or Mo can lead to a
reaction that ruptures the film. In Fig. 29 films of co-sputtered W-Si and WSi2 depos-
ited directly on oxide are shown after exposure to air at 1000°C.'^^ However, if addi-
tional Si is available, such as in an underlying layer of polysilicon, the oxidation of

378 VLSI Technology
-06
*TiSi2/n*P0LYSILIC0N
• TOSia/n^POLYSILICON
oA£/rTPOLYSILICON
200 400 600 800 1000
OXIDE THICKNESS (A)
1200
Fig. 27 Platband voltage versus oxide thickness for three electrodes. (After Sinha. Ref. 47.)
o LO

o
UJ
o OR
^
<
h-
o
<
Q.
0.6
<
U
Q
UJ
M 0.4
_l
<
S
cr 0?
o
TaSi2/n*POLY/Si02/P(IOO)Si
tox=526A
N;^ = l.8xl0'^cnn-2
Qf = 2xl0'°cm-2
Vt(CALC)=0.83V
(a )AS- RECEIVED
(b)AFTER±IOV,250°C
ISmin
J L
-4 2
BIAS (v;
Fig. 28 C-V measurements of TaSi2/n+ polysilicon test capacitors on a fully processed device wafer.
(After Sinha, Ref. 47.)

Metallization 379
PEST REACTION UPON AIR OXIDATION
Fig. 29 SEM views of adherence failure of co-sputtered (a) W-Si and (b) WSi2 films deposited on oxidized
silicon. (After Sinha, Ref. 47.)
the WSi2/polysilicon structure proceeds by the diffusion of Si to the silicide surface
to form Si02. This diffusion of Si leaves the sihcide layer intact until the polysilicon
has been consumed. The same process has been observed for TaSi2/ polysilicon and
is demonstrated by the change in resistance of such a layer through steam oxidation.
^°
The stress of the TaSi2 did not change until the polysilicon had been consumed. The
(covering) Si02 that results from oxidizing a silicide/polysilicon structure is not
expected to be very different from the oxide found on polysilicon, and this has been
observed for TaSi2/n"^ polysilicon^^ and WSi2/n"^ polysilicon.'^ For structures
involving more than one layer of silicide/n"*^ polysilicon the oxide isolation should be
similar to that obtained with multilevel polysilicon structures.
9.5.4 Device Performance
Various integrated circuits, both CMOS and NMOS, have been made from refractory
gate materials other than polysilicon. The only reported discrepancies have been
between TaSi2/n'^ polysilicon and n"^ polysilicon controls in CMOS enhancement
mode transistors, where the threshold voltages Vj differed by 0.3 V for the n- and
p-channel devices, respectively.^' Also, the use of MoSi2 directly on gate oxide leads
to a work function difference of 0.5 V compared to n"^ polysilicon.^^ Increases in cir-
cuit operational speed have been observed where high-conductivity gates have been
used both in normal silicon and silicon-on-sapphire devices.^^ Compatibility with
existing processing has been demonstrated. The requirements for gate and intercon-
nect level sheet resistances of less than 3 O / c can be met by the silicide/polysilicon
structures presendy used.
Where will the future devices lead technology? The use of shallow junctions of
approximately 0.1-jxm depth (e.g., in the source and drain areas) will require the use

380 VLSI Technology
of a conductive film to reduce the sheet resistance of about 100 O/c by an order of
magnitude. A method to accomplish this reduction has already been demonstrated in
an MOS structure utilizing PtSi Schottky contacts in the source and drain areas.
'''^
The
use of materials other than PtSi and high doping in the substrate leads to low-
resistance (non-Schottky) contacts. Lower processing temperatures and the possible
use of presently unsuitable materials will be required, along with the shallow junc-
tions. The use of other refractory materials is possible as well, since the resistivity of
TiB2 has been reported to be about 10 [xfl-cm.^^
Incorporation of a silicide layer at the gate and interconnect level also raises the
question of stability of the primary metallization (Al) contact to the silicide. The
major concern of course is the extent of the reaction that may occur in sintering the Al
(450°C for e-beam and 300°C for Al deposition processes without ionizing radiation).
Al can apparendy penetrate TaSi2.2 when heated to 500°C for 60 minutes. This may
be due to precipitated excess Si in the TaSio.i film acting as a soluble defect, and
opening the layer beneath to the Al. However, no test device failure could be related
to a failure of the Al-TaSiT contact when sintering was performed at 450°C for 30
min. In NMOS structures, if a layer of n"^ polysilicon is deposited over the windows
under the Al, no interaction between the Al and the TaSio occurs for sintering at
450°C. Al has been found to interact with PtSi, Pd2 Si, CoSi2, and MoSi2, and then
penetrate into the underlying Si substrate when sinter temperatures range from 200 to
550°C.
9.6 CORROSION AND BONDING
Once the device structure has been completed, a passivation layer may be applied
over the final metal layer. Leads which connect the chip to the outside world are
bonded to the metal through windows etched in the passivating film. The layer used
for passivation may be a low-temperature phosphosilicate glass, a plasma CVD
dielectric (either oxide or nitride), a spin-on layer of glass-containing suspension, or a
spin-on organic layer. In general, the passivating layer protects the metal pattern
from being scratched during handling prior to bonding.
The bonding wires may be either Al-1% Si or Au. With Al alloy wire bonds,
failure may occur in the wire just beyond the bond, due to thinning or fracture. Gold
wire bonds can be made easily, because of the ductility of the wire; however,
intermetallics may form and weaken the structure. The so-called "purple plague,"
AuAl2, is an indication of intermetallic formation.^^ To prevent formation of the
intermetallic, the length of time that the Au and Al alloy are in contact at high tem-
perature must be carefully controlled.
Metallization corrodes significandy in a high-humidity environment.^^ One
approach is to utilize hermetically sealed packages that can prevent the corrosion. If
the structures are not sealed, then residuals, such as CI that may be present after
plasma or reactive sputter etching, react with moisture to attack the Al, even without
an imposed electric field
Al + 3HC1 -^ AICI3 + ^2 (30)
AICI3 + 3H2O -^ A1(0H)3 + 3HC1 (31)

Metallization 381
Note that the CI is not bound after the A1(0H)3 is formed, leading to further attack of
exposed Al. The problem is compounded by placing metal lines close together and
imposing an electric field between them, such as would occur in VLSI structures.
Passivation by removing residual CI is common in most Al dry-etching processes.
This residual CI may be removed by a CF4-O2 or O2 plasma treatment immediately
after etching and before exposing the wafers to the atmosphere. Further stability may
be gained by thermally oxidizing the metal. ^^ Excessive P in phosphosilicate glass
may cause formation of HPO3 on the dielectric surface, which may in turn lead to
attack of the Al alloy structure. Maintaining a maximum of 6% P content in the
dielectric minimizes this source of corrosion. Corrosive environments where the
reactants are present in the atmosphere require not only cleaning, but passivation and
encapsulation.
9.7 FUTURE TRENDS
Multi-level metallization may be necessary in order to keep VLSI chip areas to a size
compatible with reasonable yield. Cross-unders in the bulk silicon substrate may be
possible by using epitaxially grown silicon on high-conductivity silicides. These
buried high-conductivity patterns may be an alternative to additional metal layers
above the substrate surface. With the use of lower processing temperatures will come
the use of materials currently not considered (i.e., materials that are thermodynami-
cally unstable in present process sequences), such as PtSi. A major stumbling block
to an all-low-temperature process is the required high-temperature treatment to getter
impurities during the final stages of the process. Photochemical deposition may be
useful in maintaining low-temperature processing. Increased use of thermal CVD
techniques is also likely, since the more conformal nature of the films is attractive in
metal step coverage. Development of a conductor plug to remove the metal step cov-
erage problem at contact windows is another possibility. Much of the burden for
achieving practical VLSI technologies will fall on metallization, and, for the foresee-
able future, metallization will remain an active area for the introduction of new
materials and processes.
REFERENCES
[1] J. L. Vossen, Ed., Bibliography on Metallization Materials and Techniques for Silicon Devices, Thin
Film Division, American Vacuum Society, New York, 1974-1982.
[2] M. P. Lepselter, "Beam Lead Technology," Proc. Second Symposium on the Deposition of Thin
Films by Sputtering, University of Rochester, June 1967, p. 48.
[3] W. D. Ryden and E. F. Labuda, "A Metallization Providing Two Levels of Interconnect for Beam-
Leaded Silicon Integrated Circuits," IEEE J. Solid-State Circuits, SC-12, 376 (1977).
[4] S. M. Sze, Physics of Semiconductor Devices , 2d ed.. Wiley, New York, 1981, p. 304.
[5] J. F. O'Hanlon, A User's Guide to Vacuum Technology, Wiley, New York, 1980.
[6] A. S. Grove, Physics and Technology of Semiconductor Devices, Wiley, New York, 1967.
[7] R. Glang, "Vacuum Evaporation," in L. I. Maissel and R. Glang, Eds. , Handbook of Thin Film Tech-
nology, McGraw-Hill, New York, 1970, Chapter 1, p. 1-107.
[8] S. Dushman, Scientific Foundations of Vacuum Technique, Wiley New York, 1962, p. 21
.

382 VLSI Technology
[9] R. Glang, "Vacuum Evaporation," in L. I. Maissel and R. Glang, Eds., Handbook of Thin Film Tech-
[10] R. Glang, "Vacuum Evaporation," in L. I. Maissel and R. Glang, Eds., Handbook of Thin Film Tech-
[11] J. L. Vossen and J. J. Cuomo, "Glow Discharge Sputter Deposition," in J. L. Vossen and W. Kern,
Eds., Thin Film Processes, Academic, New York, 1978, p. 12.
[12] J. A. Thornton and A. S. Penfold, "Cylindrical Magnetron Sputtering," in J. L. Vossen and W. Kern,
[13] D. B. Eraser, "The Sputter and S-Gun Magnetrons," in J. L. Vossen and W. Kern, Eds., Thin Film
Processes, Academic, New York, 1978, p. 115.
[14] R. K. Waits, "Planar Magnetron Sputtering," in J. L. Vossen and W. Kern, Eds., Thin Film
Processes, Academic, New York, 1978, p. 131.
[15] J. M. E. Harper, "Ion Beam Deposition," in J. L. Vossen and W. Kern, Eds., Thin Film Processes,
Academic, New York, 1978, p. 175.
[16] C. M. Melliar Smith and C. J. Mogab, "Plasma Assisted Etching Techniques for Pattern Delinea-
tion," in J. L. Vossen and W. Kem, Eds., Thin Film Processes, Academic, New York, 1978, p. 497.
[17] J. L. Vossen and J. J. Cuomo, "Glow Discharge Sputter Deposition," in J. L. Vossen and W. Kem,
[18] T. N. Kennedy, "Sputtered Insulator Film Contouring over Substrate Topography" , J. Vac. Sci. Tech-
nol.,13, 1135(1976).
[19] W. Kem and V. S. Ban, "Chemical Vapor Deposition of Inorganic Thin Fikns," in J. L. Vossen and
W. Kem, Eds., Thin Film Processes, Academic, New York, 1978, p. 258.
[20] A. C. Adams, Chapter 3, this volume.
[21] J. M. Shaw and J. A. Amick "Vapor Deposited Tungsten For Devices," RCA Review, 31, 306
(1970).
[22] C. F. Powell, "Chemically Deposited Metals," in C. F. Powell, J. H. Oxley, and J. M. Blocher,
Eds., Vapor Deposition, Wiley, New York, 1966, p. 277.
[23] N. E. Miller and I. Beinglass, "Hot-Wall CVD Tungsten for VLSI," Solid State TechnoL, 23, 79
(1980).
[24] I. A. Blech, D. B. Eraser, and S. E. Haszko, "Optimization of Al Step Coverage Through Computer
Simulation and Scanning Electron Microscopy," J. Vac. Sci. TechnoL, 15, 13 (1978); Errata, J. Vac.
Sci. TechnoL, 15, 1856(1978).
[25] W. Fichtner, Chapter 10, this volume.
[26] A. C. Adams, "Plasma Planarization," Solid State TechnoL, 24, 178 (1981).
[27] T. Sakurai and T. Serikawa, "Lift-Off Metallization of Sputtered Al Alloy Fihns," J. Electrochem.
Soc.,126, 1257(1979).
[28] T. Batchelder, "A Simple Metal Lift-Off Process," Solid State TechnoL, 25, 1 1 1 (1982).
[29] Handbook of Chemistry and Physics, Chemical Rubber Co., Cleveland, 1970.
[30] K. N. Tu, "Shallow And Parallel Silicide Contacts," J. Vac. Sci. TechnoL, 19, 766 (1981).
[31] A. K. Sinha, W. S. Lindenberger, D. B. Eraser, S. P. Murarka, and E. N. Fuls, "MOS Capability of
High Conductivity TaSij/n^ Poly Si Gate MOSFET", IEEE Trans. Electron Devices, ED-27, 1425
(1980).
[32] M.-A. Nicolet and M. Bartur, "Diffusion Barriers in Layered Contact Stmctures," J. Vac. Sci. Tech-
noL, 19, 186(1981)
[33] M. Wittmer, "High-Temperature Contact Stmctures for Silicon Semiconductor Devices," v^p/. Phys.
Lett., 37, 540(1980).
[34] P. B. Ghate, J. C. Blair, C. R. Fuller, andG. E. McGuire, "AppHcationofTiiW Barrier Metallization
For Integrated Circuits," Thin Solid Films, 53, 117(1978).
[35] J. Black, "Physics of Electromigration," Proc. 12th Reliability Physics Symposium, IEEE, New
York, 1974, p. 142.
[36] S. Vaidya, D. B. Eraser, and A. K. Sinha, "Electromigration Resistance of Fine Line Al," Proc. 18th
Reliability Physics Symposium, IEEE, New York, 1980, p. 165.
[37] A. Gangulee, P. S. Ho, and K. N. Tu, Eds., Low Temperature Diffusion and Application to Thin
Films, Elsevier, New York, 1975.

Metallization 383
[38] S. Vaidya, "Electromigration in Aluminum/Poly-silicon Composites," Appl. Phys. Lett., 39, 900
(1981).
[39] P. B. Ghate, J. C. Blair, and C. R. Fuller, "Metallization In Microelectronics," Thin Solid Films, 45,
69(1977).
[40] R. C. Henderson, R. F. W. Pease, A. M. Voschenkov, R. P. Helm, and R. Wadsack, "A High Speed
P-channel Random Access 1024 Bit Memory Made with Electron Lithography," IEEE Solid-State Cir-
cuits, SC-10, 92 (1915).
[41] D. M. Brown, W. E. Engler, M. Garfinkel, and P. V. Gray, "Self-Registered Molybdenum-Gate
MOSFET," J. Electrochem. Soc, 115, 874 (1966).
[42] S. P. Murarka and D. B. Eraser, "Silicide Formation in Thin Cosputtered (Titanium + Silicon) Fihns
on Polycrystalline Silicon and Si04," J. Appl. Phys., 51, 350 (1980).
[43] K. L. Wong, T. C. HoUoway, R. F. Pinizotto, Z. P. Sobczak, W. R. Hunter, and A. F. Tasch, "Com-
posite TiSi2/« ^ Poly-Si Low Resistivity Gate Electrode and Interconnect for VLSI Device Technol-
ogy," IEEE Trans. Electron Devices. ED-29, 547 ( 1982).
[44] B. L. Crowder and S. Zirinsky, "l-jjim MOSFET VLSI Technology: Part VH-Metal Silicide Inter-
connection Technology—A Future Perspective," IEEE J. Solid State Circuits, SC-14, 291 (1979).
[45] T. Mochizuki, K. Shibata, T. Inoue, and K. Ohuchi, "A New MOS Process Using MoSi2 As A Gate
Material," yp«. J. Appl. Phys., 77 (suppl. 17-1) 37 (1977).
[46] S. P. Murarka, D. B. Eraser, A. K. Sinha, and H. J. Levinstein, "Refractory Silicides of Titanium and
Tantalum for Low Resistivity Gates and Interconnects," IEEE Trans. Electron Devices, ED-27, 1409
(1980).
[47] A. K. Sinha, "Refractory Metal Silicides for VLSI Applications," J. Vac. Sci. Technol., 19, 778
(1981).
[48] S. P. Murarka, "Refractory Silicides for Integrated Circuits," J. Vac. Sci. Technol., 17, 775 (1980).
[49] T. F. Retajczyk and A. K. Sinha, '
Elastic Stiffness and Thermal Expansion Coefficients of Various
Refractory Silicides and Silicon Nitride Films," Thin Solid Films, 70, 241 (1980).
[50] S. P. Murarka, D. B. Eraser, W. S. Lindenberger, and A. K. Sinha, "Oxidation of Tantalum Disili-
cide on Polycrystalline Silicon," 7. Appl. Phys., 51, 3241 (1980).
[51] D. B. Eraser, S. P. Murarka, A. R. Tretola, and A. K. Sinha, "Tantalum Silicide/Polycrystalline
Silicon-High Conductivity Gates for CMOS LSI Applications," J. Vac. Sci. Technol., 18, 345 ( 1981).
[52] T. Mochizuki, T. Tsujimaru. M. Kashiwagi, and Y. Nishi, "Film Properties of MoSi2 and Their
Application to Self-Aligned MoSi2 Gate MOSFET," IEEE Trans. Electron Devices, ED-27, 1431
(1980).
[53] B. C. Leung and J. S. Maa, "Refractory Metal Sihcide/N+ Polysilicon in CMOS/SOS," Tech. Digest
Int. Elect., Sn{l9Sl).
[54] C. J. Koeneke, S. M. Sze, R. M. Levin, and E. Kinsbron, "Schottky MOSFET for VLSI," paper
15.6, IEEE Electron Device Meeting, Washington, D. C, Dec. 1981.
[55] R. Kieffer and F. Benesovsky, Hartstojfe, Springer, Vienna, 1963.
[56] D.-Y. Shih and P. J. Ficabora, "The Reduction of Au-Al IntermetaUic Formation and Electromigra-
tion in Hydrogen Environments," IEEE Trans. Electron Devices, ED-26, 27 (1979).
[57] J. M. Eldridge, "Corrosion Problems of Metal Conductor Lines in Integrated Circuits," Solid State
Devices, Inst. Phys. Conf. Ser. No. 57, 1980, p. 211.
[58] M. Hansen, Constitution ofBinary Alloys, McGraw-Hill, New York, 1958.
PROBLEMS
1 If the residual water vapor pressure is 5 x 10~^ Pa in an Al evaporation station at 300 K, what O content
does a deposited film have if Al is deposited at 50 A /s? Assume the reaction results in incorporating AI2 O3
in the film and that each Ht O molecule has a reaction probability 10"''.
2 Assume thai you have no way of co-depositing Al-Si while maintaining the compositional ratio
throughout the film thickness. However, individual discrete films may be deposited with accurate thickness.
A sandwich of 1 [jtm of Al on a Si film must be deposited on a Si contact. It must be stable so that sintering

384 VLSI Technology
at 450°C can be performed without attacking the substrate. Assuming equilibrium, how thick must the Si
layer be?
3 Pulsed currents of density 10^ A/cm- must be passed by a metal sihcide-to-semiconductor ohmic contact
((j)5
~ 0.4 V) in the emission range (light doping). What voltage drop is associated with the contact?
4 Metallization requires an electromigration-resistant Al conductor that must make contact through small-
diameter (~1 .25-(xm) windows. Which film deposition method would you choose? Give reasons for your
choice.
5 A MOS test capacitor is formed by depositing e-beam-evaporated Al on an oxidized silicon wafer and pat-
terning the metal film. The flatband voltage of the capacitor is shifted by 1 V relative to a measured value
obtained before a 450°C hydrogen heat treatment. What causes the shift (see Eq. 29)? If the Al severely
penetrates the silicon at 450°C, what altematives might be used?
6 In the preceding problem what charge will correspond to the voltage shift if the capacitor is formed on a
l(XX)-A-thick oxide? How can the shift be attributed to radiation-induced changes in the oxide rather than to
other sources?
7 A circuit's design requires a maximum permissible current density of 5 x 10^ A/cm^ through a conduc-
tor 1 mm long, l|xm wide, and nominally 0.5 (xm thick. Assume that 10% of the conductor length passes
over steps and is 50% of the nominal metal film thickness. What maximum voltage may be used across the
conductor if the sheet resistance is 5.6 x 10~^ n/n? (Neglecting the thinner cross sections at steps can
lead to reliability problems.)
8 Given the various Al film parameters that influence the electromigration resistance of Al conductors,
describe how you would deposit Al films to ensure a maximum service lifetime. How would you test such
films?

CHAPTER
TEN
PROCESS SIMULATION
W. nCHTNER
10.1 INTRODUCTION
Numerical simulation has emerged recently as an important aid to process and device
developments. In fact, process and device simulations are now as common as circuit
simulation for two major reasons: Computer simulations are less expensive and much
faster than experimental approaches. For example, suppose a semiconductor
manufacturer plans to develop a new CMOS process with 1.5-|jLm design rules. This
new process may involve nine lithography steps, six ion implantations, and several
diffusion, annealing, and oxidation steps. Using available software and a medium-
size computer (e.g., VAX"*" 11/780), one can simulate all critical process steps (e.g.,
channel-stop condition, threshold adjustment, etc.) in a matter of minutes or hours. A
real experiment, on the other hand, usually takes from several days to a few weeks.
By using computer simulations, we can save enough time to obtain results on process
sensitivity by also modeling variations on the process. Figure 1 summarizes process
and device simulation steps that will be treated in this chapter. For VLSI devices and
circuits, process conditions are tightly coupled to the performance of finished devices.
Therefore, process simulation cannot be a stand-alone field but has to be closely cou-
pled to device simulation. Device design is only possible when both fields are con-
sidered together.
10.2 EPITAXY
This section describes a model that simulates epitaxial doping profiles in a variety of
growth conditions. '
"*
*Trademark of Digital Equipment Corporation.
385

386 VLSI Technology
Process Simulation
Epitaxy + crystal growth (10.2)
Diffusion (10.4)
Pattern definition (lithography 10.5)
Deposition (10.6.3)
Ion implantation (10.3)
Oxidation (10.4)
Pattern transfer (Etching 10.6.2)
Device Simulation (10.7)
Intrinsic behavior of the active device (dc, ac, time)
Parasitic components (R,C)
Current — Voltage characteristics
Fig. 1 Schematic showing the coupling between process and device simulation.
10.2.1 Epitaxial Doping Model
In this model arsine (ASH3) is the doping species considered and silane (SiH^) is used
to grow silicon in a hydrogen ambient in an atmospheric pressure reactor. Pick's
second law is applied throughout the silicon to account for the thermal redistribution
of impurities during epitaxial growth.-'' Thus,
dCjzj)
dt dz
D dC_
dz
^ > z > z
f (1)
has to be solved in a region as shown in Fig. 2. C is the dopant concentration in the
silicon, D is the diffusion coefficient, and z and t are the space and time variables,
respectively.
The solution of Eq. 1 must satisfy the following initial and boundary conditions:
D
D
dz
C(z,0) =/i(z)
=
dC
dz
flit)
(2)
(3)
(4)
where /i(z) represents the impurity diffusion just before the epitaxial deposition, and
Eq. 3 states that the flux of impurities deep inside the silicon is zero. Equation 4
accounts for the fact that, during epitaxial growth, the diffusion flux of impurities in
the solid at the gas-solid interface is a function of time. An expression for/2(r ) can
be derived from a mathematical description of the mechanisms that control the incor-
poration of the impurities into the silicon host lattice during the growth process.
Figure 9 in Chap. 2 shows schematically the step sequences that occur in the gas
phase of an epitaxial reactor. Three main sequences are indicated in the figure:

Process Slviulation 387
Z=Zf
Z = CD
GAS PHASE
--
.^ EPI LAYER
C (z. )
/ SUBSTRATE
Fig. 2 Schematic cross section of a silicon wafer for the purpose of solving Pick's second law. {After Reif
atulDutton. Ref.3.)
Step 1 . Forced-connection mass transport of AS2H3 from the reactor tube entrance to
the deposition region.
Step 2. Boundary-layer mass transport of AS2H3 from the well-mixed main gas stream
through the boundar>' layer to the surface.
Step 3. Dissociation of AS2H3 through gas-phase chemical reactions into several As
containing species.
The description of mechanisms at the growing surface is based on the terrace-
ledge-kink model^ which divides the surface into adsorption (or terrace) sites, step (or
ledge) sites, and kink sites. Figure 9 in Chapter 2 also illustrates the sequence of
steps occurring at the surface.
Step 4. Adsorption of the As-containing species at a terrace site on the growing
surface.
Step 5. Chemical dissociation into As and H in the adsorbed layer. Different species
(ASH3, As, H, etc.) occupy terrace sites and are able to move at the surface.
Step 6. Surface diffusion and incorporation of adsorbed As at step and kink sites.
Step 7. The incorporated As is buried by subsequently arriving Si atoms during epi-
taxial growth.
Step 8. Desorption of hydrogen from the surface.
Based on this step sequence. Eq. 4 can be written as^^
D
dC
dz
= flit) = - k^f
pO Cizf)
K,
+ gCizf) + Ka
p
dCjZf)
dt
(5)

388 VLSI Technology
The first term describes the flux of dopant species leaving the boundary layer by
adsorbing at the surface (steps 4 through 6). The variable k,nf is a kinetic coefficient
associated with the mechanism dominating the dopant-incorporation process. P^ is
the input partial pressure, C (zy) is the dopant concentration at the interface, and Kp is
a segregation coefficient relating the epitaxial dopant concentration to the concentra-
tion of dopant species in the gas phase. The second term gC (Zf) represents the rate at
which the adsorbed layer decreases its concentration of dopant species due to the sili-
con covering step (step 7). The last term represents diffusion of dopant atoms
between the adsorbed layer and the bulk silicon. The variable K^ relates the epitaxial
dopant concentration to the concentration of the dopant species in the adsorbed layer.
Pick's second law (Eq. 1) can now be solved subject to the boundary and initial
conditions, specified in Eqs. 2 to 5.
10.2.2 Computer Implementation and Results
Figure 3 shows schematically a finite difference discretization of the simulation
region. The silicon region is partitioned into discrete spatial cells with a constant
dopant concentration within each cell [that is, C = Q + i
for (z, + Z/ + i)/2
^z ^ (z,+i + z,+2)/2].
At the initial time t = 0, the doping profile is given by Eq. 2. The simulation
starts by adding a new cell z, _i (Fig. 3b). The dopant concentration C, _i of this new
cell is computed from Eq. 5 by setting the left-hand side to zero
= k^f P -gC,_i-^^-^^ (6)
This equation accounts only for dopant introduction into the added cell and neglects
the simultaneous impurity redistribution in the silicon. Now we calculate the impur-
ity redistribution that occurs during the growth of all z, _| cells by solving Fick's law
(Eq. 1). This is illustrated in Fig. 3c. No flux of impurities enters the silicon at this
time. This concludes the calculation at one time step Ar, and we arrive at
t = f + ^ ^ where we start the cycle over until the total epitaxial deposition time is
over.
Figure 4 compares a doping profile simulated by using this model with a profile
measured by the spreading resistance technique. For the comparison shown in the fig-
ure, two consecutive independent arsenic-doped epitaxial films were deposited as
indicated in the inset. The arsine flows corresponding to the first and second layers
were adjusted to produce epitaxial doping levels of approximately lO''' and
10^^ cm"-', respectively.
Between the end of the first deposition cycle and the beginning of the second, the
reactor was purged with H2 for 8 min at 1050°C. The transition between the high and
low doping levels is typical if a lightly doped layer is grown epitaxially on top of a
heavily doped substrate or buried layer. This transition is at first abrupt and then
becomes gradual. This graded transition is a result of the autodoping phenomenon.

Process Simulation 389
^'l 1 1
Pd
1
|C|_,
c,
II 1+2
1
1 1 1 1 1 1
1
1
1
Li_
'i-l
1
1
'
ri+2l
1 1 1 1 1
'i ^i+l *l+2
z
'i 'i+l 'i+2
z
(a) (b)
I
I
I
Ci-il
ill
I r*~n+2p'
I 1 I I I
^l-l 'l 'l+l ^1+2
(c)
I
I
! I
I
I
I I I I I
'i+2
'l-l 'l 'i+1 ^1+2
(d)
Fig. 3 Implementation of the numerical technique used to solve Pick's second law with the surface boun-
dary condition dictated by the epitaxial deposition process. (After Reif and Button, Ref. 3.)
10"
^I0'«
10"
10
n—I
—I
—I
—I
—I
—I
—I
—I
—I
—I
—I
—1
—
r
n—I
—I
—I
—
r
SIMULATED
••••MEASURED
u
EPI LAYER 2-
r
EPI LAYER! —-SUBS-
DOPANT
GAS
FLOW
.15 15 TIME (MIN)
_l I I I I I I I I I I I I I I I I I I 1 1 1 1 1 L.
0.0 2.0 4.0 6.0 8.0
DEPTH (^m)
10.0 12.0
Fig. 4 Measured and simulated doping profiles corresponding to two consecutive epitaxial depositions.
The growth rate is 0.35 |jLm/min at 7 = 1050°C. (After Reif and Button, Ref. 3.)

390 VLSI Technology
10
EPITAXIAL LAYER-
__! I
-BURIED LAYER-
0.5 1.0 1.5 2£)
DEPTH (;xm)
2.5 3.0
Fig. 5 Measured and simulated doping profiles corresponding to a typical autodoping situation. The
growth rate is 0.27 iJim/min at 7 = 1050°C. (After Reif and Diitton. Ref. 3.)
Figure 5 compares a more typical experimental autodoping result with its simu-
lation. Arsenic was implanted (3 x lO'^ cm~^, 100 keV) into a boron-doped, 10
ft-cm, (100) silicon wafer, and then redistributed for 2 h at 1250°C. The substrate
was vapor etched with HCl (0.5% by volume, 2 min, 1200°C) and then baked in
hydrogen (32 min, 1200°C) before the epitaxial-deposition step. The epitaxial layer
was intended to be intrinsic (i.e., no arsine flow entered into the reactor). The epitax-
ial growth rate was approximately 0.27 |xm/min, and the total deposition time was 6
min. The results in Figs. 4 and 5 show the excellent agreement between simulation
and experiment.
10.3 ION IMPLANTATION
Successful application of ion implantation depends strongly on the ability to predict
and control electrical and mechanical effects for given implant conditions. In the
past, the basic theory of ion stopping in solids has been the LSS theory, named after
its developers Lindhard, Scharff, and Schiott (see Chap. 6). This theory has been
used widely to predict primary ion range and damage distributions in amorphous,
semi-infmite substrates. According to the LSS theory, the ion distribution has a
Gaussian shape with a projected range Rp and a standard deviation AT?^ . Range data
for different ion-target combinations have been derived on the basis of LSS and are
available in the literature.^'
^

In VLSI processing, however, it is quite common to implant into a substrate that
is covered by one or more thin layers of different materials. Typical examples are
threshold—adjust implants, chanstop and source/drain implants into gate—and
field-oxide regions which may be covered by Si3N4. Furthermore, implantations may
be performed through thin layers of heavy metals (e.g., Ta or TaSi2). The existence
of multilayered structures results in implant profile discontinuities at the interfaces
between layers. Additionally, atoms from surface layers may be knocked into deeper
layers by impinging ions. This recoil effect might degrade the electrical performance
of the finished device.
The basic assumptions of the LSS theory do not allow its application to multilay-
ered structures. In the following sections, we apply results from Chap. 6 that are per-
tinent to the theory of ion collisions in solids. The Boltzmann transport equation
(BTE) and Monte Carlo (MC) methods are widely used to simulate ion implantation
phenomena in solids. We introduce these two approaches and compare theoretical
results with experimental data.
10.3.1 The Boltzmann Transport Equation Approach and Monte Carlo
Methods
Let us consider the case of a 100-keV ^^As"^ implant through a double layer of Si3N4
and Si02 into silicon^ (Fig. 6). An arsenic atom entering the system may be scattered
not only from silicon atoms but also from nitrogen atoms in Si3N4 and oxygen atoms
in Si02. Furthermore, if the transferred energy Ej is high enough, the target atoms,
or "recoils," are set into motion, possibly creating recoils themselves until they come
to rest. Particles at each position z are described by their energy E and the direction 6
in which they are traveling with respect to the z axis.
For each particle of interest, a momentum distribution F (E, 0,z ) can be defined.
The number of particles with energies and angles in the two-dimensional interval
SILICON
N-PRIMARY N
KNOCK-ON
0-PRIMARY
KNOCK -ON
Fig. 6 Arsenic implantation through a Si3N4-Si02 double layer, fAfter Smith and Gibbons, Ref. 9.)

392 VLSI Technology
dE dB that go through a unit-area element at depth z normal to the surface is given by
F{E,Q,z) dE dz.
The spatial evolution of this momentum distribution is determined by a
Boltzmann equation for each different species k:
dfkiE, e,z) f [ F,,{E ', e') dcr{E '
-^ £, 6' ^ 0)
dz ^ [ cos 6'
Fk{E,Q) ddiE -^£',0^6')
COS0
+ Qk{E,Q,z) (7)
Ions can be scattered from an energy E ' and angle 0' into a final state (E, 0) or they
can be scattered out of {E, 0) into (£", 0') (second rhs term). For recoil distributions,
Qj^ describes the creation of recoil particles from rest.
The distribution functions are assumed known in the surface plane z = 0.
Recoil distributions are identically zero there, and the momentum distribution of the
primary ions is determined by delta functions
FiE, 0,z = 0) = Oo8(£ - EqMQ - 0) (8)
where $o is the total implanted dose in cm""^ and Eq is the incident beam energy.
The coupled set of transport equations (Eq. 7) is numerically integrated to obtain
the distributions for all depths z > 0. This step requires that the motion of each par-
ticle be confined to a finite number of discrete momentum states. Each state Fjj is
defined'^ by an energy £, (0 ^ Ej ^ ^o) and an angle 0^ (0 ^ 0^ ^ it/2).
Reasonable computation times restrict the number of elements for Fjj . Fifteen
equally spaced energy intervals and ten angular intervals have been found sufficient
for 5 to 10% accuracy in the range distributions.'^
In the MC approach, ion implantation is simulated by following the history of a
projectile through its successive collisions with target atoms using the binary collision
approximation. Distributions for the range parameters of primary and recoiled ions
and the associated damage (electronic and nuclear energy loss) can be obtained by
following A^ histories (where A^ is large, A^ > 10"^).
Each history begins with a given energy, position, and direction. The particle is
assumed to change direction with each binary nuclear collision and to move in a
straight, free-flight path between collisions. The energy is reduced as a result of
nuclear and electronic (inelastic) energy losses. The ion will stop either when its
energy drops below a prespecified value or when its position is outside the target (a
reflected ion).
Monte Carlo calculations are possible for both amorphous and crystalline targets.
In the amorphous model, the position of the target atoms is Poisson distributed. The
ion interacts with one target at a time as indicated by the impact parameters given by
P = J-^ (9)
where 7?„ is a uniformly distributed random number between zero and one and N is
the target density.

The final success of Monte Carlo calculations—as measured by comparing
theoretical results to experimental data—is strongly dependent on the choice of the
interaction potential between the projectile ions and the target atoms. Best results are
obtained with an approximation to the Thomas-Fermi potential which was described
in Chap. 6 with the screening function"
<){R) = 0.35 exp (-0.3/?) + 0.55 exp (-1.2/?)
+ 0.1 exp i-6R) (10)
At this stage, we could theoretically integrate the equations of motion for the
scattering angle 0, which in turn would allow us to calculate Ej. A computer pro-
gram called MARLOWE" based on this exact technique is available. However,
direct integration is time-consuming and can be avoided by an elegant analytical tech-
nique to evaluate the scattering angle, '^ thus allowing the calculation of Ej. The
azimuthal scattering angle (f)
is randomly selected using
(}) = 2tt/?„ (11)
Compared to the BTE approach, the MC technique has three major advantages.
First, it is intrinsically a three-dimensional technique. In modem device processing,
ions are only implanted into finite areas (e.g., windows) of a wafer, resulting in a
lateral distribution of ions under the mask edge. Although Eq. 7 could be generalized
to two or three dimensions, this has not yet been done. A second advantage of the
MC technique over the BTE approach arises when very light ions are implanted into
heavy targets (M /M2 » 1), such as in the case of H"^ implantation (see Ion Beam
Lithography, Sec. 10.5.3). In this case, many ions are backscattered towards the sur-
face, which is no problem in the MC model. In the BTE approach, however, these
ions scatter back into regions where the solution is supposedly already known. '^ A
third advantage arises in the simulation of ion implantation into crystalline materials.
In reality, of course, we know that silicon is not a random medium, but has the regu-
lar structure of the diamond lattice. No BTE results have been published accounting
for lattice effects.
10.3.2 Results and Comparisons
In this subsection, we show the results of a number of representative calculations with
both the BTE model and the MC technique. Basically, both models give the same
results in all cases, if they use the same physical parameters (e.g., potential). The
theoretical basis is the same for both methods.
Arsenic in silicon In Fig. 7, we compare BTE calculations using both the Kalbitzer^^
and Wilson'"^ cross sections with a Pearson type IV distribution^^ (see Chap. 6) gen-
erated from LSS. The implant dose is 10^^ cm~^ at an energy of 355 keV. All
theoretical results can be compared to experimental data.^^ For these conditions, the
reduced energy e is 0.5, which means that nuclear stopping dominates completely.
We see that, near the peak of the distribution, the BTE and LSS results using the Kal-
bitzer cross section agree. The LSS profile, however, is too skewed, and both pro-

394 VLSI Technology
0.24 0.32
DEPTH (^m)
0.56
Fig. 7 Comparison of LSS and transport equation calculations and experimental results for the range profile
of 355-keV arsenic implanted into silicon to a dose of lO'^ cm~^. The cross section used for each calcula-
tion is indicated in the key. (After Christel and Gibbons, Ref. JO.)
files are slightly deeper than the experimental result. The BTE result with the Wilson
cross section is in excellent agreement with the experiment.
Boron in silicon The boron-Si ion-target combination is a good test for any simula-
tion because excellent experimental data are available. ^^ Figure 8 shows MC results
obtained from simulation of 10,000 ion trajectories for the two implant energies of 50
and 100 keV. Measured electronic stopping power data are used to correct the LSS
expression (that is, k = .59ki). Electronic stopping is the dominant energy-loss
mechanism, especially in the 100-keV case. The MC results have been fitted to Pear-
son type IV distributions, given by the full drawn lines in Fig. 8. Agreement with
SIMS data'^ is excellent, particularly for the 50-keV case. The influence of the elec-
tronic stopping parameter is indicated for the 100-keV case, which is also shown for
k = 1 .50ki , a value more consistent with the results in Ref. 24.
Figure 9 shows the final damage-density distribution for a 100-keV boron implant
as calculated by the BTE method'^ together with an LSS calculation.'^ In the BTE

10- I I
I
I I I I
I
I I I I
I
I I I 1
I
I I I I
I
I I I I
1 I I M ;
i I I I !
I I I I
1 I I I I
I
I I I I
I
I I I I.
1—(c) lOOkeV
K K=I50
10" I I I I I I I I I I I I I . 1 I I I I I I I I I I I I I ill I I I I I I M I I I I I I I ill I I I I I I I I I M I 1
1000 2000 3000 4000 5000 6000
DEPTH(A)
Fig. 8 Results of MC calculations for boron implantation into silicon. 10,000 trials were used for each run.
(a) £ = 50 keV. A7yt^ = 1.59. (h) E = lOOkeV, A/A-^ = 1.59. (c)E= 100keV,A/A/. = 1.50.
result, only nuclear events contribute to the final damage. In reality, a minimum
threshold energy E^ is required to remove a silicon atom from its lattice position. The
Brice calculation includes corrections for recoil-energy loss caused by electronic
processes and shows the closeness between both calculations.
Interfaces, channeling, and lateral effects The BTE and MC models both extend
without any particular modification to multiple layer problems. Figure 10 shows MC
results^^ obtained for a 150-keV, 2 x 10^^ cm~^ phosphorus implant through 1500-A
Si02 into amorphous silicon. No discontinuity occurs in the MC data in agreement
with experimental results. The curve represents an LSS profile matched analytically.
Discontinuities occur only if the variation in the mass density between the different
layers is large.
^^
Effects of crystal structure ^^ and lateral effects^^ have been studied only by MC
methods. The influence of the crystal structure exhibits itself in the channeling
phenomenon. For the calculations, the positions of the crystal atoms ai^e fixed
according to the diamond lattice. Thermal vibrations are taken into account. The
ions interact in general with all the atoms bordering the channel. Dechanneling is an
integral part of the model. Shown in Fig. 11 are computed profiles of 150-keV P"^
through 1500-A Si02 into crystalline silicon tilted 7.5° off the (1 10) axis. The effect of
increasing damage during implantation has been taken into account. In the upper
right comer, the computed damage distribution is shown.

396 VLSI Technology
Fig. 9 As-deposited energy deposition profiles for 100-keV boron into silicon comparing the Brice and
transport equation calculations. The abscissa is normalized to the projected range of the boron and the ordi-
nate is energy density per incident particle. (After Christel and Gibbons, Ref. 10.)
—I
1
r
150 keV
P+—SiOg (O.IS^rr
ON AMORPHOUS Si
0.1 0.2 0.3
DEPTH (^m)
0.4
Fig. 10 Theoretical and experimental ion distributions in Si02-Si double-layer substrate. (After De Salvo
and Rosa. Ref. 19.)

"1 1
] r
NO DAMAGE
WITH DAMAGE
ICX)
!: 80
UJ
o
<
1 60
<
o
^ 40h
^ 20|-
0.1 0.2
DEPTH (^m)
n
!
"^, J
01 2 0.3 0.4
DEPTH (^m)
05 06
Fig. 11 Computed penetration profile of 150-keV P^ in Si02 (0. 15 p.m) on Si crystal tilted at 7.5° off the
(110) axis, taking into account the effect of increasing damage during implantation for a total dose of
2 X 10'^ ions cm"- (continuous histogram). The inset shows the damage distribution vs. depth. (After De
Salvo arid Rosa. Ref. 19.)
10.4 DIFFUSION AND OXIDATION
Solid-state diffusion is the physical mechanism that is responsible for the impurity
migration within the silicon crystal during high-temperature processing. Together
with ion implantation and epitaxy, solid-state diffusion is one of the key methods for
controlling the type, concentration level, and distribution of impurities within specific
regions of the silicon wafer. To obtain a diffused layer, impurity atoms are intro-
duced into the surface region either by a predeposition step or by ion implantation.
For VLSI devices, ion implantation is the preferred method since it allows both accu-
rate control of the amount of dopant introduced and considerable freedom in the
profile position (by a suitable choice of implant energy). A high-temperature step is
usually required to activate the implanted ions and to remove the damage associated
with the implant process (see Chap. 6).
As we have seen above, implantations are often performed through mask win-
dows which make the diffusion process a two-dimensional problem.-^'

398 VLSI Technology
10.4.1 Impurity Diffusion and Thermal Oxidation
The basic law governing the transport of the /th impurity is given by the continuity
equation^^
dCi
= div J, = V •
(A vc, + z,^x,yv,(§) (12)
where C, = Ci{x,z ) and J, are the concentration and the flux of the ith impurity, D,
is the concentration dependent diffusion coefficient, Z, and fx, are the charge state
(+1 for acceptors, —1 for donors) and the mobility of the impurity, respectively, A^,
is the electrically active concentration, and (^"i is the electric field. Let us consider a
two-dimensional problem with the lateral dimension x, the depth coordinate z, and the
time t. Equation 1 2 has to fulfill a set of initial and boundary conditions:
Condition 1:
Condition 2:
or
C,(x,z,0)=f(x,z)
Ci{x,^,t) =
(13)
Ciix, ocj) = Cg (= bulk concentration) (14)
Condition 3: No impurity flux is allowed along the lines of symmetry (x — Xf^ and
x = Xi).
dCi
= Xi^ and X = Xi (15)
dx
= for
Condition 4: The boundary condition at the surface depends on whether the surface is
being oxidized
A
dCi
~dz'
= Q
z=0
or is exposed to an impurity gas source
dCi
D;
dz
= h(C, - C*)
(16)
(17)
z=0
In Eq. 16, m is the segregation coefficient given by the ratio of the dopant concentra
tions in silicon and Si02
m =
Q
SiO,
(18)
and b accounts for the volume change associated with the formation of Si02 ( 1 unit of
Si02 consumes 0.44 units of Si). Equation 16 is valid under the assumption that the
diffusion coefficient in the oxide is much smaller than in the silicon. If this is not
true, Eq. 16 must be modified, and Eq. 12 has to be solved also in the oxide.

In Eq. 17, /? is the mass transfer (or evaporation) coefficient and C* is the dopant
concentration in the gas phase.
When the impurity concentration is extremely high, some precipitation of impur-
ity atoms (i.e., clusters) may occur. "^^ "'^
This precipitation makes some impurity
atoms electrically inactive. During impurity diffusion, these clusters can "decluster"
and therefore become electrically active. We can describe this phenomenon by the
equations^"^
dN
dt
= kjC, - k.N""
= -k,C, + ^,A^
C = N + Cc
(19)
(20)
(21)
which together with Eq. 12 describe the impurity flux. The variables k^ and k^ are
the clustering and declustering rates, Q is the concentration of the clustered impurity,
A^ is the electrically active part of the total chemical concentration C, and m is the
cluster size. Numerical solutions to these equations indicate that the kinetics of
arsenic clustering are especially important at annealing temperatures below 1(X)0°C.
Figure 12 shows the influence of the arsenic clustering on the carrier concentration.
All samples are doped to a concentration of 2 x 10^' cm~^ by ion implantation. At
1(XX)°C, equilibrium is reached with a carrier concentration N =2.81 x 10^^ cm"-^
(dashed line). From the clustering, one can predict that subsequent anneals at lower
temperatures will significantly decrease the carrier concentration. While the equili-
brium carrier concentration monotonically decreases with temperature, the time
required to reach equilibrium rapidly increases at higher temperatures.
For most practical processing situations {T >900°C, f>20 min) the effect of
dynamic clustering and declustering is not significant. The clustering phenomenon
1.5 X 10'-
lOOCC oocc
TOTAL As = 2 X 10^ cm"^
500"»C EQUILIBRIUM
1 CONCENTRATION
- —
-
o 1000 °C
D 900°C
c 800°C
J i_
^700°C
O 600°C
20 40 60 80
TWE (min)
100 120
Fig. 12 Carrier concentration as a function of annealing time, (After Tsai, Morehead, and Baglin. Ref.
24.)

400 VLSI Technology
can then be modeled by an equilibrium clustering relation"^'
~^
C = N + pA^^ (22)
where p is the temperature and impurity-dependent equilibrium constant given by
P = / (23)
The diffusion coefficient D, in Eq. 12 is, in general, a function of the concentration of
the impurities for high dopant concentrations (see Chap. 5). All process simulation
programs reported include the concentration dependence of D, obtained from the
vacancy-diffusion model
D, = Df + Drf + Di^-f +
^ (24)
with/ = N/rii. The variables Df, D~, Di^~, Di^ are the intrinsic diffusivities of
the various vacancy states in silicon, N is the electron concentration that depends on
all C, , and n, is the intrinsic concentration at the diffusion temperature.
At low impurity concentrations, A^ is approximately equal to «, and the diffusion
coefficient reduces simply to the sum of the various vacancy states, independent of
concentration
Di = Df + Dr + D,2- + D/ (25)
The individual diffusivities in Eq. 24 or Eq. 25 are given in Arrhenius form
Di = D,o exp
kT
(26)
with the prefactor D(*o and the activation energy Q- (see Chap. 5).
The electron concentration A^ can be approximated by
N = -^ -^^ (27)
with
rt
i=
Diffusion of all important group III (B) and group V (As, Sb) elements in silicon
is described well by the diffusion model, Eq. 12, together with Eq. 24. The diffusion
of phosphorus, however, is governed by a rather complex diffusion behavior and is
modeled by the three-region model (see Chap. 5).
An accurate description of the phosphorus diffusion is especially important in
emitter-push situations usually encountered in bipolar technology. A typical process
would include a base boron implant followed by a series of drive-in steps. The first
base drive is a dry oxidation step, followed by two wet oxidation steps and another
dry oxidation. Next we form the emitter by chemical predeposition followed by
drive-in steps. The resulting final doping profiles are shown^^ in Figs. 13a to c. Fig-

lire 13a is a three-dimensional surface plot, and Fig. 13b is the corresponding contour
plot result. Figure 13c shows the emitter push-out phenomenon which results in the
considerable deepening of the base-collector junction under the emitter as compared
to the inactive base region.
Although of less importance, coupled-diffusion effects also occur in MOS fabri-
cation. Consider an NMOS process with 1-fxm design rules. After growing the gate
oxide of 250-A we implant B at high energy to adjust the threshold voltage and to
prevent punch-through. Polysilicon is deposited and doped, and the source-drain
regions are opened up by lithographic and etching steps. Source and drain are formed
by a high-dose arsenic implant. Several drive-in steps follow until the device is
finally processed. Figures 14a and b are surface plots of the total concentration and
boron concentration, respectively, in the source drain regions and under the gate.
Note the redistribution of boron in the source and drain junction areas caused by the
emitter-dip effect.
LATERAL
POSITION
(a)
Fig. 13 Final phosphorus and boron doping profiles, (a) Surface plot of the phosphorus-boron impurity
distribution.

402 VLSI Technology
EMITTER MASK
BASE MASK
5.25 -
700
2 50
LATERAL POSITION (^m)
375 500 6.25 750 875 1000
(b)
10*
.^.r-EMITTER
BASE UNDER
EMITTER
2.8 4.2
DEPTH (^m)
(C)
70
Fig. 13 (continued) (b) Contour plot of phosphorus and boron concentration, (c) Phosphorus and boron
profiles in the emitter and the inactive base region. (After Penumalli, Ref. 25.)

(a)
LATERAL
POSITION
(b)
Fig. 14 Final arsenic and boron doping profiles, (a) Surface plot for the total concentration in a l-fjim-
gatelength MOS device, (b) Surface plot of the boron concentration. (After Penumalli, Ref. 25.)

404 NT-SI Technology
10.4.2 Thermal Oxidation
Thermal oxidation at high temperatures, which forms a layer of SiO: on silicon, is an
integral process step in the fabrication of silicon devices. The kinetics of oxidation
are fairly well understood for one-dimensional problems. According to the theor}-,
the oxide thickness is expressed as
d^ît) - Ad,,^[t) = Bit + to) (28)
with the oxide thickness ô- ^he rate constants A and B. and the correction time tQ
which accounts for the initial oxide thickness dr,xiO) at f =0:
^0
= dsAO) + Ad,,iO)
B
(29)
A and B are related to the linear and parabolic growth coefficients k^ and kp and to
the normalized ox-gen panial pressure Pq. by
A =
PqÎ^p
(30)
and
B - Po^kp (31)
For low dopant concentrations, kp and ki depend only on the oxidizing ambient and
the crystal orientation. The temperature dependence of these rate constants can be
expressed by one activation energy. Under high surface-concentration conditions, the
oxidation rate is significantly enhanced.-^ The reason can be attributed to the genera-
tion of excess point defects at the Si-Si02 interface. In Refs. 4 and 26. the oxidation
rate enhancement is included into Eq. 30 and Eq. 31 by adjusting the linear and para-
bolic rate coefficients to
/, = lill ' 7(Cf-l)
and
1 - hici-r--
(32)
(33)
The variables // and /^ are the intrinsic (low concentration) rate constants and 7 is a
parameter determined empirically.
7 = 2.62 X 10- exp
1.10
kT
(34)
The variable Cy is the normalized total vacancy concentration.
G^ =
Hl - c-
N_
- c:--
'n_
N ni [Hi

1 ^ Q- -V - C- —
1 - C,' + C,~ + Cv"
(35)

Process Simltation 405
with the vacanc- concentrations
C = exp
E- -£,
kT
C," = exp
E, - £-
^
kT
C,-~ = exp
2E, - £"-
- E-"
kT
E. is the position of the intrinsic le'el in the gap
£.
E,[T) = -^
In Eq. 33. 6 is an empirical constant
8 = 9.63 X 10"!^ exp
E' = 0.35 eV
£~ = £„ - .57 eV (36)
£^ - 0.11 eV
(37)
kT
(38)
and Cj is the total dopant concentration.
.At this time, a well established theon.' is not available that would allow a tlrst-
principles simulation of two-dimensional oxidation phenomena, such as the lateral
oxidation under a 813X4 mask that gives rise to the
"
"bird's beak"" geometr . Concep-
tually, such a theor>" involves a calculation of the o.xygen tlux to the silicon surface by
solving the oxygen diffusion equation"^
D„.V-C„. =
ac,
dt
(39)
where D^^ and C^x are the oxygen diffusion coefficient and concentration, respec-
tiel The boundar' conditions are the same as in the one-dimensional model. The
olume expansion rate and the velocitN" at each olume oxide element are obtained
from the oxygen flux. The motion of the outer oxide boundan.' is also described by
this elocity as well as by the oxide boundaries and boundan. conditions. At suffi-
cienth high temperatures [T = 900''C). the oxide material can flo>A- although the
viscosity is extremely high. Assuniing incompressibility. a simplified Navier-Stokes
equation
28
^V-- = Vp (40)
treats this flow ot oxide subject to the volumetric expansion at the intertace. x. V,
and p are viscosity, velocity, and pressure in the two-dimensional oxide region.
This rigorous treatment is rather involved and will consume large amounts of
CPU time. A simplified treatment of lateral oxidation uses a coordinate transforma-
tion method from the physical domain to a coordinate system in which the moving
boundar) remains stationary" in time. With this approach the solution domain is sim-
plified at the expense of complicating the diffusion equation (Eq. 12).

406 VLSI Technology
^z =bf (x,t)
Fig. 15 Simulation regions.
z =^ + bf (77, t)
t = T
Let (x, z, t) be the two spatial variables and the time in the physical coordinate
system. Let (^, r, t) be the corresponding variables in the transformed coordinate
system. The simulation regions in both systems are illustrated in Fig. 15. The coordi-
nate transformation is
^ = z - bfix, t)
Ti
= .V
T = t
where fix, t) = —-— erfc
2x
kidoAt)
(41)
(42)
(43)
(44)
and where / is a function of lateral position and time, ki is the ratio of lateral to verti-
cal oxidation, and b is defined as in Eq. 16. Applying Eqs. 41 to 44 to Eq. 12 yields
transformed equations for the {r, 4) variables.
Local oxidation is commonly used in MOS processing. Figures 16a and b show
the region and the boron profile before and after local oxidation respectively. In Fig.
16a, the as-implanted boron profile is shown. Oxidizing this profile for several hours
in wet and dry atmospheres not only redistributes the boron considerably (note the dif-
ferent length scales), but also results in the bird's beak geometry of Fig. 16b.
10.4.3 Numerical Aspects
Depending on the number of impurities present, a set of coupled nonlinear partial
differential equations, like Eq. 12, has to be solved in either one or two dimensions
subject to initial and boundary conditions. Here we shall only consider the two-
dimensional case, since it is more useful in simulating diffusion phenomena in VLSI
devices. The spatial derivatives in Eq. 12 are discretized in the usual manner by cen-
tered differences^^ on a two-dimensional grid. This reduces Eq. 12 to a set of A^ non-
linear ordinary differential equations, where A^ is the number of grid points in the

MASK
0.5
LATERAL POSITION (/xm)
1.0 1,5 2.0 2.5 3.0
(a)
Fig. 16 Effect of local oxidation, (a) Region and boron profile before oxidation, (b) Region and boron
profile after oxidation. (After Peminuilli, Ref. 25.)
mesh. A variety of different methods is available for the time integration. Implicit^^
and explicit^^ methods are both suitable for the numerical solution of diffusion prob-
lems. In terms of operations per time step, implicit methods are more CPU time-
intensive than explicit methods. However, implicit methods allow larger time steps
and are usually more stable than explicit methods.
The standard technique is the first-order backward difference method^^
'« +1 f-'ti
(45)
dCi
dt
cr
^t n+
where the superscripts denote the concentration levels at the time steps t"'^^ and t"
withAr" + '
=t"^^ -t".
The time and space discretization finally yield for each impurities species, a set
of A^ nonlinear algebraic equations that can be expressed in matrix notation as
cr
^n+/^n+
C," + BiCr )Ci' + 5(Ci,C2, ...,CJ (46)
where B(C) is a matrix whose elements are functions of C, and 5 is a vector

408 VLSI Technology
representing boundary conditions, etc. Equation 46 is solved by applying Newton's
metiiod. Rewriting it in the form
8(C) ^0 (47)
and applying Newton's method, we obtain
^ X =Ax = -giC) (48)
Solving the linearized system Eq. 48 by any conventional method"^' for x concludes
one Newton iteration by updating the concentration to
This cycle is repeated until a suitable error criterion is reached. We can now update
the time step and continue the time integration. Automatic time-step selection
schemes allowing a convenient solution of Eq. 46 are available.
10.5 LITHOGRAPHY
In this section we present the basic theory and simulation results for optical, electron-
beam, and ion-beam lithography. Optical lithography is the standard pattern-
definition process in IC fabrication, as described in Chap. 7. We shall derive the
basic relations of resist exposure for positive resists which are the basis of a
comprehensive computer program called SAMPLE.^" Electron-beam lithography is
the standard technique today for the fabrication of masks for optical and x-ray lithog-
raphy. Furthermore, direct electron-beam writing on wafers is the only technique to
obtain extremely small linewidths. Electron scattering is responsible for the forma-
tion of the final image. Ion-beam lithography, however, can achieve the smallest
linewidths of all lithographic techniques. Ion-beam lithography is basically ion
implantation using a focused beam.
10.5.1 Optical Lithography
A generalized optical system is shown in Fig. 17. The information to be replicated is
contained on a thin optically opaque layer supported by a transparent substrate. This
pattern (the mask) is transferred by the exposure system to form an aerial image,
which consists of a spatially dependent light-intensity pattern in the vicinity of the
wafer. Exposure of the resist-coated wafer to the aerial image makes the resist more
soluble (in case of a positive resist) to a chemical developer, which allows for easy
removal of the exposed sections.
The simulation of this process consists of three parts:
1. Optical computations. The end product of the optical computations is the two-
dimensional net (incident and reflected) intensity distribution /. The necessary
input information for computing / relates to the optical system, the intensity dis-
tribution pattern of the light source, and the resist and substrate parameters.

RADIATION
V//////A
~
LITHOGRAPHIC EXPOSURE TOOL
J_J i_l
VT VT
AERIAL IMAGE
RESIST
SUBSTRATE
DEVELOPMENT
RESIST PROFILE
SUBSTRATE
Fig. 17 Idealized photolithographic system. (After King, Ref. 34.)
2. Exposure computations. The interaction of the exposing radiation / with the
resist reduces the local inhibitor concentrations M. Calculation of the local
instantaneous value of M requires a knowledge of specific exposure parameters
that depend on the resist.
3. Development calculations. The development response of the resist to the
developer requires a knowledge of empirical resist constants that permit computa-
tion of the development rates from M. The development rates then permit profile
calculations for any particular development time.
We shall first consider the theoretical simulation of proximity printed im-
ages-^^"^^ (see also Chap. 7). If feature size and mask-to-wafer spacing are compar-
able to the wavelength X of the exposing light, the diffraction from the mask edges is
an electromagnetic diffraction problem that is given by Maxwell's equations under
the appropriate boundary conditions. We have to calculate the square of the electric
field I
6 I
^, since photoresists react only to the intensity of § . Assuming that the
opaque material on the mask is infinitely thin and perfectly conducting, any one-

410 VLSI Technology
i!4
2.2
1
2.0 -
1.8 -
!i
1.6
M Z =
1.4 -r
1.2
*
1.0
0.8
- » • '
, V, - V / 1
- I - V
0.6 - f,x GLASS i
0.4
0.2
VACUUM 0.05/xm
- ^z photoresist: 1.50/1 m
SILICONDIOXIDE 0.50/im
SILICON y
1 1 1 1 1 1 1
Z = 0.05/xm
J I h L
L
(a) (b)
L4
1.2
1.0
0.8
0.6
0.4
A
z«o.80/im
« 1 t
" /i '-
«
y V >j '
'/
'
1 1 1
^-^^i-_a_
-4 -3 -2 I
x(/i.m)
(c)
Fig. 18 Diffraction by a perfectly conducting infinitesimally thin half plane imbedded between the glass
substrate of a mask and a photoresist on top of SIOt and a silicon substrate. The solid line represents the
normalized field intensity |
ti |
- and the dotted line represents normalized power flow density |
t> x
jL* . (a)— (d) show different diffraction results when z is made to vary from to 1.55 |xm. (After Heit-
man and van der Berg, Ref. 35.)
dimensional pattern can be synthesized with a combination of transverse electric (TE)
slits and half-planes. The diffraction of a TE plane wave through a perfectly conduct-
ing half-plane of infinitesimal thickness depends strongly on the optical properties of
the material beneath the mask.
Figure 18 depicts simulated results^^ for a realistic proximity printing situation
with an air gap between the glass substrate of the mask and the resist. The relative
permittivities for the glass, photoresist, Si02, and Si are 2.25, 2.56 + /0.032, 3.5,
and 21.17 + /0.466, respectively. The permeabilities (jl of all materials are identical
to the vacuum value. The silicon layer under the resist causes a partial reflection

Process Siml'lation 411
that combines with the incoming wave to form a standing wave in the resist. The
irregularities in the peak positions at the resist surface (r = 0) are also caused by the
reflection. The Si02 layer causes a phase change of the reflected wave. The small
vacuum gap (0.05 |JLm) between the glass and the resist simulates the imperfect con-
tact situation.
Image formation in projection printing Most projection systems are designed to
yield a diffraction-limited image over the entire image field. The systems are usually
monochromatic (which allows the projection lens to be optimized for resolution, field
flatness, and distortion), avoiding chromatic aberration. The quality of the aerial
image relative to that of the mask pattern is determined by the modulation transfer
function (MTF) of the lithographic exposure tool defined by
M;maap(v)
MTF(v) = -=ri (50)
where Milage ^nd M^ask ^e the mask and image modulation, respectively, for a spa-
tial frequency (Chap. 7). This expression is valid for a mask with a sinusoidally vary-
ing transmission.
For an idealized imaging system, as in Fig. 19a, the angle ^ between the max-
imum pupil diameter and the image plane determines the resolution. This angle can
be described by the numerical aperture NA ,
NA = n sin ^ (51)
or the effective //number
//number =
^
where n is the index of refraction of the surrounding media {n ~ 1 for air)
.
The nature of the image depends on how the mask is illuminated and the
wavelength X. of the light. Figure 19b shows schematically the coherent illumination
of a mask with sinusoidal transmission of period P. Increasing X or decreasing P
increases the diffraction angle 4>. As long as the condition 4) =s ^4^ is fulfilled a per-
fect image is formed, since all the light is collected. Since the pattern of the mask
consists of equal lines and spaces of spatial frequency v = l/P, the pattern can be
expressed as an infinite Fourier series^"*
Mask pattern (x) = Aq + X «* sin (I'nkvx) (52)
A=i
with the Fourier coefficients a^ . The Fourier coefficients of the aerial image / can be
found from those of the mask pattern by using the definition of the MTF, Eq. 50,
/(.t) = flo + 2 MTF(^^)«/t sin {iTxkvx) (53)
k =

412 VLSI Technology
OBJECT PLANE
LENS IMAGE PLANE
(a)
MASK
COHERENT
ILLUMINATION
LENS
( + 1)
IMAGE
(-1)
SINUSOIDAL TRANSMITTANCE PERIOD p
(b)
MASK LENS IMAGE
INCOHERENT
(C)
ILLUMINATION
SINUSOIDAL TRANSMITTANCE PERIOD p
Fig. 19 (a) Simple imaging system, (b) Coherent illumination of a mask with sinusoidal transmittance of
period P. (c) Incoherent illumination of a mask with sinusoidal transmittance of period P. (After King, Ref.
34.)
Assuming that the lithographic system operates near its limiting capability, only the
fundamental spatial frequency is important and MTF (kv) = for ^ > 1 . Now we
calculate the amplitude of the aerial image
/I max 4
A(x,z) = —-— sl+ — exp [/c|)(z)] sin (I'ttvx) (54)
with the phase angle 4> describing various aberrations of the optical system. For a
perfect exposure system ^ depends only on the focus condition, given approximately
by
Mz) (55)

Prcxiess Simulation 413
where z is the distance to the focal plane. The intensity of the coherent aerial image is
given by
lix) = A
i ma
1 + — cos <^ sin {Ittvx ) + sin" {irvx
)
(56)
In the case of coherent illumination, Eqs. 55 and 56 describe the image formation for
both projection printers and contact-proximity printers. In the latter case z describes
the separation between the mask substrate and the wafer.
The other extreme of image formation occurs when the illumination conditions
are similar to the situation in Fig. 19c. For an angle > ^, the system is described
as incoherent. Light can be diffracted by an angle 2^ (compare this with ^ in the
coherent case) and still be collected by the projection optics.
Starting from Eq. 52 and applying the same approximation, we calculate the
aerial image for the incoherent case
Kx) 1+ M/iv) — sin (Ittvx
IT
(57)
where Mj is an approximation to the incoherent MTF for a circular pupil
4
M/(v) 1
IT
sin (vX/) (58)
In reality, all projection printers operate in a region between the two extremes of
coherent and incoherent imagery because the pupil of the objective lens is partially
filled, as shown^^ in Fig. 20. This condition is cailQd partial coherence. It is charac-
terized by the parameter ct; the ratio of the numerical aperture of the condenser lens,
SOURCE CONDENSER
LENS
MASK SECTION
I
Fig. 20 Definition of symbols in a partially coherent system. (After O' Toole and Neureuther. Ref. 36.)

414 VLSI Technology
1.3
12
I.I
1.0
09
>- 08
CO 0.7
UJ
06
05
04
03
0.2
0.1
00
-
1
-
-
°i^V^
^-^
^^=^"
"
-^ _
-
^^78
DEFOCUS BY
0.
ill
-
- 222 -
-
778,^
3.34
4.45
-
-
5.56
-
z-^ 6.67
778 ^m
-
^^^^ 1
(EDGE) I
POSITION (/im)
Fig. 21 Effect of focus error for a = 0.6 on the image of a mask pattern with 2-|jLm lines and 6-|j,m spaces.
NA = 0.28, X = 0.436 |xm. (After O' Toole and Neureuther. Ref. 36.)
NAc = sin a,, (remember n
NAn = sin a^
1) and the numerical aperture of the objective lens,
NA,
~NA,.
(59)
A coherent system is characterized by a = and an incoherent system by ct = ^c.
The difference between o = ^c and ct = 1 is small.
The basic effects of imaging with partially coherent light can be seen in Fig. 21
,
which shows the calculated image intensity^^ near the edge of a mask pattern consist-
ing of 2-|jLm lines and 6-fxm spaces. Since the mask is periodic, it is reflexive around
both the -Y = — l-ixmandx = 3-txmaxis.
The numerical aperture of the lens is 0.28 and the wavelength is 0.436 |jLm. The
focus error for the curves is taken in units of 0.4 Rayleigh units; one Rayleigh unit is
2.78 |JLm (= K/lNAo). The focus error d is the distance in micrometers between the
resist surface and the plane of perfect focus.
Calculation of photoresist exposure-^^ Calculations of resist exposure require a
knowledge of the optical constants of the substrate and any overlying layers and of the
thicknesses of all the corresponding layers. The key to describing the exposure
dependent optical properties of the photoresist are the exposure parameters A, B, and
C. A and 5 describe the absorption constant a according to
a = AM{z,t) + B (60)
where M is the relative amount of photoactive inhibitor present at any position z and
time t during exposure.
In the calculation, the complex index of refraction n of the photoresist is used
n = A2 - ik (61)

where n is the real part of the index and k is the extinction coefficient at the exposing
wavelength
The index n can be expressed with Eqs. 60 to 62 as
„ = „-/ AIMMiiS) ,^3j
477
During exposure, n changes as the inhibitor is destroyed by the exposing light with
intensity /. The optical sensitivity parameter C relates the destruction rate to the light
intensity:
^^^^^ = -/(r,;)M(r,,)C (64)
at
As in the proximity printing case (see Fig. 18), the light intensity can vary appreci-
ably within the resist film over thicknesses that are small compared to the resist thick-
ness. Standing waves are caused by interference between the incident light and
reflected components, resulting in a nonuniform inhibitor concentration and a
corresponding nonuniformity in n.
Because the optical properties of the resist vary during exposure as a function of
depth, the resist film is subdivided in layers thin enough to be treated as if they had
isotropic properties. ^^ Furthermore, the computation is divided into time (i.e., expo-
sure) steps small enough to minimize changes in intensity and corresponding changes
in the inhibitor concentration. If Ij and Mj denote the intensity and concentration in
the yth sublayer, we calculate Ij by holding the inhibitor concentration constant. We
proceed by incrementing the exposure-time variable by Ar^ and calculating new
values for Mj to so that the computation of Ij can be repeated. Mj is altered by the
exposure to
Mj I
r,+Ar, = Mj ,^
exp (-/^CAr,) (65)
with the initial condition Mj , =q = . Reasonable accuracy is obtained if the resist
layer thickness hzj is less than 0.03 and the exposure time increment A t^ is chosen
so that the largest change in any Mj is 0.2 or less.
Figure 22 shows a computed result of the intensity distribution /(r) with a
0.584-|xm thick photoresist film on silicon and with a 600-A SiO^ layer at the begin-
ning of exposure by a uniform incident illumination. After an exposure flux of 57 mJ
cm~^, the resulting inhibitor concentration is shown in Fig. 23. This is a typical
result for a uniform exposure of photoresist on a real substrate.
Photoresist development The description of an image exposure in the photoresist is
given by a two-dimensional matrix of inhibitor concentration values M{x,z). The
development process is modeled as a surface-controlled etching reaction which is con-

416 VLSI Technology
0.1 02 0.3 0.4 05 06
DEPTH INTO RESIST (/xm)
Fig. 22 Intensity of exposing light within a 0.584-|jLm AZ1350J photoresist film on 600 A of oxide on sili-
con. (After Dill et al., Ref. 37.)
trolled by the local value of M. M{x,z) is assumed constant in unit cells of dimen-
sions A X and A z around x and z. The etch rate R is expressed as
R{M) = a exp £, + E2M + E^M' (66)
where a gives the etch rate in fjim/s, and Ei, Ej, and £3 are experimental constants
of the resist, depending on the developer, the temperature, and the processing condi-
tions, respectively.
Development starts along the surface in contact with the developer. Cells of con-
stant M are removed by the developer according to Eq. 66 and depending on the
number of cells in contact with the developer. New cells are allowed to start etching
o 100
80
0.60-
5 040
0.20-
0! 2 3 04 05 0.6
DEPTH INTO RESIST (^m)
Fig. 23 Inhibitor concentration within a resist film on oxide on silicon after exposure to 57 mJ cm"- at a
wavelength of 0.4358 x.m. (After Dill etal.. Ref. 37.)

-0.5 0.5
DISTANCE FROM LINE CENTER (^m)
Fig. 24 Edge profile for a nominal l-|a.m line in AZ1350 photoresist developed for 85 s in 1:1 AZ
developer;water. (After Dill et al. , Ref. 37.
)
when old cells are removed. The time to remove a cell which has only the top side
exposed is given by
Az
tr
=
Ri
(67)
where Rjj is the etch rate of the particular cell, and Az is the layer thickness. Simi-
larly, if the top and one side are exposed
A.x A.
/?„Va.v- + Av-
(68)
Figure 24 shows the calculated resist edge profile of a nominal l-|jLm line that has
been exposed by a lens with NA = 0.45 at X = 0.4358 fxm. The development time
is 85 s. The edge fingers on the line are typical for a monochromatic exposure of AZ
1350J.
10.5.2 Electron-Beam Lithography
In electron-beam lithography, finely focused electron beams are used to expose
polymeric resist layers. The interaction and scattering of electrons within the resist
layer and the underlying substrate depend on the beam energy, the resist type and
thickness, the substrate parameters, and so on. The best resolution obtainable is not
limited by the characteristics of the incident beam but rather by electron scattering.
The actual process of electron scattering in solids is so complex that we have to rely
on numerical models for quantitative results. The only model of practical importance
is the Monte Carlo (MC) technique. With this technique we simulate a large number
of individual electron trajectories to obtain the energy deposited in the resist (similar
to ion implantation described in Sec. 10.3.2). Electrons undergo scattering events
with the target nuclei (elastic scattering). In addition, they suffer energy loss by
inelastic scattering processes with the target electrons. Elastic scattering results

418 VLSI Technology
Fig. 25 Schematic diagram showing the initial Monte Carlo step lengths for electron scattering in a thin-
resist film on a thick substrate. (After Kyser andMwata, Ref. 39.}
mainly in a change in the direction of the incoming electron. To model elastic
scattering, the screened Rutherford formula is used for the differential cross section
-1
dn
'2^4
6E'
sm + (69)
where dcr/dCl is the differential cross section per unit solid angle, and % is the
screening parameter
00 = 3.7Z'/3^-'^' (70)
The electron is assumed to travel in a succession of short straight paths between elas-
tic scattering events, as shown-^^ in Fig. 25. At each scattering point, the resulting
azimuthal angle is determined by selecting a random number weighted with the dif-
ferential cross section, Eq. 69. The path length , between scattering events is
selected by weighting the mean-free path between collisions by another random
number in the zero to one range. The energy of the electron is reduced at each step by
multiplying the path length by the Bethe energy loss rate
dE
ds AE
In
1.1658£
/
(71)
where E is the electron energy, Z and A are the atomic number and atomic weight of
the solids, respectively, A^o is Avogadro's number, p is the density, and / is the mean
excitation energy.

2 1 1 2
'
1
'
1
'
1
'
PMMAikA-^^y
1
Si ^g^
^ 1
2 - 2
3 - 3
4
lOkeV
, 1 1 1
4
Fig. 26 Simulated trajectories of 100 electrons in PMMA. (a) Simulation for a 10-keV delta function
beam, (b) Simulation for a 20-keV delta function beam. (After Kyser andMunita, Ref. 39.)
This process is repeated until the electron comes to rest. Depending on the angle,
scattering events can be divided into two categories: forward-scattered and backscat-
tered. Figure 26 shows 100 simulated electron trajectories for a 10-keV and a 20-keV
delta function beam incident at the origin for a 0.4- |xm PMMA film on a thick Si sub-
strate. The beam is incident along the z axis and all trajectories have been projected
onto the xz plane. These figures qualitatively show the degree of lateral forward
scattering within the film, as well as the degree and position of backscattering. Back-
scattered electrons can emerge at distances far away from the origin.
Monte Carlo results for a delta line 20-keV beam on 0.4-|jLm PMMA on Al are
shown in Fig. 27. Twenty thousand electron trajectories are simulated. The radial
distribution of energy density is shown for two different depths (0. 1 |jLm and 0.4 ixm).
For comparison, analytical results'^^
"*'
are included. At the origin the results of the
MC models are consistently higher than the results of other models.
The latent image which is the absorbed energy density of the 8-function line
source allows the calculation of the spatial distribution of energy density for any arbi-
trary beam shape by Fourier transformation. If an exposure profile is to be written
with a rectangular beam, as in Fig. 28a, the profile for the absorbed energy density is
obtained from the MC data by a convolution of a Gaussian distribution with itself over
the square dimension.'*^ The result of the convolution is
fix) = K erf
V2ct
erf
a + X
V2a
(72)
where the beam width FWHM (full-width half-maximum) = 2fl, ct is the standard
deviation, and Kisa constant. For a /ct» 1 , the edge slope is
dx
IK
V2^CT
(73)
The edge width is given by V2'itct/2, and is defined by the tangent to/(±a) inter-
cepting fix) = and fix) = IK erf (a/V2o-). The edge of fix) is symmetric
around its half-height.

420 VLSI Technology
1032
1 1 I 1
I
1 1 1 1 1

LINE SOURCE
20 keV
4000A PMMA
V 1
- GREENEICH (A/)
K)''
r - MONTE CARLO (Si) _
- 1
^^v _
I 1
-
1

1 1
1

,030
1 1
I

Zo ^4 000 A —

;^

'0

s
I0»
^____ ^^^
- -
.r.28 1 1
1 1 1 1 III
QOI 0.1
X (urn)
1.0
Fig. 27 Energy density profiles for a line source. (After Kyser and Murata. Ref. 39. and Hawiyluk et ai.
Ref. 40.)
If the exposure pattern is to be written with hnes composed of one or more Gaus-
sian shaped beams possibly with different weights, as in Fig. 28b, the beam is
described by
fix) = K Qxp
X
82
(74)
Depending on the actual beam shape, either Eq. 72 or 73 is used as the envelope func-
tion for the digital convolution of the latent image from the ideal line source. This
convolution assumes that superposition of electron exposure and subsequent energy
deposition holds.

30-
20
cr=0 25/J.m
FWHM
I
f (MAX)
-f(0)
(a)
F(x) = Ke-''^/S^
(b)
Fig. 28 Exposure patterns for arbitrary beam shapes, (a) Definition of terms. The vertical axis is the
number of electrons distributed over the incident line, normalized to 10^ electrons. (After Kyser and Pyle,
Ref. 42.) (b) Schematic representation of a Gaussian round beam.
Figure 29a shows the simulated MC result of the energy deposited within 1.8 |xm
of resist at three depths for a 25-keV beam. At the surface (z = 0), the distribution is
very narrow, but for increasing depth, it becomes broader due to backscattering con-
tributions from the substrate. To calculate the lateral distribution of deposited energy
(see Fig. 29b), the 5-function distribution is convoluted with the rectangular beam in
Fig. 28a. The energy deposited varies with z. The tails in the original line response
deep in the resist are a significant part of the total distribution in Fig. 29b.
As in optical lithography, we can calculate resist development. For positive
resists, a general relationship between R and E is
R = (A + fi£'')[l-exp i-az)] + e(£) (75)
where R is the etch rate in A/s, z is the distance below the surface, E is the local
absorbed energy density in keV cm~^, and A, fl, and n are appropriate constants.
The dependence of e is modeled as
e(£) = eo + CE"" (76)

422 VLSI Technology
004
cdq:
a: uj
UJCL
UJH 0.02-
M(->
-:LjJ
ctcr
OUJ
>- <J
tro
QcJ
UJO
CD
(a)
(b)
800-
(c)
400-
-2 -I I
DISTANCE FROM CENTER ifJ-W)
Fig. 29 Energy distributions and etch rate, (a) Lateral distribution of energy deposited in the film of a 1 .8-
|jLm polynneric resist on Si (25-keV, 2.0-|jLm written linewidth) using a Monte Carlo simulation for an ideal
line source, (b) Lateral distribution of energy deposited within a 1 .8-|JL,m resist by 25-keV electrons for the
2-|ji,m line in Fig. 44a. (c) Lateral distribution of etch rate for the same resist film and the latent image of
Q = 20 |jlC cm"-. (After Kyser atuiPyle. Ref.42.)
where C and m are constants and E is evaluated at z =0. The form of Eq. 75
impHes that for z « 1/a and vanishing incident dose Q, R ^ Eq. For z = 1/a
and g = Q, R = A + Eq- This type of dissolution behavior has been observed
experimentally for certain positive resist materials under optical and electron-beam
exposure. If a becomes large and C = 0, Eq. 75 reduces to the solubility rate
behavior of PMMA used in SAMPLE.^^ The parameter a can be interpreted to
describe the distance the solvent must diffuse into the resist before any significant
development reaction starts corresponding to a diffusion distance 1/a. The correction
term e{E ) provides the proper surface rate.

Equation 75 transforms the latent image of Fig. 29b into a solubility rate image.
Figure 29c gives the lateral etch rate distribution with the constants in Eqs. 75 and 76
set to A = 50A/S, a = 1.5 fjLm"fi = 2.5 x 10"'^ « = 1.05, C = 2.0 x 10"^°, m
= 1.5, and eo = 0.5 A/s. The development proceeds in the same manner as outlined
before in the discussion of photoresist development.
Monte Carlo simulation, together with resist modeling is an extremely powerful
tool for investigating proximity effects (see Chap. 7). Suppose we would like to
develop a fine-line array of 0.5-fxm lines and spaces in 1 ixm of PMMA resist.
Because of electron scattering, the various lines do not develop at the same time. Fig-
ure 30a shows the normalized energy density for two depths in the resist. Although
each line receives the same dose, the outer lines receive less absorbed energy E within
the film. The developed profile in Fig. 30a shows the case where the calculation is
stopped when the center line just begins to open at the interface. With an adjusted
dose for each line, all lines can be developed to the same size at the same time. By
simply specifying the depth z at which the maximum absorbed energy density ought
to be uniform, a computer program iteratively adjusts the relative line doses. For the
same line array, the dose modulation (at z = 0.5 |xm) is calculated to be 1.111 for
the outer two lines and 1.041 for the inner two lines. The center line is exposed to a
value of 1 .000. Figure 30b shows corresponding latent images and developed profiles
with this dose modulation.
The use of MC models to perform proximity-effect correction is expensive,
requiring large computer programs and long computing times. The use of analytic
functions facilitates the study of proximity effects.
The proximity function /(r), defined in Fig. 31, can be approximated by two
Gaussian distributions with standard deviations Py- , P/, , and relative areas te
fir) = K exp
—r
P/ Pb
(77)
Monte Carlo calculations'*-^ and experimental techniques'^ are used to obtain the
parameters in Eq. 77 for each particular resist-substrate situation and energy E.^^ In
actual problems, complex patterns are decomposed into primitive figures. If all prim-
itive figures are rectangles, a pattern comprised of N rectangles has 5A^ adjustable
parameters, that is, four geometric parameters (two x values and two y values) and
one exposure parameter per rectangle. The proximity function (Eq. 77) is used to cal-
culate the dose due to exposure of the ith primitive figure with area A,
A = JJf(r) dx dy (78)
For rectangles, Eq. 78 provides an analytic solution. Next we define a set of M
numbers, whose values express the quality of the correspondence between the
predicted and the desired patterns. We limit each primitive figure to only one

424 VLSI Technology
I —
VIA.A JU~
-4-2 2 4
DISTANCE FROM CENTER OF PRINCIPAL LINE (/i.m)
(a)
-4-2 2 4
DISTANCE FROM CENTER OF PRINCIPAL LINE (/im)
(b)
Fig. 30 Energy distributions (a) Top: Lateral distribution of energy deposited in the film by 20-keV elec-
trons at different levels in the film. Bottom: The simulated profile for the latent image using developer
parameters: A = 1 A/s, B = 8.0 x 10"^'' {cm'/ktM)-, and n = 2.0 (appropriate for PMMA in 1:1
MIBK-lPA). Only the profile corresponding to the first line to reach the substrate (Si) surface is shown;
Q = 80 |j,C cm"-, (b) Top: The curves give the lateral distribtuion of energy deposited at different levels
in the resist film with dose modulation of 1.111 on the outer two lines and 1.041 on the inner two lines
(1 .(XX) for the center line) of the five-line array of 0.5-|jLm lines and gaps. Bottom: Simulated developed pro-
file for the latent image above. Note that all five lines now reach the substrate surface at the same time;
Q = 80 fx C cm ~-, developer parameters are the same as in (a). (After Kyser and Pyle, Ref. 42.)

Fig. 31 Schematic of the proximity function fir ) for arbitrary resist, substrate, and for incident electron
energy. The forward-scattered electron distribution ( ) has a characteristic width Py , while the
backscattered-electron distribution (
) has a characteristic width p^, . (After Parikh. Ref. 45.)
adjustable variable (M = A^)."^^ The single parameter is the primitive figure exposure
£,; the single quantifier M, is the average dose in the primitive figure. Using Eq. 78,
we can calculate the average dose in the jth figure due to exposure of the ith figure:
1
^J A,
(79)
The total average dose in the jth figure is the sum of all contributing component doses
D, = 2^; (80)
where Dp is linear with respect to the exposures and is expressed in the form
Dji = EiKji
and the Kji are symmetric in / and j {Kij =Kji).^
Setting each of the D, equal to some average dose D results in A^ equations
£"1^:11 + £2^12 + + En^in ~ D
E]kj] + EikMj + •••
+ E„kMM — D
li^Nl ni^NN
(81)
(82)
This system can be solved to yield values for all Ej
.
The quality of correction that can be achieved with this algorithm is limited by

426 VLSI Technology
the subdivision of the total pattern into primitive figures. The increase in the number
of shapes can be controlled by partitioning a pattern only at those locations that are
influenced most strongly by proximity effects. "^^
The strategy for partitioning a pattern
is as follows:
1
.
Attempt a proximity correction at a given pattern.
2. Assess pattern quality.
3. If the pattern quality test fails at certain points, subdivide such points and their
associated regions.
4. Reattempt correction.
This procedure is repeated until the pattern quality is sufficient or until it
becomes impossible to subdivide the pattern given the technical limitations of the
electron-beam machine.
Applying this algorithm to the eight rectangles in the pattern shown in Fig. 32a
(a)
(b)
Fig. 32 Partitioned pattern (a) A pattern consisting of eight rectangles. Note regions (i) to (iv) where prox-
imity corrections are needed to complete by dissolve of the resist as well as pattern fidelity. If this pattern is
not proximity corrected, a relative exposure value of unity is given to each rectangle. If this pattern is
corrected via the self-consistent algorithm, a relative exposure value (noted in the figure) is given to each
rectangle, (b) Partitioned pattern with 21 rectangles that are obtained by using the algorithm described in
Sec. 2. The self-consistent algorithm was used to compute the relative incident electron exposures for each
of the rectangles computed. (After Parikh and Schreiber. Ref. 47.)

Process Slvili^ation 427
leads to the partitioned pattern in Fig. 32b. Note the regions (i) to (iv) in Fig. 32a,
where proximity effects necessitate corrections for complete dissolution of the resist
and for pattern quality. If this pattern is corrected by the algorithm given by Eqs. 79
through 82, a relative exposure as noted in the figures is given to each rectangle.
10.5.3 Ion Beam Lithography
Ion beam lithography can achieve higher resolution than optical, x-ray, and electron
lithographic techniques because:
1
.
Ions have a higher mass and therefore scatter less than electrons.
2. Resists such as PMMA are more sensitive to ions than to electrons.
3. Ion beams (like electron beams) can be used both in an efficient projection print-
ing mode and in a focused-beam direct-writing mode.
The simulation of ion-beam lithography is similar to electron-beam calculations
and is based on MC calculations."^^ Figure 33 shows simulated trajectories for 50 H"*"
ions implanted at 60 keV into PMMA and various substrates. The following points
should be noted:
1. The spread of the ion beam at a depth of 0.4 xm is about 0.1 |jim in all cases
(compare with Fig. 26).
2. Backscattering is completely absent for the Si substrate.
3. The amount of backscattering is limited for the Au substrate.
The simulation proceeds analogous to the electron-beam case by convolution of
the delta-line response with the real beam shape (see Eq. 72 or Eq. 74).
0.30 0.20 0.10 0£>0 O.lO 0.20
DISTANCE {fim)
0.20 0.10 0.00 OIO 0.20 0.20 0.10 0.00 0.10 0.20 0.»
Fig. 33 Trajectories of 60-keV H ions traversing through PMMA into Au. Si. and PMMA. (After Kara-
piperis etal., Ref. 48.)

428 VLSI Technology
en 1200
(a:
(b)
0.50 0.40 0.30 0.20 0.10 0.00 0.10 0.20 0.30 0.40 0.50
DISTANCE (fim)
Fig. 34 Histogram of absorbed energy in the xz plane for five 1000-A-wide lines of 60-keV H"*^ ions in the
y direction. Line spacing is 1000 A . (a) Absorbed energy at 400 A . (b) Absorbed energy at 4000 A . (After
Karapiperis etal., Ref. 48.)
Figure 34 shows histograms of absorbed energy in the xz plane for five 0.1-|JLm
lines with 0.1 -|xm spaces for 60-keV H^ implants at two depths of 0.04 |jLm and 0.4
|jLm. Note the limited degree to which the absorbed energy spreads. At the interface
between the PMMA and Si, the overlap between neighboring lines at the midpoint of
their separation is extremely small (1/80 of the peak value; compare this value to that
in Fig. 30). Proximity effects are therefore negligible which is also reflected in simu-
lated development profiles obtained by the same technique as in the electron-beam
case. Figures 35a and b shows developed profiles for a high dose, 2 x 10"^ C cm~^,
and a low dose, 0.6 x 10"^ C cm~^. The developed lines have vertical profiles and
the shape of the walls is unaffected by the exposure of the neighboring lines.
10.6 ETCfflNG AND DEPOSITION
In silicon processing, etching and deposition steps become more and more important
as device sizes shrink. The control of the etched profiles and the shapes of deposited
layers have a direct impact on the performance of the final device and circuit. Dry
etching techniques (Chap. 8) are necessary to achieve the fine linewidth in VLSI tech-
nologies. These techniques range from chemical, isotropic processes to directional,
physical processes (ion milling) with mixed physico-chemical techniques, such as
reactive-ion etching, in between. In most IC processes, at least two layers of inter-
connect are used. These layers are obtained by depositing and patterning polysilicon
and Al. Low-temperature processing requirements, together with the enhanced aniso-
tropic etching techniques results in steep edge profiles that are difficult to cover with a

- (a)
(b)
0.50 0.40 0.30 0.20 0.10 0.00 0.10 0.20 0.30 0.40 0.50
DISTANCE (/xm)
Fig. 35 Developed profiles in PMMA. Five incident 1000 A-wide lines, 1000 A apart, of 60-keV H"^ ions.
1:1 (MIBK:IPA) developer, (a) Dose: 0.6 x 10"" C cm"-. Profiles after 1, 3, 5, 7, and 9 min. (b) Dose:
2.0 X 10"^ C cm"-. Profiles after 15, 30. 45. 60. and 75 s. (After Karapiperis et a!.. Ref. 48.)
film of uniform thickness. Simulation of the deposition is needed to produce accurate
results that can help to optimize a particular source-substrate situation.
10.6.1 The String Model Algorithm
From the simulation point of view, both etching and deposition are problems which
are essentially geometric in nature. In the string model, the boundary between pro-
cessed and unprocessed regions (e.g., developed and undeveloped regions during
etching) is approximated by a series of points joined by straight line segments.
"^^'^^
The resulting profile is determined by the initial profiles that move through a medium
in which the speed of propagation is a function of the local variables at each point.
Consider the examples in Figs. 36a and b, which illustrate the application of the string
model algorithm to isotropic and anisotropic etching. A typical isotropic etching case
equivalent to this case is the development of a silicon layer being plasma etched in a
fluorine source such as CF4 or SFg. The basic reaction
Si + 4F ^ SiF, (83)
describes the chemistry of the process. If only free fluorine radicals are present, the
etching proceeds isotropically wherever the absorption of fluorine has exposed the Si.
Under these isotropic conditions, the etching is simulated by advancing all string
points at a constant rate in the direction of the perpendicular bisector of the adjacent
elements. The anisotropic etch rate is proportional to the cosine of the angle between
the flux direction and the surface normal as in Fig. 36b. In the extreme case, shadow-
ing can occur as illustrated in Fig. 36c. To incorporate the shadowing mechanism,

430 VLSI Technology
1
(7^
ISOTROPIC
INCIDENT
BEAM
ANISOTROPIC
(a )
i
INCIDENT
BEAM
i
>SHADOWED
POINTS
(b)
0=00
INCIDENT
BEAM 1 '
^V /-POINT
^^x^
n -
"local 2
(c) (d)
Fig. 36 Application of the string model to isotropic and anisotropic etching and the extreme ion milling
situation, (a) and (b) Isotropic and anisotropic advances of points along line edge profile, (c) Shadowed
points along a string, (d) Extraction of local angular orientation in ion milling model.
the positions of all points are considered with respect to a line parallel to the radiation
flux. Points that are shaded by other segments are advanced according to the isotropic
background rate. Ion milling or sputtering simulation'"' uses the same point advance-
ment and shadowing algorithm as directional etching. In addition, average angular
information is taken from adjacent segments and the incident ion beam. The ion mil-
ling situation is presented schematically in Fig. 36d. In SAMPLE,^" the etch rate is
modeled along these lines according to the sputtering yield
Sid) - 5( A cos + fi COS" 6 + C cos"* (84)

where Sq, A, B, and C characterize the sputtering yield of the material to be ion
etched, p is the atomic layer density, and (b is the current density of the ion flux.
With the string model, the growth of films through deposition is simulated by
reverse etching. The advancement of each point of the line-edge profile is controlled
by the deposition conditions. During the advancement, string segments that become
very long or very short are adjusted automatically by adding and deleting points.
10.6.2 Etching
A number of plasma etching processes can be classified^
^'^"^
empirically as isotropic
and anisotropic. Figure 37 clearly illustrates the nature of those two processes. A
layer of polysilicon is anisotropically etched below a layer of isotropically overetched
silicon dioxide. The upper figure shows the simulated result, ^^' ^° which demonstrates
the two separate etching components. The simulation uses the isotropic component in
the etching of the Si02 layer first and then proceeds with the anisotropic component in
the silicon. The result ought to be compared to the experimental data at the bottom of
Fig. 37. By identifying isotropic and anisotropic components from experimental
information, a complete dry etching process can be simulated. Figure 38 compares
simulated results^^ with an SEM micrograph for a reactive-ion etched Si02— Si struc-
ture covered by AI2O3. The etch rates used in the simulation are obtained from exper-
imental data.^^^ Si02 etches more anisotropically, while the silicon shows a more
chemical isotropic etch during the process.
An ion milling example^' is given in Figs. 39a and b. Experimental results for a
hard Ti mask on a soft Au layer or silicon are shown in Fig. 39a. A 0.4-|xm thick Ti
layer is deposited by a lift-off process and pure Ar is used during ion milling. Note
that the Ti facets at an angle of 45°. After 4 min, this facet reaches the Au interface.
For short milling times (2 min), the resulting Au profile is vertical but becomes less
steep for longer times. The corresponding simulation result in Fig. 39b clearly repro-
duces with high accuracy all phenomena found experimentally.
10.6.3 Deposition
The simulation of deposition profiles uses the same string model algorithm that the
etching model uses. The following assumptions are made in this simulation:^^'
^"^
1. The mean free path of the atoms is larger than the distance between the source
and the substrate.
2. The source-to-substrate distance is large compared to the step height.
3. The magnitude of the film growth rate follows the cosine distribution law; that is,
the growth rate is proportional to cos a where a is the angle between the vapor
stream and the surface normal.
4. The growth direction is toward the vapor stream.
5. The sticking coefficient is set to one for a cold substrate.
6. At elevated temperatures, surface migration on the substrate follows a random-
walk law. An increase of the substrate temperature increases the migration
distance.

432 VLSI Technology
PHOTO RESIST ^)
Si02
OT^m

POLY -Si
1 O/im
v
1
RESIST
SiOj
POLY- Si
SiOo
S/i
Fig. 37 Isotropic undercut followed by anisotropic etch: simulation (after Reynolds. Neureuther, and Old-
ham. Ref. 50) and experiment {after Mogab andHarshberger. Ref. 52).

3
AI2O3
440 A/min
2 O^m
Si o
770 A/min
2.0/i.m
c- -'^^^^^^^^^H
^H
1^1
^SioJI
.•-.,'^'î^H ^Hj^^^^l
-* '
:• ^â ^^^^^^^^^^H
Êll^^ppr
13,500 X
Fig. 38 Reactive ion etching of SiOT and Si: simulation (after Reynolds. Neureuther, and Oldham. Ref. 50)
and experiment (after Schwartz. Rothman. atid Schopen. Ref. 53).

434 VLSI Technology
2 min
m ^^
6 min
4 min
(a)
8 min
?nl . . . I . , , I I ... I ... I I , I . , . I , , .
(b)
DISTANCE (^m)
Fig. 39 Example of ion milling (a) SEM micrograph of a 0.4-|xm Ti (lift-off) mask on 1 |jLm of evaporated
Au or Si. (b) Simulation of the ion niilling in (a). (After Neureuther. Liu, and Ting. Ref. 51 .
)
Deposition results depend strongly on the type of evaporation source actually
used. For a unidirectional source as in Fig. 40a, the vapor stream arises at the surface
in one direction only. No film growth can occur in shadowed regions. For unshad-
owed points, the growth rate is expressed as
R{x,z) = C sin ttji + C cos aik (85)
where ai is the angle between the z axis and the vapor stream, i and k are the unit
vectors in x and z directions, respectively, and C is the growth rate of an unshadowed
surface normal to the vapor stream. In the case of dual evaporation sources (Fig.
40b), each point in an unshadowed region is exposed to two vapor streams, allowing
the growth rate to be written as
/?(jc,z) = C sin ai + sin a2 i + C cos ai + cos a (86)

VAPOR STREAM
U,
SOURCE I
SOURCE 2
.VAPOR STREAM /^
D
IQ
L
r
u,
VAPOR STREAM
(a)
(b)
(c)
Fig. 40 Evaporation sources (a) Unidirectional; (b) dual evaporation; (c) hemispherical.
For a hemispherical source (Fig. 40c) the vapor flux is distributed in a range of direc-
tions with the growth rate
Rix,z) = C cos ai — cos a2 i + C sin a2 — sin aj k (87)
where a] and a2 are the lower and upper bounds of the incident angles of the vapor
streams.
A planetary system is shown in Fig. 41. In this configuration, the rotation of the
planet along the system control axis does not affect the deposition rate. The growth
rate is calculated by holding the planet stationary and rotating only the source along
the planet axis. The growth rate for a deposition from all angles between a^m ^^d
^maY A^
55
RAx,z) = f Ax, (a - p) ^a (88)

436 VLSI Technology
SUBSTRATE
CO
PLANET /TT/' ^
CENTRAL AXIS
SUBSTRATE /,
/^ PLANET AXIS ^
Fig. 41 Schematic planetary evaporator geometry. (After Blech. Fraser, and Haszko, Ref. 55.)
and
R,(x,z) = J Az,(a - 3) da (89)
The variables A j, (a) and A z, (a) are given by
Ax, (a) = /(co) cos 6" tan a
dw
Az,(a) = /((d) cos e
,,_^
Ja
(90)
(91)
where / (co) dw is the amount of material arriving per unit area of the wafer for a rota-
tion dw.
1 +
/M -
f
/?2
rL
R'~
tan (a - p)
(92)
1 +
r
1
"*
~
2
0)
1 +
R_ r
/? L L
2r
— tan (a - P)
3/2

and 0" is the angle between z and the vapor stream. The cone source is the special
case of a planetary source with (3 = r =0. Equations 89 through 92 can be
evaluated analytically to
R,{xa^ = -
R{R~ + UN)
(R + L )-V/?2 + y/2
(93)
R^{x,z) arcsin
R
tan a, — arcsin
L
— tan a^
L(i?' + LW)
{R' + l")Vr^TW-
(94)
Figure 42 shows an example of a simulated equal-time contour for a planetary eva-
porator.''^ The shadow of the surface results in a thinning of the deposited material
both on the face and the bottom of the step. Small cracks appear at the boundary
between the shadowed and unshadowed regions and at the bottom of the vertical step.
Simulated and experimental results for l-|xm lines and spaces are compared in Fig.
43. In the symmetric case (Fig. 43a), a slight depression caused by shadowing from
both sides is predicted. In the asymmetrical case, the dip on the left and the partial
deposition on the right show good agreement.
DISTANCE (^m)
Fig. 42 Simulated time evolution of surface contours for Al deposition. (After Ting and Neureuther,
Ref.56.)

438 VLSI Technology
1.0
2.0/j.
PLANETARY
SOURCE
DISTANCE (pn)
(a) (b)
2.0/x
PLANETARY
SOURCE
DISTANCE (/xm)
(C) (d)
Fig. 43 Simulation and experimental comparison for l-^-m lines and spaces. 2-in wafer located in the out-
board planet position of an Airco Temescal 1800 system, (a) and (b) Theory and experiment for symmetri-
cal case; (c) and (d) asymmetrical case. (After Ting andNeureuther, Ref. 56.)

10.7 DEVICE SIMULATION
For the device design to be successful, process simulation has to be coupled to device
modeling to account for the interrelation between processing and device behavior.
Device modeling is based on the numerical solution of the coupled nonlinear partial
differential equationsr^'' which model the intrinsic behavior of semiconductor devices.
Depending on the problem, one-dimensional''^ or higher-dimensional models^^ are
required. In the following we consider a NMOS process for the fabrication of submi-
crometer size MOSF^Ts.-''^ Electron-beam lithography with a novel multilevel resist
structure defines the pattern. Dry etching techniques transfer the patterns. Table 1
summarizes the wafer process. At all lithographic levels a three-layer resist structure
is used (see Chap. 7). At the bottom is a thick layer of HPR resist followed by a thin
intermediate stencil layer of amorphous silicon and an upper layer of electron resist.
Positive (PBS) and negative resists (GMC) are used at different levels. Apart from
the lithographic steps, the fabrication sequences of major importance are chan-stop
and threshold-adjust implants (steps 3. 5, and 7), and the source-drain formation
implant (step 15).
Several low-temperature (T = 900°C) annealing steps occur in the whole process.
All major process steps have been modeled in two dimensions. Figure 14a shows the
total concentration as calculated by simulating the process in Table 1. Figure 44
Table 1 Wafer process outline
(substrate is 6 to 8 Q-cm. B doped)
1. Grow field oxide, 3500 A
2. Ion implant B. ]50keV.2 x lO'- cm"-
3. Active-area level lithography. PBS( -i-) resist
4. Field oxide etch
5. Ion implant B. 150 keV. 0.5 x lO'- cm"- (optional)
6. Depletion level lithography, PBS( + ) resist
7. Ion implant As. 60 keV, 3 x lO'- cm"-
8. Grow gate oxide. 250 A
9. Deposit polysilicon. 1500 A
10. Polycon level lithography. PBS( + ) resist
11. Etch polysilicon: etch oxide
12. Deposit polysilicon, 2000 A
13. Polysilicon level lithography. GMC( — ) resist
14. Etch polysilicon
15. Ion implant As, 30 keV, 7 x lO'^ cm"-
16. Grow thin oxide, deposit PSG. and planarize
17. Window-level lithography, PBS( + ) resist
18. Etch oxide
19. Form silicide
20. Deposit polysilicon plus Al
21. Metal level lithography, GMC( -) resist
22. Etch Al, etch polysilicon
23. Sinter Al, metallize backside

440 VLSI Technology
10''
y 10^6
2
8
z
10'5
05 1 Q5
DEPTH (/im) DEPTH (^m)
(a) (b)
Fig. 44 Calculated doping concentration in the channel of enhancement devices for (a) single and (b) dou-
ble boron implant. The numbers on the curves correspond to the process steps in Table 1 . {After Watts
etal..Ref.59.)
gives calculated doping concentrations in the channel of enhancement devices for the
single (step 3) and double (steps 3 and 5) boron implants, including all heat treat-
ments in the process. With Fig. 14a as input to the two-dimensional device simulator,
excellent agreement between measured and calculated results is obtained, as illus-
trated by the // V characteristics in Fig. 45. Results of similar quality are obtained for
the gate-length dependence of the threshold voltage for both enhancement and deple-
tion devices.
6-
<
#.3
Vgs=1V
o o 9 o o o 9
t 2 3 4
Vds(v)
Fig. 45 Measured (full lines) and calculated (full dots) results of enhancement device with L = 0.62 |xm,
IV = 30 (xm. (After Watts et al.. Ref. 59.)

This chapter summarizes the relevant theory and provides examples of process simu-
lation. Theoretical results have been minimized by referencing the important litera-
ture. The material presented, together with the references at the end, should enable
the reader to understand the basic features and goals of process simulation.
Process simulation is a rapidly expanding field and the literature is growing.
With the exception of several theoretical papers, most references cited are from the
late 1970s with the bulk being published in the last few years. We can expect
increased sophistication in computer programs together with an improved understand-
ing of physical processes to take over the job of designing new processes and devices
completely. Optimization of processes will become an automatic tool in the 1980s.
Process and device simulation coupled with circuit simulation will be user-oriented.
In the future, a total design system will allow on-line process design to predict the
desired device and circuit parameter sensitivities, and to facilitate circuit design and
layout with given design rules.
REFERENCES
[1] R. Reif, T. I. Kamins, and K. C. Saraswat, "A Model for Dopant Incorporation into Growing Silicon
Epitaxial Films. I. Theory." 7. Electrochem. Soc, 126, 644 ( 1979).
[2] R. Reif, T. I. Kamins, and K. C. Saraswat, "'A Model for Dopant Incorporation into Growing Silicon
Epitaxial Film. H. Comparison of Theory and Exf)eriment,'" 7. Electrochem. Soc, 126, 653 (1979).
[3] R. Reif and R. W. Dutton, "Computer Simulation in Silicon Epitaxy," J. Electrochem. Soc, 128,
909(1981).
[4] D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, "SUPREM-II-A Program for IC Process Model-
ing and Simulation," Stanford Electronics Laboratories Technical Report No. 5019-2, June 1978.
[5] P. H. Langer and J. I. Goldstein, "Impurity Redistribution during Silicon Epitaxial Growth and Sem-
iconductor Device Processing," J. Electrochem. Soc, 121, 563 (1974); see alsoy. Electrochem. Soc,
124,591(1977).
[6] M. M. Faktor and I. Garrett, Growth of Crystals from the Vapor, Chapman and Hall, New York,
1974.
[7] J. Gibbons, W. S. Johnson, and S. Mylroie, Projected Range Statistics, 2d ed., Wiley, New York,
1975.
[8] B. Smith, Ion Implantation Range Data for Silicon and Germanium Device Technologies, Research
Studies Press. Oregon, 1977.
[9] D. H. Smith and J. F. Gibbons, "Application of the Boltzmann Transport Equation to the Calculation
of Range Profiles and Recoil Implantation in Multilayered Media," in F. Chemow, J. A. Borders, and
D. K. Brice, eds.. Ion bnplantation in Semiconductors 1976, Plenum, New York, 1977.
[10] L. A. Christel and J. F. Gibbons, "An Application of the Boltzmann Transport Equation to Ion Range
and Damage Distributions in Multilayered Targets," 7. Appl. Phys., 51, 6176 (1980).
[11] M. T. Robinson and I. M. Torrens, "Computer Simulation of Atomic Displacement Cascades in
SoUds in the Binary Collision Approximation," Phys. Rev., B9, 5008 (1974).
[12] J. P. Biersack and L. G. Haggmark, "A Monte Carlo Computer Program for the Transport of Ener-
getic Ions in Amorphous Targets," Nucl. lustrum, and Methods, 174, 257 (1980).
[13] S. Kalbitzer and H. Oetzmann, "Ranges and Range Theories," Radiat. Eff., 47, 57 (1980).
[14] W. D. Wilson, L. G. Haggmark, and J. P. Biersack, "Calculations of Nuclear Stopping, Ranges and
Straggling in the Low Energy Region," Phys. Rev., B15, 2458 (1977).

442 VLSI TECHNOLCX3Y
C. Lehmann, Interaction of Radiation with Solids and Elementary Defect Production. North-Holland,
New York, 1977.
T. Hirao, K. Inoue, S. Takayanagi, and Y. Yaegashi, "The Concentration Profiles of Projectiles and
Recoiled Nitrogen in Silicon after Ion Implantation Through Si3N4 Films," J. Appl. Phys., 50, 193
(1979).
W. K. Hofker, D. P. Oosthoek, N. J. Koeman, and H. A. M. de Grefte, "Concentration Profiles of
Boron Implantations in Amorphous and Polycrystalline Silicon," Radiat. Eff., 24, 223 { 1975).
D. K. Brice, Ion Implantation Range and Energy Deposition Distributions, IFI/Plenum, New York,
1975.
A. DeSalvo and R. Rosa, "A Comprehensive Computer Program for Ion Penetration in Solids,"
Radiat. Eff., 47, 117(1980).
A. DeSalvo and R. Rosa, "Monte Carlo Calculations on Spatial Distribution of Implanted Ions in Sili-
con," Radiat. Eff., 31, 41 (1976).
R. W. Dutton, H. G. Lee, and S. Y. Oh, "Simplified Two Dimensional Analysis for Time Dependent
Carrier Transport and Impurity Redistribution," in B. T. Browne and J. J. H. Miller, eds.. Numerical
Analysis of Semiconductors Devices and Integrated Circuits, Boole Press, Dublin, 198 1
.
S. M. Hu and S. Schmidt, "Interactions in Sequential Diffusion Processes in Semiconductors." J.
Appl. Phys., 39. 4212 (196?,).
H. Ryssel, K. Miiller, K. Haberger, R. Henkelmann, and F. Jahnel, "High Concentration Effects of
Ion Implanted Boron in Silicon," A/^p/. Phys., 22, 35 (1980).
M. Y. Tsai, F. F. Morehead, and J. E. E. Baglin, "Shallow Junctions by High-Dose As Implants in
Si: Experiments and Modeling." J. Appl. Phys.. 51. 3230 ( 1980).
B. R. Penumalli. "Lateral Oxidation and Redistribution of Dopants." in B. T. Browne and J. J. H.
Miller, eds.. Numerical Analysis of Semiconductor Devices and hitegrated Circuits: Boole Press, Dub-
lin, 1981.
B. R. Penumalli, "Numerical Methods for Process Simulation," Joint IEEE, SIAM Conference on
Numerical Simulation of VLSI Devices, Nov. 2-4, 1982, Boston.
A. M. Lin, D. A. Antoniadis, and R. W. Dutton, "The Oxidation Rate Dependence of Oxidation-
Enhanced Diffusion of Boron and Phosphorus in Silicon," 7. £'/^frraf/2£'w. Soc, 128. 1131 (1981).
D. Chin, R. W. Dutton. and S. M. Hu. "Two-Dimensional Modelling of Local Oxidation," presented
at the 40th Device Research Conference, Ft. Collins. Colo.. June 21-23. 1982.
R. S. Varga, Matrix Iterative Analysis. Prentice-Hall. Englewood Cliffs, N.J.. 1962.
D. Chin. M. Kump. and R. W. Dutton. "SUPRA-Stanford University Process Analysis Program,"
Stanford Electronics Laboratories Technical Report, July 1981
.
L. A. Hageman and D. M. Young, Applied Iterative Methods. Academic, New York, 1981. A pro-
gram called ITPACK is available from these authors which contains all methods described in this refer-
ence.
"SAMPLE 1.5 User's Guide," University of California at Berkeley, 1982.
B. J. Lin, "Optical Methods for Fine Line Lithography," in R. Newman, ed.. Fine Line Lithography.
North-Holland. New York, 1980.
M. C. King, "Principles of Optical Lithography," in N. G. Einspruch, ed., VLSI Electronics—
Microstructure Science, Vol. 1, Academic, New York, 1981.
W. G. Heitman and P. M. van der Berg, "Diffraction of Electromagnetic Waves by a Semi-Infinite
Screen in a Layered Medium," Can. J. Phys.. 53, 1305 ( 1975).
M. M. OToole and A. R. Neureuther, "Influence of Partial Coherence on Projection Printing," SPIE,
Vol. 174, Developments in Semiconductor Microlithography IV, 22 (1979).
F. H. Dill, A. R. Neureuther, J. A. Tuttle, and E. J. Walley "Modelling Projection Printing of Posi-
tive Photoresists," IEEE Trans. Electron Devices, ED-22, 456 ( 1975).
P. H. Beming, "Theory and Calculations of Optical Thin Films," in G. Hass, ed.. Physics of Thin
Films. Vol. 1, Academic, New York, 1963.
D. F. Kyser and K. Murata, "Monte Carlo Simulation of Electron Beam Scattering and Energy Loss in
Thin Films on Thick Substrates," in R. Bakish, Proceedings of the 6th International Conference on
Electron and Ion Beam Science and Technology, The Electrochemical Society, Princeton, N.J. , 1974.
R. J. Hawryluk, A. M. Hawryluk, and H. I. Smith, "Energy Dissipation in a Thin Polymer Fibn by
Electron Beam Scattering," J. Appl. Phys. . 45, 255 1 (1974).

[41] J. S. Greeneich. "Electron Beam Processes," in G. R. Brewer ed., Electron-Beam Technology in
Microelectronic Fabrication. Academic, New York, 1980.
[42] D. F. Kyser and R. Pyle, "'Computer Simulation of Electron-Beam Resist Profiles," IBM J. Res.
Develop., 24 A26(19S0).
[43] D. F. Kyser, D. E. Schreiber, C. H. Ting, and R. Pyle, "Proximity Function Approximations for
Electron-Beam Lithography From Resist Profile Simulation," in R. Bakish ed.. Proceedings of the 9th
International Conference on Electron and Ion Beam Science and Technology, The Electrochemical
Society, Princeton, N.J., 1980.
[44] N. D. Wittels, "Fundamentals of Electron and X-Ray Lithography," in R. Newmann ed., Fine-Line
Lithography, North-Holland, New York, 1980.
[45] M. Parikh, "Corrections to Proximity Effects in Electron-Beam Lithography. I: Theory. 11: Implemen-
tation, m: Experiments," y. Appl. Phys.,5(i, 4371, 4378, 4383 (1979).
[46] T. H. P. Chang, "Proximity Effect in Electron-Beam Lithography," J. Vac. Sci. Technol., 12, 1271
(1975).
[47] M. Parikh and D. E. Schreiber, "Pattern Partitioning for Enhanced Proximity—Effect Corrections in
Electron-Beam Lithography," IBM J. Res. Develop., lA, 530 ( 1980).
[48] L. Karapiperis, L Adesida, C. A. Lee, and E. D. Wolf, "Ion Beam Exposure Profiles in PMMA-
Computer Simulation," 7. Vac. Sci. Technol., 19, 1259 (1981).
[49] R. E. Jewett, P. I. Hagouel, A. R. Neureuther, and T. van Duzer, "Line-Profile Resist Development
Simulation Techniques," Polym. Eng. Sci., 17, 381 (1977).
[50] J. L. Reynolds, A. R. Neureuther, and W. G. Oldham, "Simulation of Dry Etched Line Edge Pro-
files," J. Vac. Sci. Technol., 16, 1772 (1979).
[51] A. R. Neureuther, C. Y. Liu, and C. H. Ting, "Modelling Ion Milling," J. Vac. Sci. Technol., 16,
1767(1979).
[52] C. J. Mogab and W. R. Harshberger, "Plasma Processes Set to Etch Finer Lines with Less Undercut-
ting," Electronics, 51, 1 17 (1981).
[53] G. C. Schwartz, L. B. Rothman, and T. J. Schopen, "Competitive Mechanisms in Reactive Ion Etch-
ing in a CF4 Plasma," J. Electrochem. Soc, 126, 464 (1979).
[54] W. G. Oldham, A. R. Neureuther, C. K. Sung, J. L. Reynolds, and S. N. Nandgaonkar, "A General
Simulator for VLSI Lithography and Etching Processes: Part U—Application to Deposition and Etch-
ing," IEEE Trans. Electron Devices, ED-27, 1455 (1980).
[55] I. A. Blech, D. B. Eraser, and S. E. Haszko, "Optimization of Al Step Coverage through Computer
Simulation and Scanning Electron Microscopy," 7. Vac. Sci. Technol., 15, 13 (1978).
[56] C. H. Ting and A. R. Neureuther, "Applications of Profile Simulation for Thin Film Deposition and
Etching Processes," Solid State Technology, 25 (2), 115 (1982).
[57] W. Fichtner and D. J. Rose, "On the Numerical Solution of Nonlinear Elliptic PDEs Arising from
Semiconductor Device Modelling," in M. Schultz, ed., Elliptic Problem Solvers, Academic, New
York, 1981.
[58] D. C. D'Avanzo, M. Vanzi, and R. W. Dutton, "One-Dimensional Semiconductor Device Analysis
(SEDAN)," Stanford Electronics Laboratories Technical Report No. 6-201-5, October 1979.
[59] R. K. Watts, W. Fichtner, E. Fuls, L. R. Thibault, and R. L. Johnston, "Electron-Beam Lithography
for Small MOSFETs," IEEE Trans. Electron Devices, ED-28, 1338 ( 1981).
[60] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology, Wiley,
New York, 1982.
PROBLEMS
1 Diffusion from a growing epitaxial layer into an undoped substrate.
Consider the case of an undoped silicon substrate. Suppose we deposit an epitaxial layer with concen-
tration Cq on top of this substrate. Since epitaxial deposition temperatures are usually high, impurities will
diffuse out of the depositing layer into the substrate and vice versa. For a one-dimensional geometry, solve
the diffusion equation.

444 VLSI Technology
2 Diffusion from a doped substrate into an undoped epitaxial layer.
This case concerns putting an undoped layer on a homogeneously doped semi-infinite substrate. The
problem is more difficult than Prob. 1 . because we have to incorporate the fact that some of the dopant that
diffuses into the layer out of the substrate diffuses straight through and evaporates from the growth surface.
A net loss of dopant occurs if the rate that dopant atoms leave the surface at z = is greater than the rate at
which they join it from the ambient atmosphere. For a one-dimensional geometry, solve the diffusion equa-
tion incorporating the evaporation case.
3 Solve the scattering integral
= IT — 2/?
dr
(1)
V{r]
for a repulsive Coulomb potential V (r ) = C/r (Cj >0). Calculate the differential cross section
a(e)
dp
sin ^e
(2)
4 Write a FORTRAN program to calculate Pearson IV distributions.
5 Most frequently, the semiconductor substrate is subjected to a heat cycle after the implantation step, and
the impurities are redistributed. Near the mask edge, this redistribution is obtained by solving the two-
dimensional diffusion equation
dC
= D (1)
assuming intrinsic diffusion conditions. Calculate the analytical solution for the following initial condition
(i.e., profile after implantation)
C{x,z,t = (b)
= C^ [c^Cr.z.r = 0) + CR(x,z,t = 0)
]
where C ^^ is the peak concentration and
Ci^ixj.O) = — exp
2A/?;
erfc
V2AX
(2)
(3)
A/?„
'^'^''''' =
lVto''''
(a„.v + z - R')-
2Dr
1 + erf
-V ^Rp ajz - Rp) AX-
AX AR„
(4)
and
Do = A^/ + a^ AX2 (5)
a^ = tan gives the edge slope of the mask, and ^^ , A/?^ , and AX are the usual Gaussian parameters.
6 Derive Eqs. 93 and 94 for the deposition rates of a cone source.
7 Solve the diffusion problem of redistributing donor and acceptor impurities between Si and Si02 during
thermal oxidation at high temperature. Assume that the initial impurity distribution in the silicon is uniform.
8 Same as Prob. 7, but for a nonuniform initial impurity distribution. Use the method of finite differences
to discreti2e the diffusion equation.

CHAPTER
ELEVEN
VLSI PROCESS INTEGRATION
L. C. PARRILLO
11.1 INTRODUCTION
The integrated circuit (IC) was invented by Kilby' in 1958. Tiie first ICs were phase-
shift oscillators and flip-flops, fabricated in germanium substrates. The individual
components in these circuits were isolated in mesa-shaped regions which had been
etched in the substrate by using black wax (applied by hand) to mask the active
regions. The individual devices were interconnected by wire bonding. These first
working units were used for the first public announcement' of the "Solid Circuit"
(integrated circuit) concept in March 1959. Other critical developments around the
same time included the first modem diffused bipolar transistor by Hoemi.' This
transistor was based on the planar diffused process, a cornerstone of modem IC fabri-
cation, which uses silicon dioxide as a barrier to impurity diffusion. In 1958 a patent
was filed on the first use of p-n junctions for device isolation and in 1959 a patent was
filed for an IC that used evaporated aluminum metallization over an oxide layer to
provide interconnections.'
From these early primitive forms, ICs have evolved into complex electronic de-
vices containing hundreds of thousands of individual components on a single chip of
silicon. The first ICs were based on contributions from many different fields includ-
ing device physics, materials science, and chemistry. Interdisciplinary contributions
continue to be sought today in the development of new IC technologies.
Since the most important part of the IC is the transistor, this chapter focuses on
processing techniques which are used to optimize its characteristics. The major IC
technologies discussed are standard bipolar (n-p-n), integrated injection logic (I"L),
n-channel MOS (NMOS), and complementary MOS (CMOS). Table 1 gives a gen-
eralized comparison of these various devices as integrated transistors." We assume
445

446 VLSI Technology
Table 1 Characteristics of integrated transistors^
NMOS CMOS n-p-n I^L
1. General
Supply voltage range + + + - +
Power + + + - +
Speed + + + + +
Transconductance - - + + + +
Circuit density + + + - +
Drive capability
— + + + +
2. Digital
Switching speed + + + + + + +
Power + + + - +
Noise margins + + + - -
Logic swing - + + — —
3. Analog
Gain per stage
- + + +
Bandwidth - - + +
Input impedance + + + + -
Power + + + + -
Output swing - + + +
Linearity
- + + +
Analog switches + + + -
Precision elements + + + + +
Note: The symbols represent moderate (-), good ( + ), and
superior ( + + ) behavior.
that the reader has a familiarity with the basic principles of operation of these devices.
For reference, see texts on device physics written by Grove, ^ MuUer and Kamins,'^
Streetman,^ and Sze.^
11.2 BASIC CONSIDERATIONS FOR IC PROCESSING
11.2.1 Process Flow
Figure 1 illustrates the main steps in an n-channel, polysilicon-gate, metal-oxide-
semiconductor (MOS) IC fabrication process.^ The formation of the IC comprises
many steps which have been discussed in previous chapters such as ion implantation,
diffusion, oxidation, film depositions, lithography, and etching. These steps provide
precisely controlled impurity layers in the silicon which form the individual circuit
components (i.e., transistors, diodes, capacitors, resistors) as well as the dielectric
and metallic layers used for interconnecting the individual components into an IC.
The fabrication steps, which must proceed in a specific sequence, constitute an IC
process flow (or process). When the process is properly executed, each wafer con-
tains a number of individual ICs which will later be separated and packaged.

VLSI Process Integration 447
SUBSTRATE ION IMPLANT OXIDATION DEPOSITION
BORON DOPED
SILICON:
20n-cm
<100>
GETTER:
ARGON INTO
BACKSIDE
PAD OXIDE SILICON NITRIDE:
0.1^m
OXIDATION
-«
—
ION IMPLANT
4
ETCH
4—
LITHOGRAPHY
'
FIELD OXIDE;
0.45 /xm
CHAN-STOP:
3x10^2B/cm2_
60keV
DRY ETCH:
NITRIDE/PAD
OXIDE
ISOLATION
PATTERN
'
ETCH
—
ION IMPLANT OXIDATION
—
LITHOGRAPHY
WET ETCH:
NITRIDE /PAD
OXIDE
ENHANCEMENT Vj
ADJUSTMENT:
8x10"B/cm2,
35keV
GATE OXIDE:
250A
DEPLETION
IMPLANT
PATTERN
DEPOSITION
4
ETCH
<
LITHOGRAPHY
*
ION IMPLANT
LPCVD
POLYSILICON:
0.35^m
WET ETCH:
GATE OXIDE
BURIED
CONTACT
PATTERN
DEPLETION Vt
ADJUSTMENT:
3x10^2^5/j,|.^2
80keV
DIFFUSION DEPOSITION LITHOGRAPHY ETCH
DOPE
POLYSILICON
n+: PHOSPHORUS
DIFFUSION
SOURCE
LPCVD
MASK OXIDE:
0.1/xm
POLYSILICON
GATE
PATTERN
DRY ETCH
:
MASK OXIDE
OXIDATION
<
ETCH
4-^
ION IMPLANT
4
ETCH
SOURCE, DRAIN,
POLYSILICON
OXIDE:
O.l^m
WET ETCH:
MASK OXIDE
SOURCE/DRAIN:
1 x10^^As/cm2,
eOkeV
DRY ETCH:
n+ POLYSILICON
DEPOSITION LITHOGRAPHY
—
ETCH DEPOSITION
LPCVD
INTERMEDIATE
OXIDE:
0.35^m
CONTACT
WINDOW
PATTERN
DRY ETCH:
INTERMEDIATE
PLUS THERMAL
OXIDE
SPUTTER
A£
METALLIZATION:
0.7/i.m
ANNEAL
*
ETCH
-
ETCH
4
LITHOGRAPHY
'
HYDROGEN
ANNEAL
REMOVE
BACKSIDE
FILMS
DRY ETCH:
Af
METALLIZATION
METAL
INTERCONNECT
PATTERN
Fig. 1 Main steps in an n-channel, polysilicon-gate, MOS, IC process flow. (After Siqusch et ai, Ref. 7.)

448 VLSI Technology
11.2.2 Interrelation of Process Steps
Virtually all the steps in a process are strongly interrelated—a few examples are cited
here. Each of the thermal cycles in a process (e.g., oxidation, epitaxial layer growth,
glass flow, gettering) add to affect the vertical and lateral diffusion of impurities. To
obtain the desired impurity profiles, the total thermal cycle that the impurity under-
goes must be taken into account. Because silicon dioxide is often grown at the same
time on several different types of exposed silicon regions, its thickness can be dif-
ferent on the various regions—depending on how heavily doped the silicon is, the
impurity type (n or p), whether it is single-crystal or polycrystalline silicon (polysili-
con), and if an implanted area has been thermally annealed or not. The resulting
variety of oxide thicknesses must be accounted for, if, for example, the oxide films
are to be simultaneously removed, or if implants are to penetrate all oxide layers.
Polysilicon's ability to mask a given implant is a function of the polysilicon's thick-
ness and the size of its crystal grains, since ion channeling can take place through the
grains (see Chapter 6). Grain size is a function of the polysilicon film's doping level
and thermal history—hence the polysilicon's ability to act as an effective mask
against implantation (e.g., source/drain) changes during the process.
Because the process steps are so interrelated, a fundamental rule in an established
process is that no process step is changed arbitrarily. In developing a new process,
especially one with new materials, identifying the interrelationships among the vari-
ous steps can be very challenging.
11.2.3 Process Costs
Since the beginning of the IC era, the cost per electronic function has decreased by
orders of magnitude because finer features and larger substrates have produced more
complex IC chips per wafer. The key to the low cost is batch processing. Individual
groups or "lots" of 20 to 50 wafers are processed together. Although a given process
flow may have more than 100 individual steps, many individual ICs are fabricated
simultaneously. For example, an individual wafer which costs about $200 to produce
(labor, equipment, material, and overhead costs) may yield 100 good chips, for a chip
cost of about $2. A goal of semiconductor processes continues to be to minimize de-
vice cost. This usually translates to simplifying the process flow, since the least com-
plicated processes are the most reproducible and provide the highest yields.
11.3 BIPOLAR IC TECHNOLOGY
A major application of bipolar ICs is in the high-speed memory and logic needs of the
computer industry. The bipolar device has recently taken a new form in integrated
injection logic (I^ L) which is used extensively in low-power, high-density memory
and logic circuits.^ This section describes a basic fabrication sequence for bipolar ICs
and additional considerations for key steps in the device formation. We introduce I- L
device fabrication as well as techniques to avoid emitter-collector leakage currents
—
a major yield limiting mechanism in bipolar ICs.

CONTACTS Si3N4-
Fig. 2 Three-dimensional views of oxide-isolated bipolar transistor. (After Labuda and Clemens, Ref. 9.}
11.3.1 Illustrative Fabrication Process
Figure 2 shows an n-p-n bipolar transistor^ that uses a thick sihcon-dioxide layer to
electrically isolate the transistor. '° Earlier techniques for bipolar isolation relied on a
reverse-biased p-n junction that surrounded the active device. Junction isolation con-
sumed a larger area and introduced larger parasitic capacitances as compared to the
oxide-isolation'^ techniques. Figure 3 shows a process sequence that can be used to
fabricate the device of Fig. 2. Illustrations 3a through f show a top and side view of
the device at several stages of the process.
The starting material is a lightly doped p-type substrate (~10'^ atoms/cm-^), usu-
ally with (1 1 1) or (100) orientation. The substrate is oxidized and a window is opened
in the oxide using the buried-layer mask. Arsenic or antimony is then implanted
through this window, to serve as the heavily doped (n"^) portion of the collector (to
reduce collector resistance). The implanted layer is driven into the substrate in an
oxidizing ambient to form the "buried-layer." Because of the different rates of oxida-
tion between the exposed buried-layer and the surrounding oxide-covered area, a step
forms in the silicon surface at the periphery of the buried-layer (i.e., the buried-layer
region is depressed). All oxide is then stripped and an n-epitaxial layer is grown on
the substrate as shown in Fig. 3a. The step at the buried-layer periphery propagates
up through the epitaxial layer and serves as an alignment mark for the next litho-
graphic level.
After epitaxy growth, a pad layer of Si02 is grown (—500 A) and a layer of
Si3N4 (-1000 A) is deposited on the wafer. The Si3N4 layer does not oxidize
readily and thus prevents the oxidation of the underlying silicon. The thin oxide pad
serves as a buffer layer to protect the silicon from stress-induced defects during sub-
sequent high-temperature oxidation steps.'' The isolation lithography is done next as

450 VLSI Technology
BURIED-LAYER MASK ISOLATION MASK
(a)
"1
[
1 BORON IMPLANT!
( 1 i
r >
<K?<x»^ Cx^^xV
(
• « • • • • • •
^
n+ 1
.^^ P
_^
(c) (d)
A
CONTACT MASK
r
-J
1
-' ~1 1
1 1
1 1
1 1
L —._! 1
")a r
EMITTER/COLLECTOR
MASK
1
-
1
1
1
1
I
^RESIST
r^^TMT
(e) (f)
Fig. 3 Top and cross-section views of bipolar transistor fabrication, (a) Buried-Iayer mask and cross-
section after n'^ buried-layer and n-epitaxy growth, (b) Isolation mask and cross section with isolation resist
mask on nitride/pad oxide (depression in epitaxy surface is omitted for clarity), (c) Cross section after
nitride/pad oxide/silicon etch and chan-stop implant, (d) Base mask and cross section after isolation-oxide
growth and boron base implant, (e) Contact mask and cross section after base, emitter, and collector-contact
opening, (f) Emitter/collector mask and cross section after arsenic emitter/collector ion implant (I- ).

shown in Fig. 3b. Figure 3c shows that the resist is used to mask the etching of the
nitride/pad oxide layers as well as approximately half of the epitaxial layer. A boron
channel stopper (chan-stop) implant can also be performed at this point (Fig. 3c).
The purpose of the chan-stop implant is to raise the doping level of the p-type sub-
strate directly under the isolation oxide. This will prevent surface inversion of the
lightly doped p-type substrate which would electrically connect the buried layers.
The resist is then removed and the wafers are oxidized so that all of the remaining
epitaxy that is not protected by Si3 N4 is converted to Si02 (Fig. 3d). The Sis N4 can
then be stripped without disturbing the Si02. Up to this point, the thermal processes
have involved high temperatures or long times. These long thermal cycles are per-
formed before the active transistors are fabricated, to prevent the desired shallow
junctions from being driven in too deeply.
After Si3 N4 removal, the epitaxy can be oxidized and a base implant mask can be
defined using resist (Fig. 3d). The base can be implanted through the oxide so that
ion channeling of the base implant is attenuated and no subsequent oxidation of the
base implant is necessary. ^^ Contact holes to the intended base, emitter, and collector
regions can then be made simultaneously with a single mask (Fig. 3e). In this
fashion, the base-contact to emitter-contact separation is not influenced by an align-
ment step, but is set by the minimum spacing between metal contacts there. '^ This
results in a reduced transistor area as well as a reduced base resistance. As shown in
Fig. 3f, a resist mask can be used to protect the base contact area while the emitter
and collector contact legions are implanted using a high arsenic dose at low energy.
Note that the implanted emitter area is defined by the opening in the oxide over the
exposed base region (Fig. 3f).
An option here is to implant an additional phosphorus dose selectively into the
collector-contact region. The phosphorus can be diffused vertically into the buried-
layer to minimize the vertical component of collector resistance. Also, a separate
higher-dose extrinsic-base implant can be used (e.g., emitter and collector contact
covered by a resist mask) to lower the base contact resistance and to decrease the
lateral base resistance in the extrinsic-base region. Typically this portion of the
extrinsic-base layer can be 50 to 200 H/n in sheet resistance.
After the emitter is implanted, it is driven into the desired depth in a nearly inert
ambient. A very thin oxide results on the emitter, base, and collector contacts and
this can be washed off in a dilute HF solution. There is no reregistration of a contact
window within an oxide-covered emitter area. The washed emitter process minimizes
the emitter area at the risk of allowing the metallization to short out the emitter-base
junction at the periphery. The periphery of the junction is only protected by a dis-
tance equal to the lateral diffusion of the emitter under the oxide.
After the contact areas are washed, a layer of Sit, N4 can be deposited over the
wafers. This layer protects the device from mobile-ion contaminants, such as
sodium, that can diffuse through Si02 and result in junction leakage and surface
inversion. A window can be cut in this nitride sealing layer (requiring another litho-
graphic step), or the window can be formed in a self-aligned fashion. That is, the
nitride can be electrochemically converted (anodized) to SIOt where it contacts the
silicon, while the nitride on oxide layers remains intact.'"^ The anodized oxide can

452 VLSI Technology
then be stripped in dilute HF acid. The remaining nitride layer is undisturbed and has
windows that are self-aligned to the base, emitter, and collector contacts (Fig. 2).
Finally, the metallization layer is deposited and defined as shown in Fig. 2. A
variety of metallization systems can be used, including a single layer of aluminum or
composite structures such as PtSi for contact followed by TiPtAu layers.'^ In addition
to the contacts shown, Schottky-barrier diodes can also be formed in the device (e.g.,
PtSi, Pd2 Si), which can be used to clamp the collector-base junction and also to lower
the signal swing in Schottky I^ L devices.
11.3.2 Key Steps in Device Formation
Buried-layer and epitaxial layer The buried-layer's sheet resistance should be as
low as possible to reduce the collector resistance of the transistor; hence it is heavily
doped. After the dopant is introduced into the substrate, it is driven in to spread out
the doping profile and lower the impurity concentration from its initially high value.
This results in lower sheet resistance of the buried-layer because of the inverse rela-
tionship between carrier mobility and dopant concentration. However, too heavily
doped a buried-layer will cause excessive outdiffusion into the more lightly doped
n-epitaxial collector, and can also cause defects in the epitaxial layer. Antimony or
arsenic are commonly chosen as impurities in the buried-layer rather than phosphorus
because of their smaller diffusion coefficients. Typical buried-layer sheet resistance
values are about 15 to 50 ft / c.
The n-epitaxial layer serves as the collector under the base and is doped in the
10^^ to 10^^ atoms/cm-^ range. The lighter the epitaxy doping, the less collector-base
capacitance the device has. This is a key parasitic capacitance that limits the high-
speed performance of bipolar transistors. A thick enough n-epitaxial layer must be
grown so that the outdiffusion of the buried-layer impurity does not reach the base
region and raise collector-base capacitance. However, too light a doping in the epi-
taxial layer is difficult to control in the epitaxy-growth process because of autodoping
by the buried-layer impurity in the reactor. In addition, at high collector currents the
conductivity of the lightly doped n-epitaxy collector becomes modulated by the col-
lector current. This causes the base-collector junction to be pushed out into the
lightly doped epitaxy, resulting in gain degradation as well as high-frequency per-
formance degradation.^ To avoid this base push-out effect, the doping level in the col-
lector^^ should be greater than J /qv^ where J is the collector current density and v^ is
the saturation velocity (—10'' cm/s).
Isolation Referring to Fig. 3c and d, the isolation oxide is typically grown to a thick-
ness such that the top of the oxide and the silicon surface are in the same plane
(approximately twice the epitaxy thickness) to minimize surface topography. How-
ever, at the periphery of the active silicon areas a "bird's beak" (lateral oxidation
under the silicon nitride) and a "bird's head" (caused by the oxide growth at the
comers of the etched silicon in Fig. 3c) form. These effects are not desirable because
the bird's beak takes up lateral space and the bird's head produces surface topogra-
phy. A variety of exploratory approaches to minimize these effects have been
reported using atmospheric or high-pressure oxidation.'^'
'^

XTSI Process Ltegr.tiox 453
Base formation For a given emitter profile, the lower the total integrated charge is in
the active base (Gummel number), the higher the current gain is.'^ However, if the
base charge is too low it cannot support the reverse-bias oltage which is applied
across the collector-base and /or emitter-base junctions. This results in unwanted
'punchthrough'" current. Also as the base charge is reduced, the output characteris-
tics (i.e.. collector current vs. collector-emitter voltage) exhibit steeper slopes (low-
output impedance), which ma be undesirable in circuit applications. The narrower
the base is. the shorter is the diffusion time of minority carriers across the base. As
the base is made narrower for better performance, the doping level must therefore be
raised to pre'ent punchthrough. In high-frequency bipolar transistors, the base dop-
ing profile is graded from a high to a low value from emitter to collector. This profile
creates a built-m electric tleld m a direction that aids the transit of minority carriers
across the base. Typical base Gummel numbers are in the 10^- to lO'-' atoms cm-
range .
The e.xtrinsic-base region (Fig. 2) must be adequately doped to provide a low-
resistance path to the actie-base region. If the extrinsic base is doped too heavily,
however, excessive emitter-base capacitance will result along the emitter sidewall and
a low emitter-base reverse-breakdown voltage may result. The active- and extrinsic-
base regions can be formed by a single ion-implantation step, as shown schematically
in Fig. 4a. .AJtemativeh'. a doubk-base implant can be employed as shown schemati-
EMITTER
ECTOR
(As)
Fig. 4 n-p-n transistor doping profiles, (a) Single-base implant (schematic), (b) Double-base implant
(schematic), (c) Single-base implant (actual).

454 VLSI Technology
cally in Fig. 4b. The higher-dose, low-energy (shallow-base) implant is used to pro-
vide the extrinsic-base properties while the higher-energy, lower-dose (deep-base)
implant establishes the active-base properties. The common-emitter current gain
varies inversely with deep-base implant dose.'^ The double-base implant technique
allows more flexibility in designing the base structure and allows better control of its
properties.^" Figure 4c shows an actual doping profile of an n-p-n transistor that uses a
single-base implant for both active and extrinsic bases. Because of strong cooperative
diffusion effects between the arsenic emitter and the boron base, the base profile does
not smoothly decrease into the silicon as is shown schematically in Fig. 4a. The
active-base profile in Fig. 4c is both steeply graded and narrow in width for high-
speed applications. Note that the collector doping profile increases with depth above
the epitaxial doping level (~1 x 10^^ atoms/cm-^) because of outdiffusion of the
buried-layer into the relatively thin epitaxial layer.
Emitter formation To improve current gain and to minimize emitter resistance, the
emitter region is heavily doped. Consider a device with total charge in the emitter
region of Qe ~ lO'^ atoms/cm"^ (i.e., a doping level of 2 x 10^*^ atoms/cm-^ for 0.5
|xm). A typical total active-base charge is of the order oi Qg ~ 10^" atoms /cm".
Hence the common-emitter current gain for this device can be of the order of 10"^.
Such high values are generally not observed experimentally, however. To explain the
observed current gain in actual transistors, both bandgap narrowing and Auger recom-
bination must be included (see Chapter 5).
Very abrupt and shallow arsenic emitter profiles can be obtained because of
arsenic's concentration-dependent diffusion. This makes it an attractive choice for an
emitter impurity. '^
As emitters become shallower, the technique used to contact the
emitter becomes increasingly important, since it can affect the current gain of the de-
vice. This is illustrated in Fig. 5, which shows the common-emitter current gain vs.
collector current characteristics for three different shallow-emitter (0.2-|JLm) devices
processed identically except for their emitter contacts. ^^ The insert in Fig. 5 schemati-
cally illustrates the minority-carrier profiles in the emitters of each of these devices"^
at a given injection level {Vbe)- With the aluminum contact, the hole concentration
goes to zero near the original Al-Si interface, where carriers recombine with essen-
tially an infinite recombination velocity. The gradient of holes in the emitter estab-
lishes the base current. The hole gradient is made steeper (more base current) when
Pd2Si is used for the contact, since silicon is consumed during the silicide process.
The base current is reduced when a thin layer (1000 A) of arsenic-doped polysilicon is
placed between the metal and the single-crystal emitter. The recombination velocity
at the interface between the polysilicon and single-crystal silicon is no longer infinite,
and the hole gradient in the emitter is reduced. Current gain can increase by three to
seven times when polysilicon, rather than metal, is used to contact the emitter.^^
Schottky clamps A metallization technique that can be used to keep bipolar transis-
tors out of saturation is the application of Schottky-barrier-diode clamps to the collec-
tor region. Figure 6a illustrates a device without a Schottky clamp. When the
collector-emitter potential is low enough, the collector-base junction becomes

I- <
LU 1-
-z. UJ
15
350
300
250
200
150
100
50
Pn(X)
XjEB=02^r
POLY CONTACT
A I CONTACT
Pd2Sl CONTACT ^^
I I I I mil I I I mill I I I I Hill ml I I
0.001 0.01 1 1.0 10
COLLECTOR CURRENT (mA)
100
Fig. 5 CoiTimon-eminer current gain vs. collector current for shallow-emitter-junction (0.2-|jLm) n-p-n
transistors. Contact to the emitter was niade using n~ polysilicon (poly), aluminum, and Pdi Si on separate
devices. Insert shows a schematic representation of the minority-carrier profile in the emitter for the three
contact schemes at fixed base-emitter potential. (After Ning. Tang, arid Solomon, Ref. 16: Ning and Isaac,
Ref. 20.)
forward-biased and minority carriers flood the base region as well as the n-epitaxial
collector region. Since it takes time to remove these excess carriers from the base, a
delay is introduced when trying to take the transistor out of saturation (i.e., to turn the
transistor off) and circuit performance suffers. To prevent the collector-base from
becoming forward biased, a Schottky-barrier diode to the collector can be formed as
shown in Fig. 6b. A metal-silicide layer simultaneously contacts the n epitaxy and
the p-type base. By choosing a metal-silicide having a high Schottky-barrier height to
n material and, consequently, a low barrier height to p material (e.g., PtSi, Pd2Si,
etc.), the metal-silicide provides an ohmic contact to the base, and simultaneously
produces a Schottky-barrier diode to the n collector (separate ohmic contacts are also
made to the heavily doped n"^ emitter and collector by the metal-silicide). The
Schottky diode conducts current at a smaller forward-bias potential (—0.3 V) than
does the collector-base p-n junction diode (—0.7 V). Since the Schottky diode and
collector-base diodes are in parallel, the collector-base junction is clamped to the
lower potential and thus is prevented from becoming forward-biased enough to con-
duct significant current. As shown in Fig. 6b, at low Vqe potential, electrons injected
from the emitter are essentially returned out of the forward-biased Schottky diode.
The Schottky-barrier height, and hence the forward tum-on voltage of the Schottky
diode, can also be modified by using ion-implantation techniques.-^
A p"^ guard ring can also be used around the periphery of the Schottky diode to
raise its reverse-breakdown voltage (the guard ring reduces the electric field at the

456 VLSI Technology
WINDOW
(a) (b)
Fig. 6 Schottky-diode clamp technique, (a) Schematic top and side view of undamped n-p-n transistor in
saturation; op)en circles denote holes, closed circles denote electrons, (b) Schematic top and side view of
Schottky-clamped transistor with p"*"
guard ring to prevent saturation.
sharp comer of the unguarded diode). Incorporating Schottky clamps and guard rings
causes the transistor area to increase. In addition to clamping the collector-base junc-
tion to prevent saturation, Schottky diodes are used in high-density Schottky transistor
logic^^ and Schottky integrated injection logic circuits."^
11.3.3 Integratedlnjection Logic
Integrated injection^"^ logic (I^L), also called merged transistor logic,^^ has become
an increasingly important application for bipolar transistors. I'^L devices are used
extensively^ in high-density low-power memories, microprocessors, and custom-logic
ICs. Figure 7a and b shows the electrical schematic diagram and cross section of an
I^ L gate.'^^ The basic logic cell is formed by integrating a lateral p-n-p transistor (Q i)
with a vertical n-p-n transistor (Qj) having several collectors. The collector of the
lateral p-n-p transistor also serves as the base of the vertical n-p-n transistor.
The n-p-n transistor operates in the inverse (upside-down) mode with the buried-
layer serving as the emitter (and contact to the base of the p-n-p) and the top n"^ diffu-
sions acting as multiple collectors. For logic implementation, the n-p-n device serves
as an inverter and the collectors are wired to obtain specific logic functions. With a
logic-high input signal (Vm ~ 0.8 V), current is injected from Q i
into the base of ^2'
which is consequently driven into saturation. The outputs are then brought to a
logic-low potential (Vce ~ 0.1 V). Since resistors are replaced by p-n-p current
sources and the inverse-mode n-p-n transistors have automatically isolated collectors
and common emitters, the circuit packing density of I^L devices can be very high.

OUTPUTS
INPUT &
(a)
ARSENIC-DOPED
POLYSILICON CONTACT
TO COLLECTOR C3
(b)
Fig. 7 Integrated injection logic, (a) Circuit diagram, (b) Three-dimensional view of structure with self-
aligned base and collector contacts . (After Tang etal., Ref. 26.)
I^L fabrication is compatible with conventional bipolar processing so that various
bipolar circuit forms can be realized on the same chip.
The I^L structure of Fig. 7b uses fully recessed oxide isolation. Arsenic-doped
polysilicon is used to dope the n"^ collectors as well as to make contact to them. The
base contacts are self-aligned to the polysilicon collector contacts so that the base area
of the multicollector n-p-n transistor is minimized (the aluminum and polysilicon

458 VLSI Technology
electrodes are isolated by the sidewall oxide). In addition, the extrinsic-base regions
are connected by the low-resistance aluminum metal which reduces base resistance
along the I^L gate. These features improve the I^L circuit performance.^^ Self-
aligned techniques that employ polysilicon for contacting the emitter and /or base
regions are being used more frequently to minimize transistor area and parasitics."^^
Propagation delays as low as 0.063 ns and speed-power products as low as 0.043
pj /gate have been reported using these techniques.
^^
Special techniques for forming the active-base region are needed to improve
upward current gain. One technique involves implanting or diffusing the boron
directly into the buried-layer, prior to epitaxial growth. After later high-temperature
steps, the boron up-diffuses into the n-epitaxial layer ahead of the slower-diffusing
arsenic or antimony buried-layer and produces an active-base profile graded properly
for upside-down operation. ^^' ^°
The speed-power product of an I^^ L gate is proportional^^ to CV/-, where C is the
loading capacitance of a gate and V/ is the logic swing of the gate (logic-high minus
logic-low). By reducing the logic swing, the speed-power product can be improved
(the smaller logic swing, however, causes the I^L gate to be more susceptible to
being switched by spurious noise signals). The reduced logic swing can be achieved
by substituting Schottky diodes for the heavy collector diffusions as shown^^^ in Fig.
8a and b. The logic-low voltage is raised (V/ is reduced) because of the forward-bias
INPUT O
(a)
METAL
JaJ
|,V
p
I
1
P L^ L^ LjJ n^
/n-EPITAXY ION-IMPLANTED INTRINSIC BASE
(b)
Fig. 8 Schottky integrated injection logic, (a) Circuit diagram, (b) Cross section of structure. (After
Hewlett, Ref. 23.)

drop across the Schottky diode, which is in series with the hghtly doped collector. To
fabricate the device shown in Fig. 8b, the base is implanted below the surface of the
epitaxial layer using a deep boron implant. The boron implant is deep enough so that
a sufficient amount of lightly doped n epitaxy remains above it to form the Schottky-
barrier diode with the metallization.
11.3.4 Emitter-Collector Leakage
One of the most severe yield-limiting mechanisms in the fabrication of bipolar
integrated circuits is emitter-to-collector (E-C) leakage or shorts. Often a crystallo-
graphic defect which occurs in an emitter of a single transistor in a bipolar IC can
cause the circuit to fail. This kind of failure mechanism does not generally occur in
MOS ICs. This is a prime reason why MOS ICs can be fabricated with a higher yield
than bipolar ICs.
Figure 9a illustrates an ideal device. The emitter and collector are isolated; with
zero base current the collector current is negligible. Figure 9b shows a device that
suffers from E-C leakage. The emitter has penetrated the base region in a localized
area (the E-C pipe), which causes the emitter and collector to be effectively tied
together. With zero base current, the collector current can be in the milliamp range
TRANSISTOR
OUTPUT
CHARACTERISTIC
TRANSISTOR
CROSS SECTION
:^EMITTER
BASE
n- COLLECTOR (a)
x:^
^^E-C SPIKE'
(C)
Fig. 9 Electrical output characteristics (collector current vs. collector-emitter voltage with four steps of
base current) and schematic cross-sections of n-p-n bipolar transistors, (a) Ideal case, (b) Transistor with
emitter-collector pipe, (c) Transistor with emitter-collector spike.

460 VLSI Technology
OSF
TR90
TR9
(a)
SLIP
DISLOCATIONS
(b)
Fig. 10 Secco-etched wafers illustrating process-induced crystallographic defects in test-transistor array
(TR9, TR90, TR9(X)). (a) Defects are primarily oxidation-induced stacking faults (OSF). (b) Defects are
primarily slip dislocations. (After Parrillo et al., Ref. 33.)
with several volts applied between collector and emitter. Figure 9c illustrates the
effect of an E-C spike. The emitter impurity partially penetrates the base, and
punchthrough current between collector and emitter occurs there at low values of Vce
E-C pipes are generally agreed to be formed by a locally enhanced diffusion of
the emitter dopant through the base in the vicinity of material defects such as disloca-
tions.^^ In narrow-base (easily penetrated) and shallow-emitter (sensitive to surface
defects) structures, the problem becomes more severe. Figure 10a and b illustrates
two types of material defects that can cause E-C leakage.-'^ The defects appear after
stripping all dielectrics and treating the silicon with an etch that delineates material
defects. Oxidation-induced stacking faults (OSF) are crystallographic defects in the
silicon formed during oxidation (Fig. 10a). If OSFs occur in an active emitter area,
they can cause E-C shorts. In a particular study, ^-^
these were completely eliminated
from the wafers by judicious choices of oxidation temperatures and material orienta-
tion. The yield with respect to E-C leakage on large test transistors was monitored-^^
over time and showed no significant improvement after the elimination of the known
fatal OSF defects (^i in Fig. 11). Slip dislocations are another type of crystallo-
graphic defect which can originate from thermal gradients in the wafers during the
epitaxial-growth process (Fig. 10b). After the additional fatal defect of slip disloca-
tions was identified and virtually eliminated, the yield jumped up dramatically (tj in
Fig. 11). The lesson here is that when two types of fatal defects are present in about
the same density (—10"^ cm~^) both have to be eliminated or reduced to see improve-
ment in E-C leakage.

90 •
80 - Do~1o'cnn'2
•
70 "
•
- 60 - -
3 50
UJ
>
40
30
•
•
•
•
•
•
Do~io'*cm"^
20
• •
•
•
10
n
•
• A •
•
• •
1 • 1
'1
TIME
Fig. 11 Yield with respect to emitter-collector leakage of TR90 vs. time. OSFs were eliminated at ?| and
the density of slip dislocations was reduced at /t- ^o denotes the fatal defect density. (After Parrillo et ai,
Ref. 33.)
Another major source of dislocations comes about from the local oxidation pro-
cess. In general, the thicker the pad oxide is and the thinner the silicon-nitride layer
is, the less probable it is that dislocations will be generated in the silicon during the
field-oxidation step.^'^ Unfortunately, adjusting these dielectric thicknesses to mini-
mize defects generally causes more lateral oxidation ("bird's beak"). A host of other
process-induced material defects^^ can also cause E-C leakage, and these too must be
eliminated to successfully fabricate bipolar VLSI circuits.
11.4 NMOS IC TECHNOLOGY
The metal-oxide-semiconductor field-effect transistor (MOSFET) is the dominant
device used in VLSI circuits. The field-effect principle of operation was proposed in
the early 1930s by Lilienfeld and Heil. The first working MOSFET, which used a
thermally grown silicon-dioxide gate insulator, was demonstrated in 1960 by Kahng
and Atalla.^ ICs using MOSFETs were originally based on p-channel (^MOS) de-
vices; however, n-channel MOS (NMOS) devices with their higher electrv..: nobility
with respect to hole mobility, have dominated the IC market since the early 1970s.
11.4.1 Illustrative NMOS Fabrication Process
Figure 12 shows a portion of an NMOS logic circuit with two enhancement-mode
(normally off) devices (EMD^ and EMDg) in series with a depletion-mode (normally
on) device (DMD). A field oxide (FOX) surrounds the transistors, and the gate and

462 VLSI Technology
Fig. 12 Three-dimensional view of NMOS logic circuit containing two enhancement-mode devices (EMD)
in series with a depletion-mode device (DMD). For clarity the intermediate dielectric is not shown.
+Vdd
(a)
INPUTS OUTPUT
r
EMD EMDb DMD -POLYSILICON
-METAL
1 (b)
INPUTS OUTPUT
POLYSILICON ^SlN
-P-GLASS
(C)
Fig. 13 Two-input NAM) logic gate, (a) Circuit schematic, (b) Top view of layout, (c) Side view
through cross section A-A. Plasma-deposited silicon nitride (SiN) covers the structure.

source of the DMD are connected together at the buried contact. An intermediate
dielectric layer separates the overlying metal layer from the underlying layers. This
structure can be used as a two-input NAND logic gate as shown in Fig. 13. Two
HMDs are in series with a DMD and the three transistors are connected between the
positive power supply Vqq and ground V55 rails. The DMD is normally on
{Vqs = 0) and acts as a current source for the two EMDs. Gates A and B of the two
HMDs are inputs to the logic circuit, and the DMD's gate/source connection is the
output electrode of the logic circuit. The output voltage of the two-input NAND cir-
cuit is low only when both EMDs are turned on (i.e., when inputs A and B are at their
logic-high level).
Figure 14 shows a fabrication sequence for this circuit. The starting material is a
lightly doped p-type substrate. The first lithographic step is isolation (Fig. 14a) where
a composite silicon-nitride/pad oxide layer is defined using a resist mask and aniso-
tropic dry etching. The silicon-nitride oxidation mask is retained over the active de-
vice area to prevent it from oxidizing later. A boron chan-stop layer is then
implanted. After resist stripping and cleaning, the wafers are oxidized which causes a
thick field oxide to grow outside of the active area and drives in the chan-stop implant
(Fig. 14b). After stripping the nitride/pad oxide layers, the thin gate oxide layer (a
few hundred angstroms) is then grown. This is a critical step; the integrity and clean-
liness of the gate oxide is essential for proper device operation. A buried contact win-
dow is then patterned in the gate oxide (Fig. 14b). The polysilicon gate and the
source of the DMD will be later connected via this window. A boron threshold-
adjustment dose is then implanted through the gate oxide. This implant, together with
the thickness of the gate oxide, sets the desired EMD threshold voltage. Many IC
applications call for several enhancement-mode threshold voltages, which add to the
complexity of the process. In Fig. 14c the EMDs are protected by resist and the
depletion-mode threshold-adjustment dose is implanted using arsenic or phosphorus.
Next the polysilicon gate material is deposited and is doped n type. After the
polysilicon is patterned (Fig. 14d), the source/drain regions are implanted with
arsenic or phosphorus. The energy of this implant is high enough for the impurities to
enter the silicon through the exposed gate oxide, but low enough to prevent their
penetration through the polysilicon or field oxide. The sources and drains are thus
self-aligned with respect to the gates. The self-alignment minimizes the overlap of
the gate and the lateral source/drain diffusions, so that coupling capacitances are
lowered there. Note that the n"*" polysilicon contacts the silicon at the buried contact.
The phosphorus or arsenic used to dope the polysilicon can diffuse directly into the
silicon below it, so that the polysilicon, the drain of the EMD, and the source of the
DMD all become connected. The connection is made this way to avoid the additional
space requirement that would be necessary if metal were used to strap the gate and
source of the DMD together.
After implanting the source/drain, the wafers may be oxidized to provide a
dielectric on the polysilicon (for isolation between two-level polysilicon structures)
and the silicon substrate. A CD oxide doped with phosphorus is then deposited at
either low or atmospheric pressure. This P-glass intermediate dielectric serves several
functions. The phosphorus in the glass protects the underlying devices from mobile-
ion (Na"*") contamination, and also causes the glass to become viscous so that it can

464 VLSI Technology
ISOLATION MASK-7
I
1
^_r-i
BURIED CONTACT MASK
A
fA
A p,. GATE MASK/
A A i/^ l/t ry^ i/! A
DEPLETION IMPLANT MASK
-<f-
Z6 i^j
RFQiqx^ ARSENIC f
^RESISy IMPLANT
X ARSENIC ^
POLYSILICON-7 IMPLANT I
(C) (dl
i
1
1
A
j-T /
^
Lj
t 1
WINDOW MASK
^WDa, EMDf P-GLASS
BURIED
CONTACT
p-SUBSTRATE
(e)
FOX
Fig. 14 Top and cross-section views of NMOS logic gate fabrication, (a) Isolation mask and cross section
after nitride/oxide etch and boron chan-stop implant, (b) Buried contact mask and cross section after field
oxidation (FOX), gate oxidation, buried contact window etch, and boron enhancement threshold-adjustment
implant, (c) Depletion implant mask and cross section after resist-masked arsenic depletion implant,
(d) Gate mask and cross section after polysilicon gate definition and arsenic source/drain implant, (e) Win-
dow mask and cross section after P-glass flow and window etch.

flow at an elevated temperature. This high-temperature process can also serve to
activate and drive in the source/drain implants. The P-glass flow smoothes out the
surface topography, which facilitates covering the steps with metal as well as aiding
in metal patterning. The P-glass also isolates the metal from polysilicon runners.
Contact windows are then etched in the P-glass, as shown in Fig. 14e. An additional
high-temperature process after window etching (reflow) is often used to taper the
steep sidewalls of the window in the P-glass, and this facilitates metal coverage of the
window wall. Metal is then deposited and defined as depicted in Fig. 12. Contact to
polysilicon is typically made outside of the active transistor area to avoid eroding the
polysilicon in that area, and possibly causing damage in the underlying gate oxide in
subsequent processing. Aluminum is nearly universally used as a metallization either
alone or in combination with other metals. The contacts are later sintered at tempera-
tures up to 500°C in a reducing ambient, to form good ohmic contacts to the silicon
and also to anneal out radiation damage that may have been introduced during metal
deposition and patterning. Finally, an overcoat layer, such as plasma-deposited sili-
con nitride^^ (SiN), is put down on the wafer to seal it from contaminants and to serve
as a mechanical scratch protection. Windows are then etched in the top coating where
external connections (wire bonds) will be made to the metallization layer.
Starting material Conventional bulk silicon consists of lightly doped (~10'^
atoms/cm-^) p-type (100) substrates. The (100) orientation is preferred over (111)
because it introduces about ten times less interface trap density.^ The lighter the dop-
ing in the substrate is, the less sensitive the transistor threshold voltage will be to
back-gate bias effects, and the lower the source/drain-to-substrate capacitance will be.
If the substrate is too lightly doped, however, the depletion regions of the sources and
drains of the same or adjacent transistors can punch through to each other.
In addition, lightly doped substrates have higher concentrations of minority car-
riers. These carriers diffuse long distances (hundreds of micrometers) to space-charge
layers and are collected as reverse-bias leakage currents. This minority-carrier diffu-
sion current can dominate over leakage current generated within the space-charge
layers, especially at higher operating temperatures (> 40°C).^^ A technique that can
be used to circumvent this problem is to form the lightly doped p layer (~10'^
atoms/cm^) as an epitaxial layer, grown on a heavily doped p^ substrate (—10^^
atoms/cm^).^^^' ^^ The heavily doped substrate has few minority electrons, so minority
carriers must originate primarily in the thin epitaxial layer. Hence diffusion currents
in reverse-bias junctions are suppressed, even though the minority-carrier diffusion
lengths are long. This is especially important in preserving holding times in dynamic
nodes (e.g., dynamic random-access memories^^). The added cost of growing well-
controlled epitaxial films on heavily doped substrates must be weighed against
improved device performance.
Isolation Figure 15a shows two adjacent n-channel transistors. The direction of
active transistor conduction is perpendicular to the polysilicon gate. Under the
polysilicon gate between the transistors is a parasitic transistor (see the cross sections

466 VLSI Technology
POLYSILICON GATE
A
r-&7ZZA
n +
n +
1
t
V//A///A/7{
- -.
ACTIVE
///|/xq^/l
^AJ TRANSISTOR
PARASITIC TRANSISTOR
(a)
POLYSILICON GATE
(b) ^-'(c)
BORON CHAN-STOP IMPLANT
f 1
1 ,8, f ^ A-'/VH'J
PAD OXIDE
I I
I
I
^^
OXY- NITRIDE
CHAN -STOP
FOX
I I
I
I
I I
I
I
GATE
OXIDE;
(d)
(e)
(f)
(g)
K-H INITIAL SPACE
h * FINAL SPACE
Fig. 15 MOSFET isolation, (a) Top view of adjacent NMOS transistors with common polysilicon gate,
illustrating active- and parasitic-transistor conduction paths. Cross section through A-A for (b) etched field
oxide isolation and (c) local oxidation isolation structures. Details of local oxidation process: (d) after
nitride/pad oxide etch and chan-stop implant, (e) after field oxidation (FOX), which produces an oxy-nitride
film on the nitride, (f) after oxy-nitride, nitride, and pad oxide removal, (g) after gate oxide growth.
of Fig. 15b and c). If the threshold voltage of the parasitic transistor is too low, an
inversion layer can form between the induced n"*^ regions of the individual transistors
and tie them together. The parasitic threshold voltage should, in fact, be made high
enough to avoid the onset of subthreshold conduction between the adjacent transis-
tors. The parasitic threshold voltage can be made high by having a thick field oxide
and/or by raising the substrate doping level between active transistors.
Two isolation techniques are illustrated in Fig. 15. Figure 15b shows a simple
technique that consists of growing the thick field oxide everywhere, and then cutting
windows in it where active transistors will be formed (the thin gate oxide is later
grown in the windows). Figure 15c shows another technique —the local oxidation

technique.'*^ This technique has the advantage of recessing about half of the field
oxide below the silicon surface, which makes the surface more planar (compare the
topographies of Fig. 15b and c). Another advantage is that it allows chan-stop layers
to be formed self- aligned to the active transistor area. Chan-stop doses are in the mid
lO'"^ to lO'^ atoms/cm- range and the depth of the implant is adjusted to allow suffi-
cient boron to remain in the underlying silicon after oxidation. Too heavy a chan-stop
doping increases the source/drain-to-substrate capacitance, reduces junction-
breakdown voltage, and increases the sensitivity of the threshold voltage to narrow-
width effects.
The local oxidation process is illustrated in detail in Fig. 15d to g. This process
is similar to that used in bipolar isolation, except in MOSFET isolation the field oxide
does not have to penetrate all the way through an epitaxial layer as in bipolar struc-
tures. After isolation definition and chan-stop implantation (Fig. 15d), the field oxide
is selectively grown outside of the active area, typically to a thickness of several
thousand angstroms. The thinner the field oxide is, the smaller is the bird's beak and
the more planar is the surface. Too thin a field oxide, however, causes a low parasitic
threshold voltage in the field region and increases the polysilicon-to-substrate capaci-
tance. A disadvantage of the local oxidation process is that the silicon surface under
the nitride can be damaged during field oxidation—that is, a thin layer of silicon
nitride (or oxy-nitride) can form on the silicon surface due to the action of NH3 gen-
erated from the masking silicon-nitride layer. -^^
Where it occurs, the oxy-nitride film
impedes the subsequent growth of the gate oxide and causes low-voltage breakdown
of the gate oxide and other deleterious device effects. One method used to avoid the
problem, is to grow a sacrificial oxide after stripping the masking nitride and then
remove it before growing the final gate oxide."^^ ^^
The field oxidation and subsequent thermal cycles can cause significant lateral
diffusion of the chan-stop layer. The diffusion raises the surface concentration of the
substrate near the nitride periphery, and hence the threshold voltage of that portion of
the device. The edges of the device will not conduct as much as the interior portion,
and the transistor behaves as if it were narrower. For a given field oxide thickness,
less lateral intrusion of the chan-stop layer occurs at lower field oxidation tempera-
tures.'^'^ Another geometrical aspect can be seen by comparing the initial separation
between nitride islands and the final space between active transistor areas (Fig. 15g).
Because lateral oxidation occurs under the masking nitride, the space between transis-
tors grows during processing. Since there is a limit to how small the initial space can
be made (because of lithographic considerations), there is a limit on how small the
final space between transistors will be. This limitation of local oxidation has been
addressed by many researchers*'^'
'^'*^
and new approaches to forming steep-walled
oxide-isolated islands have been investigated.*^'
'^'^
Although the ideal steep-walled boxlike oxide-isolation region is attractive for
many reasons, unwanted parasitic conduction can take place in the sharp comer
region of the active transistor. The insert of Fig. 16 shows the sidewall of an oxide-
isolated transistor in the direction from source to drain. Because of the electric field
concentration at the sharp comer of the silicon boundary, the threshold voltage of the
comer region is reduced and this part of the device turns on at a lower voltage than the

468 VLSI Technology
10'
• Vbs = OV
O Vbs=-2V
2.0
V. (V)
Fig. 16 Measured and simulated drain current vs. gate potential for devices having a downward step in the
field oxide (?^). The insert illustrates the geometry where conduction is from source (S) to drain (D).
Parasitic conduction occurs at the comer. Results are shown for t^ =0.1 to 0.2 (jtm and back-gate bias
(Vgs) of and -2 V. Devices have substrate doping of 1.4 x 10^^ atoms/cm^, 5-|jLm channel length, 5-
|xm channel width, and applied drain voltage of 0. 1 V. (After lizuka, Chiu, and Moll, Ref. 45.)
interior portion away from the corner."*^ The situation becomes worse if there is a
downward step in the field oxide (t^ in the insert of Fig. 16). The larger the step is,
the lower the comer threshold becomes, and unwanted subthreshold conduction
begins at progressively lower values of Vq The calculated and measured subthresh-
old I-V curves for t^ =0.1 ixm to 0.2 |xm are shown in Fig. 16 for a device with a
field oxide 0.75 [xm thick. The comer threshold can be made the same or higher than
the threshold of the planar region by allowing a step-up in going from the active to the
field oxide regions.'^^
In addition to these effects, the geometry of the isolation oxide
wall, as well as the doping levels in the active and parasitic regions of the underlying
silicon affect the threshold sensitivity of the transistor to its physical width.
'^
Channel doping As channel lengths become shorter and gate oxides become thinner,
a higher doping level under the gate is required to provide the desired threshold (and
subthreshold) voltage characteristics."^ Using a heavily doped substrate will provide
the higher doping level; however, this increases the back-gate bias sensitivity of the

threshold voltage and increases source/drain-to-substrate capacitances as well. A
shallow ion implant is widely used to set the desired doping level in the channel
region without raising the background substrate doping level. In this way the thresh-
old sensitivity to back-gate bias can be minimized while still having the desired high
surface concentration.'^^
A shallow implant may be sufficient to provide the desired transistor properties.
Depending on the substrate doping, source/drain junction depth, and gate oxide thick-
ness, however, a single shallow threshold-adjustment implant may not be sufficient to
prevent punchthrough of the drain electric field to the source region. When the de-
vice is intended to be off (Vq <^Vj), the path for punchthrough occurs below the sil-
icon surface. This is because, owing to the influence of the gate fields, the
source/drain depletion widths are reduced at the surface.'*^ This is illustrated schemat-
ically in the insert in Fig. 17 which shows the source/drain depletion regions imping-
ing on each other below the surface for Vq <SC Vj and V^ > 0. To prevent the sub-
I0"5
-0.5
V, (V)
Fig. 17 Drain current vs. gate voltage for n-channel devices with a substrate doping of 1.9 x lO'^
atoms/cm^, source/drain junctions 0.47 ixm deep, 575-A gate oxide, drain voltage of 5 V, and back-gate
bias of V. Devices A and B have no channel implant, and devices C, D, and E have a boron channel
implant of 8 x lO" atoms/cm- at various energies. Insert schematically illustrates the source and drain
depletion regions for Vq <§; Vj and Vp > 0. (After Nihira et al.. Ref. 49; Bateman, Armstrong, and
Magowan, Ref. 48.)

470 VLSI Technology
surface punchthrough, a deep boron implant can be used to raise the substrate doping
level at the appropriate depth. Figure 17 illustrates subthreshold I-V curves for a de-
vice with a light substrate doping."^^ A short-channel device (L =1.2 |jLm) punches
through badly (curve A). Curve B shows the desired behavior of a long-channel
(L =7.8 fxm) transistor in the same substrate. A boron implant dose of 8 x lO''
atoms/cm^ was implanted in the short-channel device at a projected range of 0.3 |JLm.
This was too shallow, and the threshold voltage (curve C) rose well above the desired
value. By increasing the implant energy (curves D to E), the deep boron implant
became deep enough to allow the desired low threshold voltage (surface concentration
undisturbed) and to prevent punchthrough (peak of implant at 0.68 fxm below the sur-
face) in the 1.2-fjLm-long device. Of course the back-gate bias sensitivity increases
also. Note that the subthreshold swing factor [n = q lkT{dVc Id log /^ )] is large
{n =2.41) for the shallow implant (curve C) and becomes smaller (n = 1 .65) as the
implant is made deeper. This occurs because the high-doping region is pushed below
the silicon surface. Two boron implants can be used to establish the surface doping
for the desired threshold voltages of short-channel devices (shallow implant) and to
tailor the subsurface profile to prevent punchthrough (deep implant). ^'^^ ^'
A deleterious consequence of increasing the surface concentration is the accom-
panying reduction in carrier mobility at the surface. This reduction in surface mobil-
ity is caused by the increased vertical electric field experienced by the carriers in the
channel—which in turn is a consequence of the more heavily doped substrate.
^^'^^
Using ion implantation to form a shallow p-n junction at the surface, and choosing a
gate material with an appropriate work function, can increase the electron^"^ and
hole^^ mobilities above the mobilities found in conventional structures.
The discussion, so far, has centered around surface-channel conduction. Buried-
channel devices, however, are becoming increasingly common in ICs. They are gen-
erally of two types —normally on and normally off. An example of a normally on
buried n-channel was discussed in connection with Fig. 13, where an arsenic surface
layer provides the source-to-drain conduction at zero gate voltage. A normally off
buried n-channel device can be fabricated in a similar manner (n-type surface layer in
a p-type substrate). However, a gate material with a suitably large work-function is
chosen (e.g.,
p"*"
polysilicon^^ or MoSi2^^) to deplete the n-type surface layer of car-
riers, and to produce the normally off characteristics. When the device is turned on,
much of the current is conducted below the surface (where bulk mobility is larger than
surface mobility); thus the buried-channel device has significantly higher carrier
mobility than conventional devices. However, since the conduction path is further
removed from the gate than in conventional surface-channel devices, the transconduc-
tance gy^ = (dlfj / OVq) y can suffer. These competing effects must be weighed
against each other to ascertain the effect on transconductance.
Gate material Heavily doped n-type polysilicon has been widely used as a gate and
as an interconnect because of its ability to withstand high-temperature processing.
The resistance of the polysilicon (>0 Cl/c) may contribute significantly to the RC
delay of signals that are routed along it. More recently, refractory metals and their
silicides have been used in conjunction with polysilicon^^' ^^ or alone"*'
'^^
to reduce
the resistance. The technique of combining a refractory metal silicide on top of doped

polysilicon (called polycide)^^ has the advantage of preserving the well-understood
polysilicon-Si02 interface while lowering the overall sheet resistance of the polycide
to about 1 to 30/-. The use of certain silicides directly on gate oxide results in
larger work-functions than n^ polysilicon, thus requiring corresponding adjustments
in the channel-doping technique.'*''
^^
Source/drain formation For a shallow junction and minimal lateral diffusion,
arsenic is used extensively as a source/drain impurity. Source/drain implants are typi-
cally in the high 10^'' to lO'^ atoms /cm^ dose range to produce low-resistance
source/drain regions. Figure 18 shows the details of a shallow arsenic source/drain
I 1
2000A
Fig. 18 Transmission electron micrograph showing details of source/drain and gate regions. Parameter a is
the junction depth and c is the lateral penetration of the junction from the original implant position before
reoxidation. (After Sheng and Marcus. Ref. 60.)

472 VLSI Technology
diffusion at the edge of a polysilicon gate.^ After the arsenic was implanted into the
bare silicon source/drain regions, it was driven in in an oxidizing ambient (reoxida-
tion). Reoxidation is sometimes used to provide a dielectric on the polysilicon for
double polysilicon processes and also to help protect the source/drain regions from
phosphorus penetration from the P-glass. The results of the reoxidation are shown by
the bird's beak at the edge of the polysilicon gate and the depressed surface of the
source/drain region (Fig. 18). Excessive reoxidation can enhance these effects and
cause the shallow drain impurity profile in the silicon to be electrically deep because
the silicon surface has been depressed.
The series source/drain resistance is becoming increasingly important as device
dimensions shrink. As channel conductance increases with shorter channel length,
the resistance of the shallow source/drain regions stays fixed or actually increases
because of the need for shallower junctions. The result is that the resistance of the
source/drain limits the current-delivering capability of short-channel devices and
becomes an important parasitic resistance. Figure 19a shows a technique used to
reduce the resistance of the source/drain and gate.^^ After forming the polysilicon gate
and driving in the source/drain regions (to a depth of 0.23 [xm), a CVD oxide is
-Pt SILICIDE
SOURCE
POLYSILICON GATE
p -SUBSTRATE
DRAIN
(a)
(b) (c)
Fig. 19 Reduction of source, drain, and gate resistances, (a) Cross section of an n-channel transistor with
platinum silicide on source, drain, and gate, (b) Output I-V characteristics without silicided source/drain,
(c) Output I-V characteristics with sUicided source/drain. (After Shibata et al. , Ref. 51 .)

deposited on the device and removed in the horizontal regions by reactive ion etching.
The thicker oxide along the polysilicon's sidewall remains and a sidewall oxide
spacer is formed. Platinum is deposited and then allowed to react with the exposed
silicon in the source/drain and gate regions (Pt does not react with oxide). This
lowers the sheet resistance of the source/drain regions'" from 50 O/r to 3 Q/z. The
resulting effect on the output I-V characteristics of a 0.5-|JLm electrical-channel-length
transistor is shown in Fig. 19b and c. The increased current drive of the silicided de-
vice is most evident at lower drain voltages. Other techniques to reduce parasitic
resistance include the use of a selective deposition of tungsten only on exposed silicon
areas (source/drain and polysilicon gate) without the silicide reaction. Sheet resis-
tances of 1 n / r were achieved for these areas using 1500 A of tungsten.^'
11.4.3 Memory Technology
One of the most important VLSI products is the memory chip. This section considers
some basic concepts in producing memory-related structures. Among memory chips,
the random access memory (RAM) has the highest component density per chip. In a
RAM any bit of information in a matrix of bits can be accessed independently. Indi-
vidual rows of memory bits are accessed by a conductive word line which may be a
diffusion, polysilicon, or metal line. Similarly, individual columns of bits in the
matrix are accessed by a bit line. The acronym RAM is generally used to refer to ran-
domly addressable memories into which data can be written and retrieved indefin-
itely. In contrast, the read only memory (ROM) has data permanently coded into it
and new information cannot be entered. Static RAMs retain their data indefinitely,
unless the power to the circuit is interrupted. Dynamic RAMs require that the charge
(data) stored in each m.emory cell be "refreshed" periodically to retain the stored
information.
Figure 20 gives an example of a single static RAM cell. Figure 20a shows a six-
transistor (n-channel) cell, which uses a cross-coupled inverter pair (flip-flop) {Tx to
T^) to store 1 bit of information.^- A pair of access transistors {T^ and T^) transmit
data into and out of the cell when the word and bit lines are simultaneously activated.
The loads for the flip-flop are depletion-mode transistors {T
and T^) with their
sources and gates tied together as shown before in the NAND circuit of Fig. 13. The
data (logic 1 or 0) is retained in the cell by the positive feedback existing in the flip-
flop circuit. For example, with the gate of T^, at a high potential, its drain is forced to
a low potential {<^Vj). This potential, in turn, is fed to the gate of 7"3, and keeps T^
off. TTie drain of Ti, is then tied to the high potential by Ti (which is always on) and
so is the gate of 74. This arrangement ensures that the drain of T^, is kept high in
potential and the drain of T^ is kept low in potential. This state of the cell defines a
logic 1 or 0, which is retained unless new data is entered by T^ and T^.
Figure 20b shows a layout^- for the circuit of Fig. 20a. The width-to-channel-
length ratio of the depletion-mode load transistors (1 /5) is adjusted to provide enough
current drive to meet the speed requirements of the cell without causing excessive
steady-state (quiescent) power dissipation [Tj and 7^4 are on simultaneously in our
example and current flows between V^c ^rid V55). To minimize the cell area, buried
contacts (diffusion to polysilicon contact) are required (see Fig. 12).

474 VLSI Technology
BIT LINE BIT LINE
[3| ISOLATION
(DIFFUSION)
;^n) WORD LINE
*^^ (POLYSILICON)
I DIRECT DIFFUSION
-®T0 POLYSILICON
' CONTACT
(a)
^ POLYSILICON
^ DIFFUSION-POLYSILICON
:^ CONTACT
- Al-Si
J CONTACT
"
WINDOW
(b)
Fig. 20 Static RAM cell with transistor loads, (a) Circuit diagram of a six-transistor static RAM cell. V^c
and V55 are the power supply and ground potentials, respectively. The numbers next to the transistors indi-
cate the relative width-to-channel-length ratios, (b) Static RAM layout. (After Hunt, Ref. 62.)
The depletion-mode load transistors can be replaced by high-valued resistors,^^ as
shown in the circuit schematic of Fig. 21a (resistor MOS or RMOS cell). A high
value of resistance is desired to reduce the quiescent power dissipation in the cell.
High-valued resistors can be made in a relatively small space by using polysilicon
which has been ion-implanted to provide the proper resistance. Polysilicon is used
because its sheet resistance can be modified by many orders of magnitude using ion
implantation. Diffusions in the silicon would require too much area to produce the
same high-resistance values (>10^ O). The polysilicon resistors can be made in the
same single layer of polysilicon (gate and interconnect) by masking the polysilicon
resistor regions from the high-impurity doping used in the gate and interconnect por-
tions of the polysilicon level. Additional area can be saved by using a second level of
polysilicon for the load resistors, and overlaying these resistors on the active area of
the cell (Fig. 21b). Using this technique, static RAM cell areas can be reduced to half
the cell area required in conventional transistor load cells. ^^ To virtually eliminate

Vcc
POLYSILICON
(FIRST LEVEL
ION-IMPLANTED
POLYSILICON
RESISTOR
(SECOND LEVEL)
SOURCE
SiO,
POLYSILICON
GATE
p- SUBSTRATE I
(a) (b)
Fig. 21 Static RAM cell with resistor loads, (a) Circuit schematic of polysilicon resistor load (R j
and 7? 2)
static RAM cell, (b) Device cross section. First-level polysilicon is used for gate and routing power supply
V^c Second-level polysilicon is used for resistor load directly over an active transistor. Connection to
drain and V^c is made directly from an implanted polysilicon resistor. (After Ohzone et al., Ref. 63.)
quiescent power consumption in static RAM cells, the depletion-mode load transistors
of Fig. 20 can be replaced by p-channel transistors in a CMOS static RAM cell at the
expense of area (see Section 1 1 .5).
Because of the large number of devices needed in static RAM cells, large-
capacity memories (>16 kilobit) require large chip areas. In addition static RAMs
can dissipate a great deal of power. For these reasons large memory chips use
dynamic memory (dynamic RAM) cells, which require only one transistor and one
storage capacitor per bit of information. Additional circuitry is required to sense and
refresh the data in the dynamic cells, but it is well worth the effort because of the
much reduced chip area and power dissipation required for dynamic RAMs. Figure
22a shows the basic dynamic memory cell.^^ When a word and bit line are simultane-
ously addressed (brought to a high voltage), the access transistor is turned on and
charge is transferred into the storage capacitor if it had no charge initially (stored
"zero"), or little charge is transferred to the storage capacitor if it were fully charged
initially (stored "one"). The amount of charge that the bit line must supply to the
storage capacitor is measured by the sensing circuitry, and this information is used to
interpret whether a "zero" or "one" had been stored in the cell. The sense circuitry
then restores full charge in the capacitor if it had been there originally, or fully
depletes the capacitor if little charge had existed originally. The information in the
cell is thus "refreshed" after it is read.
An example^- of a dynamic RAM cell layout is shown in Fig. 22b and a cross
section of the cell through A-A is shown in Fig. 22c. A diffusion (source/drain) forms
the bit line and also the source of the access transistor. The capacitance of the dif-
fused bit line (i.e., the junction capacitance) and its resistance can be limiting factors
in the performance of dynamic RAMs. Several approaches are used to minimize
these parasitic effects, including the use of MoSi2 for word lines and Al for bit lines in
fabricating advanced memory chips such as the 256-kilobit dynamic RAMs.^^

476 VLSI Technology
ROW SELECT OR WORD LINE
T ACCESS TRANSISTOR (a)
BIT LINE
~1 STORAGE
"["CAPACITOR
POLYSILICON
CELL PLATE
[;
r
A
ACCESS
TRANSISTOR
(POLYSILICON)
^ALUMINUM
fWORD LINE
(b)
POLYSILICON
OXIDE
(C)
DIFFUSION DEPLETION REGION
Fig. 22 Single-transistor dynamic RAM cell with storage capacitor, (a) Circuit schematic, (b) Cell layout,
(c) Cross section through A-A. (After Hunt, Ref. 62.)
In scaling ICs to finer features, it is also desirable to shrink the area of the storage
capacitors in dynamic RAMs. As the area of the storage capacitor decreases so too
does its capacity to store charge. As less charge is stored in the cell, accurate interro-
gation of its contents becomes more difficult (small signals). In order to increase the
charge-storage capacity, the use of thinner gate insulators with higher dielectric con-
stants (e.g., Si3 N4 and Ta2 O5 with dielectric constants of ~8 and —22, respectively)
is being explored.^'
^^
Other techniques include the use of the high-capacity (Hi-C) RAM cell^ (Fig.
23). A shallow arsenic implant and deeper boron implant are used to increase the
depletion-layer capacitance under the storage capacitor and to also increase its

METAL
STORAGE GATE TRANSFER GATE
X^ , ...
'±t±t±± ±± [ n+ 1 L n-*- .X-
P + P+
IMPLANTS
METAL-
STORAGE GATE
BIT LINE
TRANSFER GATE
F^
^JPH
^/TT}'/ / J'^ff'y^'^^^'^^A
/
P+
+ +++ + + +++++ I. n+ V
7 p
I P>

/
IMPLANTS BIT LINE
(a)
(b)
Fig. 23 High-capacity (Hi-C) dynamic RAM cell structure with shallow arsenic (+) and deeper boron (-)
implants, (a) One-transistor cell with single-level polysilicon. (b) Double-level polysilicon cell. {After
Tasch, Jr., et al., Ref. 66.)
charge-Storage capacity. Simply increasing the substrate doping under the storage
capacitor (boron implant) increases the depletion-layer capacitance there. This does
not increase the cell's charge-storage capacity, however, because the surface potential
difference A <^s between an empty and a full cell decreases. By also incorporating the
shallow n-type implant (which acts like a positive oxide-fixed charge), the change in
A(t)5 coupled with the increased depletion capacitance causes the charge-storage
capacity of the cell to increase. Depending upon the back-gate bias applied to the
cell, the Hi-C RAM cell can have up to twice the charge-storage capacity of conven-
tional cells.
^^
The drain region of the access transistor acts as a conductive link between the
inversion layers under the transfer and storage gates. This drain region can be elim-
inated by using the double-level polysilicon approach^^ shown in Fig. 23b. The
second polysilicon electrode is separated from the first polysilicon electrode by a thin
Si02 layer, thermally grown on the first-level polysilicon after it has been defined.
The second-level polysilicon is then deposited and defined so that it closely overlaps
the first polysilicon level. Charge from the bit line can therefore be transmitted
directly to the area under the storage gate by the connection of inversion layers under
the transfer and storage gates. The double-level polysilicon approach is widely used
in dynamic RAMs because it reduces cell size; however, the complexity that having a
second level of polysilicon adds to the process can be costly.
Thus far we have focused on techniques to fabricate individual memory cells. To
successfully fabricate an IC having many thousands of cells requires that all com-
ponents on the chip be free of defects. In memory ICs, many chips fail because of
localized defects that cause failure in only single bits, or single rows or columns of
bits in the memory array. The yield of large dynamic RAMs can be greatly increased
by incorporating redundant (spare) rows and columns of bits which can be exchanged

478 VLSI Technology
for the faulty ones.^^ Fusible links, that can be opened by laser programming or by
electrical means, are used to disconnect the faulty rows or columns from the memory
array. After the faulty row or column is disconnected, its previous identity in the
memory array is transferred to the spare row or column by opening additional fusible
links in the memory decoding circuitry. Redundancy techniques for large dynamic
RAMs have very significantly lowered the manufacturing cost of these ICs.
The few examples of semiconductor memory structures mentioned here are all
volatile—that is, data is lost when power is removed from the chip. An entire field of
nonvolatile semiconductor memories^ also exists, however. These devices semiper-
manently retain their data, which has been preprogrammed into them either electri-
cally or by other means. The information in these devices can be electrically pro-
grammable (EPROM) and, more recently, electrically erasable and programmable
(E-PROM).^^
11.5 COMPLEMENTARY MOS IC TECHNOLOGY
First introduced in 1963 by Wanlass and Sah,^^ complementary MOS (CMOS) tech-
nology provides both NMOS and PMOS transistors on the same chip. CMOS circuits
consume low power when compared to NMOS circuits. By comparison, however,
early CMOS processes were more complex and early circuit designs required larger
chip areas (a PMOS was used for every NMOS). As NMOS circuits have grown in
density, NMOS processes have grown in complexity to avoid excessive power con-
sumption (e.g., additional masks are now used to produce a variety of threshold vol-
tages). Modem CMOS processes have been simplified so that NMOS and CMOS
technologies are now comparable in complexity. Current CMOS designs use more
NMOS than PMOS transistors, which conserves chip area while still minimizing
power consumption. CMOS technology has benefited from the advances of NMOS
technology and has emerged as one of the most important VLSI technologies.
11.5.1 Special Considerations for CMOS
Figure 24 shows the operation of a CMOS inverter.^ The p-channel transistor is
formed in the n-type substrate. The n-channel transistor is formed in the p region,
which in turn is formed in the n-type substrate. The p region acts as the n-channel
transistor's substrate (back gate), and is commonly referred to as a tub or well. The
gates of the n- and p-channel transistors are connected and serve as the input to
the inverter. The common drains of each device are the output of the inverter. The
threshold voltages of the n- and p-channel transistors are Vj^ and Vjp , respectively
(Vjp < 0). Figure 24c shows the dependence of the output voltage Vg on the input
voltage V/ of the CMOS inverter. For V/ = 0, the n-channel transistor is off (V/ <s^
Vj„), while the p-channel transistor is turned on heavily (the gate-to-source potential
of the p channel is —Vdd, which is much more negative than Vfp). Hence, Vq =
V[)D. As Vi increases above zero, the n-channel transistor eventually turns on, while
the p-channel transistor eventually turns off. When Vj is larger than {Vqd —
Vjp
),
then Vq = V55 •

Vdd
'Tp
o "0
H
(a)

1
1

1

1
Vr
2/ 4
[ ^/ Vtp
'DD
(b) (d)
Fig. 24 CMOS inverter, (a) Circuit schematic. V/^^) and V55 are the highest and lowest circuit potentials,
respectively, (b) Device cross section, (c) Output (V,^) vs. input (V/) voltage of inverter, (d) Current
through inverter as a function of input voltage (solid curve); l-V characteristics of n- and p-channel transis-
tors (dashed curves). The numbers correspond to different points on the inverter transfer characteristic.
(After Hoefflinger arid Zimtner, Ref. 2.)
A key feature of this CMOS gate is that in either logic state (Vq = Vqd or ^ss )
one of the transistors is oj^and the current conducted between Vqq and V55 is negligi-
ble. This feature is illustrated in Fig. 24d where current through the inverter (Idd) is
plotted as a function of Vj (solid curve). A significant current is conducted through
this CMOS circuit only when both transistors are on at the same time (during switch-
ing). The low power consumption of CMOS is one of its most important attributes.
Performance and ease of circuit design are other attractive features of CMOS circuits.
CMOS provides the circuit designer with flexibility in designing circuits that are
either static CMOS (a p-channel transistor for every n-channel transistor) or have
more of one type of transistor than the other (dynamic).

480 VLSI Technology
'DD
H
B o-
A o-
r^'-'
X
zir ^SS
(a) (b)
Fig. 25 CMOS two-input NAND circuit, (a) Circuit schematic, (b) Circuit layout.
The circuit schematic in Fig. 25a is an example of a static CMOS two-input
NAND gate. As in the NMOS two-input NAND gate of Fig. 13a, the logic function is
described by: the output is low ( ) only when input A and (•) input B are high (A-B).
In the CMOS gate, when A and B are high, both n-channel transistors are on and both
p-channel transistors are off. In the NMOS gate (Fig. 13a), however, when A and B
are high, the two enhancement-mode devices are on and so is the depletion-mode load
device. Hence the NMOS circuit dissipates power in this state while the CMOS cir-
cuit does not. CMOS is also desirable because the output voltage of the CMOS cir-
cuit makes a full excursion between V^o and Vss (a large excursion of output voltage
is desirable for noise margins). This is not the case with the NMOS circuit.
A disadvantage of the static CMOS circuits is their additional input capacitance,
which is due to the gate capacitance of the p-channel transistors in parallel with the
n-channel gates. Also, static CMOS circuits require a significant amount of chip area
as shown in Fig. 25b. A minimum separation is needed between n- and p-channel
transistors to prevent leakage between them. Often this space can be used for wiring
tracks, as shown by the metal output line of the circuit in Fig. 25b.
To avoid the area penalty of static CMOS circuits and to take advantage of
CMOS's low power consumption, modem complex CMOv^l circuits are designed with
many n-channel transistors (in a common p tub) and fewer p-channel transistors. Fig-
ure 26 shows an example of a dynamic logic circuit, called Domino CMOS.^° When
the clock signal is low { pi on, n i off), the signal to the output inverter is held high
and the output of the circuit is low, regardless of any signal inputs on the many
n-channel transistors. Negligible power is dissipated in this circuit when the clock is
low. When the clock signal goes high, the circuit is activated ( p
off, « i on). If a
combination of input signals is applied to turn on a branch of the series n-channel
transistors (A and B, for example), the signal to the output inverter is pulled down,
causing the output of this circuit to go up. Since the overall IC consists of many
dynamic circuits (like that in Fig. 26), which feed other similar circuits, the data cas-

DD
.Hf
M
5
c^h%H^
R I
I—
°
hi h
CLOCK —
^
1
4 o OUTPUT
H' n -1. n
Fig. 26 Dynamic (Domino) CMOS circuit. Individual inputs, A through A^, are labeled. (After Krambeck,
Lee, and Law, Ref. 70.)
cades from one dynamic circuit to another, like a series of dominos. Very significant
speed enhancement and savings in chip area can be obtained by using dynamic CMOS
circuits.
A generic problem associated with CMOS structures has been their vulnerability
to an undesirable conduction mechanism known as latchup. Latchup is a condition
where high currents are conducted between V^q and Vss , which can cause the IC to
cease functioning and even be destroyed. The CMOS inverter structure produces
lateral p-n-p as well as vertical and lateral n-p-n bipolar transistors (Fig. 27a). The
collectors of each of these bipolar transistors feed each others' bases and together
make up a thyristor (p-n-p-n device) as shown by the insert in Fig. 27a. With the
thyristor biased appropriately (or inappropriately in a CMOS circuit), the collector
current of the p-n-p supplies base current to the n-p-n, and vice versa in a positive-
feedback arrangement. A sustained current can then exist between the positive and
negative terminals of the thyristor (i.e., the latchup). The latchup current is ter-
minated when electric power to the thyristor is interrupted.
Figure 27b shows how a CMOS circuit can be induced to latchup.^' If the output
terminal is momentarily brought below the Vss potential by about 0.7 V (by a spuri-
ous noise spike from electrostatic discharge, for example), then the n"^ drain (emitter
of n-p-n) injects electrons into the p tub (base of n-p-n); the electrons reach the n sub-
strate (collector of n-p-n), where they drift out of the positive Vdq terminal. If this
electron current is high enough and if sufficient resistance exists between the V^d
contact and the p"^ source, an IR (current-resistance) drop develops, which lowers the
potential of the substrate under the p"^ source by about 0.7 V. This drop in potential
causes holes to be emitted from the p"^ source (emitter of p-n-p) into the n substrate
(base of p-n-p); the holes reach the p tub (collector of p-n-p) and drift out of the Vss
terminal. If enough hole current exists in the p tub and if sufficient resistance exists
between the Vss contact and the n^ source, an IR drop develops, which causes the n"*"
source to inject electrons into the p tub. This electron current adds to the initial elec-

482 VLSI Technology
INPUT
E2-P0LYSILIC0N
CD-SiOa
-ALUMINUM
(a)
INPUT
(b)
Fig. 27 CMOS inverter cross section, (a) Parasitic n-p-n and p-n-p bipolar transistors comprise a tliyristor
(shown in insert), (b) A latchup condition is induced by biasing the output below V55. (After Grant, Ref.
71.)
tron current and strengthens the positive feedback between the p-n-p and n-p-n
transistors, which leads to the latchup condition. The initial disturbance can now be
removed and the large latchup current will be self-sustained unless power to the
CMOS circuit is interrupted (e.g., V^q or Vss is disconnected). In a similar fashion,
latchup can be initiated by hole injection from a p^ source if the output is biased suf-
ficiently above Vod
11.5.2 Illustrative Fabrication Process
An important consideration in fabricating CMOS structures is the technique for form-
ing the substrates for the two types of MOSFETs. The early CMOS processes were
developed to be compatible with the PMOS process; hence the n-channel transistor
was formed in a p diffusion (tub) in the n substrate. Although some of the early pro-
cessing constraints disappeared and NMOS circuits have dominated MOS ICs, the
traditional p-tub approach has been the most widely used CMOS structure.
The p tub is implanted or diffused into the n substrate at a concentration that is
high enough to overcompensate the n substrate and to give good control over the

n-CHANNEL
OXIDE
^p-CHANNEL
POLYSILICON
(a)
OXIDE POLYSILICON
(b)
THERMAL
OXIDE ^P-GLASS
NITRIDE
POLYSILICON Ai
(C)
Fig, 28 Various CMOS structures, (a)ptub. (b)ntub. (c) twin tub. (After Parrillo et ai, Ref. 72.)
desired net p-type doping (Fig. 28a). The doping level in the p tub is typically five to
ten times higher than that in the n-type substrate to ensure this control. This excessive
p-tub doping produces deleterious effects in the n-channel transistor, however, such
as increased back-gate bias effects, and increased source/drain to p-tub capacitance.
An alternative approach is to use an n tub to form the p-channel transistors.^^ As
illustrated in Fig. 28b, the n-channel device is formed in the p-type substrate and this
n-tub approach is compatible with standard NMOS processing. In this case the n tub
overcompensates the p substrate and the p-channel device suffers from excessive dop-
ing effects.
Figure 27c shows an approach that uses two separate tubs implanted into very
lightly doped n-type silicon. This "twin-tub" CMOS approach^-^ allows the doping
profiles in each tub region to be tailored independently, so that neither type of device
must necessarily suffer from excessive doping effects. This approach has been used
on lighdy doped n-type (v-type)^^'
'^^
or p-type (Tr-type)'''^ substrates.

484 VLSI Technology
J,, . V
X X
n-TUB
X XX XX XX XX
XXX XXX XX xxxxxx,
p-TUB
°7,„/;
xxxxxx X XX X XXX
(a)
p-TUB
(c)
FIELD OXIDE
•
i^p* r
p-TUB
(d)
RESIST -
^
XXXXX XXX XX
P-TUB
n-TUB
(e)
P-GLASS
Fig. 29 Twin-tub CMOS structure at several stages of the process: (a) n-tub ion implant (I-); (b) p-tub
implant; (c) twin-tub drive-in; (d) nonselective p^ source/drain implant; (e) selective n* source/drain
implant using photoresist mask; (f) P-glass deposition. (After Parrillo et ai. Ref. 72.)

VLSI Prcx:ess Integration 485
The highlights of the twin-tub CMOS process^^ are illustrated in Fig. 29. The
starting material is lightly doped n epitaxy over a heavily doped n^ substrate. This
structure, combined with proper layout techniques, produces CMOS circuits that are
not prone to latchup.^^ Figure 29a to c shows how the self- aligned twin tubs are
formed using one lithographic mask step. A composite layer of Si02 (pad) and Si3 N4
is defined and silicon is exposed over the intended n-tub region. Phosphorus is
implanted as the n-tub dopant at low energy, and enters the exposed silicon, but is
masked from the adjacent region by the Si3 N4 (Fig. 29a). The wafers are then selec-
tively oxidized over the n-tub regions. The nitride is stripped and boron is implanted
for the p tub (Fig. 29b). The boron enters the silicon through the thin pad oxide but is
masked from the n tub by the thicker Si02 layer there. All oxides are then stripped
and the two tubs are driven in (Fig. 28c).
After the tubs are driven in, the intra-tub transistor isolation is performed (a tub
may contain tens of thousands of transistors of a given type within it) using the tech-
niques described in Fig. 15. After field and gate oxides have been formed, threshold
adjustment implants can be made into the channel regions of the devices.
Next, n^ polysilicon is deposited and defined and the source/drain regions are
implanted. To save another mask step, boron is first nonselectively implanted into all
sources and drains (Fig. 29d). Following this, phosphorus is selectively implanted
into the n-channel source/drain regions at a higher dose so that it overcompensates the
existing boron (Fig. 29e). After processing, the boron profile in the n-channel
source/drains is completedly covered vertically and laterally by the phosphorus. This
technique has also been used with As and BF2 for shallow junction n- and p-channel
devices, respectively.^'^ A phosphorus glass layer is later deposited (Fig. 29f) and
flowed at high temperature. After windows are dry-etched in the P-glass, aluminum
metallization is defined using dry etching. The final layer is a plasma-deposited
silicon-nitride layer which seals the devices and provides mechanical scratch protec-
tion. Figure 28c shows the finished cross section.
Isolation The same principles as discussed previously (Section 11.4.2) apply in iso-
lating the same types of MOSFETs from each other within a given tub region. How-
ever, in CMOS circuits there is the added concern of isolating the two different types
of transistors. Figure 30a shows the top view of n- and p-channel transistors strad-
dling the common tub border. Figure 30b shows a cross section of the structure
beneath the polysilicon rail. A parasitic n-channel transistor exists between the n
source (induced under the polysilicon gate) and the adjacent n tub. Similarly a parasi-
tic p-channel transistor exists between the p source and the p tub. Single or twin tubs
are typically driven in rather deeply to ensure that enough charge exists below the
transistor to prevent punchthrough to the substrate, and to keep the hf^ of the vertical
bipolar device from becoming too large (and hence susceptible to latchup). The long
diffusion length associated with driving the tub in causes a reduction in surface con-
centration of each tub near the border, and hence a reduction in the parasitic
transistor's threshold voltage. Figure 30c shows the threshold voltage of each type of

486 VLSI Technology
n- CHANNEL
ISOLATION
r^
p-TUB
p-CHANNEL
ISOLATION
-POLYSILICON
A
n-TUB
POLYSILICON
lELD OXIDE
n SOURCE p SOURCE
PARASITIC
p-CHANNEL
(bl
30
25
20 -
>
- 15
10
I
I
I
I
I
I
T
PARASITIC n-CHANNEL
Vn = O.IV
NO ADJACENT
n-TUB
WITH ADJACENT
n-TUB
_i 1 I I i_
-n—I
—

—
—
—I
—
r
PARASITIC p-CHANNEL
Vn=O.IV
WITH ADJACENT
p-TUB
J L I I I
i_
30
25
20
- 15
10
- 5
864202468
ISOLATION-TUB SPACING (/i.m)
(C)
Fig. 30 Isolation of n- and p-channel transistors, (a) Top view of adjacent n- and p-channel transistors
sharing a common polysilicon gate, (b) Cross section under the polysihcon rail, (c) Parasitic n- and
p-channel threshold voltages vs. transistor-edge-to-tub spacing. (After Parrillo etal., Ref. 72.)
parasitic device as a function of the separation between the transistor edge and the tub
border7^ The upper curve on the left shows the parasitic n-channel threshold voltage
reduction near the tub border, which occurs with no adjacent n tub and characterizes
the effect of a long diffusion of a single p-tub-type process. The interdiffusion (i.e.,
the compensation) of the two types of tub impurities further reduces the net surface
concentrations of each tub near the border, and the parasitic field thresholds are

further reduced (Fig. 30c). The n- and p-channel transistors must be placed laterally
far enough away from the tub border so that the field threshold voltages are ade-
quately large in magnitude.
To avoid some of the problems associated with deep-tub drive-in cycles, very-
high-energy (400- to 600-keV) p-tub implants can be used to place a sufficient charge
below the n-channel transistors without the long thermal cycle. ^^'^^
The deep boron
implant, performed after local oxidation, also provides a high surface concentration
under the field oxide, which serves as a chan-stop layer. Significant improvements in
packing density and latchup susceptibility have been reported using this tech-
nique.^^'
^^
Threshold adjustment The threshold voltages for the two types of transistors often
must be comparable and below 1 V in magnitude. This condition allows for both
low-voltage operation of CMOS circuits {Vqq > Vj,, +
Vjp
) and higher-current
drive for the devices at higher values of V^)^ . Meeting this condition requires some
adjustment, however. If a given material (e.g., n^ polysilicon) is used as the gate for
each type of device, the work-function difference cjj^^ will be different for the n- and
p-channel transistors. This difference causes an asymmetry in the threshold voltages
of the two types of transistors. Figure 31 shows the calculated threshold voltages of
30
n* POLYSILICON GATE
Qf=0
Vbs =
d=250A
J I I I I I I
I I I
d=250A
10 10'" 10'" 10'
SUBSTRATE DOPING (cm-^)
Fig. 31 Calculated threshold voltages of n-channel (V7-,, ) and p-channel (Vj-^) transistors as a function of
their substrate's doping, assuming an n^ -polysilicon gate, zero fixed charge Qj. and zero back-gate bias
Vb5 . Curves for gate-oxide thicknesses (d) of 250 and 650 A are shown.

488 VLSI Technology
n- and p-channel devices as a function of their substrate doping. Note that we cannot
obtain
Vjp
< 0.7 V by simply lowering the p channel's substrate doping,
whereas we can obtain Vr„ < 0.7 V by adjusting the n channel's substrate doping.
To obtain the desired p-channel threshold voltage with n"^-polysilicon gates, a
shallow boron layer is often implanted into the channel region of the p-channel de-
^•^g 55.72
ji^g boron shifts the lower curves in Fig. 31 to more positive values. This
boron threshold-adjustment dose can also be implanted into the n-channel device to
raise the magnitude of Vj-,, . With a judicious choice of n- and p-type background dop-
ing, a single, nonselective boron implant can be used to set the desired threshold volt-
age of each type of device. This technique is illustrated in Fig. 32 which shows a plot
of Vrn and Vjp vs. the boron implant dose for devices having a 650-A gate oxide and
n"*^-polysilicon gates.
^'^
This CMOS structure uses an n well implanted into a p sub-
strate. Vjn increases as the boron dose is increased, because the surface concentration
of the p substrate is increased. The magnitude of Vxp decreases primarily because of
the negatively ionized charge (boron) in the silicon depletion layer. For lower n-well
implant doses, |
V^p
decreases more quickly as the threshold-adjustment dose is
increased.
2 4 6
B IMPLANT DOSE {XlO"cnn-2)
10
Fig. 32 Threshold voltages of n-channel (Vj^) and p-channel (Vt^,) transistors as a function of boron
threshold-adjustment dose. The CMOS structure uses an n well implanted into a p-type substrate whose
doping level is 6 x lO'"* atoms/cm- V-j-p results are shown for various implant doses of the n well. (After
Ohzone et al., Ref. 55.)

10'
I (AS
n-CHANNEL
rTDIFFUSION
DOSE = 40xlo'^cnn-2)
.THRESHOLD CONTROL
B IMPLANTATION
{4 0xl0"cm-2)
iZ
V
V Vbs+2<^F
10'
0.4 0.6 0.8 1.0 1.2 I.
DEPTH {^m)
^ lo'^
10'
I 10'
10'
p-CHANNEL
THRESHOLD CONTROL
'
B IMPLANTATION
(40x l0"cm-2)
EFFECTIVE IMPURITY
CONCENTRATION
: n-WELL
: (P DOSE
l5xl0'^Cm-2)
p-SUBSTRATE
(60xio'^cm-5)
I
JUNCTION
I DEPTH
I I
i 2 3 4 5 6
DEPTH (/i.m)
(a) (b)
Fig. 33 Calculated impurity profiles under the gate, (a) n-channel device with 6 x lO'** atoms/cm-^
p-substrate doping, and 4 x lO" atoms/cm- boron threshold-adjustment implant. The n^ source/drain
junction depth (0.4 ixm) is indicated. The insert shows the threshold voltage sensitivity to back-gate bias
due to the high-low doping profile, (b) p-channel device in an n well with the same boron threshold-
adjustment implant. The p^ source/drain junction depth (0.55 fxm) is indicated. (After Ohzone et al., Ref.
55.)
The desired threshold voltages of Vj^ — —'Vjp — 0.7 V are obtained by using an
n-well phosphorus dose of 1.5 x lO'^ atoms/cm^ and a threshold-adjustment boron
dose of 4 X 10" atoms/cm^. For these conditions, the calculated impurity profiles
under the gate for each type of device^^ are shown in Fig. 33a and b. The n MOSFET
uses arsenic for the source/drain impurity. Its threshold sensitivity to back-gate bias is
initially steep and then less sensitive at larger values of V55 (see insert in Fig. 33a)
—
which is a consequence of the high-low doping profile under the gate. The p-channel
device (Fig. 33b) uses BF2 for the source/drain because it results in a shallower
implant depth than B. Note that, as a result of the threshold-adjustment implant, a net
p region exists at the surface of the p-channel device and connects the p'^-source/drain
regions. This structure is analogous to a normally off, buried, n-channel MOSFET.
That is, the work-function difference of the n"^-polysilicon gate in the device of Fig.

490 VLSI Technology
33b depletes the p region from the surface, while the underlying n well depletes the p
region from below. Hence the boron threshold-adjustment layer is depleted of car-
riers (normally off). If a large enough threshold-adjustment dose is used (e.g.,
8 X lO" atoms/cm"^ in Fig. 32), the shallow p region will not be depleted for
Vg = and the device functions as a depletion-mode transistor (normally on).
The threshold-adjustment procedure discussed above is based on n'^-polysilicon
gates. The use of different gate materials requires different threshold-adjustment
techniques for the two types of devices. MoSi2 gates have a work-function 0.8 V
larger than that for n"^ polysilicon. CMOS devices using MoSi2 have been made''^
using arsenic or phosphorus channel implants for the n channel (buried channel) and
boron implants for the p channel to provide Vj,^ = ~Vtp = 0.8 V.
Latchup prevention The critical device parameters in latchup can be described using
the thyristor diagram in the insert of Fig. 27a. The current gains hf^ of the n-p-n and
p-n-p bipolar transistors are key parameters. If the product of the current gains of the
two devices exceeds unity, the device can latch. Several techniques have been used
to lower the current gains of the two devices, including gold doping and neutron irrad-
iation to reduce the minority-carrier lifetimes. ^^ These techniques are difficult to con-
trol and cause other deleterious effects in device operation (excess leakage, for exam-
ple). The vertical n-p-n gain can be reduced by the use of p"*^
buried-layers under p
wells, ^^ or the use of high-dose, high-energy boron p well implants.
^^'
''''
Another effective technique^^ is to reduce the resistances that shunt the emitter-
base junctions of the two types of bipolar devices shown in Fig. 27a. If these shunt
resistors are made small enough, a sufficient IR drop cannot be developed across them
to forward-bias the emitter-base junctions, and the device will not latch. The shunt
resistance of the lateral p-n-p emitter-base junction can be reduced by the use of an n
epitaxy over an n^ substrate.
^^'^^
As can be seen from Fig. 27b, a more conductive
substrate reduces the lateral resistance under the p"^ source. In addition, electrons
injected from the n"^-source/drain regions into the p tub can be collected vertically out
the back of the chip, which is solidly connected to Vqj^ . The additional processing
expense to grow the epitaxial layer must be weighed against the benefit of this effec-
tive method of latchup control.
In addition to the n-epitaxy/n^-substrate structure, proper circuit-layout tech-
niques must be employed to prevent latchup in CMOS ICs.^^ Guard rings which sur-
round n- and p-channel transistors in the input/output (I/O) circuitry can be used to
divert minority carriers from creating lateral IR drops. Input protection is critical in
guarding against external signals which induce latchup as well as overstress gate
oxides. The I/O devices are generally large enough to provide high off-chip drive
capability; in comparison, the additional area needed for guard rings is usually negli-
gible for complex chips.
11.6 MINIATURIZING VLSI CIRCUITS
In this section, we discuss some basic guides for the miniaturization of individual
devices and the ICs that they produce.

11.6.1 Basic Design Rules
The rules governing the dimensions of features that are permissible in designing and
laying out an IC in a particular technology are referred to as design rules. They are
generally a list of minimum feature sizes and separations between features (including
overlaps), which are consistent with the patterning and device limitations of a particu-
lar technology. Many factors are considered in deriving a set of manufacturable
design rules, and some of the importa

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