solid state electronics ktu module 5 slides

MODULE V
MOSFET scaling – need for scaling, constant voltage scaling and constant field
scaling, Sub threshold conduction in MOS. Short channel effects- Channel length
modulation, Drain Induced Barrier Lowering, Velocity Saturation, Threshold Voltage
Variations and Hot Carrier Effects. Non-Planar MOSFETs: Fin FET –Structure,
operation and advantages

MOSFET scaling – need for scaling
• Design of high density chip in MOS VLSI technology requires that packing density should
increase, accordingly size of the IC must decrease.
• The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as
scaling.
• Scaling of MOS transistors is concerned with systematic reduction of overall dimensions
of the devices.
• The proportional scaling of all devices in a circuit would certainly result in a reduction of
the total silicon area occupied by the circuit, thereby increasing the overall functional
density of the chip.
• There are two basic types of size-reduction strategies:
✓ Full scaling (Constant-field scaling)
✓Constant voltage scaling
CMOS Digital Integrated Circuits, Analysis And Design,sung-mo Kang, Yusuf Leblebigi,second Dition

Motivation for Scaling
• More transistors --> Higher performance
• Less delay time --> Higher frequency
• Less VDD --> Lower power consumption
Nanoelectronics:An overview by Dr.Santhanu Mahapatra

Full Scaling (Constant-Field Scaling)
• Preserve the magnitude of internal electric fields in the MOSFET, while the
dimensions are scaled down by a factor of S.

Influenceof scaling
• The gate oxide capacitance per unit area, on the other hand, is changed
• Aspect ratio WIL will remain unchanged under scaling.
• Trans conductance parameter kn will be scaled by a factor of S.
• Linear-mode drain current of the scaled MOSFET
• Saturation-mode drain current is reduced by the scaling factor.

• Power dissipation of the transistor will be reduced by the factor s2 .
• Gate oxide capacitance scaled down by a factor of s.

Constant-Voltage Scaling
• The power supply voltage and all terminal voltages be scaled down proportionally with
the device dimensions.
• Constant-voltage scaling is usually preferred over full scaling- Peripheral and interface
circuitry may require certain voltage levels for all input and output voltages, which in
turn would necessitate multiple power supply voltages and complicated level shifter
arrangements.

Influence of constant voltage scaling
• All dimensions of the MOSFET are reduced by a factor of S.
• Power supply voltage and the terminal voltages remain unchanged.
• Doping densities must be increased by a factor of s2.
• Gate oxide capacitance per unit area Cox is increased by a factor of S, which means
that the trans conductance parameter is increased by S.
• Linear mode drain current of the scaled MOSFET

• Saturation current of the device
• Power dissipation of the MOSFET increases by a factor of S.
• Power density (power dissipation per unit area) is found to increase by a factor of S3 .

Difference between full scaling and constant voltage scaling

Long-channel devices
o Width and length long enough so that edge effects from
the four sides can be neglected
o Channel length L must be much greater than the sum of
the drain and source depletion widths
Short channel devices
o Width and length short enough such that the edge
effects can not be neglected
o Devices with width and length short enough such that the
edge effects can not be neglected
14
https://people.rit.edu/lffeee/mosfet_s.pdf

Sub threshold conduction in MOS
• As per drain current expression ID=0 when VG=VT.
• There is some drain conduction below threshold- subthreshold conduction.
• This current is due to weak inversion in the channel between flat band and threshold (for
band bending between zero and 2φF), which leads to a diffusion current from source to
drain.
Where
Solid StateElectronic Devices,seventh edition, Ben G. Streetman •Sanjay Kumar Banerjee

• ID depends exponentially on gate bias, VG.
• VD has little influence on ID once VD exceeds a few kT > q.
• The slope of ID-VGS curve is known as the subthreshold
slope, S.
• It has typical values of 70 mV/decade at room
temperature
• A change in the input VG of 70 mV will change the output
ID by an order of magnitude.
• Smaller the value of S, the better the transistor is as a
switch.
• A small value of S means a small change in the input bias
can modulate the output current considerably.
• S is a measure of the efficacy of the gate potential in
• modulating ID.

Short Channel Effects
• A MOS transistor is called a short-channel device if its channel length is on the
same order of magnitude as the depletion region thicknesses of the source and
drain junctions.
• If the effective channel length Leff is approximately equal to the source and drain
junction depth x.
• Effects
(i) Limitations imposed on electron drift characteristics in the channel
(ii) Modification of the threshold voltage due to the shortening channel length.
CMOS Digital Integrated Circuits, Analysis AndDesign,sung-mo Kang, Yusuf Leblebigi,second Dition

Velocity Saturation
• As the effective channel length is decreases, lateral electric field EY along the channel
increases
• At low field: Electron drift velocity Vd in the channel is proportional to the electric field
• At high field: Drift velocity tends to saturate
• As E = 105 V/cm and higher, the electron drift velocity saturates to value of about vd(sat)=
107cm/s.
• Carrier velocity saturation actually reduces the saturation-mode current
• The current is no longer a quadratic function of the gate-to-source voltage VGS, and it is
virtually independent of the channel length

Mobility Degradation
• In short-channel MOS transistors, the carrier velocity in the channel is also a
function of the normal (vertical) electric-field component Ex.
• Vertical field influences the scattering of carriers (collisions suffered by the
carriers) in the surface region, the surface mobility is reduced with respect to the
bulk mobility
• It is given by the relation
• µno is the low-field surface electron mobility and ϴ is an empirical factor.

Threshold Voltage Variations
• In short-channel MOS transistors, n+ drain and source diffusion regions in the p-
type substrate induce a significant amount of depletion charge.
• Long-channel threshold voltage expression overestimates the depletion charge
supported by the gate voltage.

• The drain depletion region is larger than the source depletion region because the
positive drain-to-source voltage reverse-biases the drain-substrate junction.
• Significant portion of the total depletion region charge under the gate is actually due
to the source and drain junction depletion, rather than the bulk depletion induced by
the gate voltage.
• The threshold voltage expression must be modified to account for this reduction.
• ∆VT0 is the threshold voltage shift (reduction) due to the short-channel effect.
• The reduction term actually represents the amount of charge differential between a
rectangular depletion region and a trapezoidal depletion region.

• Let ∆ LS and ∆ LD represent the lateral extent of the depletion regions associated
with the source junction and the drain junction
• Let xds and xdD represent the depth of the pn-j unction depletion regions
associated with the source and the drain

• From figure
• On solving for ∆LD
• Similarly
• The amount of threshold voltage reduction AV70 due to short-channel effects

• As the channel lengths are reduced, the shared charge becomes a larger fraction
of the total, and this results in a VT roll-off as a function of L.
• Narrow width effect, where the VT goes up as the channel width Z is reduced for
very narrow devices.

Drain Induced Barrier lowering
• Unintended electrostatic interactions between the source and the drain is known
as Drain- Induced Barrier Lowering (DIBL).
• It may occur if
• Small channel length MOSFETs are not scaled properly
• Source/drain junctions are too deep or the channel doping is too low
• This leads to punch- through leakage or breakdown between the source and the
drain, and loss of gate control.

• As the drain bias is increased, the conduction band
edge in the drain is pulled down.
• The drain- channel depletion width expands.
• For a long channel MOSFET, the drain bias does
not affect the source- to- channel potential barrier,
which corresponds to the built- in potential of the
source-channel p- n junction.
• Hence, unless the gate bias is increased to lower
this potential barrier, there is little drain current.
• For a short channel MOSFET, as the drain bias is
raised and the conduction band edge in the drain
is pulled down.
• The source- channel potential barrier is lowered
due to DIBL.
• There can be significant drain leakage current, with
the gate being unable to shut it off.

• Solutions
• The source/drain junctions must be made sufficiently shallow (i.e., scaled properly)
as the channel lengths are reduced, to prevent DIBL.
• Secondly, the channel doping must be made sufficiently high to prevent the drain
from being able to control the source junction.
• Anti- punch- through implant in the channel
• Instead of implant throughout the channel a localized implant is done only near the
source/drains. These are known as halo or pocket implants.
• The higher doping reduces the source/drain depletion widths and prevents their
interaction.

Channel length modulation
➢ Assumption : Drain current is constant in
saturation region
➢ As Vds increases pinch off region extends along
the channel away from drain
➢ Effective channel length decreases
➢ Id = µ Cox (W/L) (Vgs-Vth)2
➢ Transistor current increases as Leff decreases
28
Analog VLSI: Circuits and Principles By Shih-Chii Liu
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GS
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Channel length modulation Continued……….
29
www-inst.eecs.berkeley.edu/~ee105/fa07/lectures/Lecture%2017.ppt

30
Cmos Digital Integrated Circuits By Sung-Mo Kang, Yusuf Leblebici

• For short channel MOSFETs, DIBL is related to the electrical modulation of the
channel length in the pinch- off region, L.
• Since the drain current is inversely proportional to the electrical channel length
• The fractional change in the channel length is proportional to the drain bias
where λ is the channel length modulation parameter
• Drain current is modified as
Channel length modulation

Hot Electron Effects
• If we simply reduced the dimensions of the device and kept the power supply
voltages the same, the internal electric fields in the device would increase.
• For ideal scaling, power supply voltages should also be reduced to keep the internal
electric fields reasonably constant.
• In practice, power supply voltages are not scaled hand- in- hand with the device
dimensions, partly because of other system- related constraints.
• The longitudinal electric fields in the pinch- off region, and the transverse electric
fields across the gate oxide, increase with MOSFET scaling.

• When an electron travels from the source to the drain
along the channel, it gains kinetic energy, and becomes a
“hot” electron.
• As it gains more kinetic energy, it moves higher up in the
conduction band.
• A few of the electrons can become energetic enough to
surmount the potential barrier between the Si channel
and the gate oxide .
• Some of these injected hot electrons can go through the
gate oxide and be collected as gate current, thereby
reducing the input impedance.
• Some of these electrons can be trapped in the gate oxide
as fixed oxide charges. This increases the flat band
voltage, and therefore the VT.
• Energetic hot carriers can rupture Si– H bonds that exist
at the Si-SiO2 interface, creating fast interface states that
degrade MOSFET parameters.
• Solution: Lightly doped drain structure

• As the electrons travel toward the drain and become
hot, they can create secondary EHPs by impact
ionization.
• The secondary electrons are collected at the drain, and
cause the drain current in saturation to increase with
drain bias at high voltages, thereby leading to a
decrease of the output impedance.
• The secondary holes are collected at the substrate as
substrate current.
• This current can create circuit problems such as noise or
latch up in CMOS circuits

Ultra –Thin- Body MOSFET (Planar)
❑ Control over short channel effects
❑ Layered Silicon-Insulator-Silicon in place of
conventional Silicon
❑ Lower junction leakage
❑ Better electrostatic control reduce S-D leakage
❑ For high density , high performance , low
power applications
36

Different device architectures
37

Double gate MOSFET (Non-Planar MOSFETs)
❑Second gate electrode at opposite side of silicon body
❑Two channels – Top & Bottom
❑Increased gate control
❑Advantages
✓ Increased scalability
✓ Lower junction capacitance
✓ Larger drive current
❑ Disadvantages
✓ Higher series S/D resistance
✓ Difficulty in fabrication
38

FinFET(Non planar MOSFET)
• Also called tri-gate transistor.
• FinFETs can be implemented either on bulk
silicon or SOI wafer.
• This FinFET structure consists of thin (vertical)
fin of silicon body on a substrate.
• The gate is wrapped around the channel
providing excellent control from three sides of
the channel.
• This structure is called the FinFET because its Si
body resembles the back fin of a fish.
Former TSMC CTO and Berkeley professor Chenming Hu and his team presented the concept of
FinFET in 1999
A Review Paper on CMOS, SOI and FinFET Technology By Pavan H Vora, Ronak Lad (Einfochips Pvt. Ltd.)
Fig:FinFET Structure

• In bulk-MOS (planner MOS), the channel is horizontal.
• In FinFET channel, it is vertical.
• For FinFET, the height of the channel (Fin) determines the
width of the device.
• The perfect width of the channel is given by
Width of Channel = 2 X Fin Height + Fin Width
• The drive current of the FinFET can be increased by
increasing the width of the channel i.e. by increasing the
height of the Fin.
• We can also increase the device drive current by
constructing parallel multiple fins connected together.
Fig: Multi fin FET Structure

• FinFET Working: The mode of operation of a FinFET does not differ from a traditional field
effect transistor. There is one source and one drain contact as well as a gate to control the
current flow.
• In conventional MOS, a doping is inserted into the channel, reducing the various SCEs and
ensuring high Vth.
• While in FinFET, the gate structure is wrapped around the channel and the body is thin,
providing better SCEs, so channel doping becomes optional.
• It implies that FinFET suffers less from dopant-induced variations.
• Low channel doping also ensures better mobility of the carriers inside the channel. Hence,
higher performance.

Types of FinFET
Bulk FinFETs: Design at 14 nm Node and Key Characteristics Jong-Ho Lee 44

Bulk V/S SOI FinFET
Bulk FinFET SOI FinFET
Deep etching needed simpler fabrication
Need isolation no isolation problem
Cheaper Expensive
45

Advantages:
✓FinFET has higher drive current.
✓Strain technology can be used to increase carrier mobility.
✓Improved transistor sub threshold swing due to greatly improved gate control.
✓Improved channel mobility due to reduced transverse electric field,
✓Reduced parasitic capacitancesfrom the absence of depletion capacitances,
leading to improved speed,
✓Reduced power consumption
✓Much Lower off-state current comparedto bulk counterpart.
Disadvantages:
o Width quantization
o Parasitic resistance is the main adverse factor which prevents FinFETs’ application,
which leads to lower speed and high noise.
o Complex manufacturing process
46

Trigate FinFET
• An extension of the FinFET structure, and
allows variable device widths
• Can have multiple fins connected
together to increase the total drive
strength
• It requires aggressive lithography
techniques.
47
Image :https://www.semiwiki.com/forum/content/3591-intel-ansys-enable-14nm-chip-production.html

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