Answers to Problems for Microelectronic Circuits, 8th Edition - Adel Sedra & Kenneth Carless Smith

Table of Contents
Problems Solutions 2
Exercise Solutions 30
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Chapter 1–1
Solutions to End-of-Chapter Problems
1.1 (a) I =
V
R
=
0.5 V
1 k
= 0.5 mA
(b) R =
V
I
=
2 V
1 mA
= 2 k
(c) V = I R = 0.1 mA × 20 k = 2 V
(d) I =
V
R
=
5 V
100
= 0.05 A = 50 mA
Note: Volts, milliamps, and kilohms constitute a
consistent set of units.
1.2 (a) P = I2
R = (20 × 10−3
)2
× 1 × 103
= 0.4 W
Thus, R should have a
1
2
-W rating.
(b) P = I2
R = (40 × 10−3
)2
× 1 × 103
= 1.6 W
Thus, the resistor should have a 2-W rating.
(c) P = I2
R = (1 × 10−3
)2
× 100 × 103
= 0.1 W
Thus, the resistor should have a
1
8
-W rating.
(d) P = I2
R = (4 × 10−3
)2
× 10 × 103
= 0.16 W
1
4
-W rating.
(e) P = V 2
/R = 202
/(1 × 103
) = 0.4 W
1
2
-W rating.
(f) P = V 2
/R = 112
/(1 × 103
) = 0.121 W
Thus, a rating of
1
8
W should theoretically
suffice, though
1
4
W would be prudent to allow
for inevitable tolerances and measurement errors.
1.3 (a) V = I R = 2 mA × 1 k = 2 V
P = I2
R = (2 mA)2
× 1 k = 4 mW
(b) R = V/I = 1 V/20 mA = 50 k
P = V I = 1 V × 20 mA = 20 mW
(c) I = P/V = 100 mW/1 V = 100 mA
R = V/I = 1 V/100 mA = 10
(d) V = P/I = 2 mW/0.1 mA
= 20 V
R = V/I = 20 V/0.1 mA = 200 k
(e) P = I2
R ⇒ I =

P/R
I =

100 mW/1 k = 10 mA
V = I R = 10 mA × 1 k = 10 V
Note: V, mA, k, and mW constitute a
consistent set of units.
1.4 See figure on next page, which shows how to
realize the required resistance values.
1.5 Shunting the 10 k by a resistor of value of
R result in the combination having a resistance
Req,
Req =
10R
R + 10
Thus, for a 1% reduction,
R
R + 10
= 0.99 ⇒ R = 990 k
For a 5% reduction,
R
R + 10
= 0.95 ⇒ R = 190 k
For a 10% reduction,
R
R + 10
= 0.90 ⇒ R = 90 k
For a 50% reduction,
R
R + 10
= 0.50 ⇒ R = 10 k
Shunting the 10 k by
(a) 1 M results in
Req =
10 × 1000
1000 + 10
=
10
1.01
= 9.9 k
a 1% reduction;
(b) 100 k results in
Req =
10 × 100
100 + 10
=
10
1.1
= 9.09 k
a 9.1% reduction;
(c) 10 k results in
Req =
10
10 + 10
= 5 k
a 50% reduction.
1.6 VO = VDD
R2
R1 + R2
To find RO , we short-circuit VDD and look back
into node X,
RO = R2 R1 =
R1 R2
R1 + R2
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Chapter 1–2
This figure belongs to Problem 1.4.
All resistors are 5 k
12.5 kΩ
23.75 kΩ
1.67 kΩ
20 kΩ
1.7 Use voltage divider to find VO
VO = 1
2
2 + 1
= 2 V
Equivalent output resistance RO is
RO = (2 k 1 k) = 0.667 k
The extreme values of VO for ±5% tolerance
resistor are
VOmin = 3
2(1 − 0.05)
2(1 − 0.05) + 1(1 + 0.05)
= 1.93 V
VOmax = 3
2(1 + 0.05)
2(1 + 0.05) + 1(1 − 0.05)
= 2.07 V
3 V
VO
RO
1 k
2 k
The extreme values of RO for ±5% tolerance
resistors are 667 × 1.05 = 700 k and
667 × 0.95 = 633 k.
1.8
3 V
6 V
10 k
(a)
10 k
10 k
9 V
R 10 k // 20 k
6.67 k
R 20 // 10 k
6.67 k
4.5 V
(b)
10 k
10 k
R 10 // 10
5 k
9 V

Chapter 1–3
3 V
9 V
10 k
(c)
10 k 10 k
R 10 // 10 // 10
3.33 k
10 k
10 k 10 k
9 V
6 V
(d)
R 10 // 10 // 10
3.33 k
Voltage generated:
+3V [two ways: (a) and (c) with (c) having lower
output resistance]
+4.5 V (b)
+6V [two ways: (a) and (d) with (d) having a
lower output resistance]
1.9
1 k
470
3 V
VO
VO = 3
0.47
1 + 0.47
= 0.96 V
To increase VO to 1.00 V, we shunt the 1-k
resistor by a resistor R whose value is such that
1 R = 2 × 0.47.
Thus
1
1
+
1
R
=
1
0.94
15 V
5.00 V
10 k
4.7 k
R
⇒ R = 15.67 k
Now,
RO = 1 k R 0.47 k
= 0.94 4.7 =
0.94
3
= 313
To make RO = 333 , we add a series resistance
of approximately 20 , as shown below,
3 V
1 k
15.7 k
20

RO
VO
0.47 k
1.10
I2
I1
I V

R2
R1
V = I (R1 R2)
= I
R1 R2
R1 + R2
I1 =
V
R1
= I
R2
R1 + R2
I2 =
V
R2
= I
R1
R1 + R2
1.11 The parallel combination of the resistors is
R where

Chapter 1–4
1
R
=
N
3
i=1
1/Ri
The voltage across them is
V = I × R =
I
4N
i=1 1/Ri
Thus, the current in resistor Rk is
Ik = V/Rk =
I/Rk
4N
i=1 1/Ri
1.12 Connect a resistor R in parallel with RL .
To make IL = I/4 (and thus the current through
R, 3I/4), R should be such that
6I/4 = 3I R/4
⇒ R = 2 k
I
I R
RL 6 k
3
4
IL
I
4
1.13
I R1
Rin
R
0.2I 0.8I
To make the current through R equal to 0.2I, we
shunt R by a resistance R1 having a value such
that the current through it will be 0.8I; thus
0.2I R = 0.8I R1 ⇒ R1 =
R
4
The input resistance of the divider, Rin, is
Rin = R R1 = R
R
4
=
1
5
R
Now if R1 is 10% too high, that is, if
R1 = 1.1
R
4
the problem can be solved in two ways:
(a) Connect a resistor R2 across R1 of value such
that R2 R1 = R/4, thus
R2(1.1R/4)
R2 + (1.1R/4)
=
R
4
1.1R2 = R2 +
1.1R
4
⇒ R2 =
11R
4
= 2.75 R
Rin = R
1.1R
4

11R
4
= R
R
4
=
R
5
I R
Rin
1.1R
4
R
4
11R
4
}
0.2I
(b) Connect a resistor in series with the load
resistor R so as to raise the resistance of the load
branch by 10%, thereby restoring the current
division ratio to its desired value. The added
series resistance must be 10% of R (i.e., 0.1R).
0.1R
1.1R
4
Rin
R
0.8I
0.2I
I
Rin = 1.1R
1.1R
4
=
1.1R
5
that is, 10% higher than in case (a).
1.14 The source current is
iS = 0.5 sin ωt mA
having peak amplitude
Is = 0.5 mA
To ensure a peak voltage across the source of
Vs,max = 1 V, a load must be connected with
maximum value
RL,max = Vs,max/Is = 0.5/1 = 2 k
If RL = 10 k, a second resistor R must be
connected in parallel so that
R RL = 2 k
⇒
1
R
+
1
10
=
1
2
⇒ R =
1
1/2 − 1/10
= 2.5 k

Chapter 1–5
In this case,
Il = Is ×
R
RL + R
= 0.5 ×
2.5
10 + 2.5
= 0.1 mA
Thus, iL = 0.1 sin ωt mA.
1.15 (a) Between terminals 1 and 2:
3 V VTh 2..25
RTh 75
RTh
2
1
2
1
300
100
100
2.25 V
75

300
(b) Same procedure is used for (b) to obtain
0.75 V
2
3
75
(c) Between terminals 1 and 3, the open-circuit
voltage is 3 V. When we short-circuit the voltage
source, we see that the Thévenin resistance will
be zero. The equivalent circuit is then
3 V
1
3
1.16
3 k
12.31 k
0.77 V I
Now, when a resistance of 3 k is connected
between node 4 and ground,
I =
0.77
12.31 + 3
= 0.05 mA
1.17 (a) Node equation at the common mode
yields
I3 = I1 + I2
Using the fact that the sum of the voltage drops
across R1 and R3 equals 10 V, we write
10 = I1 R1 + I3 R3
= 10I1 + (I1 + I2) × 2
= 12I1 + 2I2

Chapter 1–6
5 V
10 V
5 k
10 k
2 k
R2
R1
R3
I2 I1
I3
V
That is,
12I1 + 2I2 = 10 (1)
Similarly, the voltage drops across R2 and R3 add
up to 5 V, thus
5 = I2 R2 + I3 R3
= 5I2 + (I1 + I2) × 2
which yields
2I1 + 7I2 = 5 (2)
Equations (1) and (2) can be solved together by
multiplying Eq. (2) by 6:
12I1 + 42I2 = 30 (3)
Now, subtracting Eq. (1) from Eq. (3) yields
40I2 = 20
⇒ I2 = 0.5 mA
Substituting in Eq. (2) gives
2I1 = 5 − 7 × 0.5 mA
⇒ I1 = 0.75 mA
I3 = I1 + I2
= 0.75 + 0.5
= 1.25 mA
V = I3 R3
= 1.25 × 2 = 2.5 V
To summarize:
I1 = 0.75 mA I2 = 0.5 mA
I3 = 1.25 mA V = 2.5 V
(b) A node equation at the common node can be
written in terms of V as
10 − V
R1
+
5 − V
R2
=
V
R3
Thus,
10 − V
10
+
5 − V
5
=
V
2
⇒ 0.8V = 2
⇒ V = 2.5 V
Now, I1, I2, and I3 can be easily found as
I1 =
10 − V
10
=
10 − 2.5
10
= 0.75 mA
I2 =
5 − V
5
=
5 − 2.5
5
= 0.5 mA
I3 =
V
R3
=
2.5
2
= 1.25 mA
Method (b) is much preferred, being faster, more
insightful, and less prone to errors. In general,
one attempts to identify the lowest possible
number of variables and write the corresponding
minimum number of equations.
1.18 Find the Thévenin equivalent of the circuit
to the left of node 1.
Between node 1 and ground,
RTh = (1 k 1.2 k) = 0.545 k
VTh = 10 ×
1.2
1 + 1.2
= 5.45 V
Find the Thévenin equivalent of the circuit to the
right of node 2.
Between node 2 and ground,

Chapter 1–7
RTh = 9.1 k 11 k = 4.98 k
VTh = 10 ×
11
11 + 9.1
= 5.47 V
The resulting simplified circuit is
R5 2 k
V5
1 2
5.45 V 5.47 V
I5
0.545 k 4.98 k

I5 =
5.47 − 5.45
4.98 + 2 + 0.545
= 2.66 µA
V5 = 2.66 µA × 2 k
= 5.32 mV
1.19 We first find the Thévenin equivalent of the
source to the right of vO .
V = 4 × 1 = 4 V
Then, we may redraw the circuit in Fig. P1.19 as
shown below
5 V 1 V
3 k 1 k
vo
Then, the voltage at vO is found from a simple
voltage division.
vO = 1 + (5 − 1) ×
1
3 + 1
= 2 V
1.20 Refer to Fig. P1.20. Using the voltage
divider rule at the input side, we obtain
vπ
vs
=
rπ
rπ + Rs
(1)
At the output side, we find vo by multiplying the
current gmvπ by the parallel equivalent of ro
and RL ,
vo = −gmvπ (ro RL ) (2)
Finally, vo/vs can be obtained by combining Eqs.
(1) and (2) as
vo
vs
= −
rπ
rπ + Rs
gm(ro RL )
1.21 (a) T = 10−4
µs = 10−11
s
f =
1
T
= 1011
Hz
ω = 2π f = 6.28 × 1011
rad/s
(b) f = 3 GHz = 3 × 109
Hz
T =
1
f
= 3.33 × 10−10
s
ω = 2π f = 1.88 × 1010
rad/s
(c) ω = 6.28 × 104
rad/s
f =
ω
2π
= 104
Hz
T =
1
f
= 10−4
s
(d) T = 10−7
s
f =
1
T
= 107
Hz
ω = 2π f = 6.28 × 107
rad/s
(e) f = 60 Hz
T =
1
f
= 1.67 × 10−2
s
ω = 2π f = 3.77 × 102
rad/s
(f) ω = 100 krad/s = 105
rad/s
f =
ω
2π
= 1.59 × 104
Hz
T =
1
f
= 6.28 × 10−5
s
(g) f = 270 MHz = 2.7 × 108
Hz
T =
1
f
= 3.70 × 10−9
s
ω = 2π f = 1.696 × 109
rad/s
1.22 (a) Z = 1 k at all frequencies
(b) Z = 1 /jωC = − j
1
2π f × 10 × 10−9
At f = 60 Hz, Z = − j265 k
At f = 100 kHz, Z = − j159
At f = 1 GHz, Z = − j0.016
(c) Z = 1 /jωC = − j
1
2π f × 10 × 10−12
At f = 60 Hz, Z = − j0.265 G
At f = 100 kHz, Z = − j0.16 M
At f = 1 GHz, Z = − j15.9
(d) Z = jωL = j2π f L = j2π f × 10 × 10−3
At f = 60 Hz, Z = j3.77
At f = 100 kHz, Z = j6.28 k
At f = 1 GHz, Z = j62.8 M

Chapter 1–8
(e) Z = jωL = j2π f L = j2π f (1 × 10−6
)
f = 60 Hz, Z = j0.377 m
f = 100 kHz, Z = j0.628
f = 1 GHz, Z = j6.28 k
1.23 (a) Z = R +
1
jωC
= 103
+
1
j2π × 10 × 103
× 10−9
= (1 − j15.9) k
(b) Y =
1
R
+ jωC
=
1
103
+ j2π × 10 × 103
× 0.01 × 10−6
= 10−3
(1 + j0.628)
Z =
1
Y
=
103
1 + j0.628
=
103
(1 − j0.628)
1 + 0.6282
= (717 − j450)
(c) Y =
1
R
+ jωC
=
1
10 × 103
+ j2π × 10 × 103
× 100 × 10−12
= 10−4
(1 + j0.0628)
Z =
104
1 + j0.0628
= (9.96 − j0.626) k
(d) Z = R + jωL
= 100 × 103
+ j2π × 10 × 103
× 10 × 10−3
= 105
+ j6.28 × 100
= (105
+ j628)
1.24 Y =
1
jωL
+ jωC
=
1 − ω2
LC
jωL
⇒ Z =
1
Y
=
jωL
1 − ω2 LC
The frequency at which |Z| = ∞ is found letting
the denominator equal zero:
1 − ω2
LC = 0
⇒ ω =
1
√
LC
At frequencies just below this, ∠Z = +90◦
.
At frequencies just above this, ∠Z = −90◦
.
Since the impedance is infinite at this frequency,
the current drawn from an ideal voltage source is
zero.
1.25
is
Rs
Rs

vs
Thévenin
equivalent
Norton
equivalent
voc = vs
isc = is
vs = is Rs
Thus,
Rs =
voc
isc
(a) vs = voc = 3 V
is = isc = 3 mA
Rs =
voc
isc
=
1 V
3 mA
= 1 k
(b) vs = voc = 0.5 V
is = isc = 50 µA
Rs =
voc
isc
=
0.5 V
50 µA
= 0.1 M = 10 k
1.26
Rs
RL

vs io
iO
vS
=
1
RL + RS
⇒ vS = iO (RL + RS)
Thus,
vS = 10−4
×

105
+ RS

= 10 + 10−4
× RS (1)
and,
vS = 5×10−4

104
+ RS

= 5+5×10−4
× RS(2)
Subtracting equation (2) from equation (1) gives
0 = 5 − 4 × 10−4
× RS
⇒ RS =
5
4 × 10−4
= 12.5 k
Substituting into equation (1),
vS = 10 + 10−4
× 12.5 × 103
= 11.25 V
Finally, the Norton equivalent source is found as
follows,
iS = vS/RS = 900 µA

Chapter 1–9
1.27
PL = v2
O ×
1
RL
= v2
S
R2
L
(RL + RS)2
×
1
RL
= v2
S
RL
(RL + RS)2
Since we are told that the power delivered to a
16 speaker load is 75% of the power delivered
to a 32 speaker load,
PL (RL = 16) = 0.75 × PL (RL = 32)
16
(RS + 32)2
= 0.75 ×
32
(RS + 32)2
√
16
RS + 32
=
√
24
RS + 32
⇒ (
√
24 =
√
16)RS =
√
16 × 32 −
√
24 × 16
0.9RS = 49.6
RS = 55.2
vs vO
Rs
RL

1.28 The observed output voltage is 0.5 mV/ ◦
C,
which is one quarter the voltage specified by the
sensor, presumably under open-circuit conditions:
that is, without a load connected. It follows that
that sensor internal resistance must be equal to 3
times RL, that is, 30 k.
1.29

vs vo Rs
Rs
io

is vo
io
vo = vs − io Rs
Open-circuit
(io 0)
voltage
0
Rs
vs
vs
vo
is
io
Slope Rs
Short-circuit (vo 0) current
1.30 The nominal values of VL and IL are
given by
VL =
RL
RS + RL
VS
IL =
VS
RS + RL
After a 10% increase in RL , the new values
will be
VL =
1.1RL
RS + 1.1RL
VS
IL =
VS
RS + 1.1RL
(a) The nominal values are
VL =
200
5 + 200
× 1 = 0.976 V
IL =
1
5 + 200
= 4.88 µA
will be
VL =
1.1 × 200
5 + 1.1 × 200
= 0.978 V
IL =
1
5 + 1.1 × 200
= 4.44 µA
These values represent a 2% and 9% change,
respectively. Since the load voltage remains
relatively more constant than the load current, a
Thévenin source is more appropriate here.
(b) The nominal values are
VL =
50
5 + 50
× 1 = 0.909 V
IL =
1
5 + 50
= 18.18 mA
will be
VL =
1.1 × 50
5 + 1.1 × 50
= 0.917 V
IL =
1
5 + 1.1 × 50
= 16.67 mA
respectively. Since the load voltage remains
relatively more constant than the load current, a
Thévenin source is more appropriate here.
(c) The nominal values are
VL =
0.1
2 + 0.1
× 1 = 47.6 mV
IL =
1
2 + 0.1
= 0.476 mA
will be
VL =
1.1 × 0.1
2 + 1.1 × 0.1
= 52.1 mV
IL =
1
2 + 1.1 × 0.1
= 0.474 mA
These values represent a 9% and 0.4% change,
respectively. Since the load current remains

Chapter 1–10
relatively more constant than the load voltage, a
Norton source is more appropriate here. The
Norton equivalent current source is
IS =
VS
RS
=
1
2
= 0.5 mA
(d) The nominal values are
VL =
16
150 + 16
× 1 = 96.4 mV
IL =
1
150 + 16
= 6.02 mA
will be
VL =
1.1 × 16
150 + 1.1 × 16
= 105 mV
IL =
1
150 + 1.1 × 16
= 5.97 mA
respectively. Since the load current remains
relatively more constant than the load voltage, a
Norton source is more appropriate here. The
Norton equivalent current source is
IS =
VS
RS
=
1
150
= 6.67 mA
1.31
Rs RL
RL
is
⫹
⫺
⫹
⫺
vs vo vo
Rs io
io
⫹
⫺
RL represents the input resistance of the processor
For vo = 0.95vs
0.95 =
RL
RL + Rs
⇒ RL = 19Rs
For io = 0.95is
0.95 =
Rs
Rs + RL
⇒ RL = RS/19
1.32
Case ω (rad/s) f(Hz) T(s)
a 3.14 × 1010
5 × 109
0.2 × 10−9
b 2 × 109
3.18 × 108
3.14 × 10−9
c 6.28 × 1010
1 × 1010
1 × 10−10
d 3.77 × 102
60 1.67 × 10−2
e 6.28 × 104
1 × 104
1 × 10−4
f 6.28 × 105
1 × 105
1 × 10−5
1.33 (a) Vpeak = 117 ×
√
2 = 165 V
(b) Vrms = 33.9/
√
2 = 24 V
(c) Vpeak = 220 ×
√
2 = 311 V
(d) Vpeak = 220 ×
√
2 = 311 kV
1.34 (a) v = 3 sin(2π × 20 × 103
t) V
(b) v = 120
√
2 sin(2π × 60) V
(c) v = 0.1 sin(108
t) V
(d) v = 0.1 sin(2π × 109
t) V
1.35 The waveform is symmetrical, and therefore
has an average value of 0 V. Its lowest and
highest values are -1 V and +1 V respectively. Its
frequency is 1/0.5 ms = 2 kHz. It may be
expressed as a sum of sinusoids using Eq. (1.2),
1
π

sin 2π × 2000t +
1
3
sin 6π × 2000t
+
1
5
sin 10π × 2000t + . . .

V
0.5 ms
⫹1 V
⫺1 V
t
v
1.36 The two harmonics have the ratio
126/98 = 9/7. Thus, these are the 7th and 9th
harmonics. From Eq. (1.2), we note that the
amplitudes of these two harmonics will have the
ratio 7 to 9, which is confirmed by the
measurement reported. Thus the fundamental will
have a frequency of 98/7, or 14 kHz, and peak
amplitude of 63 × 7 = 441 mV. The rms value of
the fundamental will be 441/
√
2 = 312 mV. To
find the peak-to-peak amplitude of the square
wave, we note that 4V/π = 441 mV. Thus,
Peak-to-peak amplitude
= 2V = 441 ×
π
2
= 693 mV
Period T =
1
f
=
1
14 × 103
= 71.4 µs
1.37 The rms value of a symmetrical square
wave with peak amplitude V̂ is simply V̂ . Taking
the root-mean-square of the first 5 sinusoidal
terms in Eq. (1.2) gives an rms value of,
4V̂
π
√
2

12 +

1
3
2
+

1
5
2
+

1
7
2
+

1
9
2
= 0.980V̂
which is 2% lower than the rms value of the
square wave.

Chapter 1–11
1.38 If the amplitude of the square wave is Vsq,
then the power delivered by the square wave to a
resistance R will be V 2
sq/R . If this power is to be
equal to that delivered by a sine wave of peak
amplitude V̂ , then
⫺Vsq
Vsq
0
T
V 2
sq
R
=
(V̂ /
√
2)
2
R
Thus, Vsq = V̂ /
√
2 . This result is independent of
frequency.
1.39
Decimal Binary
0 0
5 101
13 1101
32 10000
63 111111
1.40
b3 b2 b1 b0 Value Represented
0 0 0 0 +0
0 0 0 1 +1
0 0 1 0 +2
0 0 1 1 +3
0 1 0 0 +4
0 1 0 1 +5
0 1 1 0 +6
0 1 1 1 +7
1 0 0 0 –0
1 0 0 1 –1
1 0 1 0 –2
1 0 1 1 –3
1 1 0 0 –4
1 1 0 1 –5
1 1 1 0 –6
1 1 1 1 –7
Note that there are two possible representations
of zero: 0000 and 1000. For a 0.5-V step size,
analog signals in the range ±3.5 V can be
represented.
Input Steps Code
+2.5 V +5 0101
−3.0 V −6 1110
+2.7 +5 0101
−2.8 −6 1110
1.41 (a) An N-bit DAC produces 2N
discrete
equally spaced levels over a range of
VFS − 0 = VFS. Thus, the levels are spaced
VLSB =
VFS
(2N − 1)
(1)
(b) Any voltage within the range 0 to VFS can be
approximated by the nearest DAC output level,
which will be up to VLSB/2 above or below the
desired voltage. Thus, the maximum quantization
error of the converter is
VLSB/2 = VFS/2(2N
− 1).
(c) To obtain a resolution of 2 mV or less, using
Eq. (1)
0.002 ≤
5
(2N − 1)
⇒ N ≥ log2

5
0.002
+ 1

= 11.3
Taking the minimum integer satisfying this
condition, we require a 12-bit DAC which
provides a resolution of
VLSB =
5
212 − 1
= 1.22 mV
1.42 (a) When bi = 1, the ith switch is in
position 1 and a current (Vref /2i
R) flows to the
output. Thus iO will be the sum of all the currents
corresponding to “1” bits, that is,
iO =
Vref
R

b1
21
+
b2
22
+ · · · +
bN
2N

(b) bN is the LSB
b1 is the MSB
(c) iOmax =
10 V
10 k

1
21
+
1
22
+
1
23
+
1
24
+
1
25
+
1
26
+
1
27
+
1
28

= 0.99609375 mA
Corresponding to the LSB changing from 0 to 1
the output changes by (10/10) × 1/28
=
3.91 µA.
1.43 There will be 44,100 samples per second
with each sample represented by 16 bits. Thus the

Chapter 1–12
throughput or speed will be 44, 100 × 16 =
7.056 × 105
bits per second.
1.44 Each pixel requires 8 + 8 + 8 = 24 bits to
represent it. We will approximate a megapixel as
106
pixels, and a Gbit as 109
bits. Thus, each
image requires 24 × 10 × 106
= 2.4 × 108
bits.
The number of such images that fit in 16 Gbits of
memory is

2.4 × 108
16 × 109
= 66.7 = 66
1.45 (a) Av =
vO
vI
=
10 V
100 mV
= 100 V/V
or 20 log 100 = 40 dB
Ai =
iO
iI
=
vO /RL
iI
=
10 V/100
100 µA
=
0.1 A
100 µA
= 1000 A/A
or 20 log 1000 = 60 dB
Ap =
vO iO
vI iI
=
vO
vI
×
iO
iI
= 100 × 1000
= 105
W/W
or 10 log 105
= 50 dB
(b) Av =
vO
vI
=
1 V
10 µV
= 1 × 105
V/V
or 20 log 1 × 105
= 100 dB
Ai =
iO
iI
=
vO /RL
iI
=
1 V/10 k
100 nA
=
0.1 mA
100 nA
=
0.1 × 10−3
100 × 10−9
= 1000 A/A
or 20 log Ai = 60 dB
Ap =
vO iO
vI iI
=
vO
vI
×
iO
iI
= 1 × 105
× 1000
= 1 × 108
W/W
or 10 log AP = 80 dB
(c) Av =
vO
vi
=
5 V
1 V
= 5 V/V
or 20 log 5 = 14 dB
Ai =
iO
iI
=
vO /RL
iI
=
5 V/10
1 mA
=
0.5 A
1 mA
= 500 A/A
or 20 log 500 = 54 dB
Ap =
vO iO
vI iI
=
vO
vI
×
iO
iI
= 5 × 500 = 2500 W/W
or 10 log Ap = 34 dB
1.46
0.2 V
2.2 V
+3 V
3 V

vo
t
1 mA
100
ii
RL
vi
The voltage gain is
Vo
Vi
=
2.2
0.2
= 11 V/V = 20.8 dB
The current gain is
Io
Ii
=
2.2/0.1
1.0
= 22 A/A = 26.8 dB
The power gain is
Vo Io/2
Vi Ii /2
= 11 × 22 = 242 W/W = 23.8 dB
The supply power is
V 2
o
2RL
×
1
η
=
2.22
2 × 0.1 × 0.1
= 242 mW
Since the power is drawn from ±3 V supplies, the
supply current must be
242
3 − (−3)
= 40.3 mA
The power dissipated in the amplifier is the total
power drawn from the supply, less the power
dissipated in the load.
242 −
2.22
2 × 0.1
= 217.8 mW
1.47 For ±5 V supplies:
The largest undistorted sine-wave output is of
4-V peak amplitude or 4/
√
2 = 2.8 Vrms. Input
needed is 14 mVrms.
For ±10-V supplies, the largest undistorted
sine-wave output is of 9-V peak amplitude or
6.4 Vrms. Input needed is 32 mVrms.

Chapter 1–13
vO
vI
200 V/V
VDD 1.0
VDD 1.0
For ±15-V supplies, the largest undistorted
sine-wave output is of 14-V peak amplitude or
9.9 Vrms. The input needed is 9.9 V/200 =
49.5 mVrms.
1.48 vo = Avovi
RL
RL + Ro
= Avo

vs
Ri
Ri + Rs

RL
RL + Ro

vi

vi
vs Ri
Rs

RL
Avovi
Ro
Thus,
vo
vs
= Avo
Ri
Ri + Rs
RL
RL + Ro
(a) Avo = 100, Ri = 10Rs, RL = 10Ro
vo
vs
= 100 ×
10Rs
10Rs + Rs
×
10Ro
10Ro + Ro
= 82.6 V/V or 20 log 82.6 = 38.3 dB
(b) Avo = 100, Ri = Rs, RL = Ro
vo
vs
= 100 ×
1
2
×
1
2
= 25 V/V or 20 log 25 = 28 dB
(c) Avo = 100 V/V, Ri = Rs/10, RL = Ro/10
vo
vs
= 100
Rs/10
(Rs/10) + Rs
Ro/10
(Ro/10) + Ro
= 0.826 V/V or 20 log 0.826 = −1.7 dB
1.49

vi
vo
100
500
1 M 100vi
20 log Avo = 40 dB ⇒ Avo = 100 V/V
Av =
vo
vi
= 100 ×
500
500 + 100
= 83.3 V/V
or 20 log 83.3 = 38.4 dB
Ap =
v2
o/500
v2
i /1 M
= A2
v × 104
= 1.39 × 107
W/W
or 10 log (1.39 × 107
) = 71.4 dB.
For a peak output sine-wave current of 20 mA,
the peak output voltage will be 20 mA × 500
= 10 V. Correspondingly vi will be a sine wave
with a peak value of 10 V/Av = 10/83.3, or an
rms value of 10/(83.3 ×
√
2) = 0.085 V.
Corresponding output power = (10/
√
2)2
/500
= 0.1 W
1.50 (a)
vo
vs
=
vi
vs
×
vo
vi
=
1
5 + 1
× 100 ×
100
200 + 100
= 5.56 V/V
Much of the amplifier’s 100 V/V gain is lost in
the source resistance and amplifier’s output
resistance. If the source were connected directly
to the load, the gain would be
vo
vs
=
0.1
5 + 0.1
= 0.0196 V/V
This is a factor of 284× smaller than the gain
with the amplifier in place!
(b)
The equivalent current amplifier has a dependent
current source with a value of
100 V/V
200
× ii =
100 V/V
200
× 1000 × vi
= 500 × ii
Thus,
io
is
=
ii
is
×
io
ii
=
5
5 + 1
× 500 ×
200
200 + 100
= 277.8 A/A
Using the voltage amplifier model, the current
gain can be found as follows,
io
is
=
ii
is
×
vi
ii
×
io
vi
=
5
5 + 1
× 1000 ×
100 V/V
200 + 100
= 277.8 A/A

Chapter 1–14

vi
vs
io
5 k
1 k
200 k

vo 100
100 vi

Figure 1
5 k 1 k
ii
is 200
500 ii 100
io
Figure 2
1.51

vi
200 k
1 M
1 V

vo
20
100
1vi
vo = 1 V ×
1 M
1 M + 200 k
× 1 ×
100
100 + 20
=
1
1.2
×
100
120
= 0.69 V
Voltage gain =
vo
vs
= 0.69 V/V or −3.2 dB
Current gain =
vo/100
vs/1.2 M
= 0.69 × 1.2 × 104
= 8280 A/A or 78.4 dB
Power gain =
v2
o/100
v2
s /1.2 M
= 5713 W/W
or 10 log 5713 = 37.6 dB
(This takes into account the power dissipated in
the internal resistance of the source.)
1.52 In Example 1.3, when the first and the
second stages are interchanged, the circuit looks
like the figure above, and
vi1
vs
=
100 k
100 k + 100 k
= 0.5 V/V
Av1 =
vi2
vi1
= 100 ×
1 M
1 M + 1 k
= 99.9 V/V
Av2 =
vi3
vi2
= 10 ×
10 k
10 k + 1 k
= 9.09 V/V
Av3 =
vL
vi3
= 1 ×
100
100 + 10
= 0.909 V/V
Total gain = Av =
vL
vi1
= Av1 × Av2 × Av3
= 99.9 × 9.09 × 0.909 = 825.5 V/V
The voltage gain from source to load is
vL
vs
=
vL
vi1
×
vi1
vS
= Av ·
vi1
vS
= 825.5 × 0.5
= 412.7 V/V
The overall voltage has reduced appreciably. This
is because the input resistance of the first stage,

Chapter 1–15
Rin, is comparable to the source resistance Rs. In
Example 1.3 the input resistance of the first stage
is much larger than the source resistance.
1.53 (a) Case S-A-B-L (see figure below):
vo
vs
=
vo
vib
×
vib
via
×
via
vs
=

10 ×
100
100 + 1000

×

100 ×
10
10 + 10

×

100
100 + 100

vo
vs
= 22.7 V/V and gain in dB 20 log 22.7 =
27.1 dB
(b) Case S-B-A-L (see figure below):
vo
vs
=
vo
via
·
via
vib
·
vib
vs
=

100 ×
100
100 + 10 K

×

10 ×
100 K
100 K + 1 K

×

10 K
10 K + 100 K

vo
vs
= 0.89 V/V and gain in dB is 20 log 0.89 =
−1 dB. Obviously, case a is preferred because it
provides higher voltage gain.
1.54 Each of stages #1, 2, ..., (n − 1) can be
represented by the equivalent circuit:
vo
vs
=
vi1
vs
×
vi2
vi1
×
vi3
vi2
× · · · ×
vin
vi(n−1)
×
vo
vin
where
vi1
vs
=
100 k
100 k + 50 k
= 0.667 V/V
This figure belongs to 1.53, part (a).
This figure belongs to 1.53, part (b).
vo
vin
= 15 ×
200
1 k + 200
= 2.5 V/V
vi2
vi1
=
vi3
vi2
= · · · =
vin
vi(n−1)
= 15 ×
100 k
100 k + 1 k
= 14.85 V/V
Thus,
vo
vs
= 0.667 × (14.85)n−1
× 2.5 =
1.667 × (14.85)n−1
For vs = 5 mV and vo = 3 V, the gain
vo
vs
must
be ≥ 600, thus
1.667 × (14.85)n−1
≥ 600
⇒ n = 4
Thus four amplifier stages are needed, resulting in
vo
vs
= 1.667 × (14.85)3
= 5458 V/V
and correspondingly
vo = 5458 × 5 mV = 16.37 V
1.55 Deliver 0.5 W to a 100- load.
Source is 30 mV rms with 0.5-M source
resistance. Choose from these three amplifier
types:
A B C
Ri 1 M
Av 10 V/ V
Ro 10 k
Ri 10 k
Av 100 V/ V
Ro 1 k
Ri 10 k
Av 1 V/ V
Ro 20

Chapter 1–16
This figure belongs to 1.54.

Rs 50 k
200
Ri1 10 k Ron 1 k
5 mV
vs
#1 #2 #n
vi1

vi2

vin

vo

RL
100 k
1 k
100 k
#m
Ri(m 1)
vi(m 1)

vim

vi(m 1)
10vim

vim

This figure belongs to 1.55.

vi1

vi2

vi3

vo
100
20
1 k
10 k
0.5 M
10 k
100vi2 1vi3
10vi1
1 M
30 mV
rms
10 k

∼
Choose order to eliminate loading on input and
output:
A, first, to minimize loading on 0.5-M source
B, second, to boost gain
C, third, to minimize loading at 100- output.
We first attempt a cascade of the three stages in
the order A, B, C (see figure above), and obtain
vi1
vs
=
1 M
1 M + 0.5 M
=
1
1.5
⇒ vi1 = 30 ×
1
1.5
= 20 mV
vi2
vi1
= 10 ×
10 k
10 k + 10 k
= 5
⇒ vi2 = 20 × 5 = 100 mV
vi3
vi2
= 100 ×
10 k
10 k + 1 k
= 90.9
⇒ vi3 = 100 mV × 90.9 = 9.09 V
vo
vi3
= 1 ×
100
100 + 20
= 0.833
⇒ vo = 9.09 × 0.833 = 7.6 V
Po =
v2
orms
RL
=
7.62
100
= 0.57 W
which exceeds the required 0.5 W. Also, the
signal throughout the amplifier chain never drops
below 20 mV (which is greater than the required
minimum of 10 mV).
1.56 (a) Required voltage gain ≡
vo
vs
=
2 V
0.005 V
= 400 V/V
(b) The smallest Ri allowed is obtained from
0.1 µA =
5 mV
Rs + Ri
⇒ Rs + Ri = 50 k
Thus Ri = 40 k.
For Ri = 40 k. ii = 0.1 µA peak, and
Overall current gain =
vo/RL
ii
=
2 V/1 k
0.1 µA
=
2 mA
0.1 µA
= 2 × 104
A/A
Overall power gain ≡
v2
orms/RL
vs(rms) × ii(rms)

Chapter 1–17
=

2
√
2
2
1000

5 × 10−3
√
2

×

0.1 × 10−6
√
2

= 8 × 106
W/W
(This takes into account the power dissipated in
the internal resistance of the source.)
(c) If ( Avovi ) has its peak value limited to 3 V,
the largest value of RO is found from
Rs 10 k

vs vi
vo
ii
Ri
5-mV
peak
Ro
RL

Avovi 1 k
= 3 ×
RL
RL + Ro
= 2 ⇒ Ro =
1
2
RL = 500
(If Ro were greater than this value, the output
voltage across RL would be less than 2 V.)
(d) For Ri = 40 k and Ro = 500 , the
required value Avo can be found from
400 V/V =
40
40 + 10
× Avo ×
1
1 + 0.5
⇒ Avo = 750 V/V
(e) Ri = 100 k(1 × 105
)
Ro = 100 (1 × 102
)
400 =
100
100 + 10
× Avo ×
1000
1000 + 100
⇒ Avo = 484 V/V
1.57
(a)
vo = 10 mV ×
40
40 + 10
× 300 ×
100
100 + 100
= 1.2 V
(b)
vo
vs
=
1200 mV
10 mV
= 120 V/V
(c)
vo
vi
= 300 ×
100
100 + 100
= 150 V/V
(d) Rs
Rp Ri
...
Connect a resistance RP in parallel with the input
and select its value from
(Rp Ri )
(Rp Ri ) + Rs
=
1
2
Ri
Ri + Rs
⇒ 1 +
Rs
Rp Ri
= 2.5 ⇒ Rp Ri =
RS
1.5
=
10
1.5
⇒
1
Rp
+
1
Ri
=
1.5
10
Rp =
1
0.15 − 0.025
= 8 k
1.58 The equivalent circuit at the output side of a
current amplifier loaded with a resistance RL is
shown. Since
RL
Ro
Aisii
io
io = (Aisii )
Ro
Ro + RL
we can write
1 = (Aisii )
Ro
Ro + 1
(1)
and
0.5 = (Aisii )
Ro
Ro + 12
(2)
Dividing Eq. (1) by Eq. (2), we have
2 =
Ro + 12
Ro + 1
⇒ Ro = 10 k
Aisii = 1 ×
10 + 1
10
= 1.1 mA
1.59
The current gain is
io
ii
=
Rm
Ro + RL
=
5000
10 + 1000
= 4.95 A/A = 13.9 dB

Chapter 1–18

vi
vs
io
Rs
Ri
Ro 10
RL
Rmii
1 k
100
ii

vo
1 k

The voltage gain is
vo
vs
=
ii
vs
×
io
ii
×
vo
io
=
1
Rs + Ri
×
io
ii
× RL
=
1
1000 + 100
× 4.95 × 1000
= 4.90 V/V = 13.8 dB
The power gain is
voio
vsii
= 4.95 × 4.90
= 24.3 W/W = 27.7 dB
1.60
Rs 500

vs vi
Ri
Gmvi
vo
RL
Ro

2 k
Gm = 20 mA/V
Ro = 5 k
RL = 1 k
vi = vs
Ri
Rs + Ri
= vs
2
0.5 + 2
= 0.8vs
vo = Gmvi (RL Ro)
= 20
5 × 1
5 + 1
vi
= 20
5
6
× 0.8vs
Overall voltage gain ≡
vo
vs
= 13.3 V/V
1.61 To obtain the weighted sum of v1 and v2
vo = 10v1 + 20v2
we use two transconductance amplifiers and sum
their output currents. Each transconductance
amplifier has the following equivalent circuit:
Ri
10 k
Ro
Gmvi
Gm 20 mA/V
10 k
vi

Consider first the path for the signal requiring
higher gain, namely v2. See figure at top of next
page.
The parallel connection of the two amplifiers at
the output and the connection of RL means that
the total resistance at the output is
10 k 10 k 10 k =
10
3
k. Thus the
component of vo due to v2 will be
vo2 = v2
10
10 + 10
× Gm2 ×
10
3
= v2 × 0.5 × 20 ×
10
3
= 33.3v2
To reduce the gain seen by v2 from 33.3 to 20, we
connect a resistance Rp in parallel with RL ,

10
3
Rp

= 2 k
⇒ Rp = 5 k
We next consider the path for v1. Since v1 must
see a gain factor of only 10, which is half that
seen by v2, we have to reduce the fraction of v1
that appears at the input of its transconductance
amplifier to half that that appears at the input of
the v2 transconductance amplifier. We just saw
that 0.5 v2 appears at the input of the v2
transconductance amplifier. Thus, for the v1
transconductance amplifier, we want 0.25v1 to
appear at the input. This can be achieved by
shunting the input of the v1 transconductance

Chapter 1–19
amplifier by a resistance Rp1 as in the following
figure.
v1
Rs1 10 k
vi1

Rp1 Ri1
10 k

The value of Rp1 can be found from
(Rp1 Ri1)
(Rp1 Ri1) + Rs1
= 0.25
Thus,
1 +
Rs1
(Rp1 Ri1)
= 4
⇒ Rp1 Ri1 =
Rs1
3
=
10
3
Rp1 10 =
10
3
⇒ Rp1 = 5 k
The final circuit will be as follows:

Chapter 1–20
1.62 (a)

vi gmvi
Ri
i1
i2
ix
vx

ix = i1 + i2
i1 = vi /Ri
i2 = gmvi
vi = vx
⎫
⎪
⎪
⎪
⎪
⎪
⎪
⎬
⎪
⎪
⎪
⎪
⎪
⎪
⎭
ix = vx /Ri + gmvx
ix = vx

1
Ri
+ gm

vx
ix
=
1
1/Ri + gm
=
Ri
1 + gm Ri
= Rin
(b)

vi

vo
vs
vs
Rs Rin
gmvi
Rin
Ri
2
When driven by a source with source resistance
Rin as shown in the figure above,
vi =
Rin
Rs + Rin
×vs =
Rin
Rin + Rin
×vs = 0.5×vs
Thus,
vo
vs
= 0.5
vo
vi
1.63 Voltage amplifier:
vi vo
Ri
Rs
Ro
1 to 10 k
RL
1 k to
10 k
Avo vi

io
vs
For Rs varying in the range 1 k to 10 k and
vo limited to 10%, select Ri to be sufficiently
large:
Ri ≥ 10 Rsmax
Ri = 10 × 10 k = 100 k = 1 × 105

For RL varying in the range 1 k to 10 k, the
load voltage variation limited to 10%, select Ro
sufficiently low:
Ro ≤
RLmin
10
Ro =
1 k
10
= 100 = 1 × 102

Now find Avo:
vomin = 10 mV ×
Ri
Ri + Rsmax
× Avo
RLmin
Ro + RLmin
1 = 10 × 10−3
×
100 k
100 k + 10 k
× Avo ×
1 k
100 + 1 k
⇒ Avo = 121 V/V
vo
Ro
Avovi

vi Ri
Values for the voltage amplifier equivalent circuit
are
Ri = 1 × 105
, Avo = 121 V/V, and
Ro = 1 × 102

1.64 Transresistance amplifier:
To limit vo to 10% corresponding to Rs varying
in the range 1 k to 10 k, we select Ri
sufficiently low;
Ri ≤
Rsmin
10
Thus, Ri = 100 = 1 × 102

To limit vo to 10% while RLvaries over the
range 1 k to 10 k, we select Ro sufficiently
low;
Ro ≤
RLmin
10
Thus, Ro = 100 = 1 × 102

Now, for is = 10 µA,
10 μA
1 to
10 k
1 to
10 k

R i
i
i
R
R
R
R
v

Chapter 1–21
vomin = 10−5 Rsmin
Rsmin + Ri
Rm
RLmin
RLmin + Ro
1 = 10−5 1000
1000 + 100
Rm
1000
1000 + 100
⇒ Rm = 1.21 × 105

= 121 k
1.65
The node equation at E yields the current through
RE as (βib + ib) = (β + 1)ib. The voltage vc can
be found in terms of ib as
vc = −βib RL (1)
The voltage vb can be related to ib by writing for
the input loop:
vb = ibrπ + (β + 1)ib RE
Thus,
vb = rπ + (β + 1)RE ib (2)
Dividing Eq. (1) by Eq. (2) yields
vc
vb
= −
β RL
rπ + (β + 1)RE
Q.E.D
The voltage ve is related to ib by
ve = (β + 1)ib RE
That is,
ve = (β + 1)RE ib (3)
Dividing Eq. (3) by Eq. (2) yields
ve
vb
=
(β + 1)RE
(β + 1)RE + rπ
Dividing the numerator and denominator by
(β + 1) gives
ve
vb
=
RE
RE + rπ /(β + 1)
Q.E.D
1.66
vA
RL
When RL = 0,
io = isc = 5 mA =
vA
Ro
⇒ vA − 5Ro = 0 (1)
When RL = 2 k,
vo = 5 V = vA
2
Ro + 2
⇒ 2vA − 5Ro = 10 (2)
Subtracting Eqs. (2) - (1),
vA = 10 V
Substituting into Eq. (1)
Ro =
10
5
= 2 k
When RL = 1 k,
Av =
vo
vi
=
10 ×
1
2 + 1
0.001 × 200 5
= 683.3 V/V = 56.7 dB
The overall current gain is,
Ai =
io
is
=
10
2 + 1
0.001
= 3333.3 A/A = 70.5 dB
The power gain of the amplifier is,
Ap =
v2
o/RL
v2
i /Ri
=
3.332
/1
0.004872/5
= 2.34 × 106
W/W = 127.4 dB

Chapter 1–22
1.67
R

v1
gmv1
gm 100 mA/V
R 5 k
gmv2

v2
io
vo
io = gmv1 − gmv2
vo = io RL = gm R(v1 − v2)
v1 = v2 = 1 V ∴ vo = 0 V
v1 = 1.01 V
v2 = 0.99 V
5
∴ vo = 100 × 5 × 0.02 = 10 V
1.68
I1
V1
g12I2
1/g11

g21V1
g22

V2
I2

I1
V2
I2
AvoV1
V1 Ri
Ro

The correspondences between the current and
voltage variables are indicated by comparing the
two equivalent-circuit models above. At the
outset we observe that at the input side of the
g-parameter model, we have the controlled
current source g12 I2. This has no correspondence
in the equivalent-circuit model of Fig. 1.16(a). It
represents internal feedback, internal to the
amplifier circuit. In developing the model of
Fig. 1.16(a), we assumed that the amplifier is
unilateral (i.e., has no internal feedback, or that
the input side does not know what happens at the
output side). If we neglect this internal feedback,
that is, assume g12 = 0, we can compare the two
models and thus obtain:
Ri = 1/g11
Avo = g21
Ro = g22
1.69 Circuits of Fig. 1.22:

Vi Vo
R
C
(a) (b)

Vi Vo
C
R

For (a) Vo = Vi

1/sC
1/sC + R

Vo
Vi
=
1
1 + sC R
which is of the form shown for the low-pass
function in Table 1.2 with K = 1 and
ω0 = 1/RC.
For (b) Vo = Vi
⎛
⎜
⎝
R
R +
1
sC
⎞
⎟
⎠
Vo
Vi
=
sRC
1 + sC R
Vo
Vi
=
s
s +
1
RC
which is of the form shown in Table 1.2 for the
high-pass function, with K = 1 and ω0 = 1/RC.
1.70

Vi

Rs
Ri
Vs Ci

Chapter 1–23
Vi
Vs
=
Ri
1
sCi
Ri +
1
sCi
Rs +
⎛
⎜
⎜
⎝
Ri
1
sCi
Ri +
1
sCi
⎞
⎟
⎟
⎠
=
Ri
1 + sCi Ri
Rs +

Ri
1 + sCi Ri

=
Ri
Rs + sCi Ri Rs + Ri
Vi
Vs
=
Ri
(Rs + Ri ) + sCi Ri Rs
=
Ri
(Rs + Ri )
1 + s

Ci Ri Rs
Rs + Ri

which is a low-pass STC function with
K =
Ri
Rs + Ri
and ω0 = 1/Ci (Ri Rs).
For Rs = 10 k, Ri = 40 k, and Ci = 5 pF,
ω0 =
1
5 × 10−12 × (40 10) × 103
= 25 Mrad/s
f0 =
25
2π
= 4 MHz
The dc gain is
K =
40
10 + 40
= 0.8V/V
1.71 Using the voltage-divider rule.

Vo
Vi
R1
R2
C

T (s) =
Vo
Vi
=
R2
R2 + R1 +
1
sC
T (s) =

R2
R1 + R2

⎛
⎜
⎜
⎝
s
s +
1
C(R1 + R2)
⎞
⎟
⎟
⎠
which from Table 1.2 is of the high-pass type
with
K =
R2
R1 + R2
ω0 =
1
C(R1 + R2)
As a further verification that this is a high-pass
network and T(s) is a high-pass transfer function,
see that as s ⇒ 0, T (s) ⇒ 0; and as s → ∞,
T (s) = R2/(R1 + R2). Also, from the circuit,
observe as s → ∞, (1/sC) → 0 and
Vo/Vi = R2/(R1 + R2). Now, for R1 = 20 k,
R2 = 100 k and C = 0.1 µF,
f0 =
ω0
2π
=
1
2π × 0.1 × 10−6
(20 + 100) × 103
= 13.26 Hz
|T ( jω0)| =
K
√
2
=
100
20 + 100
1
√
2
= 0.59 V/V
1.72 Using the voltage divider rule,
RL
Rs
C
Vl
Vs

Vl
Vs
=
RL
RL + Rs +
1
sC
=
RL
RL + Rs
s
s +
1
C(RL + Rs)
which is of the high-pass STC type (see Table
1.2) with
K =
RL
RL + Rs
ω0 =
1
C(RL + Rs)
For f0 ≤ 200 Hz
1
2πC(RL + Rs)
≤ 200
⇒ C ≥
1
2π × 200(10 + 4) × 103
Thus, the smallest value of C that will do the job
is C = 0.057 µF or 57 nF.
1.73 The given measured data indicate that this
amplifier has a low-pass STC frequency response
with a low-frequency gain of 60 dB, and a 3-dB
frequency of 1000 Hz. From our knowledge of
the Bode plots for low-pass STC networks [Fig.
1.23(a)], we can complete the table entries and
sketch the amplifier frequency response.
f (Hz) |T |(dB) ∠T (◦
)
0 60 0
100 60 0
1000 57 −45◦
104
40 −90◦
105
20 −90◦
106
0 −90◦

Chapter 1–24
f (Hz)
20 dB/decade
3 dB
10
0
10
20
30
40
50
60
T (dB)
102
103
104
105
106
1.74 From our knowledge of the Bode plots of
STC low-pass and high-pass networks, we see
that this amplifier has a midband gain of 80 dB, a
low-frequency response of the high-pass STC
type with f3dB = 102
Hz, and a high-frequency
response of the low-pass STC type with
f3dB = 105
Hz. We thus can sketch the amplifier
frequency response and complete the table entries
as follows.
f (Hz)
3 dB
102
0
20
40
60
80
100
102
104
106
108
1010
20 dB/decade
20
dB/decade
T (dB)
f(Hz) 10−2
1 102
103
104
105
106
107
109
|T |(dB) 0 40 77 80 80 77 60 40 0
1.75 Since the overall transfer function is that of
three identical STC LP circuits in cascade (but
with no loading effects, since the buffer
amplifiers have infinite input and zero output
resistances) the overall gain will drop by 3 dB
below the value at dc at the frequency for which
the gain of each STC circuit is 1 dB down. This
frequency is found as follows: The transfer
function of each STC circuit is
T (s) =
1
1 +
s
ω0
where
ω0 = 1/C R
Thus,
|T ( jω)| =
1

1 +

ω
ω0
2
20 log
1

1 +

ω1 dB
ω0
2
= −1
⇒ 1 +

ω1 dB
ω0
2
= 100,1
ω1dB = 0.51ω0
ω1dB = 0.51/C R
1.76 Rs = 100 k, since the 3-dB frequency is
reduced by a very high factor (from 5 MHz to
100 kHz) C2 must be much larger than C1. Thus,
neglecting C1 we find C2 from
100 kHz
1
2πC2 Rs
C2
Shunt
capacitor
Initial
capacitor
C1
Rs
=
1
2πC2 × 105
⇒ C2 = 15.9 pF
If the original 3-dB frequency (5 MHz) is
attributable to C1, then
5 MHz =
1
2πC1 Rs
⇒ C1 =
1
2π × 5 × 106
× 105
= 0.32 pF
1.77 Since when C is connected to node A the
3-dB frequency is reduced by a large factor, the
value of C must be much larger than whatever
parasitic capacitance originally existed at node A
(i.e., between A and ground). Furthermore,
it must be that C is now the dominant determinant
of the amplifier 3-dB frequency (i.e., it is
dominating over whatever may be happening at

Chapter 1–25
node B or anywhere else in the amplifier). Thus,
we can write
200 kHz =
1
2πC(Ro1 Ri2)
⇒ (Ro1 Ri2) =
1
2π × 200 × 103
× 1 × 10−9
= 0.8 k
C
vo1 Ri2
Ro1

A
1 nF
# 1 # 2 # 3
B
C
Now Ri2 = 100 k.
Thus Ro1 0.8 k
Similarly, for node B,
40 kHz =
1
2πC(Ro2 Ri3)
⇒ Ro2 Ri3 =
1
2π × 40 × 103
× 1 × 10−9
= 3.98 k
Ro2 = 4.14 k
The designer should connect a capacitor of value
Cp to node B where Cp can be found from
5 kHz =
1
2πCp(Ro2 Ri3)
⇒ Cp =
1
2π × 5 × 103
× 3.98 × 103
= 8 nF
Note that if she chooses to use node A, she would
need to connect a capacitor 5 times larger!
1.78 For the input circuit, the corner frequency
f01 is found from
f01 =
1
2πC1(Rs + Ri )

V V
R
100 k 100V
R
10 k C
V
R
1 k
R
1 k C

For f01 ≤ 100 Hz,
1
2πC1(10 + 100) × 103
≤ 100
⇒ C1 ≥
1
2π × 110 × 103
× 102
= 1.4 × 10−8
F
Thus we select C1 = 1 × 10−7
F = 0.1 µF. The
actual corner frequency resulting from C1 will be
f01 =
1
2π × 10−7
× 110 × 103
= 14.5 Hz
For the output circuit,
f02 =
1
2πC2(Ro + RL )
For f02 ≤ 100 Hz,
1
2πC2(1 + 1) × 103
≤ 100
⇒ C2 ≥
1
2π × 2 × 103
× 102
= 0.8 × 10−6
Select C2 = 1 × 10−6
= 1 µF.
This will place the corner frequency at
f02 =
1
2π × 10−6
× 2 × 103
= 80 Hz
T (s) = 100
s

1 +
s
2π f01

1 +
s
2π f02

1.79 The LP factor 1/(1 + j f/105
) results in a
Bode plot like that in Fig. 1.23(a) with the
3-dB frequency f0 = 105
Hz. The high-pass
factor 1/(1 + 102
/j f ) results in a Bode plot like
that in Fig. 1.24(a) with the 3-dB frequency
f0 = 102
Hz.
The Bode plot for the overall transfer function
can be obtained by summing the dB values of the
two individual plots and then shifting the

Chapter 1–26
resulting plot vertically by 60 dB (corresponding
to the factor 1000 in the numerator). The result is
as follows:
60
50
40
30
20
10
0
1 10 102 103 104 105 106 107 108 f (Hz)
(Hz)
f = 10 102
103
104
105
106
107
108
(dB)
–
~ 40 60
57 57
60 60 60 40 20 0
20 dB/decade
20 dB/decade
20 dB/decade
Av (dB)
Av
Bandwidth = 105
− 102
= 99,900 Hz
1.80
Ti (s) =
Vi (s)
Vs(s)
=
1/sC1
1/sC1 + R1
=
1
sC1 R1 + 1
LP with a 3-dB frequency
f0i =
1
2πC1 R1
=
1
2π10−11
105
= 159 kHz
For To(s), the following equivalent circuit can be
used:

GmR2Vi
Vo R3
R2
C2

To(s) =
Vo
Vi
= −Gm R2
R3
R2 + R3 + 1/sC2
= −Gm(R2 R3)
s
s +
1
C2(R2 + R3)
which is an HP, with
3-dB frequency =
1
2πC2(R2 + R3)
=
1
2π100 × 10−9
× 110 × 103
= 14.5 Hz
∴ T (s) = Ti (s)To(s)
=
1
1 +
s
2π × 159 × 103
× − 909.1 ×
s
s + (2π × 14.5)
20 dB/decade
20 dB/decade
14.5 Hz 159 kHz
59.2 dB
Bandwidth = 159 kHz – 14.5 Hz 159 kHz
1.81 Vi = Vs
Ri
Rs + Ri
(1)
(a) To satisfy constraint (1), namely,
Vi ≥

1 −
x
100

Vs
we substitute in Eq. (1) to obtain
Ri
Rs + Ri
≥ 1 −
x
100
(2)
Thus
Rs + Ri
Ri
≤
1
1 −
x
100
Rs
Ri
≤
1
1 −
x
100
− 1 =
x
100
1 −
x
100
which can be expressed as
Ri
Rs
≥
1 −
x
100
x
100
resulting in
Vi
Vo
Ri Ro RL
CL
Vs
Rs
Gm Vi

Ri ≥ Rs

100
x
− 1

(3)
(b) The 3-dB frequency is determined by the
parallel RC circuit at the output
f0 =
1
2π
ω0 =
1
2π
1
CL (RL Ro)
Thus,
f0 =
1
2πCL

1
RL
+
1
R0

Chapter 1–27
To obtain a value for f0 greater than a specified
value f3dB we select Ro so that
1
2πCL

1
RL
+
1
Ro

≥ f3dB
1
RL
+
1
Ro
≥ 2πCL f3dB
1
Ro
≥ 2πCL f3dB −
1
RL
Ro ≤
1
2π f3dBCL −
1
RL
(4)
(c) To satisfy constraint (c), we first determine
the dc gain as
dc gain =
Ri
Rs + Ri
Gm(Ro RL )
For the dc gain to be greater than a specified
value A0,
Ri
Rs + Ri
Gm(Ro RL ) ≥ A0
The first factor on the left-hand side is (from
constraint (2)) greater or equal to (1 − x/100).
Thus
Gm ≥
A0

1 −
x
100

(Ro RL )
(5)
Substituting Rs = 10 k and x = 10% in (3)
results in
Ri ≥ 10

100
100
− 1

= 90 k
Substituting f3dB = 2 MHz, CL = 20 pF, and
RL = 10 k in Eq. (4) results in
Ro ≤
1
2π × 2 × 106
× 20 × 10−12
−
1
104
= 6.61 k
Substituting A0 = 100, x = 10%, RL = 10 k, and
Ro = 6.61 k, Eq. (5) results in
Gm ≥
100

1 −
10
100

(10 6.61) × 103
= 27.9 mA/V
1.82 Using the voltage divider rule, we obtain
Vo
Vi
=
Z2
Z1 + Z2
where
Z1 = R1
1
sC1
and Z2 = R2
1
sC2
It is obviously more convenient to work in terms
of admittances. Therefore we express Vo/Vi in the
alternate form
Vo
Vi
=
Y1
Y1 + Y2
and substitute Y1 = (1/R1) + sC1 and
Y2 = (1/R2) + sC2 to obtain
Vo
Vi
=
1
R1
+ sC1
1
R1
+
1
R2
+ s(C1 + C2)
=
C1
C1 + C2
s +
1
C1 R1
s +
1
(C1 + C2)

1
R1
+
1
R2

This transfer function will be independent of
frequency (s) if the second factor reduces to unity.
This in turn will happen if
1
C1 R1
=
1
C1 + C2

1
R1
+
1
R2

which can be simplified as follows:
C1 + C2
C1
= R1

1
R1
+
1
R2

(1)
1 +
C2
C1
= 1 +
R1
R2
or
C1 R1 = C2 R2 ⇒ C1 = C2(R2/R1)
When this condition applies, the attenuator is said
to be compensated, and its transfer function is
given by
Vo
Vi
=
C1
C1 + C2
which, using Eq. (1), can be expressed in the
alternate form
Vo
Vi
=
1
1 +
R1
R2
=
R2
R1 + R2
Thus when the attenuator is compensated
(C1R1 = C2R2), its transmission can be
determined either by its two resistors R1, R2 or by
its two capacitors. C1, C2, and the transmission is
not a function of frequency.

Chapter 1–28
1.83 The HP STC circuit whose response
determines the frequency response of the
amplifier in the low-frequency range has a phase
angle of 5.7◦
at f = 100 Hz. Using the equation
for ∠T ( jω) from Table 1.2, we obtain
tan−1 f0
100
=5.7◦
⇒ f0 = 10 Hz ⇒ τ =
1
2π10
=
15.9 ms
The LP STC circuit whose response determines
the amplifier response at the high-frequency end
has a phase angle of −5.7◦
at f = 1 kHz. Using
the relationship for ∠T( jω) given in Table 1.2,
we obtain for the LP STC circuit.
−tan−1 103
f0
= −5.7◦
⇒ f0 10 kHz ⇒ τ =
1
2π104
= 15.9 µs
At f = 100 Hz, the drop in gain is due to the HP
STC network, and thus its value is
20 log
1

1 +

10
100
2
= −0.04 dB
Similarly, at the drop in gain f = 1 kHz is caused
by the LP STC network. The drop in gain is
20 log
1

1 +

1000
10, 000
2
= −0.04 dB
The gain drops by 3 dB at the corner frequencies
of the two STC networks, that is, at f = 10 Hz and
f = 10 kHz.

Exercise 1–1
Chapter 1
Solutions to Exercises within the Chapter
Ex: 1.1 When output terminals are
open-circuited, as in Fig. 1.1a:
For circuit a. voc = vs(t)
For circuit b. voc = is(t) × Rs
When output terminals are short-circuited, as in
Fig. 1.1b:
For circuit a. isc =
vs(t)
Rs
For circuit b. isc = is(t)
For equivalency
Rsis(t) = vs(t)
Rs a
b

vs (t)
Figure 1.1a
is (t)
a
b
Rs
Figure 1.1b
Ex: 1.2
voc vs
Rs

isc
voc = 10 mV
isc = 10 µA
Rs =
voc
isc
=
10 mV
10 µA
= 1 k
Ex: 1.3 Using voltage divider:
vo(t) = vs(t) ×
RL
Rs + RL
vs (t) vo
Rs

RL
Given vs(t) = 10 mV and Rs = 1 k.
If RL = 100 k
vo = 10 mV ×
100
100 + 1
= 9.9 mV
If RL = 10 k
vo = 10 mV ×
10
10 + 1
9.1 mV
If RL = 1 k
vo = 10 mV ×
1
1 + 1
= 5 mV
If RL = 100
vo = 10 mV ×
100
100 + 1 K
0.91 mV
For vo = 0.8vs,
RL
RL + Rs
= 0.8
Since Rs = 1 k,
RL = 4 k
Ex: 1.4 Using current divider:
Rs
is 10 A RL
io
io = is ×
Rs
Rs + RL
Given is = 10 µA, Rs = 100 k.
For
RL = 1 k, io = 10 µA ×
100
100 + 1
= 9.9 µA
For
RL = 10 k, io = 10 µA ×
100
100 + 10
9.1 µA
For
RL = 100 k, io = 10 µA×
100
100 + 100
= 5 µA
For RL = 1 M, io = 10 µA ×
100 K
100 K + 1 M
0.9 µA
For io = 0.8is,
100
100 + RL
= 0.8
⇒ RL = 25 k

Exercise 1–2
Ex: 1.5 f =
1
T
=
1
10−3
= 1000 Hz
ω = 2π f = 2π × 103
rad/s
Ex: 1.6 (a) T =
1
f
=
1
60
s = 16.7 ms
(b) T =
1
f
=
1
10−3
= 1000 s
(c) T =
1
f
=
1
106
s = 1 µs
Ex: 1.7 If 6 MHz is allocated for each channel,
then 470 MHz to 806 MHz will accommodate
806 − 470
6
= 56 channels
Since the broadcast band starts with channel 14, it
will go from channel 14 to channel 69.
Ex: 1.8 P =
1
T
T

0
v2
R
dt
=
1
T
×
V 2
R
× T =
V 2
R
Alternatively,
P = P1 + P3 + P5 + · · ·
=

4V
√
2π
2
1
R
+

4V
3
√
2π
2
1
R
+

4V
5
√
2π
2
1
R
+ · · ·
=
V 2
R
×
8
π2
×

1 +
1
9
+
1
25
+
1
49
+ · · ·

It can be shown by direct calculation that the
infinite series in the parentheses has a sum that
approaches π2
/8; thus P becomes V 2
/R as found
from direct calculation.
Fraction of energy in fundamental
= 8/π2
= 0.81
Fraction of energy in first five harmonics
=
8
π2

1 +
1
9
+
1
25

= 0.93
Fraction of energy in first seven harmonics
=
8
π2

1 +
1
9
+
1
25
+
1
49

= 0.95
Fraction of energy in first nine harmonics
=
8
π2

1 +
1
9
+
1
25
+
1
49
+
1
81

= 0.96
Note that 90% of the energy of the square wave is
in the first three harmonics, that is, in the
fundamental and the third harmonic.
Ex: 1.9 (a) D can represent 15 equally-spaced
values between 0 and 3.75 V. Thus, the values are
spaced 0.25 V apart.
vA = 0 V ⇒ D = 0000
vA = 0.25 V ⇒ D = 0000
vA = 1 V ⇒ D = 0000
vA = 3.75 V ⇒ D = 0000
(b) (i) 1 level spacing: 20
× +0.25 = +0.25 V
(ii) 2 level spacings: 21
× +0.25 = +0.5 V
(iii) 4 level spacings: 22
× +0.25 = +1.0 V
(iv) 8 level spacings: 23
× +0.25 = +2.0 V
(c) The closest discrete value represented by D is
+1.25 V; thus D = 0101. The error is -0.05 V, or
−0.05/1.3 × 100 = −4%.
Ex: 1.10 Voltage gain = 20 log 100 = 40 dB
Current gain = 20 log 1000 = 60 dB
Power gain = 10 log Ap = 10 log (Av Ai )
= 10 log 105
= 50 dB
Ex: 1.11 Pdc = 15 × 8 = 120 mW
PL =
(6/
√
2)2
1
= 18 mW
Pdissipated = 120 − 18 = 102 mW
η =
PL
Pdc
× 100 =
18
120
× 100 = 15%
Ex: 1.12 vo = 1 ×
10
106
+ 10
10−5
V = 10 µV
PL = v2
o/RL =
(10 × 10−6
)2
10
= 10−11
W
With the buffer amplifier:
vo = 1 ×
Ri
Ri + Rs
× Avo ×
RL
RL + Ro
= 1 ×
1
1 + 1
× 1 ×
10
10 + 10
= 0.25 V
PL =
v2
o
RL
=
0.252
10
= 6.25 mW
Voltage gain =
vo
vs
=
0.25 V
1 V
= 0.25 V/V
= −12 dB
Power gain (Ap) ≡
PL
Pi
where PL = 6.25 mW and Pi = vi i1,
vi = 0.5 V and
ii =
1 V
1 M + 1 M
= 0.5 µA

Exercise 1–3
This figure belongs to Exercise 1.15.

vs vi1
10vi1
100 k
1 M vi2
1 k
100 k
100vi2
vL
1 k
100
Stage 1 Stage 2

Thus,
Pi = 0.5 × 0.5 = 0.25 µW
and
Ap =
6.25 × 10−3
0.25 × 10−6
= 25 × 103
10 log Ap = 44 dB
Ex: 1.13 Open-circuit (no load) output voltage =
Avovi
Output voltage with load connected
= Avovi
RL
RL + Ro
0.8 =
1
Ro + 1
⇒ Ro = 0.25 k = 250
Ex: 1.14 Avo = 40 dB = 100 V/V
PL =
v2
o
RL
=

Avovi
RL
RL + Ro
2
RL
= v2
i ×

100 ×
1
1 + 1
2
1000 = 2.5 v2
i
Pi =
v2
i
Ri
=
v2
i
10,000
Ap ≡
PL
Pi
=
2.5v2
i
10−4
v2
i
= 2.5 × 104
W/W
10 log Ap = 44 dB
Ex: 1.15 Without stage 3 (see figure above)
vL
vs
=

1 M
100 k + 1 M

(10)

100 k
100 k + 1 k

×(100)

100
100 + 1 k

vL
vs
= (0.909)(10)(0.9901)(100)(0.0909)
= 81.8 V/V
Ex: 1.16 Refer the solution to Example 1.3 in the
text.
vi1
vs
= 0.909 V/V
vi1 = 0.909 vs = 0.909 × 1 = 0.909 mV
vi2
vs
=
vi2
vi1
×
vi1
vs
= 9.9 × 0.909 = 9 V/V
vi2 = 9 × vS = 9 × 1 = 9 mV
vi3
vs
=
vi3
vi2
×
vi2
vi1
×
vi1
vs
= 90.9 × 9.9 × 0.909
= 818 V/V
vi3 = 818 vs = 818 × 1 = 818 mV
vL
vs
=
vL
vi3
×
vi3
vi2
×
vi2
vi1
×
vi1
vs
= 0.909 × 90.9 × 9.9 × 0.909 744 V/V
vL = 744 × 1 mV = 744 mV
Ex: 1.17 Using voltage amplifier model, the
three-stage amplifier can be represented as
vi
Ri
Ro
Avovi

Ri = 1 M
Ro = 10
Avo = Av1 × Av2 × Av3 = 9.9 × 90.9 × 1 =
900 V/V
The overall voltage gain
vo
vs
=
Ri
Ri + Rs
× Avo ×
RL
RL + Ro

Exercise 1–4
For RL = 10
Overall voltage gain
=
1 M
1 M + 100 K
× 900 ×
10
10 + 10
= 409 V/V
For RL = 1000
Overall voltage gain
=
1 M
1 M + 100 K
× 900 ×
1000
1000 + 10
= 810 V/V
∴ Range of voltage gain is from 409 V/V to
810 V/V.
Ex: 1.18
ii io
Ais ii
RL
Ro
Rs Ri
is
ii = is
Rs
Rs + Ri
io = Aisii
Ro
Ro + RL
= Aisis
Rs
Rs + Ri
Ro
Ro + RL
Thus,
io
is
= Ais
Rs
Rs + Ri
Ro
Ro + RL
Ex: 1.19
Ri
Ro
Gmvi
RL
Ri

vi

vo
vs
vi = vs
Ri
Ri + Rs
vo = Gmvi (Ro RL )
= Gmvs
Ri
Ri + Rs
(Ro RL )
Thus,
vo
vs
= Gm
Ri
Ri + Rs
(Ro RL )
Ex: 1.20 Using the transresistance circuit model,
the circuit will be
Ri
Rs
is
ii Ro
RL
vo
Rmii

ii
is
=
Rs
Ri + Rs
vo = Rmii ×
RL
RL + Ro
vo
ii
= Rm
RL
RL + Ro
Now
vo
is
=
vo
ii
×
ii
is
= Rm
RL
RL + Ro
×
Rs
Ri + Rs
= Rm
Rs
Rs + Ri
×
RL
RL + Ro
Ex: 1.21
vb = ibrπ + (β + 1)ib Re
= ibrπ + (β + 1)Re
But vb = vx and ib = ix , thus
Rin ≡
vx
ix
=
vb
ib
= rπ + (β + 1)Re
Ex: 1.22
f Gain
10 Hz 60 dB
10 kHz 40 dB
100 kHz 20 dB
1 MHz 0 dB

Exercise 1–5
Gain (dB)
20 dB/decade
3 dB
frequency
0
20
40
60
1 10 10 10 10 10 10 10 f (Hz)
Ex: 1.23
RL
Ro
Ri Vi
Vi Gm Vo CL

Vo = Gm Vi Ro RL CL
=
Gm Vi
1
Ro
+
1
RL
+ sCL
Thus,
Vo
Vi
=
Gm
1
Ro
+
1
RL
×
1
1 +
sCL
1
Ro
+
1
RL
Vo
Vi
=
Gm(RL Ro)
1 + sCL (RL Ro)
which is of the STC LP type.
ω0 =
1
CL (RL Ro)
=
1
4.5 × 10−9(103 Ro)
For ω0 to be at least wπ × 40 × 103
, the highest
value allowed for Ro is
Ro =
103
2π × 40 × 103 × 103 × 4.5 × 10−9 − 1
=
103
1.131 − 1
= 7.64 k
The dc gain is
Gm(RL Ro)
To ensure a dc gain of at least 40 dB (i.e., 100),
the minimum value of Gm is
⇒ RL ≥ 100/(103
7.64 × 103
) = 113.1 mA/V
Ex: 1.24 Refer to Fig. E1.24
V2
Vs
=
Ri
Rs +
1
sC
+Ri
=
Ri
Rs + Ri
s
s +
1
C(Rs + Ri )
which is an HP STC function.
f3dB =
1
2πC(Rs + Ri )
≤ 100 Hz
C ≥
1
2π(1 + 9)103
× 100
= 0.16 µF

Answers to Problems for Microelectronic Circuits, 8th Edition - Adel Sedra & Kenneth Carless Smith

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Answers to Problems for Microelectronic Circuits, 8th Edition - Adel Sedra & Kenneth Carless Smith