Solutions for Problems in Microelectronic Circuits, 8th International Edition – Sedra & Smith

Exercise 1–1
Chapter 1
Solutions to Exercises within the Chapter
Ex: 1.1 When output terminals are
open-circuited, as in Fig. 1.1a:
For circuit a. voc = vs(t)
For circuit b. voc = is(t) × Rs
When output terminals are short-circuited, as in
Fig. 1.1b:
For circuit a. isc =
vs(t)
Rs
For circuit b. isc = is(t)
For equivalency
Rsis(t) = vs(t)
Rs a
b

vs (t)
Figure 1.1a
is (t)
a
b
Rs
Figure 1.1b
Ex: 1.2
voc vs
Rs

isc
voc = 10 mV
isc = 10 µA
Rs =
voc
isc
=
10 mV
10 µA
= 1 k
Ex: 1.3 Using voltage divider:
vo(t) = vs(t) ×
RL
Rs + RL
vs (t) vo
Rs

RL
Given vs(t) = 10 mV and Rs = 1 k.
If RL = 100 k
vo = 10 mV ×
100
100 + 1
= 9.9 mV
If RL = 10 k
vo = 10 mV ×
10
10 + 1
9.1 mV
If RL = 1 k
vo = 10 mV ×
1
1 + 1
= 5 mV
If RL = 100
vo = 10 mV ×
100
100 + 1 K
0.91 mV
For vo = 0.8vs,
RL
RL + Rs
= 0.8
Since Rs = 1 k,
RL = 4 k
Ex: 1.4 Using current divider:
Rs
is 10 A RL
io
io = is ×
Rs
Rs + RL
Given is = 10 µA, Rs = 100 k.
For
RL = 1 k, io = 10 µA ×
100
100 + 1
= 9.9 µA
For
RL = 10 k, io = 10 µA ×
100
100 + 10
9.1 µA
For
RL = 100 k, io = 10 µA ×
100
100 + 100
= 5 µA
For RL = 1 M, io = 10 µA ×
100 K
100 K + 1 M
0.9 µA
For io = 0.8is,
100
100 + RL
= 0.8
⇒ RL = 25 k
Sedra, Smith, Carusone, Gaudet Microelectronic Circuits, 8th International Edition © Oxford University Press 2021
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Exercise 1–2
Ex: 1.5 f =
1
T
=
1
10−3
= 1000 Hz
ω = 2πf = 2π × 103
rad/s
Ex: 1.6 (a) T =
1
f
=
1
60
s = 16.7 ms
(b) T =
1
f
=
1
10−3
= 1000 s
(c) T =
1
f
=
1
106
s = 1 µs
Ex: 1.7 If 6 MHz is allocated for each channel,
then 470 MHz to 608 MHz will accommodate
806 − 470
6
= 23 channels
Since the broadcast band starts with channel 14, it
will go from channel 14 to channel 36.
Ex: 1.8 P =
1
T
T

0
v2
R
dt
=
1
T
×
V2
R
× T =
V2
R
Alternatively,
P = P1 + P3 + P5 + · · ·
=

4V
√
2π
2
1
R
+

4V
3
√
2π
2
1
R
+

4V
5
√
2π
2
1
R
+ · · ·
=
V2
R
×
8
π2
×

1 +
1
9
+
1
25
+
1
49
+ · · ·

It can be shown by direct calculation that the
infinite series in the parentheses has a sum that
approaches π2
/8; thus P becomes V2
/R as found
from direct calculation.
Fraction of energy in fundamental
= 8/π2
= 0.81
Fraction of energy in first five harmonics
=
8
π2

1 +
1
9
+
1
25

= 0.93
Fraction of energy in first seven harmonics
=
8
π2

1 +
1
9
+
1
25
+
1
49

= 0.95
Fraction of energy in first nine harmonics
=
8
π2

1 +
1
9
+
1
25
+
1
49
+
1
81

= 0.96
Note that 90% of the energy of the square wave is
in the first three harmonics, that is, in the
fundamental and the third harmonic.
Ex: 1.9 (a) D can represent 15 equally-spaced
values between 0 and 3.75 V. Thus, the values are
spaced 0.25 V apart.
vA = 0 V ⇒ D = 0000
vA = 0.25 V ⇒ D = 0000
vA = 1 V ⇒ D = 0000
vA = 3.75 V ⇒ D = 0000
(b) (i) 1 level spacing: 20
× +0.25 = +0.25 V
(ii) 2 level spacings: 21
× +0.25 = +0.5 V
(iii) 4 level spacings: 22
× +0.25 = +1.0 V
(iv) 8 level spacings: 23
× +0.25 = +2.0 V
(c) The closest discrete value represented by D is
+1.25 V; thus D = 0101. The error is -0.05 V, or
−0.05/1.3 × 100 = −4%.
Ex: 1.10 Voltage gain = 20 log 100 = 40 dB
Current gain = 20 log 1000 = 60 dB
Power gain = 10 log Ap = 10 log (Av Ai)
= 10 log 105
= 50 dB
Ex: 1.11 Pdc = 15 × 8 = 120 mW
PL =
(6/
√
2)2
1
= 18 mW
Pdissipated = 120 − 18 = 102 mW
η =
PL
Pdc
× 100 =
18
120
× 100 = 15%
Ex: 1.12 vo = 1 ×
10
106
+ 10
10−5
V = 10 µV
PL = v2
o/RL =
(10 × 10−6
)2
10
= 10−11
W
With the buffer amplifier:
vo = 1 ×
Ri
Ri + Rs
× Avo ×
RL
RL + Ro
= 1 ×
1
1 + 1
× 1 ×
10
10 + 10
= 0.25 V
PL =
v2
o
RL
=
0.252
10
= 6.25 mW
Voltage gain =
vo
vs
=
0.25 V
1 V
= 0.25 V/V
= −12 dB
Power gain (Ap) ≡
PL
Pi
where PL = 6.25 mW and Pi = vii1,
vi = 0.5 V and
ii =
1 V
1 M + 1 M
= 0.5 µA

Exercise 1–3
Thus,
Pi = 0.5 × 0.5 = 0.25 µW
and
Ap =
6.25 × 10−3
0.25 × 10−6
= 25 × 103
10 log Ap = 44 dB
Ex: 1.13 Open-circuit (no load) output voltage =
Avovi
Output voltage with load connected
= Avovi
RL
RL + Ro
0.8 =
1
Ro + 1
⇒ Ro = 0.25 k = 250
Ex: 1.14 Avo = 40 dB = 100 V/V
PL =
v2
o
RL
=

Avovi
RL
RL + Ro
2
RL
= v2
i ×

100 ×
1
1 + 1
2
1000 = 2.5 v2
i
Pi =
v2
i
Ri
=
v2
i
10,000
Ap ≡
PL
Pi
=
2.5v2
i
10−4
v2
i
= 2.5 × 104
W/W
10 log Ap = 44 dB
Ex: 1.15 Without stage 3 (see figure)
vL
vs
=

1 M
100 k + 1 M

(10)

100 k
100 k + 1 k

×(100)

100
100 + 1 k

vL
vs
= (0.909)(10)(0.9901)(100)(0.0909)
= 81.8 V/V
This figure belongs to Exercise 1.15.

vs vi1
10vi1
100 k
1 M vi2
1 k
100 k
100vi2
vL
1 k
100
Stage 1 Stage 2

Ex: 1.16 Refer the solution to Example 1.3 in the
text.
vi1
vs
= 0.909 V/V
vi1 = 0.909 vs = 0.909 × 1 = 0.909 mV
vi2
vs
=
vi2
vi1
×
vi1
vs
= 9.9 × 0.909 = 9 V/V
vi2 = 9 × vS = 9 × 1 = 9 mV
vi3
vs
=
vi3
vi2
×
vi2
vi1
×
vi1
vs
= 90.9 × 9.9 × 0.909
= 818 V/V
vi3 = 818 vs = 818 × 1 = 818 mV
vL
vs
=
vL
vi3
×
vi3
vi2
×
vi2
vi1
×
vi1
vs
= 0.909 × 90.9 × 9.9 × 0.909 744 V/V
vL = 744 × 1 mV = 744 mV
Ex: 1.17 Using voltage amplifier model, the
three-stage amplifier can be represented as
vi
Ri
Ro
Avovi

Ri = 1 M
Ro = 10
Avo = Av1×Av2×Av3 = 9.9×90.9×1 = 900 V/V
The overall voltage gain
vo
vs
=
Ri
Ri + Rs
× Avo ×
RL
RL + Ro

Exercise 1–4
For RL = 10 :
Overall voltage gain
=
1 M
1 M + 100 K
× 900 ×
10
10 + 10
= 409 V/V
For RL = 1000 :
Overall voltage gain
=
1 M
1 M + 100 K
× 900 ×
1000
1000 + 10
= 810 V/V
∴ Range of voltage gain is from 409 V/V to
810 V/V.
Ex: 1.18
ii io
Ais ii
RL
Ro
Rs Ri
is
ii = is
Rs
Rs + Ri
io = Aisii
Ro
Ro + RL
= Aisis
Rs
Rs + Ri
Ro
Ro + RL
Thus,
io
is
= Ais
Rs
Rs + Ri
Ro
Ro + RL
Ex: 1.19
Ri
Ro
Gmvi
RL
Ri

vi

vo
vs
vi = vs
Ri
Ri + Rs
vo = Gmvi(Ro RL)
= Gmvs
Ri
Ri + Rs
(Ro RL)
Thus,
vo
vs
= Gm
Ri
Ri + Rs
(Ro RL)
Ex: 1.20 Using the transresistance circuit model,
the circuit will be
Ri
Rs
is
ii Ro
RL
vo
Rmii

ii
is
=
Rs
Ri + Rs
vo = Rmii ×
RL
RL + Ro
vo
ii
= Rm
RL
RL + Ro
Now
vo
is
=
vo
ii
×
ii
is
= Rm
RL
RL + Ro
×
Rs
Ri + Rs
= Rm
Rs
Rs + Ri
×
RL
RL + Ro
Ex: 1.21
vb = ibrπ + (β + 1)ibRe
= ib[rπ + (β + 1)Re]
But vb = vx and ib = ix, thus
Rin ≡
vx
ix
=
vb
ib
= rπ + (β + 1)Re
Ex: 1.22
f Gain
10 Hz 60 dB
10 kHz 40 dB
100 kHz 20 dB
1 MHz 0 dB

Exercise 1–5
Gain (dB)
20 dB/decade
3 dB
frequency
0
20
40
60
1 10 10 10 10 10 10 10 f (Hz)
Ex: 1.23
RL
Ro
Ri Vi
Vi Gm Vo CL

Vo = GmVi[Ro RL CL]
=
GmVi
1
Ro
+
1
RL
+ sCL
Thus,
Vo
Vi
=
Gm
1
Ro
+
1
RL
×
1
1 +
sCL
1
Ro
+
1
RL
Vo
Vi
=
Gm(RL Ro)
1 + sCL(RL Ro)
which is of the STC LP type.
ω0 =
1
CL(RL Ro)
=
1
4.5 × 10−9(103 Ro)
For ω0 to be at least wπ × 40 × 103
, the highest
value allowed for Ro is
Ro =
103
2π × 40 × 103 × 103 × 4.5 × 10−9 − 1
=
103
1.131 − 1
= 7.64 k
The dc gain is
Gm(RL Ro)
To ensure a dc gain of at least 40 dB (i.e., 100),
the minimum value of Gm is
⇒ RL ≥ 100/(103
7.64 × 103
) = 113.1 mA/V
Ex: 1.24 Refer to Fig. E1.24
V2
Vs
=
Ri
Rs +
1
sC
+Ri
=
Ri
Rs + Ri
s
s +
1
C(Rs + Ri)
which is an HP STC function.
f3dB =
1
2πC(Rs + Ri)
≤ 100 Hz
C ≥
1
2π(1 + 9)103
× 100
= 0.16 µF
Ex: 1.25 T = 50 K
ni = BT3/2
e−Eg/(2kT)
= 7.3 × 1015
(50)3/2
e−1.12/(2×8.62×10−5×50)
9.6 × 10−39
/cm3
T = 350 K
ni = BT3/2
e−Eg/(2kT)
= 7.3 × 1015
(350)3/2
e−1.12/(2×8.62×10−5×350)
= 4.15 × 1011
/cm3
Ex: 1.26 ND = 1017
/cm3
From Exercise 1.26, ni at
T = 350 K = 4.15 × 1011
/cm3
nn = ND = 1017
/cm3
pn
∼
=
ni2
ND
=
(4.15 × 1011
)2
1017
= 1.72 × 106
/cm3
Ex: 1.27 At 300 K, ni = 1.5 × 1010
/cm3
pp = NA
Want electron concentration
= np =
1.5 × 1010
106
= 1.5 × 104
/cm3
∴ NA = pp =
ni2
np
=
(1.5 × 1010
)2
1.5 × 104
= 1.5 × 1016
/cm3
Ex: 1.28 (a) νn−drift = −μnE
Here negative sign indicates that electrons move
in a direction opposite to E.
We use

Exercise 1–6
νn-drift = 1350 ×
1
2 × 10−4
∵ 1 µm = 10−4
cm
= 6.75 × 106
cm/s = 6.75 × 104
m/s
(b) Time taken to cross 2-µm
length =
2 × 10−6
6.75 × 104
30 ps
(c) In n-type silicon, drift current density Jn is
Jn = qnμnE
= 1.6 × 10−19
× 1016
× 1350 ×
1 V
2 × 10−4
= 1.08 × 104
A/cm2
(d) Drift current In = AJn
= 0.25 × 10−8
× 1.08 × 104
= 27 µA
The resistance of the bar is
R = ρ ×
L
A
= qnμn ×
L
A
= 1.6 × 10−19
× 1016
× 1350 ×
2 × 10−4
0.25 × 10−8
= 37.0 k
Alternatively, we may simply use the preceding
result for current and write
R = V/In = 1 V/27 µA = 37.0 k
Note that 0.25 µm2
= 0.25 × 10−8
cm2
.
Ex: 1.29 Jn = qDn
dn(x)
dx
From Fig. E1.29,
n0 = 1017
/cm3
= 105
/(µm)3
Dn = 35 cm2
/s = 35 × (104
)2
(µm)2
/s
= 35 × 108
(µm)2
/s
dn
dx
=
105
− 0
0.5
= 2 × 105
µm−4
Jn = qDn
dn(x)
dx
= 1.6 × 10−19
× 35 × 108
× 2 × 105
= 112 × 10−6
A/µm2
= 112 µA/µm2
For In = 1 mA = Jn × A
⇒ A =
1 mA
Jn
=
103
µA
112 µA/(µm)2
9 µm2
Ex: 1.30 Using Eq. (1.44),
Dn
μn
=
Dp
μp
= VT
Dn = μnVT = 1350 × 25.9 × 10−3
∼
= 35 cm2
/s
Dp = μpVT = 480 × 25.9 × 10−3
∼
= 12.4 cm2
/s
Ex: 1.31 Equation (1.49)
W =

2 s
q

1
NA
+
1
ND

V0
=

2 s
q

NA + ND
NAND

V0
W2
=
2 s
q

NA + ND
NAND

V0
V0 =
1
2

q
s

NAND
NA + ND

W2
Ex: 1.32 In a p+
n diode NA ND
Equation (1.49) W =

2 s
q

1
NA
+
1
ND

V0
We can neglect the term
1
NA
as compared to
1
ND
,
thus
W

2 s
qND
· V0
Equation (1.50) xn = W
NA
NA + ND
W
NA
NA
= W
Equation (1.51), xp = W
ND
NA + ND
since NA ND
W
ND
NA
= W

NA
ND

Equation (1.52), QJ = Aq

NAND
NA + ND

W
Aq
NAND
NA
W
= AqNDW
Equation (1.53), QJ = A

2 sq

NAND
NA + ND

V0

Exercise 1–7
A

2 sq

NAND
NA

V0 since NA ND
= A

2 sqNDV0
Ex: 1.33 In Example 1.10, NA = 1018
/cm3
and
ND = 1016
/cm3
In the n-region of this pn junction
nn = ND = 1016
/cm3
pn =
n2
i
nn
=
(1.5 × 1010
)2
1016
= 2.25 × 104
/cm3
As one can see from above equation, to increase
minority-carrier concentration (pn) by a factor of
2, one must lower ND (= nn) by a factor of 2.
Ex: 1.34
Equation (1.64) IS = Aqn2
i

Dp
LpND
+
Dn
LnNA

since
Dp
Lp
and
Dn
Ln
have approximately
similar values, if NA ND, then the term
Dn
LnNA
can be neglected as compared to
Dp
LpND
∴ IS
∼
= Aqn2
i
Dp
LpND
Ex: 1.35 IS = Aqn2
i

Dp
LpND
+
Dn
LnNA

= 10−4
× 1.6 × 10−19
× (1.5 × 1010
)2
×
⎛
⎜
⎜
⎝
10
5 × 10−4
×
1016
2
+
18
10 × 10−4
× 1018
⎞
⎟
⎟
⎠
= 1.46 × 10−14
A
I = IS(eV/VT − 1)
ISeV/VT = 1.45 × 10−14
e0.605/(25.9×10−3)
= 0.2 mA
Ex: 1.36 W =

2 s
q

1
NA
+
1
ND

(V0 − VF)
=

2 × 1.04 × 10−12
1.6 × 10−19

1
1018
+
1
1016

(0.814 − 0.605)
= 1.66 × 10−5
cm = 0.166 µm
Ex: 1.37 W =

2 s
q

1
NA
+
1
ND

(V0 + VR)
=

2 × 1.04 × 10−12
1.6 × 10−19

1
1018
+
1
1016

(0.814 + 2)
= 6.08 × 10−5
cm = 0.608 µm
Using Eq. (1.52),
QJ = Aq

NAND
NA + ND

W
= 10−4
× 1.6 × 10−19

1018
× 1016
1018
+ 1016

× 6.08 ×
10−5
cm
= 9.63 pC
Reverse current I = IS = Aqn2
i

Dp
LpND
+
Dn
LnNA

= 10−14
× 1.6 × 10−19
× (1.5 × 1010
)2
×

10
5 × 10−4
× 1016
+
18
10 × 10−4
× 1018

= 7.3 × 10−15
A
Ex: 1.38 Equation (1.69),
Cj0 = A

sq
2

NAND
NA + ND

1
V0

= 10−4

1.04 × 10−12
× 1.6 × 10−19
2

1018
× 1016
1018
+ 1016

1
0.814

= 3.2 pF
Equation (1.70),
Cj =
Cj0

1 +
VR
V0
=
3.2 × 10−12

1 +
2
0.814
= 1.72 pF
Ex: 1.39 Cd =
dQ
dV
=
d
dV
(τT I)
=
d
dV
[τT × IS(eV/VT − 1)]
= τT IS
d
dV
(eV/VT − 1)
= τT IS
1
VT
eV/VT
=
τT
VT
× ISeV/VT
∼
=

τT
VT

I

Exercise 1–8
Ex: 1.40 Equation (1.73),
τp =
L2
p
Dp
=
(5 × 10−4
)2
10
= 25 ns
Equation (3.57),
Cd =

τT
VT

I
In Example 1.6, NA = 1018
/cm3
,
ND = 1016
/cm3
Assuming NA ND,
τT τp = 25 ns
∴ Cd =

25 × 10−9
25.9 × 10−3

0.1 × 10−3
= 96.5 pF

Chapter 1–1
Solutions to End-of-Chapter Problems
1.1 (a) V = IR = 5 mA × 1 k = 5 V
P = I2
R = (5 mA)2
× 1 k = 25 mW
(b) R = V/I = 5 V/1 mA = 5 k
P = VI = 5 V × 1 mA = 5 mW
(c) I = P/V = 100 mW/10 V = 10 mA
R = V/I = 10 V/10 mA = 1 k
(d) V = P/I = 1 mW/0.1 mA
= 10 V
R = V/I = 10 V/0.1 mA = 100 k
(e) P = I2
R ⇒ I =

P/R
I =

1000 mW/1 k = 31.6 mA
V = IR = 31.6 mA × 1 k = 31.6 V
Note: V, mA, k, and mW constitute a
consistent set of units.
1.2 (a) I =
V
R
=
5 V
1 k
= 5 mA
(b) R =
V
I
=
5 V
1 mA
= 5 k
(c) V = IR = 0.1 mA × 10 k = 1 V
(d) I =
V
R
=
1 V
100
= 0.01 A = 10 mA
Note: Volts, milliamps, and kilohms constitute a
consistent set of units.
1.3 (a) P = I2
R = (20 × 10−3
)2
× 1 × 103
= 0.4 W
Thus, R should have a
1
2
-W rating.
(b) P = I2
R = (40 × 10−3
)2
× 1 × 103
= 1.6 W
Thus, the resistor should have a 2-W rating.
(c) P = I2
R = (1 × 10−3
)2
× 100 × 103
= 0.1 W
Thus, the resistor should have a
1
8
-W rating.
(d) P = I2
R = (4 × 10−3
)2
× 10 × 103
= 0.16 W
1
4
-W rating.
(e) P = V2
/R = 202
/(1 × 103
) = 0.4 W
1
2
-W rating.
(f) P = V2
/R = 112
/(1 × 103
) = 0.121 W
Thus, a rating of
1
8
W should theoretically
suffice, though
1
4
W would be prudent to allow
for inevitable tolerances and measurement errors.
1.4 See figure on next page, which shows how to
realize the required resistance values.
1.5 Shunting the 10 k by a resistor of value of
R results in the combination having a resistance
Req,
Req =
10R
R + 10
Thus, for a 1% reduction,
R
R + 10
= 0.99 ⇒ R = 990 k
For a 5% reduction,
R
R + 10
= 0.95 ⇒ R = 190 k
For a 10% reduction,
R
R + 10
= 0.90 ⇒ R = 90 k
For a 50% reduction,
R
R + 10
= 0.50 ⇒ R = 10 k
Shunting the 10 k by
(a) 1 M results in
Req =
10 × 1000
1000 + 10
=
10
1.01
= 9.9 k
a 1% reduction;
(b) 100 k results in
Req =
10 × 100
100 + 10
=
10
1.1
= 9.09 k
a 9.1% reduction;
(c) 10 k results in
Req =
10
10 + 10
= 5 k
a 50% reduction.
1.6 Use voltage divider to find VO
VO = 5
2
2 + 3
= 2 V
Equivalent output resistance RO is
RO = (2 k 3 k) = 1.2 k

Chapter 1–2
This figure belongs to Problem 1.4.
All resistors are 5 k
12.5 kΩ
23.75 kΩ
1.67 kΩ
20 kΩ
The extreme values of VO for ±5% tolerance
resistor are
VOmin = 5
2(1 − 0.05)
2(1 − 0.05) + 3(1 + 0.05)
= 1.88 V
VOmax = 5
2(1 + 0.05)
2(1 + 0.05) + 3(1 − 0.05)
= 2.12 V
5 V
VO
RO
3 k
2 k
The extreme values of RO for ±5% tolerance
resistors are 1.2 × 1.05 = 1.26 k and
1.2 × 0.95 = 1.14 k.
1.7 VO = VDD
R2
R1 + R2
To find RO, we short-circuit VDD and look back
into node X,
RO = R2 R1 =
R1R2
R1 + R2
1.8
3 V
6 V
10 k
(a)
10 k
10 k
9 V
R 10 k // 20 k
6.67 k
R 20 // 10 k
6.67 k
4.5 V
(b)
10 k
10 k
R 10 // 10
5 k
9 V

Chapter 1–3
3 V
9 V
10 k
(c)
10 k 10 k
R 10 // 10 // 10
3.33 k
10 k
10 k 10 k
9 V
6 V
(d)
R 10 // 10 // 10
3.33 k
Voltage generated:
+3V [two ways: (a) and (c) with (c) having lower
output resistance]
+4.5 V (b)
+6V [two ways: (a) and (d) with (d) having a
lower output resistance]
1.9
10 k
4.7 k
15 V
VO
VO = 15
4.7
10 + 4.7
= 4.80 V
To increase VO to 10.00 V, we shunt the 10-k
resistor by a resistor R whose value is such that
10 R = 2 × 4.7.
15 V
5.00 V
10 k
4.7 k
R
Thus
1
10
+
1
R
=
1
9.4
⇒ R = 156.7 ≈ 157 k
Now,
RO = 10 k R 4.7 k
= 9.4 4.7 =
9.4
3
= 3.133 k
To make RO = 3.33, we add a series resistance of
approximately 200 , as shown below,
15 V
10 k
157 k
200

RO
VO
4.7 k
1.10
I2
I1
I V

R2
R1
V = I(R1 R2)
= I
R1R2
R1 + R2
I1 =
V
R1
= I
R2
R1 + R2
I2 =
V
R2
= I
R1
R1 + R2

Chapter 1–4
1.11 Connect a resistor R in parallel with RL.
To make IL = I/4 (and thus the current through
R, 3I/4), R should be such that
6I/4 = 3IR/4
⇒ R = 2 k
I
I R
RL 6 k
3
4
IL
I
4
1.12 The parallel combination of the resistors is
R where
1
R
=
N

i=1
1/Ri
The voltage across them is
V = I × R =
I
N
i=1 1/Ri
Thus, the current in resistor Rk is
Ik = V/Rk =
I/Rk
N
i=1 1/Ri
1.13
I R1
Rin
R
0.2I 0.8I
To make the current through R equal to 0.2I, we
shunt R by a resistance R1 having a value such
that the current through it will be 0.8I; thus
0.2IR = 0.8IR1 ⇒ R1 =
R
4
The input resistance of the divider, Rin, is
Rin = R R1 = R
R
4
=
1
5
R
Now if R1 is 10% too high, that is, if
R1 = 1.1
R
4
the problem can be solved in two ways:
(a) Connect a resistor R2 across R1 of value such
that R2 R1 = R/4, thus
R2(1.1R/4)
R2 + (1.1R/4)
=
R
4
1.1R2 = R2 +
1.1R
4
⇒ R2 =
11R
4
= 2.75 R
Rin = R
1.1R
4

11R
4
= R
R
4
=
R
5
I R
Rin
1.1R
4
R
4
11R
4
}
0.2I
(b) Connect a resistor in series with the load
resistor R so as to raise the resistance of the load
branch by 10%, thereby restoring the current
division ratio to its desired value. The added
series resistance must be 10% of R (i.e., 0.1R).
0.1R
1.1R
4
Rin
R
0.8I
0.2I
I
Rin = 1.1R
1.1R
4
=
1.1R
5
that is, 10% higher than in case (a).
1.14 For RL = 10 k , when signal source
generates 0−0.5 mA, a voltage of 0−2 V may
appear across the source
To limit vs ≤ 1 V, the net resistance has to be
≤ 2 k. To achieve this we have to shunt RL with
a resistor R so that (R RL) ≤ 2 k.
R RL ≤ 2 k.
RRL
R + RL
≤ 2 k
For RL = 10 k
R ≤ 2.5 k
The resulting circuit needs only one additional
resistance of 2 k in parallel with RL so that

Chapter 1–5
vs ≤ 1 V. The circuit is a current divider, and the
current through RL is now 0–0.1 mA.
R
00.5 mA
is vs

RL
1.15 (a) Between terminals 1 and 2:
1.5 V VTh
RTh
RTh
2
1
2
1
1 k
1 k
1 k
0.75 V
0.5 k

1 k
(b) Same procedure is used for (b) to obtain
0.75 V
2
3
0.5 k
(c) Between terminals 1 and 3, the open-circuit
voltage is 1.5 V. When we short circuit the
voltage source, we see that the Thévenin
resistance will be zero. The equivalent circuit is
then
1.5 V
1
3
1.16
3 k
12.31 k
0.77 V I
Now, when a resistance of 3 k is connected
between node 4 and ground,

Chapter 1–6
I =
0.77
12.31 + 3
= 0.05 mA
1.17
5 V
10 V
5 k
10 k
2 k
R2
R1
R3
I2 I1
I3
V
(a) Node equation at the common mode yields
I3 = I1 + I2
Using the fact that the sum of the voltage drops
across R1 and R3 equals 10 V, we write
10 = I1R1 + I3R3
= 10I1 + (I1 + I2) × 2
= 12I1 + 2I2
That is,
12I1 + 2I2 = 10 (1)
Similarly, the voltage drops across R2 and R3 add
up to 5 V, thus
5 = I2R2 + I3R3
= 5I2 + (I1 + I2) × 2
which yields
2I1 + 7I2 = 5 (2)
Equations (1) and (2) can be solved together by
multiplying Eq. (2) by 6:
12I1 + 42I2 = 30 (3)
Now, subtracting Eq. (1) from Eq. (3) yields
40I2 = 20
⇒ I2 = 0.5 mA
Substituting in Eq. (2) gives
2I1 = 5 − 7 × 0.5 mA
⇒ I1 = 0.75 mA
I3 = I1 + I2
= 0.75 + 0.5
= 1.25 mA
V = I3R3
= 1.25 × 2 = 2.5 V
To summarize:
I1 = 0.75 mA I2 = 0.5 mA
I3 = 1.25 mA V = 2.5 V
(b) A node equation at the common node can be
written in terms of V as
10 − V
R1
+
5 − V
R2
=
V
R3
Thus,
10 − V
10
+
5 − V
5
=
V
2
⇒ 0.8V = 2
⇒ V = 2.5 V
Now, I1, I2, and I3 can be easily found as
I1 =
10 − V
10
=
10 − 2.5
10
= 0.75 mA
I2 =
5 − V
5
=
5 − 2.5
5
= 0.5 mA
I3 =
V
R3
=
2.5
2
= 1.25 mA
Method (b) is much preferred, being faster, more
insightful, and less prone to errors. In general,
one attempts to identify the lowest possible
number of variables and write the corresponding
minimum number of equations.
1.18 Find the Thévenin equivalent of the circuit
to the left of node 1.
Between node 1 and ground,
RTh = (1 k 1.2 k) = 0.545 k

Chapter 1–7
VTh = 10 ×
1.2
1 + 1.2
= 5.45 V
Find the Thévenin equivalent of the circuit to the
right of node 2.
Between node 2 and ground,
RTh = 9.1 k 11 k = 4.98 k
VTh = 10 ×
11
11 + 9.1
= 5.47 V
The resulting simplified circuit is
R5 2 k
V5
1 2
5.45 V 5.47 V
I5
0.545 k 4.98 k

I5 =
5.47 − 5.45
4.98 + 2 + 0.545
= 2.66 µA
V5 = 2.66 µA × 2 k
= 5.32 mV
1.19 We first find the Thévenin equivalent of the
source to the right of vO.
V = 4 × 1 = 4 V
Then, we may redraw the circuit in Fig. P1.19 as
shown below
5 V 4 V
3 k 1 k
vo
Then, the voltage at vO is found from a simple
voltage division.
vO = 4 + (5 − 4) ×
1
3 + 1
= 4.25 V
1.20 Refer to Fig. P1.20. Using the voltage
divider rule at the input side, we obtain
vπ
vs
=
rπ
rπ + Rs
(1)
At the output side, we find vo by multiplying the
current gmvπ by the parallel equivalent of ro
and RL,
vo = −gmvπ (ro RL) (2)
Finally, vo/vs can be obtained by combining Eqs.
(1) and (2) as
vo
vs
= −
rπ
rπ + Rs
gm(ro RL)
1.21 (a) T = 10−4
ms = 10−7
s
f =
1
T
= 107
Hz
ω = 2πf = 6.28 × 107
rad/s
(b) f = 1 GHz = 109
Hz
T =
1
f
= 10−9
s
ω = 2πf = 6.28 × 109
rad/s
(c) ω = 6.28 × 102
rad/s
f =
ω
2π
= 102
Hz
T =
1
f
= 10−2
s
(d) T = 10 s
f =
1
T
= 10−1
Hz
ω = 2πf = 6.28 × 10−1
rad/s
(e) f = 60 Hz
T =
1
f
= 1.67 × 10−2
s
ω = 2πf = 3.77 × 102
rad/s
(f) ω = 1 krad/s = 103
rad/s
f =
ω
2π
= 1.59 × 102
Hz
T =
1
f
= 6.28 × 10−3
s
(g) f = 1900 MHz = 1.9 × 109
Hz
T =
1
f
= 5.26 × 10−10
s
ω = 2πf = 1.194 × 1010
rad/s
1.22 (a) Z = R +
1
jωC
= 103
+
1
j2π × 10 × 103
× 10 × 10−9

Chapter 1–8
= (1 − j1.59) k
(b) Y =
1
R
+ jωC
=
1
104
+ j2π × 10 × 103
× 0.01 × 10−6
= 10−4
(1 + j6.28)
Z =
1
Y
=
104
1 + j6.28
=
104
(1 − j6.28)
1 + 6.282
= (247.3 − j1553)
(c) Y =
1
R
+ jωC
=
1
100 × 103
+ j2π × 10 × 103
× 100 × 10−12
= 10−5
(1 + j0.628)
Z =
105
1 + j0.628
= (71.72 − j45.04) k
(d) Z = R + jωL
= 100 + j2π × 10 × 103
× 10 × 10−3
= 100 + j6.28 × 100
= (100 + j628),
1.23 (a) Z = 1 k at all frequencies
(b) Z = 1 /jωC = −j
1
2πf × 10 × 10−9
At f = 60 Hz, Z = −j265 k
At f = 100 kHz, Z = −j159
At f = 1 GHz, Z = −j0.016
(c) Z = 1 /jωC = −j
1
2πf × 10 × 10−12
At f = 60 Hz, Z = −j0.265 G
At f = 100 kHz, Z = −j0.16 M
At f = 1 GHz, Z = −j15.9
(d) Z = jωL = j2πfL = j2πf × 10 × 10−3
At f = 60 Hz, Z = j3.77
At f = 100 kHz, Z = j6.28 k
At f = 1 GHz, Z = j62.8 M
(e) Z = jωL = j2πfL = j2πf(1 × 10−6
)
f = 60 Hz, Z = j0.377 m
f = 100 kHz, Z = j0.628
f = 1 GHz, Z = j6.28 k
1.24 Y =
1
jωL
+ jωC
=
1 − ω2
LC
jωL
⇒ Z =
1
Y
=
jωL
1 − ω2LC
The frequency at which |Z| = ∞ is found letting
the denominator equal zero:
1 − ω2
LC = 0
⇒ ω =
1
√
LC
At frequencies just below this, ∠Z = +90◦
.
At frequencies just above this, ∠Z = −90◦
.
Since the impedance is infinite at this frequency,
the current drawn from an ideal voltage source is
zero.
1.25
is
Rs
Rs

vs
Thévenin
equivalent
Norton
equivalent
voc = vs
isc = is
vs = isRs
Thus,
Rs =
voc
isc
(a) vs = voc = 1 V
is = isc = 0.1 mA
Rs =
voc
isc
=
1 V
0.1 mA
= 10 k
(b) vs = voc = 0.1 V
is = isc = 1 µA
Rs =
voc
isc
=
0.1 V
1 µA
= 0.1 M = 100 k

Chapter 1–9
1.26

Rs
RL

vs vo
vo
vs
=
RL
RL + Rs
vo = vs

1 +
Rs
RL

Thus,
vs
1 +
Rs
100
= 40 (1)
and
vs
1 +
Rs
10
= 10 (2)
Dividing Eq. (1) by Eq. (2) gives
1 + (Rs /10)
1 + (Rs /100)
= 4
⇒ RS = 50 k
Substituting in Eq. (2) gives
vs = 60 mV
The Norton current is can be found as
is =
vs
Rs
=
60 mV
50 k
= 1.2 µA
1.27 The nominal values of VL and IL are
given by
VL =
RL
RS + RL
VS
IL =
VS
RS + RL
After a 10% increase in RL, the new values will be
VL =
1.1RL
RS + 1.1RL
VS
IL =
VS
RS + 1.1RL
(a) The nominal values are
VL =
200
5 + 200
× 1 = 0.976 V
IL =
1
5 + 200
= 4.88µA
VL =
1.1 × 200
5 + 1.1 × 200
= 0.978 V
IL =
1
5 + 1.1 × 200
= 4.44µA
These values represent a 0.2% and 9% change,
respectively. Since the load voltage remains
relatively more constant than the load current, a
Thévenin source is more appropriate here.
(b) The nominal values are
VL =
50
5 + 50
× 1 = 0.909 V
IL =
1
5 + 50
= 18.18 mA
VL =
1.1 × 50
5 + 1.1 × 50
= 0.917 V
IL =
1
5 + 1.1 × 50
= 16.67 mA
These values represent a 1% and 8% change,
respectively. Since the load voltage remains
relatively more constant than the load current, a
Thévenin source is more appropriate here.
(c) The nominal values are
VL =
0.1
2 + 0.1
× 1 = 47.6 mV
IL =
1
2 + 0.1
= 0.476 mA
VL =
1.1 × 0.1
2 + 1.1 × 0.1
= 52.1 mV
IL =
1
2 + 1.1 × 0.1
= 0.474 mA
These values represent a 9% and 0.4% change,
respectively. Since the load current remains
relatively more constant than the load voltage, a
Norton source is more appropriate here. The
Norton equivalent current source is
IS =
VS
RS
=
1
2
= 0.5 mA
(d) The nominal values are
VL =
16
150 + 16
× 1 = 96.4 mV

Chapter 1–10
IL =
1
150 + 16
= 6.02 mA
VL =
1.1 × 16
150 + 1.1 × 16
= 105 mV
IL =
1
150 + 1.1 × 16
= 5.97 mA
These values represent a 9% and 1% change,
respectively. Since the load current remains
relatively more constant than the load voltage, a
Norton source is more appropriate here. The
Norton equivalent current source is
IS =
VS
RS
=
1
150
= 6.67 mA
1.28
PL = v2
O ×
1
RL
= v2
S
R2
L
(RL + RS)2
×
1
RL
= v2
S
RL
(RL + RS)2
vs vO
Rs
RL

Since we are told that the power delivered to a
16 speaker load is 75% of the power delivered
to a 32 speaker load,
PL(RL = 16) = 0.75 × PL(RL = 32)
16
(RS + 32)2
= 0.75 ×
32
(RS + 32)2
√
16
RS + 32
=
√
24
RS + 32
⇒ (
√
24 =
√
16)RS =
√
16 × 32 −
√
24 × 16
0.9RS = 49.6
RS = 55.2
1.29 The observed output voltage is 1 mV/ ◦
C,
which is one half the voltage specified by the
sensor, presumably under open-circuit conditions:
that is, without a load connected. It follows that
that sensor internal resistance must be equal to
RL, that is, 5 k.
1.30

vs vo Rs
Rs
io

is vo
io
vo = vs − ioRs
Open-circuit
(io 0)
voltage
0
Rs
vs
vs
vo
is
io
Slope Rs
Short-circuit (vo 0) current
1.31
Rs RL
RL
is
⫹
⫺
⫹
⫺
vs vo vo
Rs io
io
⫹
⫺
RL represents the input resistance of the processor
For vo = 0.95vs
0.95 =
RL
RL + Rs
⇒ RL = 19Rs
For io = 0.95is
0.95 =
Rs
Rs + RL
⇒ RL = RS/19
1.32
Case ω (rad/s) f(Hz) T(s)
a 3.14 × 1010
5 × 109
0.2 × 10−9
b 2 × 109
3.18 × 108
3.14 × 10−9
c 6.28 × 1010
1 × 1010
1 × 10−10
d 3.77 × 102
60 1.67 × 10−2
e 6.28 × 104
1 × 104
1 × 10−4
f 6.28 × 105
1 × 105
1 × 10−5

Chapter 1–11
1.33 (a) v = 10 sin(2π × 103
t), V
(b) v = 120
√
2 sin(2π × 60), V
(c) v = 0.1 sin(2000t), V
(d) v = 0.1 sin(2π × 103
t), V
1.34 Comparing the given waveform to that
described by Eq. (1.2), we observe that the given
waveform has an amplitude of 0.5 V (1 V
peak-to-peak) and its level is shifted up by 0.5 V
(the first term in the equation). Thus the
waveform looks as follows:
v
T
t
1V
0
...
Average value = 0.5 V
Peak-to-peak value = 1 V
Lowest value = 0 V
Highest value = 1 V
Period T =
1
f0
=
2π
ω0
= 10−3
s
Frequency f =
1
I
= 1 kHz
1.35 (a) Vpeak = 117 ×
√
2 = 165 V
(b) Vrms = 33.9/
√
2 = 24 V
(c) Vpeak = 220 ×
√
2 = 311 V
(d) Vpeak = 220 ×
√
2 = 311 kV
1.36 The two harmonics have the ratio
126/98 = 9/7. Thus, these are the 7th and 9th
harmonics. From Eq. (1.2), we note that the
amplitudes of these two harmonics will have the
ratio 7 to 9, which is confirmed by the
measurement reported. Thus the fundamental will
have a frequency of 98/7, or 14 kHz, and peak
amplitude of 63 × 7 = 441 mV. The rms value of
the fundamental will be 441/
√
2 = 312 mV. To
find the peak-to-peak amplitude of the square
wave, we note that 4V/π = 441 mV. Thus,
Peak-to-peak amplitude
= 2V = 441 ×
π
2
= 693 mV
Period T =
1
f
=
1
14 × 103
= 71.4 µs
1.37 The rms value of a symmetrical square
wave with peak amplitude V̂ is simply V̂. Taking
the root-mean-square of the first 5 sinusoidal
terms in Eq. (1.2) gives an rms value of,
4V̂
π
√
2

12 +

1
3
2
+

1
5
2
+

1
7
2
+

1
9
2
= 0.980V̂
which is 2% lower than the rms value of the
square wave.
1.38 If the amplitude of the square wave is Vsq,
then the power delivered by the square wave to a
resistance R will be V2
sq/R . If this power is to be
equal to that delivered by a sine wave of peak
amplitude V̂, then
⫺Vsq
Vsq
0
T
V2
sq
R
=
(V̂/
√
2)
2
R
Thus, Vsq = V̂/
√
2 . This result is independent of
frequency.
1.39
Decimal Binary
0 0
6 110
11 1011
28 11100
59 111011
1.40 (a) For N bits there will be 2N
possible
levels, from 0 to VFS. Thus there will be (2N
− 1)
discrete steps from 0 to VFS with the step size
given by
Step size =
VFS
2N − 1
This is the analog change corresponding to a
change in the LSB. It is the value of the
resolution of the ADC.
(b) The maximum error in conversion occurs
when the analog signal value is at the middle of a
step. Thus the maximum error is

Chapter 1–12
Step
1
2
× step size =
1
2
VFS
2N − 1
This is known as the quantization error.
(c)
5 V
2N − 1
≤ 2 mV
2N
− 1 ≥ 2500
2N
≥ 2501 ⇒ N = 12,
For N = 12,
Resolution =
5
212 − 1
= 1.2 mV
Quantization error =
1.2
2
= 0.6 mV
1.41
b3 b2 b1 b0 Value Represented
0 0 0 0 +0
0 0 0 1 +1
0 0 1 0 +2
0 0 1 1 +3
0 1 0 0 +4
0 1 0 1 +5
0 1 1 0 +6
0 1 1 1 +7
1 0 0 0 –0
1 0 0 1 –1
1 0 1 0 –2
1 0 1 1 –3
1 1 0 0 –4
1 1 0 1 –5
1 1 1 0 –6
1 1 1 1 –7
Note that there are two possible representations
of zero: 0000 and 1000. For a 0.5-V step size,
analog signals in the range ±3.5 V can be
represented.
Input Steps Code
+2.5 V +5 0101
−3.0 V −6 1110
+2.7 +5 0101
−2.8 −6 1110
1.42 (a) When bi = 1, the ith switch is in
position 1 and a current (Vref /2i
R) flows to the
output. Thus iO will be the sum of all the currents
corresponding to “1” bits, that is,
iO =
Vref
R

b1
21
+
b2
22
+ · · · +
bN
2N

(b) bN is the LSB
b1 is the MSB
(c) iOmax =
10 V
10 k

1
21
+
1
22
+
1
23
+
1
24
+
1
25
+
1
26
+
1
27
+
1
28

= 0.99609375 mA
Corresponding to the LSB changing from 0 to 1
the output changes by (10/10) × 1/28
=
3.91 µA.
1.43 There will be 44,100 samples per second
with each sample represented by 16 bits. Thus the
throughput or speed will be 44, 100 × 16 =
7.056 × 105
bits per second.
1.44 Each pixel requires 8 + 8 + 8 = 24 bits to
represent it. We will approximate a megapixel as
106
pixels, and a Gbit as 109
bits. Thus, each
image requires 24 × 10 × 106
= 2.4 × 108
bits.
The number of such images that fit in 16 Gbits of
memory is
2.4 × 108
16 × 109
= 66.7 = 66
1.45 (a) Av =
vO
vI
=
10 V
100 mV
= 100 V/V
or 20 log 100 = 40 dB
Ai =
iO
iI
=
vO/RL
iI
=
10 V/100
100 µA
=
0.1 A
100 µA

Chapter 1–13
= 1000 A/A
or 20 log 1000 = 60 dB
Ap =
vOiO
vIiI
=
vO
vI
×
iO
iI
= 100 × 1000
= 105
W/W
or 10 log 105
= 50 dB
(b) Av =
vO
vI
=
1 V
10 µV
= 1 × 105
V/V
or 20 log 1 × 105
= 100 dB
Ai =
iO
iI
=
vO/RL
iI
=
1 V/10 k
100 nA
=
0.1 mA
100 nA
=
0.1 × 10−3
100 × 10−9
= 1000 A/A
or 20 log Ai = 60 dB
Ap =
vOiO
vIiI
=
vO
vI
×
iO
iI
= 1 × 105
× 1000
= 1 × 108
W/W
or 10 log AP = 80 dB
(c) Av =
vO
vi
=
5 V
1 V
= 5 V/V
or 20 log 5 = 14 dB
Ai =
iO
iI
=
vO/RL
iI
=
5 V/10
1 mA
=
0.5 A
1 mA
= 500 A/A
or 20 log 500 = 54 dB
Ap =
vOiO
vIiI
=
vO
vI
×
iO
iI
= 5 × 500 = 2500 W/W
or 10 log Ap = 34 dB
1.46 For ±5 V supplies:
The largest undistorted sine-wave output is of
4-V peak amplitude or 4/
√
2 = 2.8 Vrms. Input
needed is 14 mVrms.
For ±10-V supplies, the largest undistorted
sine-wave output is of 9-V peak amplitude or
6.4 Vrms. Input needed is 32 mVrms.
For ±15-V supplies, the largest undistorted
sine-wave output is of 14-V peak amplitude or
9.9 Vrms. The input needed is 9.9 V/200 =
49.5 mVrms.
vO
vI
200 V/V
VDD 1.0
VDD 1.0
1.47
0.2 V
2.2 V
+3 V
3 V

vo
t
1 mA
20 mA
(average)
20 mA
(average)
100
ii
RL
vi
Av =
vo
vi
=
2.2
0.2
= 11 V/V
or 20 log 11 = 20.8 dB
Ai =
io
ii
=
2.2 V/100
1 mA
=
22 mA
1 mA
= 22 A/A
or 20 log Ai = 26.8 dB
Ap =
po
pi
=
(2.2/
√
2)2
/100
0.2
√
2
×
10−3
√
2
= 242 W/W
or 10 log AP = 23.8 dB
Supply power = 2 × 3 V ×20 mA = 120 mW
Output power =
v2
orms
RL
=
(2.2/
√
2)2
100
= 24.2 mW
Input power =
24.2
242
= 0.1 mW (negligible)
Amplifier dissipation Supply power − Output
power

Chapter 1–14
= 120 − 24.2 = 95.8 mW
Amplifier efficiency =
Output power
supply power
× 100
=
24.2
120
× 100 = 20.2%
1.48 vo = Avovi
RL
RL + Ro
= Avo

vs
Ri
Ri + Rs

RL
RL + Ro

vi

vi
vs Ri
Rs

RL
Avovi
Ro
Thus,
vo
vs
= Avo
Ri
Ri + Rs
RL
RL + Ro
(a) Avo = 100, Ri = 10Rs, RL = 10Ro:
vo
vs
= 100 ×
10Rs
10Rs + Rs
×
10Ro
10Ro + Ro
= 82.6 V/V or 20 log 82.6 = 38.3 dB
(b) Avo = 100, Ri = Rs, RL = Ro:
vo
vs
= 100 ×
1
2
×
1
2
= 25 V/V or 20 log 25 = 28 dB
(c) Avo = 100 V/V, Ri = Rs/10, RL = Ro/10:
vo
vs
= 100
Rs/10
(Rs/10) + Rs
Ro/10
(Ro/10) + Ro
= 0.826 V/V or 20 log 0.826 = −1.7 dB
1.49 (a)
vo
vs
=
vi
vs
×
vo
vi

vi
vs
io
5 k
1 k
200 k

vo 100
100 vi

Figure 1
5 k 1 k
ii
is 200
500 ii 100
io
Figure 2
=
1
5 + 1
× 100 ×
100
200 + 100
= 5.56 V/V
Much of the amplifier’s 100 V/V gain is lost in
the source resistance and amplifier’s output
resistance. If the source were connected directly
to the load, the gain would be
vo
vs
=
0.1
5 + 0.1
= 0.0196 V/V
This is a factor of 284× smaller than the gain
with the amplifier in place!
(b)
The equivalent current amplifier has a dependent
current source with a value of
100 V/V
200
× ii =
100 V/V
200
× 1000 × vi
= 500 × ii
Thus,
io
is
=
ii
is
×
io
ii
=
5
5 + 1
× 500 ×
200
200 + 100
= 277.8 A/A
Using the voltage amplifier model, the current
gain can be found as follows,
io
is
=
ii
is
×
vi
ii
×
io
vi
=
5
5 + 1
× 1000 ×
100 V/V
200 + 100
= 277.8 A/A
1.50 In Example 1.3, when the first and the
second stages are interchanged, the circuit looks
like the figure above, and
vi1
vs
=
100 k
100 k + 100 k
= 0.5 V/V

Chapter 1–15
Av1 =
vi2
vi1
= 100 ×
1 M
1 M + 1 k
= 99.9 V/V
Av2 =
vi3
vi2
= 10 ×
10 k
10 k + 1 k
= 9.09 V/V
Av3 =
vL
vi3
= 1 ×
100
100 + 10
= 0.909 V/V
Total gain = Av =
vL
vi1
= Av1 × Av2 × Av3
= 99.9 × 9.09 × 0.909 = 825.5 V/V
The voltage gain from source to load is
vL
vs
=
vL
vi1
×
vi1
vS
= Av ·
vi1
vS
= 825.5 × 0.5
= 412.7 V/V
The overall voltage has reduced appreciably. This
is because the input resistance of the first stage,
Rin, is comparable to the source resistance Rs. In
Example 1.3 the input resistance of the first stage
is much larger than the source resistance.
1.51 The equivalent circuit at the output side of a
current amplifier loaded with a resistance RL is
shown. Since
io = (Aisii)
Ro
Ro + RL
we can write
1 = (Aisii)
Ro
Ro + 1
(1)
and
0.5 = (Aisii)
Ro
Ro + 12
(2)
Dividing Eq. (1) by Eq. (2), we have
RL
Ro
Aisii
io
2 =
Ro + 12
Ro + 1
⇒ Ro = 10 k
Aisii = 1 ×
10 + 1
10
= 1.1 mA
1.52
The current gain is
io
ii
=
Rm
Ro + RL
=
5000
10 + 1000
= 4.95 A/A = 13.9 dB
The voltage gain is
vo
vs
=
ii
vs
×
io
ii
×
vo
io
=
1
Rs + Ri
×
io
ii
× RL
=
1
1000 + 100
× 4.95 × 1000
= 4.90 V/V = 13.8 dB
The power gain is
voio
vsii
= 4.95 × 4.90
= 24.3 W/W = 27.7 dB
1.53
Gm = 60 mA/V
Ro = 20 k
RL = 1 k
vi = vs
Ri
Rs + Ri
= vs
2
1 + 2
=
2
3
vs
vo = Gmvi(RL Ro)
= 60
20 × 1
20 + 1
vi
= 60
20
21
×
2
3
vs
Overall voltage gain ≡
vo
vs
= 38.1 V/V

Chapter 1–16

vi
vs
io
Rs
Ri
Ro 10
RL
Rmii
1 k
100
ii

vo
1 k

Rs 10 k

vs vi
vo
ii
Ri
5-mV
peak
Ro
RL

Avovi 1 k
1.54

vi
vo
100
500
1 M 100vi
20 log Avo = 40 dB ⇒ Avo = 100 V/V
Av =
vo
vi
= 100 ×
500
500 + 100
= 83.3 V/V
or 20 log 83.3 = 38.4 dB
Ap =
v2
o/500
v2
i /1 M
= A2
v × 104
= 1.39 × 107
W/W
or 10 log (1.39 × 107
) = 71.4 dB.
For a peak output sine-wave current of 20 mA,
the peak output voltage will be 20 mA × 500
= 10 V. Correspondingly vi will be a sine wave
with a peak value of 10 V/Av = 10/83.3, or an
rms value of 10/(83.3 ×
√
2) = 0.085 V.
Corresponding output power = (10/
√
2)2
/500
= 0.1 W
1.55

vi
200 k
1 M
1 V

vo
20
100
1vi
vo = 1 V ×
1 M
1 M + 200 k
× 1 ×
100
100 + 20
=
1
1.2
×
100
120
= 0.69 V
Voltage gain =
vo
vs
= 0.69 V/V or −3.2 dB
Current gain =
vo/100
vs/1.2 M
= 0.69 × 1.2 × 104
= 8280 A/A or 78.4 dB
Power gain =
v2
o/100
v2
s /1.2 M
= 5713 W/W
or 10 log 5713 = 37.6 dB
(This takes into account the power dissipated in
the internal resistance of the source.)
1.56 (a) Case S-A-B-L (see figure on next page):
vo
vs
=
vo
vib
×
vib
via
×
via
vs
=

10 ×
100
100 + 1000

×

100 ×
10
10 + 10

×

100
100 + 100

vo
vs
= 22.7 V/V and gain in dB 20 log 22.7 =
27.1 dB
(b) Case S-B-A-L (see figure on next page):
vo
vs
=
vo
via
·
via
vib
·
vib
vs
=

100 ×
100
100 + 10 K

×

10 ×
100 K
100 K + 1 K

×

10 K
10 K + 100 K

vo
vs
= 0.89 V/V and gain in dB is 20 log 0.89 =
−1 dB. Obviously, case a is preferred because it
provides higher voltage gain.
1.57 Each of stages #1, 2, ..., (n − 1) can be
represented by the equivalent circuit:
vo
vs
=
vi1
vs
×
vi2
vi1
×
vi3
vi2
× · · · ×
vin
vi(n−1)
×
vo
vin
where

Chapter 1–17
This figure belongs to 1.56, part (a).
This figure belongs to 1.56, part (b).
vi1
vs
=
10 k
10 k + 10 k
= 0.5 V/V
vo
vin
= 10 ×
200
1 k + 200
= 1.67 V/V
vi2
vi1
=
vi3
vi2
= · · · =
vin
vi(n−1)
= 10×
10 k
10 k + 10 k
= 9.09 V/V
Thus,
vo
vs
= 0.5 × (9.09)n−1
× 1.67 = 0.833 × (9.09)n−1
For vs = 5 mV and vo = 3 V, the gain
vo
vs
must
be ≥ 600, thus
0.833 × (9.09)n−1
≥ 600
⇒ n = 4
Thus four amplifier stages are needed, resulting in
vo
vs
= 0.833 × (9.09)3
= 625.7 V/V
and correspondingly
vo = 625.7 × 5 mV = 3.13 V
This figure belongs to 1.57.

Rs 10 k
200
Ri1 10 k Ron 1 k
5 mV
vs
#1 #2 #n
vi1

vi2

vin

vo

RL
10 k
1 k
10 k
#m
Ri(m 1)
vi(m 1)

vim

vi(m 1)
10vim

vim

1.58 Deliver 0.5 W to a 100- load.
Source is 30 mV rms with 0.5-M source
resistance. Choose from these three amplifier
types:
A B C
Ri 1 M
Av 10 V/ V
Ro 10 k
Ri 10 k
Av 100 V/ V
Ro 1 k
Ri 10 k
Av 1 V/ V
Ro 20
Choose order to eliminate loading on input and
output:
A, first, to minimize loading on 0.5-M source
B, second, to boost gain
C, third, to minimize loading at 100- output.
We first attempt a cascade of the three stages in
the order A, B, C (see figure above), and obtain
vi1
vs
=
1 M
1 M + 0.5 M
=
1
1.5

Chapter 1–18
⇒ vi1 = 30 ×
1
1.5
= 20 mV
vi2
vi1
= 10 ×
10 k
10 k + 10 k
= 5
⇒ vi2 = 20 × 5 = 100 mV
vi3
vi2
= 100 ×
10 k
10 k + 1 k
= 90.9
⇒ vi3 = 100 mV × 90.9 = 9.09 V
vo
vi3
= 1 ×
100
100 + 20
= 0.833
⇒ vo = 9.09 × 0.833 = 7.6 V
Po =
v2
orms
RL
=
7.62
100
= 0.57 W
which exceeds the required 0.5 W. Also, the
signal throughout the amplifier chain never drops
below 20 mV (which is greater than the required
minimum of 10 mV).
1.59
(a) Current gain =
io
ii
= Ais
Ro
Ro + RL
= 100
10
11
= 90.9 A/A = 39.2 dB
(b) Voltage gain =
vo
vs
=
ioRL
ii(Rs + Ri)
=
io
ii
RL
Rs + Ri
= 90.9 ×
1
10 + 0.1
= 9 V/V =19.1 dB
(c) Power gain = Ap =
voio
vsii
= 9 × 90.9
= 818 W/W = 29.1 dB
1.60
(a)
vo = 10 mV ×
20
20 + 100
× 1000 ×
100
100 + 100
= 833 mV
(b)
vo
vs
=
833 mV
10 mV
= 83.3 V/V
(c)
vo
vi
= 1000 ×
100
100 + 100
= 500 V/V
(d)
Rs
Rp Ri
...
Connect a resistance RP in parallel with the input
and select its value from
(Rp Ri)
(Rp Ri) + Rs
=
1
2
Ri
Ri + Rs
⇒ 1 +
Rs
Rp Ri
= 12 ⇒ Rp Ri =
RS
11
=
100
11
⇒
1
Rp
+
1
Ri
=
11
100
Rp =
1
0.11 − 0.05
= 16.7 k
1.61 To obtain the weighted sum of v1 and v2
vo = 10v1 + 20v2
we use two transconductance amplifiers and sum
their output currents. Each transconductance
amplifier has the following equivalent circuit:
Ri
10 k
Ro
Gmvi
Gm 20 mA/V
10 k
vi

Consider first the path for the signal requiring
higher gain, namely v2. See figure at top of next
page.
The parallel connection of the two amplifiers at
the output and the connection of RL means that
the total resistance at the output is
10 k 10 k 10 k =
10
3
k.

Chapter 1–19
Thus the component of vo due to v2 will be
vo2 = v2
10
10 + 10
× Gm2 ×
10
3
= v2 × 0.5 × 20 ×
10
3
= 33.3v2
To reduce the gain seen by v2 from 33.3 to 20, we
connect a resistance Rp in parallel with RL,

10
3
Rp

= 2 k ⇒ Rp = 5 k
We next consider the path for v1. Since v1 must
see a gain factor of only 10, which is half that
seen by v2, we have to reduce the fraction of v1
that appears at the input of its transconductance
amplifier to half that that appears at the input of
the v2 transconductance amplifier. We just saw
that 0.5 v2 appears at the input of the v2
transconductance amplifier. Thus, for the v1
transconductance amplifier, we want 0.25v1 to
appear at the input. This can be achieved by
shunting the input of the v1 transconductance
amplifier by a resistance Rp1 as in the figure in
the next column.
v1
Rs1 10 k
vi1

Rp1 Ri1
10 k

The value of Rp1 can be found from
(Rp1 Ri1)
(Rp1 Ri1) + Rs1
= 0.25
Thus,
1 +
Rs1
(Rp1 Ri1)
= 4
⇒ Rp1 Ri1 =
Rs1
3
=
10
3
Rp1 10 =
10
3
⇒ Rp1 = 5 k
The final circuit will be as follows:

Chapter 1–20
1.62
R

v1
gmv1
gm 100 mA/V
R 5 k
gmv2

v2
io
vo
io = gmv1 − gmv2
vo = ioRL = gmR(v1 − v2)
v1 = v2 = 1 V ∴ vo = 0 V
v1 = 1.01 V
v2 = 0.99 V
∴ vo = 100 × 5 × 0.02 = 10 V
1.63 (a)

vi gmvi
Ri
i1
i2
ix
vx

ix = i1 + i2
i1 = vi/Ri
i2 = gmvi
vi = vx
⎫
⎪
⎪
⎪
⎪
⎪
⎪
⎬
⎪
⎪
⎪
⎪
⎪
⎪
⎭
ix = vx/Ri + gmvx
ix = vx

1
Ri
+ gm

vx
ix
=
1
1/Ri + gm
=
Ri
1 + gmRi
= Rin
(b)

vi

vo
vs
vs
Rs Rin
gmvi
Rin
Ri
2
When driven by a source with source resistance
Rin as shown in the figure above,
vi =
Rin
Rs + Rin
× vs =
Rin
Rin + Rin
× vs = 0.5 × vs
Thus,
vo
vs
= 0.5
vo
vi
1.64 Voltage amplifier:
vi vo
Ri
Rs
Ro
1 to 10 k
RL
1 k to
10 k
Avo vi

io
vs
For Rs varying in the range 1 k to 10 k and
vo limited to 10%, select Ri to be sufficiently
large:
Ri ≥ 10 Rsmax
Ri = 10 × 10 k = 100 k = 1 × 105

For RL varying in the range 1 k to 10 k, the
load voltage variation limited to 10%, select Ro
sufficiently low:
Ro ≤
RLmin
10
Ro =
1 k
10
= 100 = 1 × 102

Now find Avo:
vomin = 10 mV ×
Ri
Ri + Rsmax
× Avo
RLmin
Ro + RLmin
1 = 10 × 10−3
×
100 k
100 k + 10 k
× Avo ×
1 k
100 + 1 k
⇒ Avo = 121 V/V
vo
Ro
Avovi

vi Ri

Chapter 1–21
Values for the voltage amplifier equivalent circuit
are
Ri = 1 × 105
, Avo = 121 V/V, and
Ro = 1 × 102

1.65 Transresistance amplifier:
To limit vo to 10% corresponding to Rs varying
in the range 1 k to 10 k, we select Ri
sufficiently low;
Ri ≤
Rsmin
10
Thus, Ri = 100 = 1 × 102

To limit vo to 10% while RLvaries over the
range 1 k to 10 k, we select Ro sufficiently
low;
Ro ≤
RLmin
10
Thus, Ro = 100 = 1 × 102

Now, for is = 10 µA,
10 µA
1 to
10 k
1 to
10 k

R i
i
i
R
R
R
R
v
vomin = 10−5 Rsmin
Rsmin + Ri
Rm
RLmin
RLmin + Ro
1 = 10−5 1000
1000 + 100
Rm
1000
1000 + 100
⇒ Rm = 1.21 × 105

= 121 k
1.66
The node equation at E yields the current through
RE as (βib + ib) = (β + 1)ib. The voltage vc can
be found in terms of ib as
vc = −βibRL (1)
The voltage vb can be related to ib by writing for
the input loop:
vb = ibrπ + (β + 1)ibRE
Thus,
vb = [rπ + (β + 1)RE]ib (2)
Dividing Eq. (1) by Eq. (2) yields
vc
vb
= −
βRL
rπ + (β + 1)RE
Q.E.D
The voltage ve is related to ib by
ve = (β + 1)ibRE
That is,
ve = [(β + 1)RE]ib (3)
Dividing Eq. (3) by Eq. (2) yields
ve
vb
=
(β + 1)RE
(β + 1)RE + rπ
Dividing the numerator and denominator by
(β + 1) gives
ve
vb
=
RE
RE + [rπ /(β + 1)]
Q.E.D
1.67 Ro =
Open-circuit output voltage
Short-circuit output current
=
10 V
5 mA
= 2 k
vo = 10 ×
2
2 + 2
= 5 V

Chapter 1–22
Av =
vo
vi
=
10(2/4)
1 × 10−6
× (200 5) × 103
1025 V/V or 60.2 dB
Ai =
io
ii
=
vo/RL
vi/Ri
=
vo
vi
Ri
RL
= 1025 ×
5 k
2 k
= 2562.5 A/A or 62.8 dB
The overall current gain can be found as
io
is
=
vo/RL
1 µA
=
5 V/2 k
1 µA
=
2.5 mA
1 µA
= 2500 A/A
or 68 dB.
Ap =
v2
o/RL
i2
i Ri
=
52
/(2 × 103
)

10−6
×
200
200 + 5
2
5 × 103
= 2.63 × 106
W/W or 64.2 dB
1.68
I1
V1
g12I2
1/g11

g21V1
g22

V2
I2

I1
V2
I2
AvoV1
V1 Ri
Ro

The correspondences between the current and
voltage variables are indicated by comparing the
two equivalent-circuit models above. At the
outset we observe that at the input side of the
g-parameter model, we have the controlled
current source g12I2. This has no correspondence
in the equivalent-circuit model of Fig. 1.16(a). It
represents internal feedback, internal to the
amplifier circuit. In developing the model of
Fig. 1.16(a), we assumed that the amplifier is
unilateral (i.e., has no internal feedback, or that
the input side does not know what happens at the
output side). If we neglect this internal feedback,
that is, assume g12 = 0, we can compare the two
models and thus obtain:
Ri = 1/g11
Avo = g21
Ro = g22
1.69

Vi

Rs
Ri
Vs Ci
Vi
Vs
=
Ri
1
sCi
Ri +
1
sCi
Rs +
⎛
⎜
⎜
⎝
Ri
1
sCi
Ri +
1
sCi
⎞
⎟
⎟
⎠
=
Ri
1 + sCiRi
Rs +

Ri
1 + sCiRi

=
Ri
Rs + sCiRiRs + Ri
Vi
Vs
=
Ri
(Rs + Ri) + sCiRiRs
=
Ri
(Rs + Ri)
1 + s

CiRiRs
Rs + Ri

which is a low-pass STC function with
K =
Ri
Rs + Ri
and ω0 = 1/[Ci(Ri Rs)].
For Rs = 10 k, Ri = 40 k, and Ci = 5 pF,
ω0 =
1
5 × 10−12 × (40 10) × 103
= 25 Mrad/s
f0 =
25
2π
= 4 MHz
The dc gain is
K =
40
10 + 40
= 0.8V/V

Chapter 1–23
1.70 Using the voltage-divider rule.

Vo
Vi
R1
R2
C

T(s) =
Vo
Vi
=
R2
R2 + R1 +
1
sC
T(s) =

R2
R1 + R2

⎛
⎜
⎜
⎝
s
s +
1
C(R1 + R2)
⎞
⎟
⎟
⎠
which from Table 1.2 is of the high-pass type
with
K =
R2
R1 + R2
ω0 =
1
C(R1 + R2)
As a further verification that this is a high-pass
network and T(s) is a high-pass transfer function,
see that as s ⇒ 0, T(s) ⇒ 0; and as s → ∞,
T(s) = R2/(R1 + R2). Also, from the circuit,
observe as s → ∞, (1/sC) → 0 and
Vo/Vi = R2/(R1 + R2). Now, for R1 = 10 k,
R2 = 40 k and C = 1 µF,
f0 =
ω0
2π
=
1
2π × 1 × 10−6
(10 + 40) × 103
= 3.18 Hz
|T(jω0)| =
K
√
2
=
40
10 + 40
1
√
2
= 0.57 V/V
1.71 The given measured data indicate that this
amplifier has a low-pass STC frequency response
with a low-frequency gain of 40 dB, and a 3-dB
frequency of 104
Hz. From our knowledge of the
Bode plots for low-pass STC networks [Fig.
1.23(a)], we can complete the table entries and
sketch the amplifier frequency response.
f (Hz)
20 dB/decade
3 dB
10
0
10
20
30
37
40
T , dB
102
103
104
105
106
f(Hz) |T|(dB) ∠T(◦
)
0 40 0
100 40 0
1000 40 0
104
37 −45◦
105
20 −90◦
106
0 −90◦
1.72 Rs = 100 k, since the 3-dB frequency is
reduced by a very high factor (from 5 MHz to
100 kHz) C2 must be much larger than C1. Thus,
neglecting C1 we find C2 from
100 kHz
1
2πC2Rs
Rs
C2
Shunt
capacitor
Initial
capacitor
C1

Thevenin
equivalent at
node A Node A
=
1
2πC2 × 105
⇒ C2 = 15.9 pF
If the original 3-dB frequency (5 MHz) is
attributable to C1, then
5 MHz =
1
2πC1Rs
⇒ C1 =
1
2π × 5 × 106
× 105
= 0.32 pF
1.73 For the input circuit, the corner frequency
f01 is found from
f01 =
1
2πC1(Rs + Ri)
For f01 ≤ 100 Hz,
1
2πC1(10 + 100) × 103
≤ 100

Chapter 1–24

V V
R
100 k 100V
R
10 k C
V
R
1 k
R
1 k C

⇒ C1 ≥
1
2π × 110 × 103
× 102
= 1.4 × 10−8
F
Thus we select C1 = 1 × 10−7
F = 0.1 µF. The
actual corner frequency resulting from C1 will be
f01 =
1
2π × 10−7
× 110 × 103
= 14.5 Hz
For the output circuit,
f02 =
1
2πC2(Ro + RL)
For f02 ≤ 100 Hz,
1
2πC2(1 + 1) × 103
≤ 100
⇒ C2 ≥
1
2π × 2 × 103
× 102
= 0.8 × 10−6
Select C2 = 1 × 10−6
= 1 µF.
This will place the corner frequency at
f02 =
1
2π × 10−6
× 2 × 103
= 80 Hz
T(s) = 100
s

1 +
s
2πf01

1 +
s
2πf02

1.74 Circuits of Fig. 1.22:

Vi Vo
R
C
(a) (b)

Vi Vo
C
R

For (a) Vo = Vi

1/sC
1/sC + R

Vo
Vi
=
1
1 + sCR
which is of the form shown for the low-pass
function in Table 1.2 with K = 1 and ω0 = 1/RC.
For (b) Vo = Vi
⎛
⎜
⎝
R
R +
1
sC
⎞
⎟
⎠
Vo
Vi
=
sRC
1 + sCR
Vo
Vi
=
s
s +
1
RC
which is of the form shown in Table 1.2 for the
high-pass function, with K = 1 and ω0 = 1/RC.
1.75 Using the voltage divider rule,
RL
Rs
C
Vl
Vs

Vl
Vs
=
RL
RL + Rs +
1
sC
=
RL
RL + Rs
s
s +
1
C(RL + Rs)
which is of the high-pass STC type (see Table
1.2) with
K =
RL
RL + Rs
ω0 =
1
C(RL + Rs)
For f0 ≤ 100 Hz
1
2πC(RL + Rs)
≤ 100
⇒ C ≥
1
2π × 100(20 + 5) × 103
Thus, the smallest value of C that will do the job
is C = 0.064 µF or 64 nF.
1.76 From our knowledge of the Bode plots of
STC low-pass and high-pass networks, we see
that this amplifier has a midband gain of 40 dB, a
low-frequency response of the high-pass STC
type with f3dB = 102
Hz, and a high-frequency

Chapter 1–25
response of the low-pass STC type with
f3dB = 106
Hz. We thus can sketch the amplifier
frequency response and complete the table entries
as follows.
40 dB
3 dB
3 dB
1
40
30
20
10
0
10
20 dB/decade
20 dB/decade
3-dB Bandwidth
10 10 10 10 10 10 10
f f
f
(Hz)
T , dB
f(Hz) 1 10 102
103
104
105
106
107
108
|T|(dB) 0 20 37 40 40 40 37 20 0
1.77 Since the overall transfer function is that of
three identical STC LP circuits in cascade (but
with no loading effects, since the buffer
amplifiers have infinite input and zero output
resistances) the overall gain will drop by 3 dB
below the value at dc at the frequency for which
the gain of each STC circuit is 1 dB down. This
frequency is found as follows: The transfer
function of each STC circuit is
T(s) =
1
1 +
s
ω0
where
ω0 = 1/CR
Thus,
|T(jω)| =
1

1 +

ω
ω0
2
20 log
1

1 +

ω1 dB
ω0
2
= −1
⇒ 1 +

ω1 dB
ω0
2
= 100,1
ω1dB = 0.51ω0
ω1dB = 0.51/CR
1.78 Since when C is connected to node A the
3-dB frequency is reduced by a large factor, the
value of C must be much larger than whatever
parasitic capacitance originally existed at node A
(i.e., between A and ground). Furthermore, it
must be that C is now the dominant determinant
of the amplifier 3-dB frequency (i.e., it is
dominating over whatever may be happening at
node B or anywhere else in the amplifier). Thus,
we can write
200 kHz =
1
2πC(Ro1 Ri2)
⇒ (Ro1 Ri2) =
1
2π × 200 × 103
× 1 × 10−9
= 0.8 k
C
vo1 Ri2
Ro1

A
1 nF
# 1 # 2 # 3
B
C
Now Ri2 = 100 k.
Thus Ro1 0.8 k
Similarly, for node B,
20 kHz =
1
2πC(Ro2 Ri3)
⇒ Ro2 Ri3 =
1
2π × 20 × 103
× 1 × 10−9
= 7.96 k
Ro2 = 8.65 k
The designer should connect a capacitor of value
Cp to node B where Cp can be found from

Chapter 1–26
10 kHz =
1
2πCp(Ro2 Ri3)
⇒ Cp =
1
2π × 10 × 103
× 7.96 × 103
= 2 nF
Note that if she chooses to use node A, she would
need to connect a capacitor 10 times larger!
1.79 The LP factor 1/(1 + jf/105
) results in a
Bode plot like that in Fig. 1.23(a) with the
3-dB frequency f0 = 105
Hz. The high-pass factor
1/(1 + 102
/jf) results in a Bode plot like that in
Fig. 1.24(a) with the 3-dB frequency
f0 = 102
Hz.
The Bode plot for the overall transfer function
can be obtained by summing the dB values of the
two individual plots and then shifting the
resulting plot vertically by 60 dB (corresponding
to the factor 1000 in the numerator). The result is
as follows:
60
50
40
30
20
10
0
1 10 102 103 104 105 106 107 108 f (Hz)
(Hz)
f = 10 102
103
104
105
106
107
108
(dB)
–
~ 40 60
57 57
60 60 60 40 20 0
20 dB/decade
20 dB/decade
20 dB/decade
Av (dB)
Av
Bandwidth = 105
− 102
= 99,900 Hz
1.80 Ti(s) =
Vi(s)
Vs(s)
=
1/sC1
1/sC1 + R1
=
1
sC1R1 + 1
LP with a 3-dB frequency
f0i =
1
2πC1R1
=
1
2π10−11
105
= 159 kHz
For To(s), the following equivalent circuit can be
used:

GmR2Vi
Vo R3
R2
C2

To(s) =
Vo
Vi
= −GmR2
R3
R2 + R3 + 1/sC2
= −Gm(R2 R3)
s
s +
1
C2(R2 + R3)
which is an HP, with
3-dB frequency =
1
2πC2(R2 + R3)
=
1
2π100 × 10−9
× 110 × 103
= 14.5 Hz
∴ T(s) = Ti(s)To(s)
=
1
1 +
s
2π × 159 × 103
× − 909.1 ×
s
s + (2π × 14.5)
20 dB/decade
20 dB/decade
14.5 Hz 159 kHz
59.2 dB
Bandwidth = 159 kHz – 14.5 Hz 159 kHz
1.81 Vi = Vs
Ri
Rs + Ri
(1)
(a) To satisfy constraint (1), namely,
Vi ≥

1 −
x
100

Vs
we substitute in Eq. (1) to obtain
Ri
Rs + Ri
≥ 1 −
x
100
(2)
Thus
Rs + Ri
Ri
≤
1
1 −
x
100
Rs
Ri
≤
1
1 −
x
100
− 1 =
x
100
1 −
x
100
which can be expressed as

Chapter 1–27
Ri
Rs
≥
1 −
x
100
x
100
resulting in
Vi
Vo
Ri Ro RL
CL
Vs
Rs
Gm Vi

Ri ≥ Rs

100
x
− 1

(3)
(b) The 3-dB frequency is determined by the
parallel RC circuit at the output
f0 =
1
2π
ω0 =
1
2π
1
CL(RL Ro)
Thus,
f0 =
1
2πCL

1
RL
+
1
R0

To obtain a value for f0 greater than a specified
value f3dB we select Ro so that
1
2πCL

1
RL
+
1
Ro

≥ f3dB
1
RL
+
1
Ro
≥ 2πCL f3dB
1
Ro
≥ 2πCL f3dB −
1
RL
Ro ≤
1
2πf3dBCL −
1
RL
(4)
(c) To satisfy constraint (c), we first determine
the dc gain as
dc gain =
Ri
Rs + Ri
Gm(Ro RL)
For the dc gain to be greater than a specified
value A0,
Ri
Rs + Ri
Gm(Ro RL) ≥ A0
The first factor on the left-hand side is (from
constraint (2)) greater or equal to (1 − x/100).
Thus
Gm ≥
A0

1 −
x
100

(Ro RL)
(5)
Substituting Rs = 10 k and x = 10% in (3)
results in
Ri ≥ 10

100
100
− 1

= 90 k
Substituting f3dB = 2 MHz, CL = 20 pF, and
RL = 10 k in Eq. (4) results in
Ro ≤
1
2π × 2 × 106
× 20 × 10−12
−
1
104
= 6.61 k
Substituting A0 = 100, x = 10%, RL = 10 k, and
Ro = 6.61 k, Eq. (5) results in
Gm ≥
100

1 −
10
100

(10 6.61) × 103
= 27.9 mA/V
1.82 Using the voltage divider rule, we obtain
Vo
Vi
=
Z2
Z1 + Z2
where
Z1 = R1
1
sC1
and Z2 = R2
1
sC2
It is obviously more convenient to work in terms
of admittances. Therefore we express Vo/Vi in the
alternate form
Vo
Vi
=
Y1
Y1 + Y2
and substitute Y1 = (1/R1) + sC1 and
Y2 = (1/R2) + sC2 to obtain
Vo
Vi
=
1
R1
+ sC1
1
R1
+
1
R2
+ s(C1 + C2)
=
C1
C1 + C2
s +
1
C1R1
s +
1
(C1 + C2)

1
R1
+
1
R2

This transfer function will be independent of
frequency (s) if the second factor reduces to unity.
This in turn will happen if
1
C1R1
=
1
C1 + C2

1
R1
+
1
R2

which can be simplified as follows:
C1 + C2
C1
= R1

1
R1
+
1
R2

(1)

Chapter 1–28
1 +
C2
C1
= 1 +
R1
R2
or
C1R1 = C2R2
When this condition applies, the attenuator is said
to be compensated, and its transfer function is
given by
Vo
Vi
=
C1
C1 + C2
which, using Eq. (1), can be expressed in the
alternate form
Vo
Vi
=
1
1 +
R1
R2
=
R2
R1 + R2
Thus when the attenuator is compensated
(C1R1 = C2R2), its transmission can be
determined either by its two resistors R1, R2 or by
its two capacitors. C1, C2, and the transmission is
not a function of frequency.
1.83 The HP STC circuit whose response
determines the frequency response of the
amplifier in the low-frequency range has a phase
angle of 5.7◦
at f = 100 Hz. Using the equation
for ∠T(jω) from Table 1.2, we obtain
tan−1 f0
100
= 5.7◦
⇒ f0 = 10 Hz
The LP STC circuit whose response determines
the amplifier response at the high-frequency end
has a phase angle of −5.7◦
at f = 1 kHz. Using
the relationship for ∠T(jω) given in Table 1.2,
we obtain for the LP STC circuit.
−tan−1 103
f0
= −5.7◦
⇒ f0 10 kHz
At f = 100 Hz, the drop in gain is due to the HP
STC network, and thus its value is
20 log
1

1 +

10
100
2
= −0.04 dB
Similarly, at the drop in gain f = 1 kHz is caused
by the LP STC network. The drop in gain is
20 log
1

1 +

1000
10, 000
2
= −0.04 dB
The gain drops by 3 dB at the corner frequencies
of the two STC networks, that is, at f = 10 Hz and
f = 10 kHz.
1.84 Use the expression in Eq. (1.26), with
B = 7.3 × 1015
cm−3
K−3/2
;
k = 8.62 × 10−5
eV/K; and Eg = 1.12 V
we have
T = −55◦
C = 218 K:
ni = 2.68 × 106
cm−3
;
N
ni
= 1.9 × 1016
That is, one out of every 1.9 × 1016
silicon atoms
is ionized at this temperature.
T = 0◦
C = 273 K:
ni = 1.52 × 109
cm−3
;
N
ni
= 3.3 × 1013
T = 20◦
C = 293 K:
ni = 8.60 × 109
cm−3
;
N
ni
= 5.8 × 1012
T = 75◦
C = 348 K:
ni = 3.70 × 1011
cm−3
;
N
ni
= 1.4 × 1011
T = 125◦
C = 398 K:
ni = 4.72 × 1012
cm−3
;
N
ni
= 1.1 × 1010
1.85 Use Eq. (1.26) to find ni,
ni = BT3/2
e−Eg/2kT
Substituting the values given in the problem,
ni = 3.56 × 1014
(300)3/2
e−1.42/(2×8.62×10−5×300)
= 2.2 × 106
carriers/cm3
1.86 The concentration of free carriers (both
electrons and holes) in intrinsic silicon is found in
Example 3.1 to be 1.5 × 1010
carriers/cm3
at
room temperature. Multiplying this by the
volume of the wafer gives
1.5 × 1010
×
π × 152
× 0.3
4
=
7.95 × 1010
free electrons

Chapter 1–29
1.87 Since NA ni, we can write
pp ≈ NA = 5 × 1018
cm−3
Using Eq. (1.27), we have
np =
n2
i
pp
= 45 cm−3
1.88 Hole concentration in intrinsic Si = ni
ni = BT3/2
e−Eg/2kT
= 7.3 × 1015
(300)3/2
e−1.12/(2×8.62×10−5×300)
= 1.5 × 1010
holes/cm3
In phosphorus-doped Si, hole concentration drops
below the intrinsic level by a factor of 108
.
∴ Hole concentration in P-doped Si is
pn =
1.5 × 1010
108
= 1.5 × 102
cm−3
Now, nn ND and pnnn = n2
i
nn = n2
i /pn =
(1.5 × 1010
)
2
1.5 × 102
= 1.5 × 1018
cm−3
ND = nn = 1.5 × 1018
atoms/cm3
1.89 T = 27◦
C = 273 + 27 = 300 K
At 300 K, ni = 1.5 × 1010
/cm3
Phosphorus-doped Si:
nn ND = 1017
/cm3
pn =
n2
i
ND
=
(1.5 × 1010
)
2
1017
= 2.25 × 103
/cm3
Hole concentration = pn = 2.25 × 103
/cm3
T = 125◦
C = 273 + 125 = 398 K
At 398 K, ni = BT3/2
e−Eg/2kT
= 7.3 × 1015
× (398)3/2
e−1.12/(2×8.62×10−5×398)
= 4.72 × 1012
/cm3
pn =
n2
i
ND
= 2.23 × 108
/cm3
At 398 K, hole concentration is
pn = 2.23 × 108
/cm3
1.90 (a) The resistivity of silicon is given by
Eq. (1.41).
For intrinsic silicon,
p = n = ni = 1.5 × 1010
cm−3
Using μn = 1350 cm2
/V · s and
μp = 480 cm2
/V · s, and q = 1.6 × 10−19
C we
have
ρ = 2.28 × 105
-cm.
Using R = ρ ·
L
A
with L = 0.001 cm and
A = 3 × 10−8
cm2
, we have
R = 7.6 × 109
.
(b) nn ≈ ND = 5 × 1016
cm−3
;
pn =
n2
i
nn
= 4.5 × 103
cm−3
/V · s and
μp = 400 cm2
/V · s, we have
ρ = 0.10 -cm; R = 3.33 k.
(c) nn ≈ ND = 5 × 1018
cm−3
;
pn =
n2
i
nn
= 45 cm−3
/V · s and
μp = 400 cm2
/V · s, we have
ρ = 1.0 × 10−3
-cm; R = 33.3 .
As expected, since ND is increased by 100, the
resistivity decreases by the same factor.
(d) pp ≈ NA = 5 × 1016
cm−3
; np =
n2
i
nn
= 4.5 × 103
cm−3
ρ = 0.31 -cm; R = 10.42 k
(e) Since ρ is given to be 2.8 × 10−6
-cm, we
directly calculate R = 9.33 × 10−2
.

Chapter 1–30
1.91 Cross-sectional area of Si bar
= 5 × 4 = 20 µm2
Since 1 µm = 10−4
cm, we get
= 20 × 10−8
cm2
Current I = Aq(pμp + nμn)E
= 20 × 10−8
× 1.6 × 10−19
(1016
× 500 + 104
× 1200) ×
1 V
10 × 10−4
= 160 µA
1.92 Use Eq. (1.45):
Dn
μn
=
Dp
μp
= VT
Dn = μnVT and Dp = μpVT where
VT = 25.9 mV.
Doping
Concentration μn μp Dn Dp
(carriers/cm3
) cm2
/V · s cm2
/V · s cm2
/s cm2
/s
Intrinsic 1350 480 35 12.4
1016
1200 400 31 10.4
1017
750 260 19.4 6.7
1018
380 160 9.8 4.1
1.93 Electric field:
E =
3 V
10 µm
=
3 V
10 × 10−6
m
=
3 V
10 × 10−4
cm
= 3000 V/cm
3 V
10 µm
νp-drift = μpE = 480 × 3000
= 1.44 × 106
cm/s
νn-drift = μnE = 1350 × 3000
= 4.05 × 106
cm/s
νn
νp
=
4.05 × 106
1.44 × 106
= 2.8125 or
νn = 2.8125 νp
Or, alternatively, it can be shown as
νn
νp
=
μnE
μpE
=
μn
μp
=
1350
480
= 2.8125
1.94 Jdrift = q(nμn + pμp)E
Here n = ND, and since it is n-type silicon, one
can assume p n and ignore the term pμp. Also,
E =
1 V
10 µm
=
1 V
10 × 10−4
cm
= 103
V/cm
Need Jdrift = 2 mA/µm2
= qNDμnE
2 × 10−3
A
10−8
cm2
= 1.6 × 10−19
ND × 1350 × 103
⇒ ND = 9.26 × 1017
/cm3
1.95
pn0 =
n2
i
ND
=
(1.5 × 1010
)
2
1016
= 2.25 × 104
/cm3
From Fig. P1.95,
dp
dx
= −
108
pn0 − pn0
W
−
108
pn0
50 × 10−7
since 1 nm = 10−7
cm
dp
dx
= −
108
× 2.25 × 104
50 × 10−7
= −4.5 × 1017
Hence
Jp = −qDp
dp
dx
= −1.6 × 10−19
× 12 × (−4.5 × 1017
)
= 0.864 A/cm2
1.96 From Table 1.3,
VT at 300 K = 25.9 mV
Using Eq. (1.46), built-in voltage V0 is obtained:

Chapter 1–31
V0 = VT ln

NAND
n2
i

= 25.9 × 10−3
×
ln

1017
× 1016

1.5 × 1010
2

= 0.754 V

xp xn
W
Holes Electrons
Depletion width
W =

2 s
q

1
NA
+
1
ND

V0 ← Eq. (1.50)
W =

2 × 1.04 × 10−12
1.6 × 10−19

1
1017
+
1
1016

× 0.754
= 0.328 × 10−4
cm = 0.328 µm
Use Eqs. (1.51) and (1.52) to find xn and xp:
xn = W
NA
NA + ND
= 0.328 ×
1017
1017
+ 1016
= 0.298 µm
xp = W
ND
NA + ND
= 0.328 ×
1016
1017
+ 1016
= 0.03 µm
Use Eq. (1.53) to calculate charge stored on either
side:
QJ = Aq

NAND
NA + ND

W, where junction area
= 100 µm2
= 100 × 10−8
cm2
QJ = 100 × 10−8
× 1.6 × 10−19

1017
· 1016
1017
+ 1016

× 0.328 × 10−4
Hence, QJ = 4.8 × 10−14
C
1.97 Equation (1.49):
W =

2 s
q

1
NA
+
1
ND

V0,
Since NA ND, we have
W

2 s
q
1
ND
V0
V0 =
qND
2 s
·W2
Here W = 0.2 µm = 0.2 × 10−4
cm
So V0 =
1.6 × 10−19
× 1016
×

0.2 × 10−4
2
2 × 1.04 × 10−12
= 0.31 V
QJ = Aq

NAND
NA + ND

W ∼
= AqNDW
since NA ND, we have QJ = 3.2 fC.
1.98 Using Eq. (1.46) and NA = ND
= 5 × 1016
cm−3
and ni = 1.5 × 1010
cm−3
,
we have V0 = 778 mV.
Using Eq. (1.50) and
s = 11.7 × 8.854 × 10−14
F/cm, we have
W = 2 × 10−5
cm = 0.2 µm. The extension of
the depletion width into the n and p regions is
given in Eqs. (1.51) and (1.52), respectively:
xn = W·
NA
NA + ND
= 0.1 µm
xp = W·
ND
NA + ND
= 0.1 µm
Since both regions are doped equally, the
depletion region is symmetric.
Using Eq. (1.53) and
A = 20 µm2
= 20 × 10−8
cm2
, the charge
magnitude on each side of the junction is
QJ = 1.6 × 10−14
C.
1.99 Using Eq. (1.47) or (1.48), we have charge
stored: QJ = qAxnND.
Here xn = 0.1 µm = 0.1 × 10−4
cm

Chapter 1–32
A = 10 µm × 10 µm = 10 × 10−4
cm
× 10 × 10−4
cm
= 100 × 10−8
cm2
So,
QJ = 1.6×10−19
×100×10−8
×0.1×10−4
×1018
= 1.6 pC
1.100 V0 = VT ln

NAND
n2
i

If NA or ND is increased by a factor of 10, then
new value of V0 will be
V0 = VT ln

10 NAND
n2
i

The change in the value of V0 is
VT ln10 = 59.6 mV.
1.101 This is a one-sided junction, with the
depletion layer extending almost entirely into the
more lightly doped (n-type) material. A thin
space-charge region in the p-type region stores
the same total charge with higher much higher
charge density.
Charge
density
n-type
p-type
qNA
Xn
X
qND
Increasing ND by 4× will increase the charge
density on the n − type side of the junction by 4×.
We see from Eq. (1.45) that since NA ND ni
(i.e. at least a couple of orders of magnitude) a
4× increase in ND will have comparatively little
effect on V0. Thus, we can assume V0 is
unchanged in Eq. (1.49), and the junction width
(residing almost entirely in the n-type material) is
W ≈

2 s
q
1
NA
V0 ∝
1
√
ND
A 4× increase in ND therefore results in a 2×
decrease in the width of the depletion region on
the n-type side of the junction, as illustrated
below.
Charge
density
n-type
p-type
qNA
X
4qND
Xn
2
1
1.102 The area under the triangle is equal to the
built-in voltage.
V0 =
1
2
EmaxW
Using Eq. (1.49):
V0 =
Emax
2

2 s
q

1
NA
+
1
ND

×

V0
⇒ Emax =

2qNAND
s(NA + ND)
V0
Substituting Eq. (1.45) for V0,
Emax =

2kTNAND
s(NA + ND)
ln

NAND
n2
i

Finally, we can substitute for ni using Eq. (1.26)
Emax =

2kTNAND
s(NA + ND)

ln(NAND) − 2 ln B − 3 ln T +
Eg
kT

1.103 Using Eq. (1.46) with NA = 1017
cm−3
,
ND = 1016
cm−3
, and ni = 1.5 × 1010
, we have
V0 = 754 mV
Using Eq. (1.55) with VR = 5 V, we have
W = 0.907 µm.
Using Eq. (1.56) with A = 1 × 10−6
cm2
, we
have QJ = 13.2 × 10−14
C.
1.104 Equation (1.65):
IS = Aqn2
i

Dp
LpND
+
Dn
LnNA


Chapter 1–33
A = 100 µm2
= 100 × 10−8
cm2
IS = 100 × 10−8
× 1.6 × 10−19
×

1.5 × 1010
2

10
5 × 10−4
× 1016
+
18
10 × 10−4
× 1017

= 7.85 × 10−17
A
I ∼
= ISeV/VT
= 7.85 × 10−17
× e750/25.9
∼
= 0.3 mA
1.105 Equation (1.54):
W =

2 s
q

1
NA
+
1
ND

(V0 + VR)
=

2 s
q

1
NA
+
1
ND

V0

1 +
VR
V0

= W0

1 +
VR
V0
Equation (1.55):
Qj = A

2 sq

NA ND
NA + ND

· (V0 + VR)
= A

2 sq

NA ND
NA + ND

V0 ·

1 +
VR
V0

= QJ0

1 +
VR
V0
1.106 Equation (1.62):
I = Aqn2
i

Dp
LpND
+
Dn
LnNA

eV/VT
− 1

Here Ip = Aqn2
i
Dp
LpND

eV/VT
− 1

In = Aqn2
i
Dn
LnNA

eV/VT
− 1

Ip
In
=
Dp
Dn
·
Ln
Lp
·
NA
ND
=
10
20
×
10
5
×
1018
1016
Ip
In
= 100
Now I = Ip + In = 100 In + In ≡ 1 mA
In =
1
101
mA = 0.0099 mA
Ip = 1 − In = 0.9901 mA
1.107 ni = BT3/2
e−Eg/2kT
At 300 K,
ni = 7.3 × 1015
× (300)
3/2
×e−1.12/(2×8.62×10−5×300)
= 1.4939 × 1010
/cm2
n2
i (at 300 K) = 2.232 × 1020
At 305 K,
ni = 7.3 × 1015
× (305)
3/2
× e−1.12/(2×8.62×10−5×305)
= 2.152 × 1010
n2
i (at 305 K) = 4.631 × 1020
so
n2
i (at 305 K)
n2
i (at 300 K)
= 2.152
Thus IS approximately doubles for every 5◦
C rise
in temperature.
1.108 Equation (1.63)
I = Aqn2
i

Dp
LpND
+
Dn
LnNA

eV/VT
− 1

So Ip = Aqn2
i
Dp
LpND

eV/VT
− 1

In = Aqn2
i
Dn
LnNA

eV/VT
− 1

For p+
−n junction NA ND, thus Ip In and
I Ip = Aqn2
i
Dp
LpND

eV/VT
− 1

For this case using Eq. (1.65):
IS Aqn2
i
Dp
LpND
= 104
× 10−8
× 1.6 × 10−19
×

1.5 × 1010
2 10
10 × 10−4
× 1017
= 3.6 × 10−16
A
I = IS

eV/VT
− 1

= 1.0 × 10−3

Chapter 1–34
3.6 × 10−16

eV/(25.9×10−3
) − 1

= 1.0 × 10−3
⇒ V = 0.742 V
1.109 VZ = 12 V
Rated power dissipation of diode = 0.25 W.
If continuous current “I” raises the power
dissipation to half the rated value, then
12 V × I =
1
2
× 0.25 W
I = 10.42 mA
Since breakdown occurs for only half the time,
the breakdown current I can be determined from
I × 12 ×
1
2
= 0.25 W
⇒ I = 41.7 mA
1.110 Equation (1.73), Cj =
Cj0

1 +
VR
V0
m
For VR = 1 V, Cj =
0.4 pF

1 +
1
0.75
1/3
= 0.3 pF
For VR = 10 V, Cj =
0.4 pF

1 +
10
0.75
1/3
= 0.16 pF
1.111 Equation (1.81):
Cd =

τT
VT

I
5 pF =

τT
25.9 × 10−3

× 1 × 10−3
τT = 5 × 10−12
× 25.9
= 129.5 ps
For I = 0.1 mA:
Cd =

τT
VT

× I
=

129.5 × 10−12
25.9 × 10−3

× 0.1 × 10−3
= 0.5 pF
1.112 Equation (1.72):
Cj0 = A

sq
2

NAND
NA + ND

1
V0

V0 = VT ln

NAND
n2
i

= 25.9 × 10−3
× ln

1017
× 1016

1.5 × 1010
2

= 0.754 V
Cj0 = 100 × 10−8

1.04 × 10−12 × 1.6 × 10−19
2

1017 × 1016
1017 + 1016

1
0.754
= 31.6 fF
Cj =
Cj0

1 +
VR
V0
=
31.6 fF

1 +
3
0.754
= 14.16 fF
1.113 Equation (1.66):
α = A

2 sq
NAND
NA + ND
Equation (1.68):
Cj =
α
2
√
V0 + VR
Substitute for α from Eq. (1.66):
Cj =
A

2 sq
NAND
NA + ND
2
√
V0 + VR
×
√
s
√
s
= A s ×
1

2 s
q

NA + ND
NAND

(V0 + VR)
= sA
1

2 s
q

1
NA
+
1
ND

(V0 + VR)
=
sA
W

Chapter 1–35
Widths of p and n regions
Depletion
region
xn
xp 0
Wp
np (x)
pn0
np0
n region
p region
pn, np
pn(xn)
pn(x)
np (xp)
Wn
1.114 (a) See figure at top of page.
(b) The current I = Ip + In.
Find current component Ip:
pn(xn) = pn0eV/VT and pn0 =
n2
i
ND
Ip = AJp = AqDp
dp
dx
dp
dx
=
pn(xn) − pn0
Wn − xn
=
pn0eV/VT − pn0
Wn − xn
= pn0

eV/VT − 1

Wn − xn
=
n2
i
ND

eV/VT − 1

(Wn − xn)
∴ Ip = AqDp
dp
dx
= Aqn2
i
Dp
(Wn − xn)ND
×

eV/VT − 1

Similarly,
In = Aqn2
i
Dn

Wp − xp

NA
×

eV/VT − 1

I = Ip + In
= Aqn2
i
Dp
(Wn − xn) ND
+
Dn

Wp − xp

NA
!
×

eV/VT − 1

The excess change, Qp, can be obtained by
multiplying the area of the shaded triangle of the
pn(x) distribution graph by Aq.
Qp = Aq ×
1
2

pn (xn) − pn0
#
(Wn − xn)
=
1
2
Aq

pn0eV/VT − pn0
#
(Wn − xn)
=
1
2
Aqpn0

eV/VT − 1

(Wn − xn)
=
1
2
Aq
ni
2
ND
(Wn − xn)

eV/VT − 1

=
1
2
(Wn − xn)2
Dp
· Ip
1
2
W2
n
DP
· Ip for Wn xn
(c) For Q Qp, I Ip,
Q
1
2
W2
n
Dp
I
Thus, τT =
1
2
W2
n
Dp
, and
Cd =
dQ
dV
= τT
dI
dV
But I = IS

eV/VT − 1

dI
dV
=
ISeV/VT
VT
I
VT
so Cd
∼
= τT ·
I
VT
.
(d) Cd =
1
2
W2
n
10
1 × 10−3
25.9 × 10−3
= 8 × 10−12
F
Solve for Wn:
Wn = 0.64 µm

Solutions for Problems in Microelectronic Circuits, 8th International Edition – Sedra & Smith

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Solutions for Problems in Microelectronic Circuits, 8th International Edition – Sedra & Smith