Stratix V FPGA Intro Presentation

Stratix V FPGAs: Built for Bandwidth April 2010

Agenda Altera’s device roadmap and family plan Markets and target applications Benefits and solutions Summary

Market Dynamics for High-End Systems Mobile Internet driving bandwidth at 50% annualized growth rate Fixed footprints Existing power ceilings 40G/100G system deployment with 400G on the horizon Communications Demand for Higher Bandwidth in Same Footprint at Same or Lower Power and Cost Worldwide proliferation of HD/1080p Move to digital cinema and 4K2K Fixed power budget Heightened intelligence and defense needs More sensors, higher precision driven to decision points faster Power and uptime critical Higher bandwidth, performance and lower latency Power consumption affects total cost of ownership Cloud computing driving up bandwidth Broadcast Military Computer and Storage

Stratix V FPGA Family on 28-nm Process Stratix V FPGAs are built on TSMC’s high-performance 28-nm HKMG process Optimized for low power Ideal choice for devices used in next-generation, high-bandwidth systems 35% higher performance than alternative process options 30% lower total power versus previous generations Enables fastest and most power-efficient transceivers

Stratix V FPGAs – Built for Bandwidth Highest Bandwidth Hard IP and Flexibility IP Solutions and Ecosystem Highest bandwidth 66 transceivers capable of 12.5 Gbps and 7 x72 800-MHz DDR3 interfaces Devices with 28-Gbps transceivers Unprecedented level of integration Embedded HardCopy Blocks supporting PCI Express Gen3 and 40G/100G Ethernet High-performance, high-precision DSP Enhanced logic fabric with 1,100K LEs, 53 Mb RAM, and 3,680 18x18 multipliers Ultimate flexibility Fine-grain and easy-to-use partial reconfiguration Configuration via PCI Express 50% higher system performance and 30% lower power IP

Stratix V Device Family Variants Stratix V GT variant 28 Gbps for high-performance, ultra-high bandwidth applications Stratix V GX variant Up to 66 transceivers at 12.5 Gbps for high performance, high bandwidth Stratix V GS variant Optimized for high-performance, high-precision DSP applications with transceivers up to 12.5 Gbps Stratix V E variant For highest density, high-performance applications 28-Gbps Transceivers Variable-Precision DSP Block

Stratix V Device Family Plan Note: Subject to change. See the Stratix V handbook for the latest information. Device Interconnect Hard IP Core Fabric Transceivers (12.5G, 28G) GPIO 72-Bit DDR3 x8 PCIe Gen3 40G/100G Ethernet LEs Memory (Mb) 18x18 Multipliers fPLLs Stratix V GT FPGA 5SGT B5 32, 4 597 4 1 Yes 424K 47 640 32 5SGT B7 32, 4 597 4 1 Yes 635K 51 684 32 Stratix V GX FPGA 5SGX A3 36, 0 624 4 1 or 2 Yes 239K 29 400 24 5SGX A4 36, 0 624 4 1 or 2 Yes 311K 33 486 24 5SGX A5 48, 0 840 6 1 or 4 Yes 424K 47 640 32 5SGX A7 48, 0 840 6 1 or 4 Yes 635K 51 684 32 5SGX B5 66, 0 648 4 1 or 4 Yes 403K 41 700 32 5SGX B6 66, 0 648 4 1 or 4 Yes 536K 53 738 32 Stratix V GS FPGA 5SGS B5 27, 0 1,020 7 1 or 2 No 482K 32 3,310 16 5SGS B7 27, 0 1,020 7 1 or 2 No 726K 40 3,680 16 Stratix V E FPGA 5SE B9 - 900 7 - No 968K 33 1,064 32 5SE BA - 900 7 - No 1,087K 43 1,100 32

Stratix V Device Package Plan Notes: Flip-chip ball-grid array (BGA) with 1.0-mm pitch GPIO, LVDS, transceivers Pin migration Note: Subject to change. See the Stratix V handbook for the latest information. Device F780 (29 mm) F1152 (35 mm) F1152 (35 mm) F1517 (40 mm) F1517 (40 mm) F1932 (45 mm) 5SGT B5 597, 149, 36 5SGT B7 597, 149, 36 5SGX A3 270, 68, 24 560, 140, 24 444, 111, 36 624, 156, 36 5SGX A4 270, 68, 24 560, 140, 24 444, 111, 36 624, 156, 36 5SGX A5 560, 140, 24 444, 111, 36 707, 176, 36 597, 149, 48 840, 210, 48 5SGX A7 560, 140, 24 444, 111, 36 707, 176, 36 597, 149, 48 840, 210, 48 5SGX B5 439, 109, 66 648, 162, 66 5SGX B6 439, 109, 66 648, 162, 66 5SGS B5 523, 130, 27 781, 195, 27 1020,255,27 5SGS B7 523, 130, 27 781, 195, 27 1020,255,27

Stratix V Hard IP Variants Stratix V FPGA: PCI Express Stratix V FPGA: 40G/100G PCIe Gen3 Mainstream variant with one hard IP for PCI Express Gen3, Gen2, and Gen1 x8 Stratix V FPGA: Mainstream 40G/100G variant with hard PCS IP for 40G/100G Ethernet and one hard IP for PCI Express Gen3, Gen2, and Gen1 x8 All Hard IP Variants Support Configuration via PCI Express (CvPCIe) PCI Express enhanced variant with up to 4 hard IP instances for PCI Express Gen3, Gen2, and Gen1 x8 PCIe Gen3 PCIe Gen3 PCIe Gen3 PCIe Gen3 PCIe Gen3 40G/100G 40G/100G 40G/100G

Stratix V Transceiver, Memory, and I/O Innovations Built for Bandwidth

High-Bandwidth Transceivers 28-Gbps transceivers 20 Gbps to 28 Gbps Up to 4 full-duplex transceiver channels CEI-28G compliant 12.5-Gbps transceivers 150 Mbps to 12.5 Gbps Up to 66 full-duplex transceiver channels SFP+ and 10GBASE-KR compliant Independent transceivers Change transceiver settings (PMA or PCS) without interrupting other transceiver channels Overcome channel losses Ultra-low transmit jitter (LC PLL) and excellent jitter tolerance (analog CDR) Four signal-conditioning techniques to compensate for losses

Flexible Transceiver Architecture Scalability and flexibility through a continuous bank of transceivers Complete PMA+PCS per channel Flexible clocking options with abundant transmit clock sources enabling up to 44 independent data rates Stratix V FPGAs Offer Up to 66 Full-Duplex Transceiver Channels with PCS and PMA . . . . LC Transmit PLLs Clock Networks Hard PCS Hard PCS Hard PCS Hard PCS Hard PCS Hard PCS Hard PCS Hard PCS Hard PCS Hard PCS Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA . . . . Transmit Clock Source Number Data Range (Gbps) 28G LC PLL 4 20 - 28 12G LC PLL 22 3.25 - 12.5 CMU PLL 22 0.6 – 12.5 Core PLL (fPLL) 22 0.6 – 3.75

Designed for Backplanes and Optical Modules Drive 40” backplanes at 12.5 Gbps 10GBASE-KR compliant (IEEE 802.3AP Clause 72) Interface to optical modules directly Built in electronic dispersion compensation (EDC) XFP, SFP+, QSFP, and CFP compliance Signal conditioning Pre-emphasis and de-emphasis Four-stage continuous time linear equalizer (CTLE) 5-tap decision feedback equalizer (DFE) Adaptive dispersion compensation engine (ADCE) On-die instrumentation Monitor eye margin within the receiver Evaluate effectiveness of signal-conditioning techniques

Stratix V FPGA On-Die Instrumentation View eye margin inside receiver EyeQ enables complete X and Y reconstruction of eye opening post equalization Evaluate effectiveness of signal-conditioning techniques Select optimal pre-emphasis, CTLE, and DFE settings for largest eye opening Maximize productivity by minimizing board bring-up and debug time Minimize Board Bring Up/Debug Time With Dynamic Reconfiguration and EyeQ Tx Rx Lossy Medium Pre-Emphasis EQ CDR

Highest Bandwidth at Lowest Power Highest Bandwidth and Power Efficiency Lower power - 50% power reduction at 11.3 Gbps A fraction of the power (< 10%) compared to external transceivers 28 Gbps ~200 mW per channel 12.5 Gbps ~170 mW per channel 6.5 Gbps ~ 80 mW per channel

10G Protocols Supported in Stratix V FPGAs New or enhanced in Stratix V FPGAs Note: Subject to change. See the Stratix V handbook for the latest information. Standard Electrical Serial Line Rate Link Lanes HIP 10G IEEE 802.3ba 40G 10.3125 Gbps Chip-to-module and BP 4 Yes IEEE 802.3ba 100G 10.3125 Gbps Chip-to-module 10 Yes IEEE 802.3ae 10GBASE-R 10.3125 Gbps Chip-to-module 1 to N Yes IEEE 802.3ba 10GBASE-KR 10.3125 Gbps Backplane 1 to N Yes 10G GPON/EPON 10 Gbps C2C and C2M 1 to N Yes OIF SFI-S 9.95 to 11.1 Gbps Chip-to-module (8,10, 12, 16) +1 OIF SFI-5.2 (40G) 9.95 to 11.1 Gbps Chip-to-module 5 10G Interlaken 10.6921 Gbps Chip-to-chip, cable 1 to N Yes SONET/SDH OC-192 (10G) 9.95 Gbps Chip-to-chip 1 to N SONET/SDH OC-192 (40G) 9.95 Gbps Chip-to-chip 4 SFP+ 8.5 to 11.32 Gbps Optical module std 1 to N Yes XFP 9.95328 to 11/32 Gbps Optical module std 1 to N OIF/CEI 11G-SR 9.95 to 11.1 Gbps Chip-to-chip I/O technology OIF/CEI 11G-LR 9.95 to 11.1 Gbps Backplane I/O technology OTU-2 10.709 Gbps Chip-to-chip See SFI-S OTU-3 10.7545 Gbps SFI-S See SFI-S OTU-4 11.2 Gbps SFI-S See SFI-S 10G SDI 10.6921 Gbps Chip-to-chip, cable 1 to N QDR InfiniBand 10 Gbps Chip-to-module 1 to N

6G Protocols Supported in Stratix V FPGAs New or enhanced in Stratix V FPGAs Note: Subject to change. See the Stratix V handbook for the latest information. Standard Electrical serial line rate Link Lanes HIP 6G PCIe 3.0 8 Gbps Chip-to-module and BP 1, 2, 4, 8 Yes PCIe 2.0 5 Gbps Chip-to-module and BP 1, 2, 4, 8 Yes Interlaken 4.976 Gbps to 6.375 Gbps Chip-to-module and BP 1 to 24 Yes SRIO 2.0+ 1.25, 2.5, 3.125, 5 to 6.25 Gbps Chip-to-module and BP 1, 2, 4 Yes CPRI 4.0+ 0.6144, 1.2288, 2.4576, 3.072, 4.9152, 6.144 Gbps Chip-to-chip 1 to N Yes OBSAI 4.0+ (RP3) 0.768, 1.536, 3.072, 6.144 Gbps Chip-to-module and BP 1 to N SATA 3.0 6 Gbps Chip-to-module and BP 1 to N SAS 2.0 6 Gbps Chip-to-module and BP 1 to N SPAUI 6.375 Gbps Chip-to-chip and BP 4 or 6 DDR-XAUI 6.25 Gbps Chip-to-chip and BP 4 QPI 4, 4,8, 6.4, 8 Gbps Chip-to-chip (5, 10, 20)+1 HyperTransport™ 3.0+ 0.4, 2.4, 2.8, 3.2 Gbps Chip-to-module and BP (2, 4, 8)+2, (16)+4 HighGig+, HighGig2+ 3.75, 6.25 Gbps Chip-to-module and BP 4 8G FC 8.5 Gbps C2C and C2M 1 to N OIF/CEI 6G-SR 4.976 to 6.375 Gbps Chip-to-chip I/O technology OIF/CEI 6G-LR 4.976 to 6.375 Gbps Backplane I/O technology 4G FC 4.25 Gbps C2C and C2M 1 to N

3G Protocols Supported in Stratix V FPGAs New or enhanced in Stratix V FPGAs Note: Subject to change. See the Stratix V handbook for the latest information. Standard Electrical Serial Line Rate Link Lanes HIP 3G GIGE (Cisco SGMII) 1.25 Gbps Chip-to-chip 1 to N GIGE (IEEE 1000 Base-X) 1.25 Gbps C2C and C2M 1 to N SD-SDI/HD-SDI/3G-SDI 0.270, 1.485, 2.970 Gbps Chip-to-chip, cable 1 to N SATA 1.0/2.0 1.5 and 3 Gbps Chip-to-chip and BP 1 to N SAS 1.0 3 Gbps Chip-to-chip and BP 1 to N SRIO 1.0 (1.3) 1.25, 2.5, 3.125, 5 Gbps Chip-to-chip and BP 1, 4 Yes JESD204A 3.125 Gbps Chip-to-chip 1 to 32 XAUI 3.125 Gbps Backplane 4 Yes PCIe 1.0 2.5 Gbps Chip-to-chip and BP 1, 2, 4, 8 Yes GPON 0.155, 0.622, 1.244, 2.488 Gbps Chip-to-chip 1 to N CPRI 2.0+ 0.6144, 1.2288, 2.4576 Gbps Chip-to-chip 1 to N OBSAI 4.0 (RP3) 0.768, 1.536, 3.072 Gbps Chip-to-chip and BP 1 to N SONET/SDH OC-12, OC-48 0.622 to 2.488 Gbps Chip-to-chip 1 to N SFI-4.2 (10G) 3.125 Gbps Chip-to-chip 4 SFI-5.1 (40G) 3.125 Gbps Chip-to-chip 16 TFI-5 (40G) 2.488 to 3.11 Gbps Chip-to-chip 16 Sxl-5 2.488 to 3.125 Gbps Chip-to-chip I/O technology SPI-4.2 (10G) 0.622 Gbps Chip-to-chip 16 SPI-5.1 (40G) 2.5 Gbps Chip-to-chip 16

New UniPHY enables half the latency of ALTMEMPHY High system reliability Duty cycle correction Calibration algorithms VT compensated deskew delays PVT tracking mechanisms Sharing of PLLs and DLLs across multiple interfaces Hard I/O FIFOs and read/write paths Ease of use UniPHY available as cleartext Nios processor-based calibration sequencer for easier debug and customization Easy-to-use application of timing and pin constraints Improved documentation Stratix V FPGA External Memory Interface Implementing Memory Subsystem Quickly and Easily Memory Stratix V FPGA PHY Architecture (UniPHY) UniPHY Memory IP Controller I/O Structure Clock Gen I/O Block DQS Path DQ I/O FIFO Re-config Calibration Sequencer Write Path Read Path Address/cmd Path PLL DLL Hard IP

Highest memory bandwidth DDR3 at 1,600 Mbps (800 MHz) Up to 7 x 72 DDR3 DIMMs with multi-rank support Guaranteed timing closure and highest performance in timing-critical paths Hardened read/write paths Hardened I/O FIFOs Supporting LVDS channels capable of 1.6 Gbps on ubiquitous I/Os Stratix V Memory and I/O Performance Delivering Highest Memory and I/O Bandwidth Interface Performance DDR3 800 MHz DDR2 400 MHz QDR II 333 MHz QDR II+ 550 MHz RLDRAM III 800 MHz RLDRAM II 533 MHz LVDS 1.6 Gbps

New Embedded HardCopy Block 700K equivalent LEs 14M ASIC gates 65% reduction in power and 2X performance improvement versus soft logic 3-6 months turn-around time for new variants to address new target applications Stratix V initial variants include PCIe Gen3 x8 and/or 40G/100G Ethernet hard IP Increased System Integration and Performance Without the Cost and Power Penalty Embedded HardCopy Block Embedded HardCopy Block

Stratix V Integrated Hard IP More Available Logic for Higher System Integration in a Smaller FPGA Embedded HardCopy Block Hard IP PCIe Gen3, Gen2, Gen1 x8 PCS, PHY/MAC, data link, transaction layer 40GE/100GE MLD/PCS – gearbox, block sync, alignment marker, reorder virtual channel, async buffer/deskew, block striper/destriper, scrambler/descrambler Transceiver PCS Hard IP Interlaken Gearbox, block sync, 64b/67b, frame sync, scrambler/descrambler, CRC-32, async buffer/deskew 10GE (10GBASE-R) Gearbox, block sync, scrambler/descrambler, 64b/66b, rate matcher Serial RapidIO ® 2.0 Word aligner, lane sync state machine, deskew, rate matcher CPRI/OBSAI Word aligner, bit slip (deterministic latency)

Higher Effective Density With Stratix V Hard IP Stratix V FPGA 5SGXA7 ~630K LEs PCIe Gen3 x8 PCIe Gen3 x8 12 Ch @ 5G Interlaken 12 Ch @ 5G Interlaken Integrated Hard IP Enables a 630K-LE Stratix V FPGA to Be Equivalent to a 1070K-LE Part 630K LEs + 440K LEs = 1,070K LEs Interlaken – PCI Express Switch/Bridge Higher Effective Density Hard IP LE Savings Interlaken (24 Ch @ 5K LEs) 120K LEs PCIe Gen3 x8 (2 x 160K LEs) 320K LEs Total LE savings 440K LEs

Stratix V FPGA Core Innovations

Partial Reconfiguration in Stratix V FPGAs Ultimate flexibility enables differentiation Partial and dynamic reconfiguration for flexible client-side interface Application operation not affected during reconfiguration Built on proven methodology using LogicLock™ and incremental compile No system downtime with dynamic updates Faster reconfiguration Reduces cost and power through integration Easy-to-Use Partial Reconfiguration A1 C1 D1 E1 F1 B1 A2 C2 D1 E1 F1 B1 A2 C2 FPGA Core FPGA Core Partial Reconfiguration for Core Transceivers Transceivers Dynamic Reconfiguration for Transceivers

Configuration Via PCIe (CvPCIe) Load FPGA fabric image via PCIe Gen3 x8 instead of flash memory Faster configuration and enhanced system flexibility Lower cost by using cheaper configuration file memory Three steps for CvPCIe Program PCIe HIP via serial flash PCIe link bring up within 100ms CvPCIe streams FPGA core programming file from host PC 2 3 4 Pins Configure PCIe HIP PCIe Link Gen3, Gen2, Gen1 x1, x2, x4, x8 Load FPGA Image via PCIe Link Serial SPI Flash PCIe Hard IP Endpoint Host PC 1 3

Stratix V Fractional PLLs — fPLLs fPLLs (up to 32) support: Conventional integer mode for general-purpose PLL (GPLL) Fractional mode for high-resolution clock synthesis Replaces board-level clock frequency sources (VCXOs) Reduces clock pins Provides additional clock sources for transceivers fPLLs in Stratix V FPGAs Reduce Cost, Power, and Board Space f IN f VCO f PDF Phase Freq Detect Charge Pump Low Pass Filter VCO Div By N Div By M Delta Sigma Mod f IN f VCO f PDF Phase Freq Detect Charge Pump Low Pass Filter VCO Div By N Div By M Delta Sigma Mod Note: Replaces and retains all features of general-purpose PLLs in Stratix IV FPGAs Σ

Industry’s First Variable-Precision DSP Block Architected for Variable-Precision DSP Applications in Military, Wireless, Broadcast, and Medical New Stratix V FPGA Capability Benefits Variable-precision DSP architecture Integrated coefficient registers and hard pre-adder 64-bit DSP architecture Native support for floating-point DSP Highest efficiency and performance across multiple-precision DSP datapaths and functions such as FIR, FFT, and floating point Variable-precision modes: 9x9, 18x18, 27x27, 18x36, 36x36, 54x54 Complex multiplication Single- and double-precision floating point

Variable DSP Block Configurations Independent Multipliers 9 x 9 Three per block 18 x 18 with 32-bit resolution Two per block 27 x 27 One per block 18 x 36 One per block 36 x 36 Two cascaded blocks 54 x 54 Four cascaded blocks Independent Complex multipliers 18 x 25 Three cascaded blocks 27 x 27 Four cascaded blocks Sum of Multipliers Two 18 x 18 One per block Four 18 x 18 Two cascaded blocks Two 18 x 36 Two cascaded blocks Two 27 x 27 Two cascaded blocks

Enhanced Adaptive Logic Module Contains 2 more registers for a total of 4 per ALM Improves timing closure for register-rich or heavily pipelined designs Improves logic efficiency Maintains 8-input fracturable LUT efficiency 1 ALM = 2.65 logic elements Enhanced ALM Packs More Logic, Maximizes Performance, and Increases Productivity 4 Registers Per ALM

Internal Memory Block Enhancements Faster MLAB 600-MHz f MAX Integrated address and data registers Optimal for wide and shallow FIFOs Flexible M20K Optimal for packet and video frame buffers Bypassable, pipelined or non-pipelined hard ECC M9K and M144K in Stratix IV FPGA Delivering Higher Performance and More Internal Memory MLAB 640 Bits M20K 20,480 Bits 32 x 20 64 x 10 512 x 40 1K x 20 2K x 10 4K x 5 8K x 2 16K x 1

Enhanced Stratix V Multi-Track Routing Industry’s Best FPGA Routing Architecture Used in Stratix Series FPGAs 5.5X the competition More connections between logic elements Every hop translates to routing delay Minimizes routing congestion Enables >90% FPGA utilization Higher performance Reduces compile times by 50% compared to competing solutions Intra-LAB 1 Hop 2 Hop 3 Hop Hops Reachable Logic Elements (LEs) 1 1,007 2 3,498 3 6,042 Total 10,547

Highest System Performance on 28 nm TSMC’s high-performance process 50% increase in memory interface performance 1.6-Tbps serial switching capability Enhanced core fabric 1,840 GMACS of signal-processing performance Embedded HardCopy Blocks for 2X performance vs. soft logic 800-MHz DDR3 DIMM 12.5-/28-Gbps Serial Transceivers Embedded Hardcopy Blocks 600-MHz Memory Blocks Enhanced ALM and Routing 50% Increase in System Performance Up to 3,680 Variable-Precision DSP Blocks

Stratix V FPGAs Consume 30% Less Power At the Industry’s Highest Performance, Stratix V FPGAs Deliver 30% Less Total Power Programmable Power Technology Core voltage at 0.85 V Embedded HardCopy Blocks and integrated hard IP in core and transceivers 28-nm HKMG process optimizations

Innovations and Techniques to Control Power At the Industry’s Highest Performance, Stratix V FPGAs Deliver 30% Less Core Power Power Reduction Method Lower Static Power Lower Dynamic Power 28-nm Process Innovations   Programmable Power Technology  Lower Core Voltage (0.85 V)   Extensive Hardening of IP, Embedded HardCopy Blocks   Hard Power-Down of Functional Blocks   Clock Gating  Customized Extra-Low Leakage Devices  Partial Reconfiguration   DDR3 and Dynamic On-Chip Termination  

Design Security Enhanced AES algorithm in accordance with FIPS-197 256-bit volatile and non-volatile keys Key bits scrambled Key bits placed under layers of metal Key bits distributed among other logic Tamper-protection bit Accept only encrypted configuration files Easy to use on-board and off-board key programming Stratix V FPGAs Secure Designs Through Industry-Leading Anti-Tamper Features

Stratix V FPGA SEU Immunity Reduced system downtime for highly reliable system designs Automatic SEU detection Operates in the background Error location identification Automatic SEU correction – scrubbing Internal scrubbing system - runs in background and does not require user design or external components SEU immunity through device Fast error detection and correction, built into the silicon ECC on user RAM, built into the silicon Stratix V FPGAs Detect and Correct SEU

Stratix V FPGA IP, Reference Designs, and Development Kits

Stratix V Solution Strategy Provide complete solutions to enable customer success Flexible and hardware-verified IP solutions Reference designs to kick-start system design Development kits Focus on developing Altera IP and extending partnerships to expand IP portfolio Interoperability testing for key I/O protocols Deliver next-generation reference designs with development kits from Altera and our partners Complete Integrated Solution Ensures Time to Market and Customer Success Stratix V Solution Dev Kits IP Reference Designs

Altera’s IP Portfolio Highlights for Stratix V FPGAs Function Solution Type Provider Hard 10/40/100 Gbps Ethernet PCS IP core (hard) Altera Soft 40/100 Gbps Ethernet MAC and PCS IP core Altera and partner 10GBASE-R PCS IP core (hard) Altera 10G Ethernet MAC IP core Altera and partner Gigabit Ethernet MAC and PCS IP core Altera XAUI PCS IP core (hard) Altera Hard PCI Express Gen3, Gen2, Gen1 IP core (hard) Altera Soft PCI Express Gen3, Gen2, Gen1 IP core Altera and partner Interlaken (Hard PCS) IP core Altera Serial RapidIO Gen2 IP core Altera SFI 4.1, 5.1, 5.2 and SFI-S IP core Partner CPRI IP core Altera DDR1/2/3 SDRAM IP core Altera QDR II/QDR II + SRAM IP core Altera RLDRAM II IP core Altera and partner Floating-Point DSP Functions IP core Altera

Reference Designs and Development Kits Reference Designs Function Solution Type Provider 100G Aggregation to Interlaken Reference design Altera Deep Packet Inspection Reference design Partner High-Assurance Security Supervisor Reference design Partner Ethernet to Optical Transfer for OTN4 Reference design Partner Partial Reconfiguration for OTN4 Muxponder Reference design Altera and partner 40G Packet Processing and Traffic Management Reference design Altera 100G MAC-Interlaken Bridge Reference design Altera and partner HyperTransport™ 3.0 Reference design Partner PCI Express Gen3, Gen2, Gen1 Reference design Altera DDR1/2/3 SDRAM Reference design Altera Development Kits Function Provider Function FPGA Development Kit Altera FPGA Development Kit Signal Integrity and Interoperability Kit Altera Signal Integrity and Interoperability Kit Packet Datapath Processing Altera Packet Datapath Processing OTN4 With Ethernet Optical to Transport Partner OTN4 With Ethernet Optical to Transport

Highest bandwidth with 12.5- and 28-Gbps transceivers Highest level of system integration through extensive hard IP integration and new Embedded HardCopy Blocks 50% higher system performance at 30% lower total power Ultimate flexibility with easy-to-use partial reconfiguration Lowest risk path to HardCopy V ASICs Productivity advantage with Quartus II software system solutions, tools, and IP for vertical markets Stratix V FPGAs and HardCopy V ASICs Built for Bandwidth

Stratix V FPGA Intro Presentation

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Stratix V FPGA Intro Presentation