Techniques for Minimizing Power Consumption in DFT during Scan Test Activity

INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY
VOLUME 5 ISSUE 2 – MAY 2015 - ISSN: 2349 - 9303
174
Techniques for Minimizing Power Consumption in
DFT during Scan Test Activity
Mathavi.A1
Hema.B2
Kalasalingam Institute of Technology,
PG Student of ECE
Kalasalingam Institute of Technology,
Asst. prof of ECE
mathaviathimoolam@gmail.com hema.shivam@gmail.com
Abstract--- Lessening in test force is vital to enhance battery lifetime in versatile electronic gadgets utilizing intermittent
individual test. It's to expand dependability of testing, and to lessen test expense. A conservative test set with exceedingly
viable examples, every identifying different issues, is attractive for lower test expenses. Such examples build exchanging
action amid dispatch and catch operations. In this paper, we exhibit a novel circuit strategy to essentially dispense with test
force dissemination in combinational logic by veiling sign moves at the logic inputs amid sweep moving is exhibited. We
execute the concealing impact by embeddings an additional supply gating transistor in the supply to ground way for the first-
level doors at the yields of the output flip-flops. The gating transistor supply is killed in the output in mode, basically gating
the supply. Further, DFT punishments are decreased by embracing specific trigger Scan structural planning. This building
design diminishes exchanging action in the circuit-under-test (CUT) and builds the clock recurrence of the checking
methodology. The assistant chain moves in the contrast between sequential test vectors and just the obliged moves (alluded to
as trigger information) are connected. Power necessities are significantly decreased by the utilization of a two-stage heuristic
technique. Utilizing ISCAS 89 benchmark circuits, this adequacy is to enhance SoC test measures (power, time, and
information volume) is tentatively assessed and affirmed.
Index Terms---Circuit-under-test (CUT), First-level gates, Masking effect, Power dissipation, Selective trigger.
1. INTRODUCTION
INTELLECTUAL property (IP) centers are generally
utilized for planning a framework on-chip (SoC). Despite the
fact that IP centers can help to decrease the outline process
duration, regardless they posture numerous difficulties when
testing is considered. The precomputed test examples that are
given by center merchants must be connected to every center
inside the force requirements of the entire SoC. As a
framework integrator may utilize a center in diverse stages
with different test instruments, the test instrument of the
center must consider issues identified with information
volume, application time, and force utilization amid test.
Besides, different models, (for example, for deferral issues)
must be considered to enhance the general test quality.
Power dissemination amid test mode can be altogether higher
than that amid useful mode because of taking after reasons
[5], the outline under test (DUT) has a hardware implanted to
diminish the test-multifaceted nature is regularly sit out of
gear amid the typical operations, however utilized widely as
a part of the testing mode, the test proficiency demonstrates a
high relationship with the switch rate, in a circuit, parallel
testing is much of the time utilized to lessen application time.
Since the data vectors amid utilitarian mode are typically
emphatically related contrasted with factually free
continuous information
vectors amid testing. Swarup Bhunia [1] demonstrated that
embeddings blocking logic into the boost way of the output
flip-lemon to
anticipate proliferation of output expansive influence to logic
doors offers a straightforward and powerful answer for
altogether diminish test force, autonomous of test set.
Mohammad Hosseinabady [2] demonstrated that the output
structural planning uses an activating (empowering) tie
notwithstanding the information registers. Moreover,
activating affix equipment is intended to exploit comparable
neighboring information into the information enrolls, the
activating chain chooses where an information flip-flop must
flip or hold its old worth. Alongside test reformatting
systems, this structural planning can decrease test time and
force. It can likewise decrease the information volume by
empowering the utilization of pressure calculation on its
reformatted information. It is material to postpone
shortcoming testing. Yet, information in this building design
is checked at a higher clock recurrence. Arnab Sinha [3]
demonstrated that to minimize the force by the utilization of
a two-stage heuristic technique, which can be abused by any
chip-format project amid the position and steering of sweep
cells. At-pace or significantly speedier than-at-rate testing
propose design era under low exchanging action limitations
may prompt misfortune in test quality and/or example check
swelling, Samah Mohamed [4] demonstrated that outline for
testability (DFT) support for empowering the utilization of
an arrangement of examples enhanced for expense and

175
quality as seems to be, yet in a low influence way.
Apportioning the outline and testing one parcel at once has
been proposed to diminish dispatch and catch force amid
inherent individual test (BIST) [6], LOS [7] and LOC [8]. In
broadside testing [9], it needs two back to back catch cycles,
called the dispatch cycle and the catch cycle. Some effective
techniques, which decrease the catch control in stuck-at issue
testing, neglect to diminish test power in both dispatch cycle
and catch cycle for broadside testing. In the event that one
strategy tries to lessen test power under broadside testing, it
is sensible for it to identify all the testable deficiencies of
broadside testing, as [10][11][12]. Flaw scope can be
enhanced with the force diminishment plots in [13]. Wang,
al. proposed programmed test example era strategy to update
test vectors for decreasing force scattering amid sweep
testing [14]. With their programmed test example era
(ATPG), repetitive moves in combinational logic can be
diminished however not killed. In [15], an ATPG procedure
that lessens exchanging action (amid testing of consecutive
circuits with full-sweep) has been introduced. The tests
produced by this ATPG can be utilized for an at-rate testing
of chips and has scarcely passed on with any danger of harm
because of unnecessary warmth.
Whatever remains of the paper is composed as takes after:
Section II delineates the proposed piece logic system; sweep
chain reordering and a specific trigger for decrease move
control and averts excess exchanging in combinational logic.
Segment III presents exploratory results as far as territory,
defer and force for an ISCAS89 benchmark circuit. Segment
IV presents related works. Area V closes the paper.
2. REORDERING TEST VECTORS AND SCAN
CHAIN FLIPFLOPS
The element power dissemination in the combinational
circuit can be lessened by bringing down the action of the
circuit. The test mode normally disperses more power than
the typical mode, particularly if a sweep component is
utilized. Amid the information examine in process, the
distinction between two contiguous bits travels through the
output way because of the movement operation; numerous
drifting moves are then connected to the CUT. Numerous
methods are proposed to lessen the quantity of these moves
for force dispersal administration. These systems can be
classified as takes after:
• Transition methods to decrease the distinction
between two sequential test vecto Transition techniques to
reduce the difference between two consecutive test vectors
 Transition techniques to reduce the effect of the
difference between two consecutive bits in the scan
chain
 Transition techniques by partitioning to reduce the
effective length of the scan chain
 Techniques to block transitions in a circuit
 Scan reordering techniques and
 Integrated techniques that use two or more of the
aforementioned techniques.
2.1 Block Logic Method for prevents redundant
switching in combinational circuits
Embeddings blocking logic into the boost way of
the sweep flip-flops [as demonstrated in Fig.1(a)] to
anticipate engendering of output progressively outstretching
influence to logic doors offers a straightforward and
successful answer for altogether decrease test force,
autonomous of test set. Blocking doors (of sort NOR or
NAND) are controlled by the test empower signal [as in Fig.
1(b)], and the jolt ways stay settled at either logic "0" or "1"
amid the whole sweep shift
operation.
Fig. 1 (a). Scan architecture with blocking circuitry
Fig. 1(b). Blocking Logic
2.2 Scan chain reorder for minimizing transition
between flip-flops
Consider the ISCAS89 benchmark circuit with
three flip-flops. We consider eight tests –cases and their
corresponding responses. We construct an acyclic graph
from the test-sequence and their respective responses. The
vertices in the graph represent the flip-flops and the edges
represent the transitions between each pair of flip-flops. The
edge–weights represent the total bit-difference between them
as obtained from the table. The greedy algorithm starts from
any scan cell which is ff1 in our case, as the choice of initial
state is not so crucial when the number of scan cells in the
graph is considerably high [16]. The final series in this case
BL
D Q
SFF
D Q
SFF
To comb. gates
To comb. gates
TC~
TC
~
CL
K
CL
K

176
is ff1-ff3-ff2. Cutting the cyclic graph at each edge will give
us the scan-in and scan-out flip-flops. Each cutting solution
differs in number of transitions and propagation and the one
with least number of transitions will give the optimal
solution to our problem.
Fig. 2. Test sequence and Weighted Graph
2.3 Selective trigger scan architecture for reduce
transition between test vectors
We begin clarification of our proposed building design
with a straightforward sample. Give us a chance to expect
that V1 in Fig.3a is a current test vector in an output chain
and V2 is the following test vector that must be moved.
Looking at V1 and V2 moves (Fig.3a), there are just three
distinctions in their bits that are called vital moves. If we
somehow managed to utilize a standard output chain and
movement V2 into the sweep chain in eight test tickers, with
every movement, moves indicated in Fig.3b would happen.
Case in point, moving the furthest right 1 of V2 into the
sweep chain causes five moves in the eight output flip-flops.
Through and through, moving V2 would bring about 32
moves that are called pointless moves. Then again, parallel
stacking V2 specifically into our building design disposes of
superfluous moves on the info of a CUT. Hence, our
scan architecture should eliminate the unnecessary
transitions. In addition, the following features should be
considered for the proposed scan architecture and DFT
method:
 Scan architecture should not add extra inputs
compared to a conventional scan approach.
 A DFT approach must add no delay to the normal
operation of the circuit.
The proposed architecture, shown in Fig. 4, serves
two purposes. One is to reduce the activity at the data outputs
and the second is to facilitate test data compression. As
shown in Fig. 4, the NOR gate compare the previous cell and
next cell test vector, if the value will be same again the
previous value saved into the TR. If the value will be differ
the next cell value saved into TR.
Fig. 3. (a). Transitions between 2 test vectors. (b). Unnecessary
transitions in scan architecture
Fig. 4. Scan cell structure of the proposed architecture
3. EXPERIMENTAL RESULTS
We assess our configuration utilizing modelsim.
We recreate an ISCAS89 benchmark circuits and acquired
power, zone and time. We pick piece logic, output chain
reordering and specific trigger for trial assessment. Fig.5.
Speaks to, the reenactment consequence of square logic,
sweep chain reordering and particular trigger. Particular
trigger diminished number of move between test vectors.
Piece logic averts excess information move into
combinational circuits. Sweep chain reordering diminished
power through revise the output cells. Fig.6. Demonstrates
the force report of piece logic, sweep chain reordering and
particular trigger. The aggregate force utilization is 123
MHz. The flip-failure check is decreased. Along these lines,
the zone overhead is decreased. Table.1. Demonstrates the
static force andareacomparison.Fig.5. The simulation result of
proposed architecture
Fig. 6. Power report for proposed architecture
FF1 FF2 FF3
V1 1 0 0
R1 0 1 0
V2 0 1 0
R2 0 0 1
V3 1 1 1
R3 0 1 1
V4 1 0 1
R4 0 1 0

177
TABLE.1. POWER AND AREA COMPARISON
ANALYSIS
Static(MHz) Gate
Count
Mixed At-Speed
Testing
131 268
Selective Trigger 123 142
4. RELATED WORK
Scan cell testing has been extensively used to
increase fault coverage in the CUT. The proposed
architecture reduces number transitions between scan cells
and test vectors. So, the power consumption in the scan cell
testing has been reduced.
5. CONCLUSION
In this paper, square logic, output chain reordering
and a particular trigger are proposed for force minimization.
At moving operation excess information moved into the
combinational circuit. Particular trigger diminishes the
number moves between test vectors to utilizing NOR door.
Sweep chain reordering revamps the output cells for lessen
number of moves between output cells. Both of these
techniques, used to minimize the force and region contrasted
with the current blended at-rate testing. From there on, the
static force is lessened by 6.1% to 11% and the zone
overhead diminished by 47% contrasted with Mixed At-
Speed testing with slight addition in element power.
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