Thyristor theory and design considerations
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This document provides an overview of thyristor theory and design considerations. It discusses the basic characteristics and operation of thyristors such as silicon controlled rectifiers (SCRs) and triacs. Thyristors act as switches that can withstand voltage until triggered, at which point they become low impedance current paths. The document outlines considerations for triggering thyristors and driving circuits, as well as applications like motor control, phase control, and transient voltage suppression. It provides guidance on reliability testing and mounting techniques for thyristors.
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significant effect than any of the other factors. Negative
gate bias will decrease the turn−off time.
Figure 2.7. Waveshapes Illustrating Thyristor
Turn−Off Time
PRINCIPAL
VOLTAGE
PRINCIPAL
CURRENT
REAPPLIED
dv/dt
FORWARD
0
REVERSE
di/dt
FORWARD
REVERSE
0
trr tgr
tq
For applications in which an SCR is used to control ac
power, during the entire negative half of the sine wave a
reverse voltage is applied. Turn off is easily accomplished
for most devices at frequencies up to a few kilohertz. For
applications in which the SCR is used to control the
output of a full−wave rectifier bridge, however, there is no
reverse voltage available for turn−off, and complete
turn−off can be accomplished only if the bridge output is
reduced close to zero such that the principal current is
reduced to a value lower than the device holding current
for a sufficiently long time. Turn−off problems may occur
even at a frequency of 60 Hz particularly if an inductive
load is being controlled.
In triacs, rapid application of a reverse polarity voltage
does not cause turn−off because the main blocking
junctions are common to both halves of the device. When
the first triac structure (SCR−1) is in the conducting state,
a quantity of charge accumulates in the N−type region as
a result of the principal current flow. As the principal
current crosses the zero reference point, a reverse current
is established as a result of the charge remaining in the
N−type region, which is common to both halves of the
device. Consequently, the reverse recovery current
becomes a forward current to the second half of the triac.
The current resulting from stored charge causes the
second half of the triac to go into the conducting state in
the absence of a gate signal. Once current conduction has
been established by application of a gate signal, therefore,
complete loss in power control can occur as a result of
interaction within the N−type base region of the triac
unless sufficient time elapses or the rate of application of
the reverse polarity voltage is slow enough to allow nearly
all the charge to recombine in the common N−type region.
Therefore, triacs are generally limited to low−frequency
−60 Hz applications. Turn−off or commutation of triacs is
more severe with inductive loads than with resistive loads
because of the phase lag between voltage and current
associated with inductive loads. Figure 2.8 shows the
waveforms for an inductive load with lagging current
power factor. At the time the current reaches zero
crossover (Point A), the half of the triac in conduction
begins to commutate when the principal current falls
below the holding current. At the instant the conducting
half of the triac turns off, an applied voltage opposite the
current polarity is applied across the triac terminals (Point
B). Because this voltage is a forward bias to the second
half of the triac, the suddenly reapplied voltage in
conjunction with the remaining stored charge in the
high−voltage junction reduces the over−all device capa-
bility to support voltage. The result is a loss of power
control to the load, and the device remains in the
conducting state in absence of a gate signal. The measure
of triac turn−off ability is the rate of rise of the opposite
polarity voltage it can handle without remaining on. It is
called commutating dv/dt (dv/dt[c]). Circuit conditions
and temperature affect dv/dt(c) in a manner similar to the
way tq is affected in an SCR.
It is imperative that some means be provided to restrict
the rate of rise of reapplied voltage to a value which will
permit triac turn−off under the conditions of inductive
load. A commonly accepted method for keeping the
commutating dv/dt within tolerable levels is to use an RC
snubber network in parallel with the main terminals of the
triac. Because the rate of rise of applied voltage at the
triac terminals is a function of the load impedance and the
RC snubber network, the circuit can be evaluated under
worst−case conditions of operating case temperature and
maximum principal current. The values of resistance and
capacitance in the snubber area then adjusted so that the
rate of rise of commutating dv/dt stress is within the
specified minimum limit under any of the conditions
mentioned above. The value of snubber resistance should
be high enough to limit the snubber capacitance discharge
currents during turn−on and dampen the LC oscillation
during commutation. The combination of snubber values
having highest resistance and lowest capacitance that
provides satisfactory operation is generally preferred.](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-14-320.jpg)
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Consider the gate current waveform in Figure 3.6; the
triggering pulse width is made large enough such that
τuutfl; the threshold trigger current is shown as Ithr. All
of the charge supplied at a transient current level less than
Ithr is lost by recombination, as shown in the shaded
regions.
The gate spreading resistance (r′G) of the gate junction
varies inversely with peak current; the higher the peak
current, the smaller the gate spreading resistance. Varia-
tion of gate spreading resistance measured by the method
of Time Domain Reflectometry is plotted in Figure 3.8.
From the data of Figure 3.7, it is clear that for larger
values of capacitance a lower voltage level is required
for turn−on. The peak current of the spike in Figure 3.6 is
given by I
pk
+ ΔV
Rs ) r′G
; the smaller ΔV, the smaller
Ipk. Smaller Ipk in turn yields large r′G, so that r′G is
dependent on the value of capacitance used in capaci-
tance charge triggering. This reasoning is confirmed by
measuring the fall time of the gate trigger voltage and
calculating the transient gate spreading resistance, r′G,
from: Rs ) r′G +
tf
2.2 C
. Results are plotted in
Figure 3.9. As expected, r′G increases with increasing
values of capacitance used. Referring back to Figure 3.6,
for the same amount of charge (C ΔV), the larger the (Rs +
r′G)C time constant of the current spike, the more charge
under the threshold level is lost in recombination.
Increasing the value of C will increase the time constant
more rapidly than if r′G were invariant. Therefore,
increasing the value of C should increase the charge lost
as shown in Figure 3.7. Note that a two order of
magnitude increase in capacitance increased the charge
by less than 3:1.
C, CAPACITANCE (pF)
2000100
7.0
3.0
2.0
1.0
1000200 500
5.0
10
5000
,MINIMUMTRIGGERCHARGE,Q(nc)
15
Qin
10,000
VAK = 10 V
TA = −15°C
HIGH UNIT
LOW UNIT
PULSE WIDTH = 50 ms
Figure 3.7. Variation of Trigger Charge versus
Capacitance Used
GATE CURRENT (mA)
2000.1
3.0
0.5
0.3
0.2
10020 50
2.0
1.0
500
NORMALIZEDGATESPREADINGRESISTANCE
1000
LOW UNIT
HIGH UNIT
IA = 1 A
TA = 25°C
VAK = 10 V
Z0 = 50 W
0.7
Figure 3.8. Variation of Gate Spreading Resistance
versus Gate Peak Current
EFFECT OF TEMPERATURE
The higher the temperature, the less charge required to
turn on the device, as shown in Figure 3.10. At the range
of temperatures where the SCR is operated the life time of
minority carriers increases with temperature; therefore
less charge into the gate is lost in recombination.
As analyzed in Appendix II, there are three components
of charge involved in gate triggering: (1) Qr, charge lost in
recombination, (2) Qdr, charge drained out through the
built−in gate−cathode shunt resistance, (3) Qtr, net charge
for triggering. All of them are temperature dependent.
Since the temperature coefficient of voltage across a p−n
junction is small, Qdr may be considered invariant of
temperature. At the temperature range of operation, the
temperature is too low to give rise to significant impurity
gettering, lifetime increases with temperature causing Qr
to decrease with increasing temperature. Also, Qtr
decreases with increasing temperature because at a
constant current the αT of the device in the blocking state
increases with temperature;7 in other words, to attain αT =
1 at an elevated temperature, less anode current, hence
gate current [see equation (3) of Appendix I], is needed;
therefore, Qtr decreases. The input charge, being equal to
the sum of Qtr, Qr, and Qdr, decreases with increasing
temperature.
The minimum current trigger charge decreases roughly
exponentially with temperature. Actual data taken on an
MCR729 deviate somewhat from exponential trend
(Figure 3.10). At higher temperatures, the rate of decrease
is less; also for different pulse widths the rates of decrease
of Qin are different; for large pulse widths the recombina-
tion charge becomes more significant than that of small
pulse widths. As the result, it is expected and Figure 3.10
shows that Qin decreases more rapidly with temperature at
high pulse widths. These effects are analyzed in](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-33-320.jpg)
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Appendix II [equation (7), page 235]. The theory and
experiment agree reasonably well.
C, CAPACITANCE (pF)
1000200
30
10
20
0
300 500
40
2000
r
VAK = 10 V
T = 25°C
,GATESPREADINGRESISTANCE()G′W
(RS ) rȀG )
t
f
2.2C
T, TEMPERATURE (°C)
+65−15
10
8.0
9.0
4.0
+25
20
+105
Q
VAK = 10 V
t = GATE CURRENT PULSE WIDTH
(Q = it)
,MINIMUMTRIGGERCHARGE(nc)in
7.0
6.0
5.0
t = 1 ms
t = 500 ns
t = 100 ns
t = 300 ns
Figure 3.9. Variation of Transient Base Spreading
Resistance versus Capacitance
Figure 3.10. Variation of Q versus Temperature
EFFECT OF BLOCKING VOLTAGE
An SCR is an avalanche mode device; the turn−on of
the device is due to multiplication of carriers in the
middle collector junction. The multiplication factor is
given by the empirical equation
M + · 1
1 * ( V
VB
)n
(6)
where
M 5 Multiplication factor
V 5 Voltage across the middle “collector’’ junction
(voltage at which the device is blocking prior to
turn−on)
VB 5 Breakdown voltage of the middle “collector’’
junction
n 5 Some positive number
Note as V is increased, M also increases and in turn α
increases (the current amplification factor α = γδβM
where γ 5 Emitter efficiency, β 5 Base transport
factor, and δ 5 Factor of recombination).
The larger the V, the larger is α T. It would be expected
for the minimum gate trigger charge to decrease with
increasing V. Experimental results show this effect (see
Figure 3.11). For the MCR729, the gate trigger charge is
only slightly affected by the voltage at which the device is
blocking prior to turn−on; this reflects that the exponent,
n, in equation (6) is small.
EFFECT OF GATE CIRCUIT
As mentioned earlier, to turn on the device, the total
amplification factor must be greater than unity. This
means that if some current is being drained out of the gate
which bleeds the regeneration current, turn−on will be
affected. The higher the gate impedance, the less the gate
trigger charge. Since the regenerative current prior to
turn−on is small, the gate impedance only slightly affects
the required minimum trigger charge; but in the case of
over−driving the gate to achieve fast switching time, the
gate circuit impedance will have noticeable effect.
EFFECT OF INDUCTIVE LOAD
The presence of an inductive load tends to slow down
the change of anode current with time, thereby causing
the required charge for triggering to increase with the
value of inductance. For dc or long pulse width current
triggering, the inductive load has little effect, but its effect
increases markedly at short pulse widths, as shown in
Figure 3.12. The increase in charge occurs because at
short pulse widths, the trigger signal has decreased to a
negligible value before the anode current has reached a
level sufficient to sustain turn−on.](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-34-320.jpg)
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Depending on the logic family used, resistor R1 (pull-up
resistor) and R3 (base-emitter leakage resistor) may or may
not be required. If, for example, the logic is a typical TTL
totem-pole output gate that must supply 5 mA to the base of
the NPN transistor and still maintain a “high” (2.4 V) logic
output, then R1 and R2 are required. If the “high” logic
level is not required, then the TTL circuit can directly
source the base current, limited by resistor R2.
To illustrate this circuit, consider the case where the
selected TRIAC requires a positive-gate current of
100 mA. The interface transistor, a popular 2N4401, has a
specified minimum hFE (at a collector current of 150 mA)
of 100. To ensure that this transistor is driven hard into
saturation, under “worse case” (low temperature) condi-
tions, a forced hFE of 20 is chosen — thus, 5 mA of base
current. For this example, the collector supply is chosen to
be the same as the logic supply (+5 V); but for the circuit
configuration, it could be a different supply, if required.
The collector-resistor, R4, is simply
R4 + (VCC * VCE(sat) * VGT(typ))ńIGT
+ (5 * 1 * 0.9)ń100 mA + 40 W
A 39 ohm, 1 W resistor is then chosen, since its actual
dissipation is about 0.4 W.
If the “logic 1” output level is not important, then the
base limiting resistor R2 is required, and the pull-up
resistor R1 is not. Since the collector resistor of the TTL
upper totem-pole transistor, Q2, is about 100 Ω, this
resistor plus R2 should limit the base current to 5 mA.
Thus R2 calculates to
R2 + [(VCC * VBE * VGT)ń5 mA] * 100 W
+ [(5 * 0.7 * 0.9)ń0.005] 100 W
[ 560 W (specified)
When the TTL output is low, the lower transistor of the
totem-pole, Q3, is a clamp, through the 560 Ω resistor,
across the 2N4401; and, since the 560 Ω resistor is relatively
low, no leakage-current shunting resistor, R3, is required.
In a similar manner, if the TTL output must remain at
“logic 1” level, the resistor R1 can be calculated as
described earlier (R3 may or may not be required).
For low-logic activation (logic “0”), the circuit of
Figure 6.54 can be used. In this example, the PNP-interface
transistor 2N4403, when turned on, will supply positive-
gate current to the thyristor. To ensure that the high logic
level will keep the thyristor off, the logic gate and the
transistor emitter must be supplied with the same power
supply. The base resistors, as in the previous example, are
dictated by the output characteristics of the logic family
used. Thus if a TTL gate circuit is used, it must be able to
sink the base current of the PNP transistor (IOL(MAX) =
16 mA).
When thyristor operation in quadrants II and III is
desired, the circuits of Figures 6.55 and 6.56 can be used;
Figure 6.55 is for high logic output activation and
Figure 6.56 is for low. Both circuits are similar to those on
Figures 6.53 and 6.54, but with the transistor polarity and
power supplies reversed.
+ 5 V
LOGIC GATE
R1
R2
Q1
G
R4
R3
MT2
MT1
60 Hz
LINE
LOAD
Figure 6.54. Low-Logic Activation with
Interface Transistor
LOGIC GATE
R3
R1
R2
Q1
R4
R5
LOAD
G
MT1
MT2
60 Hz
LINE
− VEE
Figure 6.55. High-Logic Output Activation
Figure 6.55 sinks current from the thyristor gate
through a switched NPN transistor whose emitter is
referenced to a negative supply. The logic circuit must also
be referenced to this negative supply to ensure that
transistor Q1 is turned off when required; thus, for TTL
gates, VEE would be −5 V.
In Figure 6.56, the logic-high bus, which is now ground, is
the common ground for both the logic, and the thyristor and
the load. As in the first example (Figure 6.53), the negative
supply for the logic circuit (−VEE) and the collector supply
for the PNP transistor need not be the same supply. If, for
power-supply current limitations, the collector supply is
chosen to be another supply (−VCC), it must be within the
VCEO ratings of the PNP transistor. Also, the power
dissipation of collector resistor, R3, is a function of −VCC —
the lower −VCC, the lower the power rating.](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-123-320.jpg)
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Any Opto TRIAC can be used in the circuit of
Figure 6.59 by using Table 6.8. The value of R is based on
the photo-TRIAC’s current-handling capability. For
example, when the MOC3011 operates with a 120 V line
voltage (approximately 175 V peak), a peak IGT current of
175 V/180 ohm (approximately 1 A) flows when the line
voltage is at its maximum. If less than 1 A of IGT is needed,
R can be increased. Circuit operation is as follows:
Table 6.8. Specifications for Typical Optically
Coupled TRIAC Drivers
Device
Type
Maximum Required
LED Trigger
Current (mA)
Peak
Blocking
Voltage
R(Ohms)
MOC3011
MOC3011
MOC3021
MOC3031
15
10
15
15
250
250
400
250
180
180
360
51
When an op-amp, logic gate, transistor or any other
appropriate device turns on the LED, the emitted light
triggers the photo-TRIAC. Since, at this time, the main
TRIAC is not on, MT2-to-gate is an open circuit. The
60 Hz line can now cause a current flow via R, the
photo-TRIAC, Gate-MT1 junction and load. This
Gate-MT1 current triggers the main TRIAC, which then
shorts and turns off the photo-TRIAC. The process repeats
itself every half cycle until the LED is turned off.
Triggering the main TRIAC is thus accomplished by
turning on the LED with the required LED-trigger current
indicated in Table 6.7.
MICROPROCESSORS
Microprocessor systems are also capable of controlling ac
power loads when interfaced with thyristors. Commonly, the
output of the MPU drives a PIA (peripheral interface
adaptor) which then drives the next stage. The PIA Output
Port generally has a TTL compatible output with significant-
ly less current source and sink capability than standard TTL.
(MPUs and PIAs are sometimes constructed together on the
same chip and called microcontrollers.)
When switching ac loads from microcomputers, it is
good practice to optically isolate them from unexpected
load or ac line phenomena to protect the computer
system from possible damage. In addition, optical
isolation will make UL recognition possible.
A typical TTL-compatible microcontroller, such as the
MC3870P offers the following specifications:
IOH + 300 mA (VOH + 2.4 V)
IOL + 1.8 mA (VOL + 0.4 V)
VCC + 5 V
Since this is not adequate for driving the optocoupler
directly (10 mA for the MOC3011), an interface transistor
is necessary.
The circuit of Figure 6.60 may be used for thyristor
triggering from the 3870 logical “1.”
MC3870
MT1
MT2
R
G
LOAD
Q1
R2
R1
R3
+ 5 V
Figure 6.60. Logical “1” Activation from MC3870P
Microcomputer
60 Hz
LINE
The interface transistor, again, can be the 2N4401. With
10 mA of collector current (for the MOC3011) and a base
current of 0.75 mA, the VCE(sat) will be approximately
0.1 V.
R1 can be calculated as in a previous example.
Specifically:
1.8 mA (maximum IOL for the 3870)
u 5 VńR1; R1 u 2.77 k
R1 can be 3 k, 1ń4 W
With a base current of 0.75 mA, R1 will drop (0.75 mA)
(3 k) or 2.25 V. This causes a VOH of 2.75 V, which is
within the logical “1” range.
R2 + [2.75 V–VBE(on)]ńIB + (2.75–0.75)ń0.75 + 2.66 k
R2 can be a 2.7 k, 1ń4 W resistor..
R3 must limit IC to 10 mA :
R3 + [5 V–VCE(sat) – VF(diode)ń10 mA]
+ (5–0.1–1.2)ń10 mA + 370 W
Since R3 is relatively small, no base-emitter leakage
resistor is required.](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-125-320.jpg)
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146
Assume the case temperature changes by 40°C for a
single power pulse of 66.67 W and 3 s duration. Then from
equation (5.6):
Cpkg +
(66.7 Watts) (3 seconds)
40°C
+ 5 Joules
°C
The heatsink thermal resistance can be determined by
applying dc power, measuring the final case temperature,
and using equation (5.0).
TC * TA
PD
+ 175-25
5
+ 30°CńW
The application requires a 3 s on-time and 180 s period at
66.7 W. Then
Pavg + (66.7 W) (3ń180) + 1.111 W
Where Δ TC (N + 1) = maximum rise above ambient
Pd = applied average power within a pulse
PAV G = average power within a period
r(ton + tp) = time dependent factor for sum of ton
and tp
r(ton) = time dependent factor for ton
r(tp) = time dependent factor for tp
DTC (N ) 1) + [PAVG ) (Pd * PAVG) r(ton ) tp) ) Pd r(ton)
* Pd r(tp)]qCA
tp
PAVG
ton
Nth
PULSE
N + 1
PULSE
Pd
0
Figure 6.6. Steady State Peak Case Temperature Rise
Using equation (5.3), the theoretical steady state case
temperature rise is:
TCSS * TA + (66.7 W) (30°CńW) + 2000°C
and
R(ton) + R (3 s) + (40°C measured rise)ń2000+ 0.02
From equation (5.4) and (5.1):
R (Tp) + (1 * e*180ń150) + .6988
R (ton ) Tp) + (1 * 1*183ń150) + .7047
Then from Figure 6:
delta TC = (1.111 + 46.225 + 1.333 − 46.61) 30 = 61.8°C
If the ambient temperature is 25°C, TC = 87°C.
COMPENSATING FOR MAXIMUM
SPECIFIED LEAKAGE
Identical value parallel resistors around each triac will
prevent breakdown resulting from mismatched leakages.
Figure 7 derives the method for selecting the maximum
allowed resistor size. A worst case design assumes that the
series pair will operate at maximum TJ and that one of the
triacs leaks at the full specified value while the other has no
leakage at all. A conservative design results when the toler-
ances in the shunt resistors place the highest possible resis-
tor across the low leakage unit and the lowest possible
resistor around the high leakage unit.
This method does not necessarily provide equal voltage
balancing. It prevents triac breakover. Perfect voltage shar-
ing requires expensive high-wattage resistors to provide
large bleeder currents.
V1 +
VSR1
R1 ) R2
)
DILR1R2
R1 ) R2
Let R1 = R (1 + p) and R2 = R (1−p) where
R = Nominal resistor value
p = 0.05 for 5% tolerance, etc.
R x
2 VDRM * VS (1 ) p)
DIL (1 * p2)
Worst case becomes:
and IDRM (T1) = 0; IDRM (T2) = Spec. max. value
ΔIL = Spec. Max. Value
IDRM (T2)
IDRM (T1)
R1
T1
ΔIL
T2
VS
I1
R2
I2
V1
Figure 6.7. Maximum Allowed Resistor for Static
Voltage Sharing](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-146-320.jpg)
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Ideally, turn-on speed mismatch should not be allowed to
force the slower thyristor into breakdown. An RC snubber
across each thyristor prevents this. In the worst case, one
device turns on instantly while the other switches at the
slowest possible turn-on time. The rate of voltage rise at the
slower device is roughly dV
dt
+
VIRs
2L
, where VI is the maxi-
mum voltage across L. This rate should not allow the volt-
age to exceed VDRM in less than Tgt to prevent breakover.
But what if the thyristors are operated without a snubber, or
if avalanche occurs because of a transient overvoltage
condition?
The circuit in Figure 13 was constructed to investigate
this behavior. The capacitor, resistor, and inductor create a
pulse forming network to shape the current wave. The ini-
tial voltage on the capacitor was set by a series string of
sidac bidirectional breakover devices.
Test results showed that operation of the triac switch was
safe as long as the rate of current rise was below 200 A/μs.
This was true even when the devices turned on because of
breakover. However, a 0.002 μf capacitor with no series
limiting impedance was sufficient to cause damage in the
Q3 firing polarity.
Circuit malfunctions because of breakover will be tem-
porary if the triac is not damaged. Test results suggest that
there will be no damage when the series inductance is suffi-
cient to hold dl/dt to acceptable values. Highly energetic
transients such as those resulting from lightning strikes can
cause damage to the thyristor by I2t surge overstress.
Device survival requires the use of voltage limiting devices
in the circuit and dV
dt
limiting snubbers to prevent unwanted
turn-on. Alternatively, a large triac capable of surviving the
surge can be used.
DQ for turn-off at I
H
DQ + ŕ
t2
t1
Ipk SINwt dt +
Ipk
w
(cos wt1 * cos wt2)
IH1 + Ipk Sinwt1
thus t1 + 1
w
Sin*1
IH1
Ipk
Worst case : IH2 + 0; f2 + wt2 + p
DQ +
Ipk
w
(1 ) cos[SIN*1
IH1
Ipk
])
DQ +
Ipk
wȧ
ȡ
Ȣ
1 ) I * ǒIH1
Ipk
Ǔ
2
Ǹ ȧ
ȣ
Ȥ
IH2
T1
ΔQ
T2
IH1
ωt = 0 t1 t2
lpk
Δ
Q
Figure 6.14. Forward Recovery Charge for Turn-Off at lH](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-151-320.jpg)
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222
Assume that the response curve in Figure 8.1 for a die
area of 58,000 square mils applies. Also, that the device is
mounted on an MS−15 heat sink using Dow Corning
DC340 silicone compound with an air flow of 1.0 lb/min
flowing across the heat−sink. (From MS−15 Data Sheet,
RθCS = 0.1°C/W and RθSA = 0.55°C/W).
Procedure: Average each pulse over the period using
equation 1−3 (Appendix A, Method 2), i.e.,
Pavg + 0.7 Pr 0.71
tr
t
) Pon ton
t
) 0.7 Pf 0.71
tf
t
+ (0.7) (900) (0.71)
(20)
500
) (18)
(150)
500
) (0.7) (900) (0.71) 80
500
+ 17.9 ) 5.4 ) 71.5
+ 94.8 W
T1 = [Pavg + (0.7 Pr − Pavg) @ r(t1 − to)] RθJC
From equation 1−4, Method 2A:
At this point it is observed that the thermal response
curves of Figure 8.1 do not extend below 100 μs. Heat
transfer theory for one dimensional heat flow indicates that
the response curve should follow the tǸ law at small times.
Using this as a basis for extending the curve, the response
at 14.2 μs is found to be 0.023.
We then have:
T1 = [94.8 + (630 − 94.8).023] (0.5)
T1 = (107.11)(0.5) = 53.55°C
For T2 we have, by using superposition:
T2 = [Pavg − Pavg @ r(t2 − to) + 0.7 Pr @
T2 = r(t2 − to) − 0.7 Pr @ r(t2 − t1) + Pon @
T2 = r(t2 − t1)] RθJC
T2 = [Pavg + (0.7 Pr − Pavg) @ r(t2 − to) +
T2 = (Pon − 0.7 Pr) @ r(t2 − t1)] RθJC
T2 = [94.8 + (630 − 94.8) @ r(164 μs) + (18 − 630)
T2 = @ r(150 μs)] (0.5)
T2 = [94.8 + (535.2)(.079) − (612)(.075)] (0.5)
T2 = [94.8 + 42.3 − 45.9] (0.5)
T2 = (91.2)(0.5) = 45.6°C
Figure 8.8. Idealized Waveforms of IC, VCE and
PD in a DC to AC Inverter
(a)
(b)
(c)
(d)
PD
Pon
Pf
t0 t1 t2 t3
Time
Time
t(Time)
PD
IC
VCE
Collector−EmitterVoltageCollectorCurrentPowerDissipation
t(Time)
Pon
Pr
T1 T2T3
0.7 Pf0.7 Pf 0.7 Pr
0.7 tr 0.7 tfton
tontoff
tf tr
t
For the final point T3 we have:
T3 = [Pavg − Pavg @ r(t3 − to) + 0.7 Pr @
T3 = r(t3 − to) − 0.7 Pr @ r(t3 − t1) + Pon @
T3 = r(t3 − t1) − Pon @ r(t3 − t2)
T3 = + 0.7 Pf @ r(t3 − t2)] RθJC
T3 = [Pavg + (0.7 Pr − Pavg) @ r(t3 − to) +
T3 = (Pon − 0.7 Pr) @ r(t3 − t1) + (0.7 Pf − Pon)
T3 = @ r(t3 − t2)] RθJC
T3 = [94.8 + (535.2) @ r(221 μs) + (−612) @ r(206.8 μs)
T3 = + (612) @ r(56.8μs)] (0.5)
T3 = [94.8 + (535.2)(0.09) − (612) (0.086) +
T3 = (612)(0.045)] (0.5)
T3 = [94.8 + 481.7− 52.63 + 27.54] (0.5)
T3 = (117.88)(0.5) = 58.94°C](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-222-320.jpg)
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The junction temperature at the end of the rise, on, and
fall times, TJ1, TJ2, and TJ3, is as follows:
TJ1 = T1 + TA + RθCA @ Pavg
RθCA = RθCS = RθSA = 0.1 + 0.55
TJ1 = 53.55 + 50 + (0.65)(94.8) = 165.17°C
TJ2 = T2 + TA + RθCA @ Pavg
TJ2 = 45.6 + 50 + (0.65)(94.8)
TJ2 = 157.22°C
TJ3 = T3 + TA + RθCA @ Pavg
TJ3 = 58.94 + 50 + (0.65)(94.8)
TJ3 = 170.56°C
TJ(avg) = Pavg (RθJC + RθCS + RθSA) + TA
TJ(avg) = (94.8)(0.5 + 0.1 + 0.55) + 50
TJ(avg) = (94.8)(1.15) + 50 = 159.02°C
Inspection of the results of the calculations T1, T2, and
T3 reveal that the term of significance in the equations is
the average power. Even with the poor switching times
there was a peak junction temperature of 11.5°C above the
average value. This is a 7% increase which for most
applications could be ignored, especially when switching
times are considerably less. Thus the product of average
power and steady state thermal resistance is the determin-
ing factor for junction temperature rise in this application.
SUMMARY
This report has explained the concept of transient
thermal resistance and its use. Methods using various
degrees of approximations have been presented to deter-
mine the junction temperature rise of a device. Since the
thermal response data shown is a step function response,
modeling of different wave shapes to an equivalent
rectangular pulse of pulses has been discussed.
The concept of a duty cycle family of curves has also
been covered; a concept that can be used to simplify
calculation of the junction temperature rise under a
repetitive pulse train.
APPENDIX A METHODS OF SOLUTION
In the examples, a type 2N3647 transistor will be used;
its steady state thermal resistance, RθJC, is 35°C/W and its
value for r(t) is shown in Figure A1.
Definitions:
P1, P2, P3 ... Pn = power pulses (Watts)
T1, T2, T3 ... Tn = junction to case temperature at
T end of P1, P2, P3 ... Pn
t0, t1, t2, ... tn = times at which a power pulse
begins or ends
r(tn − tk) = transient thermal resistance factor at
end of time interval (tn − tk).
Table 8.1. Several Possible Methods of Solutions
1. Junction Temperature Rise Using Pulse−By−Pulse
Method
A. Temperature rise at the end of the nth pulse for pulses
with unequal amplitude, spacing, and duration.
B. Temperature rise at the end of the nth pulse for pulses
with equal amplitude, spacing, and duration.
2. Temperature Rise Using Average Power Concept
Under Steady State Conditions For Pulses Of Equal
Amplitude, Spacing, And Duration
A. At the end of the nth pulse.
B. At the end of the (n + 1) pulse.
3. Temperature Rise Using Average Power Concept
Under Transient Conditions.
A. At the end of the nth pulse for pulses of equal
amplitude, spacing and duration.
B. At the end of the n + 1 pulse for pulses of equal
amplitude, spacing and duration.
C. At the end of the nth pulse for pulses of unequal
amplitude, spacing and duration.
D. At the end of the n + 1 pulse for pulses of unequal
amplitude, spacing and duration.
METHOD 1A − FINDING TJ AT THE END OF THE Nth
PULSE IN A TRAIN OF UNEQUAL AMPLITUDE,
SPACING, AND DURATION
General Equation:
Tn + ȍ
n
i+1
Pi [r(t2n−1 − t2i−2) (1−1)
− r(tn−1 − t2i−1)]RθJC
where n is the number of pulses and Pi is the peak value
of the ith pulse.
To find temperature at the end of the first three pulses,
Equation 1−1 becomes:
T1 = P1 r(t1) RθJC (1−1A)
T2 = [P1 r(t3) − P1 r(t3 − t1) (1−1B)
T2 = + P2 r(t3 − t2)] RθJC
T3 = [P1 r(t5) − P1 r(t5 − t1) + P2 r(t5 − t2) (1−1C)
T3 = − P2 r(t5 − t3) + P3 r(t5 − t4)] RθJC
Example:
Conditions are shown on Figure 4 as:
P1 = 40 W
P2 = 20 W
P3 = 30 W
t0 = 0
t1 = 0.1 ms
t2 = 0.3 ms
t3 = 1.3 ms
t4 = 3.3 ms
t5 = 3.5 ms
Therefore,
t1 − t0 = 0.1 ms
t2 − t1 = 0.2 ms
t3 − t2 = 1 ms
t4 − t3 = 2 ms
t5 − t4 = 0.2 ms
t3 − t1 = 1.2 ms
t5 − t1 = 3.4 ms
t5 − t2 = 3.2 ms
t5 − t3 = 2.2 ms](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-223-320.jpg)
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Procedure:
Find r(tn − tk) for preceding time intervals from Figure 8.2,
then substitute into Equations 1−1A, B, and C.
T1 = P1 r(t1) RθJC = 40 @ 0.05 @ 35 = 70°C
T2 = [P1 r(t3) − P1 r(t3 − t1) + P2 r(t3 − t2)] RθJC
T2 = [40 (0.175) − 40 (0.170) + 20 (0.155)] 35
T2 = [40 (0.175 − 0.170) + 20 (0.155)] 35
T2 = [0.2 + 3.1] 35 = 115.5°C
T3 = [P1 r(t5) − P1 r(t5 − t1) + P2 r(t5 − t2)
T3 = − P2 r(t5 − t3) + P3 r(t5 − t4)] θJC
T3 = [40 (0.28) − 40 (0.277) + 20 (0.275) − 20 (0.227)
T3 = + 30 (0.07)] 35
T3 = [40 (0.28 − 0.277) + 20 (0.275 − 0.227)
T3 = + 30 (0.07)] 35
T3 = [0.12 + 0.96 + 2.1]{ 35 = 3.18 @ 35 = 111.3°C
Note, by inspecting the last bracketed term in the
equations above that very little residual temperature is left
from the first pulse at the end of the second and third pulse.
Also note that the second pulse gave the highest value of
junction temperature, a fact not so obvious from inspection
of the figure. However, considerable residual temperature
from the second pulse was present at the end of the third
pulse.
METHOD 1B − FINDING TJ AT THE END OF THE Nth
PULSE IN A TRAIN OF EQUAL AMPLITUDE, SPACING,
AND DURATION
The general equation for a train of equal repetitive pulses
can be derived from Equation 1−1. Pi = PD, ti = t, and the
spacing between leading edges or trailing edges of adjacent
pulses is τ.
General Equation:
ȍ
n
i+1
r[(n − i) τ +
t]
(1−2)
− r[(n − i) τ]
Tn = PDRθJC
Expanding:
Tn = PD RθJC r[(n − 1) τ + t] − r[(n − 1) τ]
Tn = + r[(n − 2) τ + t) − r[(n − 2) τ] + r[(n − 3)
Tn = τ + t] − r[(n − 3) τ] + . . . + r[(n − i) τ + t]
Tn = − r[(n − i) τ] . . . . . + r(t)] (1−2A)
Relative amounts of temperature residual from P1, P2, and
P3 respectively are indicated by the terms in brackets.
{
For 5 pulses, equation 1−2A is written:
T5 = PD RθJC [r(4 τ + t) − r(4τ) + r(3τ + t)]
T5 = − r(3τ) + r(2τ + t) − r(2τ) + r(τ + t)
T5 = − r(τ) + r(t)]
Example:
Conditions are shown on Figure 8.5 substituting values
into the preceding expression:
T5 = (5) (35) [r(4.20 + 5) − r(4.20) + r(3.20 + 5)
T5 = + r(3.20) + r(2.20 + 5) − r(2.20) + r(20 + 5)
T5 = − r(20) + r(5)]
T5 = (5) (35) [0.6 − 0.76 + 0.73 − 0.72 + 0.68
T5 = − 0.66 + 0.59 − 0.55 + 0.33] − (5)(35)(0.40)
T5 = 70.0°C
Note that the solution involves the difference between
terms nearly identical in value. Greater accuracy will be
obtained with long or repetitive pulse trains using the
technique of an average power pulse as used in Methods 2
and 3.
METHOD 2 − AVERAGE POWER METHOD, STEADY
STATE CONDITION
The essence of this method is shown in Figure 8.6.
Pulses previous to the nth pulse are averaged. Temperature
due to the nth or n + 1 pulse is then calculated and
combined properly with the average temperature.
Assuming the pulse train has been applied for a period of
time (long enough for steady state conditions to be
established), we can average the power applied as:
Pavg + PD
t
t
(1−3)
METHOD 2A − FINDING TEMPERATURE AT THE END
OF THE Nth PULSE
Applicable Equation:
(1−4)Tn = [Pavg + (PD − Pavg) r(t)] RθJC
or, by substituting Equation 1−3 into 1−4,
Tn + ƪt
t ) ǒ1– t
t
Ǔ r(t)ƫPD RqJC (1−5)
The result of this equation will be conservative as it adds
a temperature increase due to the pulse (PD − Pavg) to the
average temperature. The cooling between pulses has not
been accurately accounted for; i.e., TJ must actually be less
than TJ(avg) when the nth pulse is applied.](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-224-320.jpg)
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Example: Find Tn for conditions of Figure 8.5.
Procedure: Find Pavg from equation (1−3) and
substitute values in equation (1−4) or
(1−5).
Tn = [(1.25) + (5.0 − 1.25)(0.33)] (35)
Tn = 43.7 + 43.2 = 86.9°C
METHOD 2B − FINDING TEMPERATURE AT THE END
OF THE N + 1 PULSE
Applicable Equation:
Tn + 1 = [Pavg + (PD − Pavg) r(t + τ)
Tn + 1 + PD r(t) − PD r(τ)] RθJC
(1−6)
or, by substituting equation 1−3 into 1−6,
(1−7)
t
t ) ǒ1– t
t
Ǔr(t ) t)Tn + 1 =
) r(t) * r(t) PDRθJC
Example: Find Tn for conditions of Figure 8.5.
Procedure: Find Pavg from equation (1−3) and
substitute into equation (1−6) or (1−7).
Tn + 1 = [(1.25) + (5 − 1.25)(0.59) + (5)(0.33)
Tn + 1 − (5)(0.56)] (35) = 80.9°C
Equation (1−6) gives a lower and more accurate value for
temperature than equation (1−4). However, it too gives a
higher value than the true TJ at the end of the n + 1th pulse.
The error occurs because the implied value for TJ at the end
of the nth pulse, as was pointed out, is somewhat high.
Adding additional pulses will improve the accuracy of the
calculation up to the point where terms of nearly equal
value are being subtracted, as shown in the examples using
the pulse by pulse method. In practice, however, use of this
method has been found to yield reasonable design values
and is the method used to determine the duty cycle of
family of curves − e.g., Figure 8.2.
Note that the calculated temperature of 80.9°C is 10.9°C
higher than the result of example 1B, where the tempera-
ture was found at the end of the 5th pulse. Since the thermal
response curve indicates thermal equilibrium in 1 second,
50 pulses occurring 20 milliseconds apart will be required
to achieve stable average and peak temperatures; therefore,
steady state conditions were not achieved at the end of the
5th pulse.
METHOD 3 − AVERAGE POWER METHOD,
TRANSIENT CONDITIONS
The idea of using average power can also be used in the
transient condition for a train of repetitive pulses. The
previously developed equations are used but Pavg must be
modified by the thermal response factor at time t(2n − 1).
METHOD 3A − FINDING TEMPERATURE AT THE END
OF THE Nth PULSE FOR PULSES OF EQUAL
AMPLITUDE, SPACING AND DURATION
Applicable Equation:
(1−8)Tn + ƪt
t r t(2n–1) ) ǒ1 – t
t
Ǔr(t)ƫ PD RθJC
Conditions: (See Figure 8.5)
Procedure: At the end of the 5th pulse
(See Figure 8.7) . . .
T5 = [5/20 @ r(85) + (1 − 5/20)r(5)] (5)(35)
T5 = [(0.25)(0765) + (0.75)(0.33)] (175)
T5 = 77°C
This value is a little higher than the one calculated by
summing the results of all pulses; indeed it should be,
because no cooling time was allowed between Pavg and the
nth pulse. The method whereby temperature was calculated
at the n + 1 pulse could be used for greater accuracy.
METHOD 3B − FINDING TEMPERATURE AT THE END
OF THE N + 1 PULSE FOR PULSES OF EQUAL
AMPLITUDE, SPACING AND DURATION
Applicable Equation:
(1−9)
t
t r(t2n–1) ) ǒ1 – t
t
ǓTn + 1 =
r(t ) t) ) r(t) * r(t) PD RθJC
Example: Conditions as shown on Figure 8.5. Find
temperature at the end of the 5th pulse.
For n + 1 = 5, n = 4, t2n−1 = t7 = 65 ms,
5
20
r(65 ms) ) ǒ1 – 5
20
Ǔ r(25 ms)T5 =
) r(5 ms) * r(20 ms) (5)(35)
T5 = [(0.25)(0.73) + (0.75)(0.59) + 0.33 − 0.55](5)(35)
T5 = 70.8°C](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-225-320.jpg)
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The answer agrees quite well with the answer of Method
1B where the pulse−by−pulse method was used for a
repetitive train.
METHOD 3C − FINDING TJ AT THE END OF THE Nth
PULSE IN A RANDOM TRAIN
The technique of using average power does not limit
itself to a train of repetitive pulses. It can be used also
where the pulses are of unequal magnitude and duration.
Since the method yields a conservative value of junction
temperature rise it is a relatively simple way to achieve a
first approximation. For random pulses, equations 1−4
through 1−7 can be modified. It is necessary to multiply
Pavg by the thermal response factor at time t(2n − 1). Pavg is
determined by averaging the power pulses from time of
application to the time when the last pulse starts.
Applicable Equations:
ȍ
n
i+1
Pi (1−10)General: Pavg =
t(2i−1)−t(2i−2)
t(2n)−t(2i−2)
For 3 Pulses:
(1−11)Pavg = P1
t1 − t0
t4 − t0
t3 − t2
t4 − t2
+ P2
Example: Conditions are shown on Figure 8.4 (refer to
Method 1A).
Procedure: Find Pavg from equation 1−3 and the junction
temperature rise from equation 1−4.
Conditions: Figure 8.4
Pavg
0.1
3.3
) 20 1
3
+ 1.21 ) 6.67= 40 @
= 7.88 Watts
T3 = [Pavg r(t5) + (P3 − Pavg) r(t5 − t4)] RθJC
= [7.88 (0.28) + (30 − 7.88) @ 0.07] 35
= [2.21 + 1.56] 35 = 132°C
This result is high because in the actual case considerable
cooling time occurred between P2 and P3 which allowed TJ
to become very close to TC. Better accuracy is obtained
when several pulses are present by using equation 1−10 in
order to calculate TJ − tC at the end of the nth + 1 pulse. This
technique provides a conservative quick answer if it is easy
to determine which pulse in the train will cause maximum
junction temperature.
METHOD 3D − FINDING TEMPERATURE AT THE END
OF THE N + 1 PULSE IN A RANDOM TRAIN
The method is similar to 3C and the procedure is
identical. Pavg is calculated from Equation 1−10 modified
by r(t2n − 1) and substituted into equation 1−6, i.e.,
Tn + 1 = [Pavg r(t2n−1) + (PD − Pave) r(t2n−1 −
Tn + 1 = t2n−2) + PD r(t2n+1 − t2n) − PD r(t2n+1
Tn + 1 = − t2n−1)] RθJC
The previous example cannot be worked out for the n + 1
pulse because only 3 pulses are present.
Table 8.2. Summary Of Numerical Solution For The
Repetitive Pulse Train Of Figure 5
Temperature
Desired
Temperature Obtained, °C
Pulse by
Pulse
Average Power
Nth Pulse
Average Power
N + 1 Pulse
At End of
5th Pulse
70.0 (1B) 77 (3A) 70.8 (3B)
Steady State
Peak
− 86.9 (2A) 80.9 (2B)
Note: Number in parenthesis is method used.
Figure 8.9. 2N3467 Transient Thermal Response
1.0
0.1
0.01
0.01 0.1 1.0 10 100 1000
t, Time (ms)
r(t),TransientThermalResistance
(Normalized)
0.2
0.02
0.3
0.03
0.5
0.05
0.7
0.07
0.02 0.2 2.0 20 2000.05 0.5 5.0 50 500](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-226-320.jpg)
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235
APPENDIX II
CHARGE AND PULSE WIDTH
In the region of large pulse widths using current
triggering, where transit time effects are not a factor, we
can consider the input gate charge for triggering, Qin, as
consisting of three components:
1. Triggering charge Qtr, assumed to be constant.
2. Charge lost in recombination, Qr, during current
regeneration prior to turn−on.
3. Charge drained, Qdr, which is by−passed through the
built−in gate cathode shunt resistance (the presence of
this shunting resistance is required to increase the dv/dt
capability of the device).
Mathematically, we have
Qin = Qtr + Qdr + Qr = IGτ (1)
Qr is assumed to be proportional to Qin; to be exact,
Qr = Qin (1 − exp−τ/τ1) (2)
where IG =
τ =
τ1 =
gate current,
pulse width of gate current,
effective life time of minority carriers in the
bases
The voltage across the gate to cathode P−N junction during
forward bias is given by VGK (usually 0.6 V for silicon).*
The gate shunt resistance is Rs (for the MCR729, typically
100 ohms), so the drained charge can be expressed by
Qdr +
VGC
Rs
t (3)
Combining equations (1), (2), and (3), we get
Qin + IGt + (Qtr )
VGC
Rs
t) exp. tńt1 (4)
Note that at region A and C of Figure 3.3(c) Qin has an
increasing trend with pulse width as qualitatively described
by Equation (4).
Assume life time at the temperature range of operation
increases as some power of temperature
τ1 = KTm (5)
where K and m are positive real numbers. Combining
Equations (4) and (5), we can get the slope of Qin with
respect to temperature to be
slope +
dQin
dT
+ – m(Qtr )
VGC
Rs
t) t
t1
exp.tńt1
T
(6)
In reality, Qtr is not independent of temperature, in which
case the Equation (6) must be modified by adding an
additional term to become:
slope + –m(Qtr )
VGC
Rs
t) t
t1
exp.tńt1
T
)
dQtr
dT
exptńt1 (7)
Physically, not only does Qtr decrease with temperature
so that dQtr/dT is a negative number, but also |dQtr/dTI
decreased with temperature as does |dα/dTI in the tempera-
ture range of interest.
Equation (6) [or (7)] indicates two things:
1. The rate of change of input trigger charge decreases as
temperature (life time) increases.
2. The larger the pulse width of gate trigger current, the
faster the rate of change of Qin with respect to change
in temperature. Figure 3.11 shows these trends.
*VGC is not independent of IG. For example, for the
MCR729 the saturation VGC is typically 1 V, but at lower
IG’s the VGC is also smaller, e.g. for IG = 5 mA, VGC is
typically 0.3 V.](https://image.slidesharecdn.com/thyristortheoryanddesignconsiderations-141123162253-conversion-gate02/85/Thyristor-theory-and-design-considerations-235-320.jpg)
Thyristor theory and design considerations
- 1. http://onsemi.com 1 Thyristor Theory and Design Considerations Handbook HBD855/D Rev. 1, Nov−2006 © SCILLC, 2005 Previous Edition © 2005 as Excerpted from DL137/D “All Rights Reserved’’
- 2. http://onsemi.com 2 ABOUT THYRISTORS Thyristors can take many forms, but they have certain things in common. All of them are solid state switches which act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low−impedance current paths and remain in that condition until the current either stops or drops below a minimum value called the holding level. Once a thyristor has been triggered, the trigger current can be removed without turning off the device. Silicon controlled rectifiers (SCRs) and triacs are both members of the thyristor family. SCRs are unidirectional devices where triacs are bidirectional. An SCR is designed to switch load current in one direction, while a triac is designed to conduct load current in either direction. Structurally, all thyristors consist of several alternating layers of opposite P and N silicon, with the exact structure varying with the particular kind of device. The load is applied across the multiple junctions and the trigger current is injected at one of them. The trigger current allows the load current to flow through the device, setting up a regenerative action which keeps the current flowing even after the trigger is removed. These characteristics make thyristors extremely useful in control applications. Compared to a mechanical switch, a thyristor has a very long service life and very fast turn on and turn off times. Because of their fast reaction times, regenerative action and low resistance once triggered, thyristors are useful as power controllers and transient overvoltage protectors, as well as simply turning devices on and off. Thyristors are used in motor controls, incandescent lights, home appliances, cameras, office equipment, programmable logic controls, ground fault interrupters, dimmer switches, power tools, telecommunication equipment, power supplies, timers, capacitor discharge ignitors, engine ignition systems, and many other kinds of equipment. Although thyristors of all sorts are generally rugged, there are several points to keep in mind when designing circuits using them. One of the most important is to respect the devices’ rated limits on rate of change of voltage and current (dv/dt and di/dt). If these are exceeded, the thyristor may be damaged or destroyed. On the other hand, it is important to provide a trigger pulse large enough and fast enough to turn the gate on quickly and completely. Usually the gate trigger current should be at least 50 percent greater than the maximum rated gate trigger current. Thyristors may be driven in many different ways, including directly from transistors or logic families, power control integrated circuits, by optoisolated triac drivers, programmable unijunction transistors (PUTs) and SIDACs. These and other design considerations are covered in this manual. Of interest too, is a new line of Thyristor Surge Suppressors in the surface mount SMB package covering surge currents of 50, 80 and 100 amps, with breakover voltages from 77 to 400 volts. NP Series Thyristor Surge Protector Devices (TSPD) protect telecommunication circuits such as central office, access, and customer premises equipment from overvoltage conditions. These are bidirectional devices so they are able to have functionality of 2 devices in one package, saving valuable space on board layout. These devices will act as a crowbar when overvoltage occurs and will divert the energy away from circuit or device that is being protected. Use of the NP Series in equipment will help meet various regulatory requirements including: GR−1089−CORE, IEC 61000−4−5, ITU K.20/21/45, IEC 60950, TIA−968−A, FCC Part 68, EN 60950, UL 1950. See ON Semiconductor application note AND8022/D for additional information.
- 3. http://onsemi.com 3 Sections 1 thru 9 CHAPTER 1 Theory and Applications Page Section 1: Symbols and Terminology 4. . . . . . . . . . . . . . Section 2: Theory of Thyristor Operation 10. . . . . . . . . Basic Behavior 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristics 13. . . . . . . . . . . . . . . . . . . . . . False Triggering 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Theory of SCR Power Control 16. . . . . . . . . . . . . . . . . . Triac Theory 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Methods of Control 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . Zero Point Switching Techniques 25. . . . . . . . . . . . . . . . Section 3: Thyristor Drivers and Triggering 29. . . . . . . Pulse Triggering of SCRs 29. . . . . . . . . . . . . . . . . . . . . . Effect of Temperature, Voltage and Loads 33. . . . . . . . Using Negative Bias and Shunting 35. . . . . . . . . . . . . . . Snubbing Thyristors 38. . . . . . . . . . . . . . . . . . . . . . . . . . . Using Sensitive Gate SCRs 40. . . . . . . . . . . . . . . . . . . . Drivers: Programmable Unijunction Transistors 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section 4: The SIDAC, A New High Voltage Bilateral Trigger 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section 5: SCR Characteristics 60. . . . . . . . . . . . . . . . . . SCR Turn−Off Characteristics 60. . . . . . . . . . . . . . . . . . . SCR Turn−Off Mechanism 60. . . . . . . . . . . . . . . . . . . . . SCR Turn−Off Time tq 60. . . . . . . . . . . . . . . . . . . . . . . . . Parameters Affecting tq 65. . . . . . . . . . . . . . . . . . . . . . . . Characterizing SCRs for Crowbar Applications 71. . . . Switches as Line−Type Modulators 79. . . . . . . . . . . . . . Parallel Connected SCRs 85. . . . . . . . . . . . . . . . . . . . . . RFI Suppression in Thyristor Circuits 89. . . . . . . . . . . . Section 6: Applications 93. . . . . . . . . . . . . . . . . . . . . . . . . Phase Control with Thyristors 93. . . . . . . . . . . . . . . . . . . Motor Control 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Control with Trigger Devices 102. . . . . . . . . . . . . Cycle Control with Optically Isolated Triac Drivers 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Power Control with Solid−State Relays 110. . . . . . . Triacs and Inductive Loads 114. . . . . . . . . . . . . . . . . . . . Inverse Parallel SCRs for Power Control 117. . . . . . . . Page Interfacing Digital Circuits to Thyristor Controlled AC Loads 118. . . . . . . . . . . . . . . . . . . . . . . . . DC Motor Control with Thyristors 127. . . . . . . . . . . . . . . Programmable Unijunction Transistor (PUT) Applications 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triac Zero−Point Switch Applications 136. . . . . . . . . . . AN1045 — Series Triacs in AC High Voltage Switching Circuits 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . AN1048 — RC Snubber Networks for Thyristor Power Control and Transient Suppression 152. . . . . . . AND8005 — Automatic AC Line Voltage Selector 174. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND8006 — Electronic Starter for Flourescent Lamps 177. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND8007 — Momentary Solid State Switch for Split Phase Motors 181. . . . . . . . . . . . . . . . . . . . . . . . . AND8008 — Solid State Control Solutions for Three Phase 1 HP Motor 186. . . . . . . . . . . . . . . . . . . AND8015 — Long Life Incandescent Lamps using SIDACs 194. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND8017 — Solid State Control for Bi−Directional Motors 198. . . . . . . . . . . . . . . . . . . . . . . . . Section 7: Mounting Techniques for Thyristors 201. . . Mounting Surface Considerations 202. . . . . . . . . . . . . . Thermal Interface 203. . . . . . . . . . . . . . . . . . . . . . . . . . . . Insulation Considerations 204. . . . . . . . . . . . . . . . . . . . . Fastening Techniques 209. . . . . . . . . . . . . . . . . . . . . . . . Insulated Packages 210. . . . . . . . . . . . . . . . . . . . . . . . . . Surface Mount Devices 212. . . . . . . . . . . . . . . . . . . . . . . Thermal System Evaluation 214. . . . . . . . . . . . . . . . . . . Section 8: Reliability and Quality 218. . . . . . . . . . . . . . . . Using Transient Thermal Resistance Data in High Power Pulsed Thyristor Applications 218. . . . . . . Thyristor Construction 230. . . . . . . . . . . . . . . . . . . . . . . . In−Process Controls and Inspections 230. . . . . . . . . . . Reliability Tests 231. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress Testing 233. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environmental Testing 233. . . . . . . . . . . . . . . . . . . . . . . . Section 9: Appendices 234. . . . . . . . . . . . . . . . . . . . . . . . .
- 4. http://onsemi.com 4 SECTION 1 SYMBOLS AND TERMINOLOGY SYMBOLS The following are the most commonly used schematic symbols for Thyristors: Name of Device Symbol Silicon Controlled Rectifier (SCR) Triac Programmable Unijunction Transistor (PUT) Thyristor Surge Protective Devices & Sidac MT1 MT2 MT1 G MT2 K G A K G A
- 5. http://onsemi.com 5 THYRISTOR TERMINOLOGY (The following terms are used in SCR and TRIAC specifications.) Symbol Terminology Definition di/dt CRITICAL RATE OF RISE OF ON−STATE CURRENT The maximum rate of change of current the device will withstand after switching from an off−state to an on−state when using recommended gate drive. In other words, the maximum value of the rate of rise of on−state current which a Triac or SCR can withstand without damage. (di/dt)c RATE OF CHANGE OF COMMUTATING CURRENT (Triacs) Is the ability of a Triac to turn off itself when it is driving an inductive load and a resultant commutating dv/dt condi- tion associated with the nature of the load. dv/dt CRITICAL RATE OF RISE OF OFF−STATE VOLTAGE Also, commonly called static dv/dt. It is the minimum value of the rate of rise of forward voltage which will cause switching from the off−state to the on−state with gate open. IDRM PEAK REPETITIVE BLOCKING CURRENT The maximum value of current which will flow at VDRM and specified temperature when the SCR or Triac is in the off−state. Frequently referred to as leakage current in the forward off−state blocking mode. IGM FORWARD PEAK GATE CURRENT (SCR) PEAK GATE CURRENT (Triac) The maximum peak gate current which may be safely applied to the device to cause conduction. IGT GATE TRIGGER CURRENT The maximum value of gate current required to switch the device from the off−state to the on−state under specified conditions. The designer should consider the maximum gate trigger current as the minimum trigger current value that must be applied to the device in order to assure its proper triggering. IH HOLDING CURRENT The minimum current that must be flowing (MT1 & MT2; cathode and anode) to keep the device in a regenerative on−state condition. Below this holding current value the device will return to a blocking state, off condition. IL LATCHING CURRENT The minimum current that must be applied through the main terminals of a Triac (or cathode and anode of an SCR) in order to turn from the off−state to the on−state while its IGT is being correctly applied. IRRM PEAK REPETITIVE REVERSE BLOCKING CURRENT The maximum value of current which will flow at VRRM and specified temperature when the SCR or Triac is in the reverse mode, off−state. Frequently referred to as leakage current in the reverse off−state blocking mode. IT(AV) AVERAGE ON−STATE CURRENT (SCR) The maximum average on−state current the device may safely conduct under stated conditions without incurring damage.
- 6. http://onsemi.com 6 THYRISTOR TERMINOLOGY (The following terms are used in SCR and TRIAC specifications.) Symbol Terminology Definition ITM PEAK REPETITIVE ON−STATE CURRENT (SCR) (also called PEAK DISCHARGE CURRENT) Peak discharge current capability of a thyristor useful when connected to discharge peak current usually from a capacitor. This is a rarely specified parameter. (See MCR68 and MCR69 data sheets, for examples where it is specified.) IT(RMS) ON−STATE RMS CURRENT The maximum value of on−state rms current that can be applied to the device through the two main terminals of a Triac (or cathode and anode if an SCR) on a continuous basis. ITSM PEAK NON−REPETITIVE SURGE CURRENT The maximum allowable non−repetitive surge current the device will withstand at a specified pulse width, usually specified at 60 Hz. I2t CIRCUIT FUSING CONSIDERATIONS (Current squared time) The maximum forward non−repetitive overcurrent capa- bility that the device is able to handle without damage. Usually specified for one−half cycle of 60 Hz operation. PG(AV) FORWARD AVERAGE GATE POWER (SCR) AVERAGE GATE POWER (Triac) The maximum allowable value of gate power, averaged over a full cycle, that may be dissipated between the gate and cathode terminal (SCR), or main terminal 1 if a Triac. PGM FORWARD PEAK GATE POWER (SCR) PEAK GATE POWER (Triac) The maximum instantaneous value of gate power dissipation between gate and cathode terminal for an SCR or between gate and a main terminal MT1 for a Triac, for a short pulse duration. RθCA THERMAL RESISTANCE, CASE−TO−AMBIENT The thermal resistance (steady−state) from the device case to the ambient. RθJA THERMAL RESISTANCE, JUNCTION−TO−AMBIENT The thermal resistance (steady−state) from the semicon- ductor junction(s) to the ambient. RθJC THERMAL RESISTANCE, JUNCTION−TO−CASE The thermal resistance (steady−state) from the semicon- ductor junction(s) to a stated location on the case. RθJM THERMAL RESISTANCE, JUNCTION−TO−MOUNTING SURFACE The thermal resistance (steady−state) from the semicon- ductor junction(s) to a stated location on the mounting surface. TA AMBIENT TEMPERATURE The air temperature measured below a device in an environment of substantially uniform temperature, cooled only by natural air currents and not materially affected by radiant and reflective surfaces. TC CASE TEMPERATURE The temperature of the device case under specified conditions.
- 7. http://onsemi.com 7 THYRISTOR TERMINOLOGY (The following terms are used in SCR and TRIAC specifications.) Symbol Terminology Definition tgt TURN−ON TIME (SCR) (Also called Gate Controlled Turn−on Time) The time interval between a specified point at the beginning of the gate pulse and the instant when the device voltage has dropped to a specified low value during the switching of an SCR from the off state to the on state by a gate pulse. TJ OPERATING JUNCTION TEMPERATURE The junction temperature of the device at the die level as a result of ambient and load conditions. In other words, the junction temperature must be operated within this range to prevent permanent damage. tq TURN−OFF TIME (SCR) The time interval between the instant when the SCR current has decreased to zero after external switching of the SCR voltage circuit and the instant when the thyristor is capable of supporting a specified wave form without turning on. Tstg STORAGE TEMPERATURE The minimum and maximum temperature at which the device may be stored without harm with no electrical connections. VDRM PEAK REPETITIVE OFF−STATE FORWARD VOLTAGE The maximum allowed value of repetitive forward voltage which may be applied and not switch the SCR or Triac on or do damage to the thyristor. VGD GATE NON−TRIGGER VOLTAGE At the maximum rated operational temperature, and at a specified main terminal off−state voltage applied, this parameter specifies the maximum DC voltage that can be applied to the gate and still not switch the device from off−state to and on−state. VGM FORWARD PEAK GATE VOLTAGE (SCR) PEAK GATE VOLTAGE (Triac) The maximum peak value of voltage allowed between the gate and cathode terminals with these terminals forward biased for an SCR. For a Triac, a bias condition between the gate and main terminal MT1. VGT GATE TRIGGER VOLTAGE The gate dc voltage required to produce the gate trigger current. V(Iso) RMS ISOLATION VOLTAGE The dielectric withstanding voltage capability of a thyristor between the active portion of the device and the heat sink. Relative humidity is a specified condition. VRGM PEAK REVERSE GATE BLOCKING VOLTAGE (SCR) The maximum allowable peak reverse voltage applied to the gate on an SCR. Measured at a specified IGR which is the reverse gate current. VRRM PEAK REPETITIVE REVERSE OFF−STATE VOLTAGE The maximum allowed value of repetitive reverse voltage which may be applied and not switch the SCR or Triac on or do damage to the thyristor.
- 8. http://onsemi.com 8 THYRISTOR TERMINOLOGY (The following terms are used in SCR and TRIAC specifications.) Symbol Terminology Definition VTM PEAK FORWARD ON−STATE VOLTAGE (SCR) PEAK ON−STATE VOLTAGE (Triac) The maximum voltage drop across the main terminals at stated conditions when the devices are in the on−state (i.e., when the thyristor is in conduction). To prevent heating of the junction, the VTM is measured at a short pulse width and low duty cycle. ZθJA(t) TRANSIENT THERMAL IMPEDANCE, JUNCTION−TO−AMBIENT The transient thermal impedance from the semiconduc- tor junction(s) to the ambient. ZθJC(t) TRANSIENT THERMAL IMPEDANCE, JUNCTION−TO−CASE The transient thermal impedance from the semiconduc- tor junction(s) to a stated location on the case.
- 9. http://onsemi.com 9 Thyristor Surge Protector Devices (TSPD) and Sidac Terminology* Symbol Terminology Definition IBO BREAKOVER CURRENT The breakover current IBO is the corresponding parame- ter defining the VBO condition, that is, where breakdown is occurring. ID1, ID2 OFF−STATE CURRENT (TSPD) The maximum value of current which will flow at specific voltages (VD1 and VD2) when the TSPD is clearly in the off−state. Frequently referred to as leakage current. Ipps PULSE SURGE SHORT CIRCUIT CURRENT NON−REPETITIVE (TSPD) The maximum pulse surge capability of the TSPD (non−repetitive) under double exponential decay wave- form conditions. Ppk INSTANTANEOUS PEAK POWER DISSIPATION (TSPD) Defines the instantaneous peak power dissipation when the TSPD (thyristor surge suppressor devices) are subjected to specified surge current conditions. Rs SWITCHING RESISTANCE (Sidac) The effective switching resistance usually under a sinusoidal, 60 Hz condition. VBO BREAKOVER VOLTAGE It is the peak voltage point where the device switches to an on−state condition. V(BR) BREAKDOWN VOLTAGE (TSPD) VBR is the voltage where breakdown occurs. Usually given as a typical value for reference to the Design Engineer. VDM OFF−STATE VOLTAGE (TSPD) The maximum off−state voltage prior to the TSPD going into a characteristic similar to an avalanche mode. When a transient or line signal exceeds the VDM, the device begins to avalanche, then immediately begins to conduct. VT ON−STATE VOLTAGE (TSPD) The maximum voltage drop across the terminals at stated conditions when the TSPD devices are in the on−state (i.e., conduction). To prevent overheating, VT is measured at a short pulse width and a low duty cycle. * All of the definitions on this page are for ones that were not already previously defined under Triac and SCR terminology.
- 10. http://onsemi.com 10 SECTION 2 THEORY OF THYRISTOR OPERATION Edited and Updated To successfully apply thyristors, an understanding of their characteristics, ratings, and limitations is imperative. In this chapter, significant thyristor characteristics, the basis of their ratings, and their relationship to circuit design are discussed. Several different kinds of thyristors are shown in Table 2.1. Silicon Controlled Rectifiers (SCRs) are the most widely used as power control elements; triacs are quite popular in lower current (under 40 A) ac power applica- tions. Diacs, SUSs and SBSs are most commonly used as gate trigger devices for the power control elements. Table 2.1. Thyristor Types *JEDEC Titles Popular Names, Types Reverse Blocking Diode Thyristor {Four Layer Diode, Silicon {Unilateral Switch (SUS) Reverse Blocking Triode Thyristor {Silicon Controlled Rectifier {(SCR) Reverse Conducting Diode Thyristor {Reverse Conducting Four {Layer Diode Reverse Conducting Triode Thyristor {Reverse Conducting SCR Bidirectional Triode Thyristor {Triac * JEDEC is an acronym for the Joint Electron Device Engineering Councils, an industry standardization activity co−sponsored by the Electronic Industries Association (EIA) and the National Electrical Manufacturers Association (NEMA). {Not generally available. Before considering thyristor characteristics in detail, a brief review of their operation based upon the common two−transistor analogy of an SCR is in order. BASIC BEHAVIOR The bistable action of thyristors is readily explained by analysis of the structure of an SCR. This analysis is essentially the same for any operating quadrant of triac because a triac may be considered as two parallel SCRs oriented in opposite directions. Figure 2.1(a) shows the schematic symbol for an SCR, and Figure 2.1(b) shows the P−N−P−N structure the symbol represents. In the two−transistor model for the SCR shown in Figure 2.1(c), the interconnections of the two transistors are such that regenerative action occurs. Observe that if current is injected into any leg of the model, the gain of the transistors (if sufficiently high) causes this current to be amplified in another leg. In order for regeneration to occur, it is necessary for the sum of the common base current gains (α) of the two transistors to exceed unity. Therefore, because the junction leakage currents are relatively small and current gain is designed to be low at the leakage current level, the PNPN device remains off unless external current is applied. When sufficient trigger current is applied (to the gate, for example, in the case of an SCR) to raise the loop gain to unity, regeneration occurs and the on−state principal current is limited primarily by external circuit impedance. If the initiating trigger current is removed, the thyristor remains in the on state, providing the current level is high enough to meet the unity gain criteria. This critical current is called latching current. In order to turn off a thyristor, some change in current must occur to reduce the loop gain below unity. From the model, it appears that shorting the gate to cathode would accomplish this. However in an actual SCR structure, the gate area is only a fraction of the cathode area and very little current is diverted by the short. In practice, the principal current must be reduced below a certain level, called holding current, before gain falls below unity and turn−off may commence. In fabricating practical SCRs and Triacs, a “shorted emitter” design is generally used in which, schematically, a resistor is added from gate to cathode or gate to MT1. Because current is diverted from the N−base through the resistor, the gate trigger current, latching current and holding current all increase. One of the principal reasons for the shunt resistance is to improve dynamic perfor- mance at high temperatures. Without the shunt, leakage current on most high current thyristors could initiate turn−on at high temperatures.
- 11. http://onsemi.com 11 Sensitive gate thyristors employ a high resistance shunt or none at all; consequently, their characteristics can be altered dramatically by use of an external resistance. An external resistance has a minor effect on most shorted emitter designs. Figure 2.1. Two−transistor analogy of an SCR: (a) schematic symbol of SCR; (b) P−N−P−N structure represented by schematic symbol; (c) two−transistor model of SCR. P ANODE GATE CATHODE (b) N P N GATE ANODE CATHODE (a) ANODE GATE CATHODE IB1 IC2 (c) IC1 IB2 IK P N N P P N Junction temperature is the primary variable affect- ing thyristor characteristics. Increased temperatures make the thyristor easier to turn on and keep on. Consequently, circuit conditions which determine turn−on must be designed to operate at the lowest anticipated junction temperatures, while circuit condi- tions which are to turn off the thyristor or prevent false triggering must be designed to operate at the maximum junction temperature. Thyristor specifications are usually written with case temperatures specified and with electrical conditions such that the power dissipation is low enough that the junction temperature essentially equals the case temperature. It is incumbent upon the user to properly account for changes in characteristics caused by the circuit operating condi- tions different from the test conditions. TRIGGERING CHARACTERISTICS Turn−on of a thyristor requires injection of current to raise the loop gain to unity. The current can take the form of current applied to the gate, an anode current resulting from leakage, or avalanche breakdown of a blocking junction. As a result, the breakover voltage of a thyristor can be varied or controlled by injection of a current at the gate terminal. Figure 2.2 shows the interaction of gate current and voltage for an SCR. When the gate current Ig is zero, the applied voltage must reach the breakover voltage of the SCR before switching occurs. As the value of gate current is increased, however, the ability of a thyristor to support applied voltage is reduced and there is a certain value of gate current at which the behavior of the thyristor closely resembles that of a rectifier. Because thyristor turn−on, as a result of exceeding the breakover voltage, can produce high instantaneous power dissipation non−uniformly distributed over the die area during the switching transition, extreme temperatures resulting in die failure may occur unless the magnitude and rate of rise of principal current (di/dt) is restricted to tolerable levels. For normal operation, therefore, SCRs and triacs are operated at applied voltages lower than the breakover voltage, and are made to switch to the on state by gate signals high enough to assure complete turn−on indepen- dent of the applied voltage. On the other hand, diacs and other thyristor trigger devices are designed to be triggered by anode breakover. Nevertheless they also have di/dt and peak current limits which must be adhered to. Figure 2.2. Thyristor Characteristics Illustrating Breakover as a Function of Gate Current Ig4 Ig3 Ig2 Ig1 = 0 V − A triac works the same general way for both positive and negative voltage. However since a triac can be switched on by either polarity of the gate signal regardless of the voltage polarity across the main terminals, the situation is somewhat more complex than for an SCR. The various combinations of gate and main terminal polarities are shown in Figure 2.3. The relative sensitivity depends on the physical structure of a particular triac, but as a rule, sensitivity is highest in quadrant I and quadrant IV is generally considerably less sensitive than the others.
- 12. http://onsemi.com 12 Figure 2.3. Quadrant Definitions for a Triac MT2(+) MT2(−) G(−) G(+) QUADRANT II QUADRANT I MT2(+), G(−) MT2(+), G(+) QUADRANT III QUADRANT IV MT2(−), G(−) MT2(−), G(+) Gate sensitivity of a triac as a function of temperature is shown in Figure 2.4. Figure 2.4. Typical Triac Triggering Sensitivity in the Four Trigger Quadrants IGT,GATETRIGGERCURRENT(mA) 30 20 10 7 3 5 120−80 −60 −40 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) 3 4 QUADRANT 1 2 3 4 OFF−STATE VOLTAGE = 12 Vdc ALL QUADRANTS Since both the junction leakage currents and the current gain of the “transistor” elements increase with tempera- ture, the magnitude of the required gate trigger current decreases as temperature increases. The gate — which can be regarded as a diode — exhibits a decreasing voltage drop as temperature increases. Thus it is impor- tant that the gate trigger circuit be designed to deliver sufficient current to the gate at the lowest anticipated temperature. It is also advisable to observe the maximum gate current, as well as peak and average power dissipation ratings. Also in the negative direction, the maximum gate ratings should be observed. Both positive and negative gate limits are often given on the data sheets and they may indicate that protective devices such as voltage clamps and current limiters may be required in some applications. It is generally inadvisable to dissipate power in the reverse direction. Although the criteria for turn−on have been described in terms of current, it is more basic to consider the thyristor as being charge controlled. Accordingly, as the duration of the trigger pulse is reduced, its amplitude must be correspondingly increased. Figure 2.5 shows typical behavior at various pulse widths and temperatures. The gate pulse width required to trigger a thyristor also depends upon the time required for the anode current to reach the latching value. It may be necessary to maintain a gate signal throughout the conduction period in applications where the load is highly inductive or where the anode current may swing below the holding value within the conduction period. When triggering an SCR with a dc current, excess leakage in the reverse direction normally occurs if the trigger signal is maintained during the reverse blocking phase of the anode voltage. This happens because the SCR operates like a remote base transistor having a gain which is generally about 0.5. When high gate drive currents are used, substantial dissipation could occur in the SCR or a significant current could flow in the load; therefore, some means usually must be provided to remove the gate signal during the reverse blocking phase. Figure 2.5. Typical Behavior of Gate Trigger Current as Pulse Width and Temperature Are Varied IGTM,PEAKGATECURRENT(mA) 300 30 10 7 3 5 0.2 PULSE WIDTH (μs) 50 70 100 0.5 1 2 5 10 20 50 100 200 OFF−STATE VOLTAGE = 12 V TJ = −55°C 25°C 100°C LATCH AND HOLD CHARACTERISTICS In order for the thyristor to remain in the on state when the trigger signal is removed, it is necessary to have sufficient principal current flowing to raise the loop gain to unity. The principal current level required is the latching current, IL. Although triacs show some depen- dency on the gate current in quadrant II, the latching current is primarily affected by the temperature on shorted emitter structures. In order to allow turn off, the principal current must be reduced below the level of the latching current. The current level where turn off occurs is called the holding current, IH. Like the latching current, the holding current is affected by temperature and also depends on the gate impedance.
- 13. http://onsemi.com 13 Reverse voltage on the gate of an SCR markedly increases the latch and hold levels. Forward bias on thyristor gates may significantly lower the values shown in the data sheets since those values are normally given with the gate open. Failure to take this into account can cause latch or hold problems when thyristors are being driven from transistors whose saturation voltages are a few tenths of a volt. Thyristors made with shorted emitter gates are obvious- ly not as sensitive to the gate circuit conditions as devices which have no built−in shunt. SWITCHING CHARACTERISTICS When triacs or SCRs are triggered by a gate signal, the turn−on time consists of two stages: a delay time, td, and a rise time, tr, as shown in Figure 2.6. The total gate controlled turn−on time, tgt, is usually defined as the time interval between the 50 percent point of the leading edge of the gate trigger voltage and 90 percent point of the principal current. The rise time tr is the time interval required for the principal current to rise from 10 to 90 percent of its maximum value. A resistive load is usually specified. Figure 2.6. Waveshapes Illustrating Thyristor Turn−On Time For A Resistive Load PRINCIPAL VOLTAGE PRINCIPAL CURRENT 90% POINT 10% POINT 90% POINT 10% POINT 0 0 trtd ton GATE CURRENT IGT IGT 50% 50% POINT (WAVESHAPES FOR A SENSITIVE LOAD) 0 Delay time decreases slightly as the peak off−state voltage increases. It is primarily related to the magnitude of the gate−trigger current and shows a relationship which is roughly inversely proportional. The rise time is influenced primarily by the off−state voltage, as high voltage causes an increase in regenerative gain. Of major importance in the rise time interval is the relationship between principal voltage and current flow through the thyristor di/dt. During this time the dynamic voltage drop is high and the current density due to the possible rapid rate of change can produce localized hot spots in the die. This may permanently degrade the blocking characteristics. Therefore, it is important that power dissipation during turn−on be restricted to safe levels. Turn−off time is a property associated only with SCRs and other unidirectional devices. (In triacs of bidirectional devices a reverse voltage cannot be used to provide circuit−commutated turn−off voltage because a reverse voltage applied to one half of the structure would be a forward−bias voltage to the other half.) For turn−off times in SCRs, the recovery period consists of two stages, a reverse recovery time and a gate or forward blocking recovery time, as shown in Figure 2.7. When the forward current of an SCR is reduced to zero at the end of a conduction period, application of reverse voltage between the anode and cathode terminals causes reverse current flow in the SCR. The current persists until the time that the reverse current decreases to the leakage level. Reverse recovery time (trr) is usually measured from the point where the principal current changes polarity to a specified point on the reverse current waveform as indicated in Figure 2.7. During this period the anode and cathode junctions are being swept free of charge so that they may support reverse voltage. A second recovery period, called the gate recovery time, tgr, must elapse for the charge stored in the forward−blocking junction to recombine so that forward−blocking voltage can be reapplied and successfully blocked by the SCR. The gate recovery time of an SCR is usually much longer than the reverse recovery time. The total time from the instant reverse recovery current begins to flow to the start of the forward−blocking voltage is referred to as circuit− commutated turn−off time tq. Turn−off time depends upon a number of circuit conditions including on−state current prior to turn−off, rate of change of current during the forward−to−reverse transition, reverse−blocking voltage, rate of change of reapplied forward voltage, the gate bias, and junction temperature. Increasing junction temperature and on− state current both increase turn−off time and have a more
- 14. http://onsemi.com 14 significant effect than any of the other factors. Negative gate bias will decrease the turn−off time. Figure 2.7. Waveshapes Illustrating Thyristor Turn−Off Time PRINCIPAL VOLTAGE PRINCIPAL CURRENT REAPPLIED dv/dt FORWARD 0 REVERSE di/dt FORWARD REVERSE 0 trr tgr tq For applications in which an SCR is used to control ac power, during the entire negative half of the sine wave a reverse voltage is applied. Turn off is easily accomplished for most devices at frequencies up to a few kilohertz. For applications in which the SCR is used to control the output of a full−wave rectifier bridge, however, there is no reverse voltage available for turn−off, and complete turn−off can be accomplished only if the bridge output is reduced close to zero such that the principal current is reduced to a value lower than the device holding current for a sufficiently long time. Turn−off problems may occur even at a frequency of 60 Hz particularly if an inductive load is being controlled. In triacs, rapid application of a reverse polarity voltage does not cause turn−off because the main blocking junctions are common to both halves of the device. When the first triac structure (SCR−1) is in the conducting state, a quantity of charge accumulates in the N−type region as a result of the principal current flow. As the principal current crosses the zero reference point, a reverse current is established as a result of the charge remaining in the N−type region, which is common to both halves of the device. Consequently, the reverse recovery current becomes a forward current to the second half of the triac. The current resulting from stored charge causes the second half of the triac to go into the conducting state in the absence of a gate signal. Once current conduction has been established by application of a gate signal, therefore, complete loss in power control can occur as a result of interaction within the N−type base region of the triac unless sufficient time elapses or the rate of application of the reverse polarity voltage is slow enough to allow nearly all the charge to recombine in the common N−type region. Therefore, triacs are generally limited to low−frequency −60 Hz applications. Turn−off or commutation of triacs is more severe with inductive loads than with resistive loads because of the phase lag between voltage and current associated with inductive loads. Figure 2.8 shows the waveforms for an inductive load with lagging current power factor. At the time the current reaches zero crossover (Point A), the half of the triac in conduction begins to commutate when the principal current falls below the holding current. At the instant the conducting half of the triac turns off, an applied voltage opposite the current polarity is applied across the triac terminals (Point B). Because this voltage is a forward bias to the second half of the triac, the suddenly reapplied voltage in conjunction with the remaining stored charge in the high−voltage junction reduces the over−all device capa- bility to support voltage. The result is a loss of power control to the load, and the device remains in the conducting state in absence of a gate signal. The measure of triac turn−off ability is the rate of rise of the opposite polarity voltage it can handle without remaining on. It is called commutating dv/dt (dv/dt[c]). Circuit conditions and temperature affect dv/dt(c) in a manner similar to the way tq is affected in an SCR. It is imperative that some means be provided to restrict the rate of rise of reapplied voltage to a value which will permit triac turn−off under the conditions of inductive load. A commonly accepted method for keeping the commutating dv/dt within tolerable levels is to use an RC snubber network in parallel with the main terminals of the triac. Because the rate of rise of applied voltage at the triac terminals is a function of the load impedance and the RC snubber network, the circuit can be evaluated under worst−case conditions of operating case temperature and maximum principal current. The values of resistance and capacitance in the snubber area then adjusted so that the rate of rise of commutating dv/dt stress is within the specified minimum limit under any of the conditions mentioned above. The value of snubber resistance should be high enough to limit the snubber capacitance discharge currents during turn−on and dampen the LC oscillation during commutation. The combination of snubber values having highest resistance and lowest capacitance that provides satisfactory operation is generally preferred.
- 15. http://onsemi.com 15 Figure 2.8. Inductive Load Waveforms IH V I B A dr dt c FALSE TRIGGERING Circuit conditions can cause thyristors to turn on in the absence of the trigger signal. False triggering may result from: 1) A high rate of rise of anode voltage, (the dv/dt effect). 2) Transient voltages causing anode breakover. 3) Spurious gate signals. Static dv/dt effect: When a source voltage is suddenly applied to a thyristor which is in the off state, it may switch from the off state to the conducting state. If the thyristor is controlling alternating voltage, false turn−on resulting from a transient imposed voltage is limited to no more than one−half cycle of the applied voltage because turn−off occurs during the zero current crossing. How- ever, if the principal voltage is dc voltage, the transient may cause switching to the on state and turn−off could then be achieved only by a circuit interruption. The switching from the off state caused by a rapid rate of rise of anode voltage is the result of the internal capacitance of the thyristor. A voltage wavefront impressed across the terminals of a thyristor causes a capacitance−charging current to flow through the device which is a function of the rate of rise of applied off−state voltage (i = C dv/dt). If the rate of rise of voltage exceeds a critical value, the capacitance charging current exceeds the gate triggering current and causes device turn−on. Operation at elevated junction temperatures reduces the thyristor ability to support a steep rising voltage dv/dt because of increased sensitivity. dv/dt ability can be improved quite markedly in sensitive gate devices and to some extent in shorted emitter designs by a resistance from gate to cathode (or MT1) however reverse bias voltage is even more effective in an SCR. More commonly, a snubber network is used to keep the dv/dt within the limits of the thyristor when the gate is open. TRANSIENT VOLTAGES: — Voltage transients which occur in electrical systems as a result of distur- bance on the ac line caused by various sources such as energizing transformers, load switching, solenoid closure, contractors and the like may generate voltages which are above the ratings of thyristors. Thyristors, in general, switch from the off state to the on state whenever the breakover voltage of the device is exceeded, and energy is then transferred to the load. However, unless a thyristor is specified for use in a breakover mode, care should be exercised to ensure that breakover does not occur, as some devices may incur surface damage with a resultant degradation of blocking characteristics. It is good practice when thyristors are exposed to a heavy transient environ- ment to provide some form of transient suppression. For applications in which low−energy, long−duration transients may be encountered, it is advisable to use thyristors that have voltage ratings greater than the highest voltage transient expected in the system. The use of voltage clipping cells (MOV or Zener) is also an effective method to hold transient below thyristor ratings. The use of an RC “snubber” circuit is effective in reducing the effects of the high−energy short−duration transients more frequently encountered. The snubber is commonly required to prevent the static dv/dt limits from being exceeded, and often may be satisfactory in limiting the amplitude of the voltage transients as well. For all applications, the dv/dt limits may not be exceeded. This is the minimum value of the rate of rise off−state voltage applied immediately to the MT1−MT2 terminals after the principal current of the opposing polarity has decreased to zero. SPURIOUS GATE SIGNALS: In noisy electrical environments, it is possible for enough energy to cause gate triggering to be coupled into the gate wiring by stray capacitance or electromagnetic induction. It is therefore advisable to keep the gate lead short and have the common return directly to the cathode or MT1. In extreme cases, shielded wire may be required. Another aid commonly used is to connect a capacitance on the order of 0.01 to 0.1 μF across the gate and cathode terminals. This has the added advantage of increasing the thyristor dv/dt capability, since it forms a capacitance divider with the anode to gate capacitance. The gate capacitor also reduces the rate of application of gate trigger current which may cause di/dt failures if a high inrush load is present. THYRISTOR RATINGS To insure long life and proper operation, it is important that operating conditions be restrained from exceeding thyristor ratings. The most important and fundamental ratings are temperature and voltage which are interrelated to some extent. The voltage ratings are applicable only up to the maximum temperature ratings of a particular part number. The temperature rating may be chosen by the manufacturer to insure satisfactory voltage ratings, switching speeds, or dv/dt ability.
- 16. http://onsemi.com 16 OPERATING CURRENT RATINGS Current ratings are not independently established as a rule. The values are chosen such that at a practical case temperature the power dissipation will not cause the junction temperature rating to be exceeded. Various manufacturers may chose different criteria to establish ratings. At ON Semiconductors, use is made of the thermal response of the semiconductor and worst case values of on−state voltage and thermal resistance, to guarantee the junction temperature is at or below its rated value. Values shown on data sheets consequently differ somewhat from those computed from the standard formula: TC(max) = T (rated) − RθJC PD(AV) where TC (max) = Maximum allowable case temperature T (rated) = Rated junction temperature or maximum rated case temperature with zero principal current and rated ac blocking voltage applied. RθJC = Junction to case thermal resistance PD(AV) = Average power dissipation The above formula is generally suitable for estimating case temperature in situations not covered by data sheet information. Worst case values should be used for thermal resistance and power dissipation. OVERLOAD CURRENT RATINGS Overload current ratings may be divided into two types: non−repetitive and repetitive. Non−repetitive overloads are those which are not a part of the normal application of the device. Examples of such overloads are faults in the equipment in which the devices are used and accidental shorting of the load. Non−repeti- tive overload ratings permit the device to exceed its maximum operating junction temperature for short peri- ods of time because this overload rating applies following any rated load condition. In the case of a reverse blocking thyristor or SCR, the device must block rated voltage in the reverse direction during the current overload. How- ever, no type of thyristor is required to block off−stage voltage at any time during or immediately following the overload. Thus, in the case of a triac, the device need not block in either direction during or immediately following the overload. Usually only approximately one hundred such current overloads are permitted over the life of the device. These non−repetitive overload ratings just described may be divided into two types: multicycle (which include single cycle) and subcycle. For an SCR, the multicycle overload current rating, or surge current rating as it is commonly called, is generally presented as a curve giving the maximum peak values of half sine wave on−state current as a function of overload duration measured in number of cycles for a 60 Hz frequency. For a triac, the current waveform used in the rating is a full sine wave. Multicycle surge curves are used to select proper circuit breakers and series line impedances to prevent damage to the thyristor in the event of an equipment fault. The subcycle overload or subcycle surge rating curve is so called because the time duration of the rating is usually from about one to eight milliseconds which is less than the time of one cycle of a 60 Hz power source. Overload peak current is often given in curve form as a function of overload duration. This rating also applies following any rated load condition and neither off−state nor reverse blocking capability is required on the part of the thyristor immediately following the overload current. The subcycle surge current rating may be used to select the proper current−limiting fuse for protection of the thyristor in the event of an equipment fault. Since this use of the rating is so common, manufacturers simply publish the i2t rating in place of the subcycle current overload curve because fuses are commonly rated in terms of i2t. The i2t rating can be approximated from the single cycle surge rating (ITSM) by using: i2t = I2 TSM t/2 where the time t is the time base of the overload, i.e., 8.33 ms for a 60 Hz frequency. Repetitive overloads are those which are an intended part of the application such as a motor drive application. Since this type of overload may occur a large number of times during the life of the thyristor, its rated maximum operating junction temperature must not be exceeded during the overload if long thyristor life is required. Since this type of overload may have a complex current waveform and duty−cycle, a current rating analysis involving the use of the transient thermal impedance characteristics is often the only practical approach. In this type of analysis, the thyristor junction−to−case transient thermal impedance characteristic is added to the user’s heat dissipator transient thermal impedance characteris- tic. Then by the superposition of power waveforms in conjunction with the composite thermal impedance curve, the overload current rating can be obtained. The exact calculation procedure is found in the power semiconduc- tor literature. THEORY OF SCR POWER CONTROL The most common form of SCR power control is phase control. In this mode of operation, the SCR is held in an off condition for a portion of the positive half cycle and then is triggered into an on condition at a time in the half cycle determined by the control circuitry (in which the circuit current is limited only by the load — the entire line voltage except for a nominal one volt drop across the SCR is applied to the load).
- 17. http://onsemi.com 17 One SCR alone can control only one half cycle of the waveform. For full wave ac control, two SCRs are connected in inverse parallel (the anode of each con- nected to the cathode of the other, see Figure 2.9a). For full wave dc control, two methods are possible. Two SCRs may be used in a bridge rectifier (see Figure 2.9b) or one SCR may be placed in series with a diode bridge (see Figure 2.9c). Figure 2.10 shows the voltage waveform along with some common terms used in describing SCR operation. Delay angle is the time, measured in electrical degrees, during which the SCR is blocking the line voltage. The period during which the SCR is on is called the conduction angle. It is important to note that the SCR is a voltage controlling device. The load and power source determine the circuit current. Now we arrive at a problem. Different loads respond to different characteristics of the ac waveform. Some loads are sensitive to peak voltage, some to average voltage and some to rms voltage. Figures 2.11(b) and 2.12(b) show the various characteristic voltages plotted against the conduc- tion angle for half wave and full wave circuits. These voltages have been normalized to the rms of the applied voltage. To determine the actual peak, average or rms voltage for any conduction angle, we simply multiply the normalized voltage by the rms value of the applied line voltage. (These normalized curves also apply to current in a resistive circuit.) Since the greatest majority of circuits are either 115 or 230 volt power, the curves have been redrawn for these voltages in Figures 2.11(a) and 2.12(a). A relative power curve has been added to Figure 2.12 for constant impedance loads such as heaters. (Incandes- cent lamps and motors do not follow this curve precisely since their relative impedance changes with applied voltage.) To use the curves, we find the full wave rated power of the load, then multiply by the fraction associated with the phase angle in question. For example, a 180° conduction angle in a half wave circuit provides 0.5 x full wave full−conduction power. An interesting point is illustrated by the power curves. A conduction angle of 30° provides only three per cent of full power in a full wave circuit, and a conduction angle of 150° provides 97 per cent of full power. Thus, the control circuit can provide 94 per cent of full power control with a pulse phase variation of only 120°. Thus, it becomes pointless in many cases to try to obtain conduction angles less than 30° or greater than 150°. CONTROL CHARACTERISTICS The simplest and most common control circuit for phase control is a relaxation oscillator. This circuit is shown diagrammatically as it would be used with an SCR in Figure 2.13. The capacitor is charged through the resistor from a voltage or current source until the breakover voltage of the trigger device is reached. At that time, the trigger device changes to its on state, and the capacitor is discharged through the gate of the SCR. Turn−on of the SCR is thus accomplished with a short, high current pulse. Commonly used trigger devices are programmable unijunction transistors, silicon bilateral switches, SIDACs, optically coupled thyristors, and power control integrated circuits. Phase control can be obtained by varying the RC time constant of a charging circuit so that trigger device turn−on occurs at varying phase angles within the controlled half cycle. If the relaxation oscillator is to be operated from a pure dc source, the capacitor voltage−time characteristic is shown in Figure 2.14. This shows the capacitor voltage as it rises all the way to the supply voltage through several time constants. Figure 2.14(b) shows the charge charac- teristic in the first time constant greatly expanded. It is this portion of the capacitor charge characteristic which is most often used in SCR and Triac control circuits. Generally, a design starting point is selection of a capacitance value which will reliably trigger the thyristor when the capacitor is discharged. Gate characteristics and ratings, trigger device properties, and the load impedance play a part in the selection. Since not all of the important parameters for this selection are completely specified, experimental determination is often the best method. Low−current loads and strongly inductive circuits sometimes cause triggering difficulty because the gate current pulse goes away before the principal thyristor current achieves the latching value. A series gate resistor can be used to introduce a RC discharge time constant in the gate circuit and lengthen trigger pulse duration allowing more time for the main terminal current to rise to the latching value. Small thyristors will require a series gate resistance to avoid exceeding the gate ratings. The discharge time constant of a snubber, if used, can also aid latching. The duration of these capacitor discharge duration currents can be estimated by tw10 = 2.3 RC where tw10 = time for current to decay to 10% of the peak.
- 18. http://onsemi.com 18 (a) ac Control CONTROL CIRCUIT LINE LOAD (b) Two SCR dc Control CONTROL CIRCUIT LINE LOAD (c) One SCR dc Control CONTROL CIRCUIT LINE LOAD Figure 2.9. SCR Connections For Various Methods Of Phase Control Figure 2.10. Sine Wave Showing Principles Of Phase Control FULL WAVE RECTIFIED OPERATION VOLTAGE APPLIED TO LOAD DELAY ANGLE CONDUCTION ANGLE
- 19. http://onsemi.com 19 Figure 2.11. Half−Wave Characteristics Of Thyristor Power Control Figure 2.12. Full−Wave Characteristics Of Thyristor Power Control 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 180160140120100806040200 CONDUCTION ANGLE (a) NORMALIZEDSINEWAVErmsVOLTAGE POWERASFRACTIONOFFULLCONDUCTION NORMALIZEDSINEWAVErmsVOLTAGE POWERASFRACTIONOFFULLCONDUCTION VOLTAGEVOLTAGE 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 180160140120100806040200 CONDUCTION ANGLE (a) HALF WAVE FULL WAVE PEAK VOLTAGE rms POWER AVG PEAK VOLTAGE rms AVG POWER APPLIED VOLTAGE 230 V 115 V 360 180 320 160 280 140 240 120 200 100 160 80 120 60 80 40 40 20 0 0 180160140120100806040200 CONDUCTION ANGLE (b) APPLIED VOLTAGE 230 V 115 V 360 180 320 160 280 140 240 120 200 100 160 80 120 60 80 40 40 20 0 0 180160140120100806040200 CONDUCTION ANGLE (b) HALF WAVE FULL WAVE PEAK VOLTAGE PEAK VOLTAGE rms rms AVG AVG
- 20. http://onsemi.com 20 In many of the recently proposed circuits for low cost operation, the timing capacitor of the relaxation oscillator is charged through a rectifier and resistor using the ac power line as a source. Calculations of charging time with this circuit become exceedingly difficult, although they are still necessary for circuit design. The curves of Figure 2.14 simplify the design immensely. These curves show the voltage−time characteristic of the capacitor charged from one half cycle of a sine wave. Voltage is normalized to the rms value of the sine wave for convenience of use. The parameter of the curves is a new term, the ratio of the RC time constant to the period of one half cycle, and is denoted by the Greek letter τ. It may most easily be calculated from the equation τ = 2RCf. Where: R = resistance in Ohms C = capacitance in Farads f = frequency in Hertz. Figure 2.13(a). Capacitor Charging From dc Source Figure 2.13(b). Expanded Scale 0.9 1 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 TIME CONSTANTS CAPACITORVOLTAGEAS FRACTIONOFSUPPLYVOLTAGE 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1 1.2 TIME CONSTANTS CAPACITORVOLTAGEAS FRACTIONOFSUPPLYVOLTAGE
- 21. http://onsemi.com 21 Figure 2.14(a). Capacitor Voltage When Charged Figure 2.14(b). Expansion of Figure 2.15(a). 1.80 1.40 1.20 1 0.80 0.707 0.60 0.40 0.20 0 0 180 20 160 40 140 60 120 80 100 100 80 120 60 140 40 30 160 20 180 0 DELAY ANGLE IN DEG. CONDUCTION ANGLE IN DEG. 0 180 20 160 40 140 60 120 80 100 100 80 120 60 140 40 160 20 180 0 DELAY ANGLE IN DEG. CONDUCTION ANGLE IN DEG. NORMALIZEDVOLTAGEASAFRACTIONOF rmsCHARGINGSOURCEVOLTAGE NORMALIZEDVOLTAGEASAFRACTIONOF rmsCHARGINGSOURCEVOLTAGE 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 R CV VC CAPACITOR VOLTAGE, VC APPLIED VOLTAGE, V τ = 0.1 0.2 0.3 0.4 0.5 0.7 1 1.5 2 3 5 τ = 0.1 0.2 0.3 0.5 0.7 1 1.5 2 2.5 3 4 5 7 10 15 20 50
- 22. http://onsemi.com 22 Figure 2.14(c). Expansion of Figure 2.14(b) 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 NORMALIZEDVOLTAGEASAFRACTIONOF rmsCHARGINGSOURCEVOLTAGE 0.0696 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 DELAY ANGLE IN DEG. 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 CONDUCTION ANGLE IN DEG. rms CHARGING SOURCE VOLTAGE τ = 0.1 0.2 0.3 0.5 10.7 1.5 2 2.5 3 4 5 7 8.5 10 12.5 15 20 35 50 To use the curves when starting the capacitor charge from zero each half cycle, a line is drawn horizontally across the curves at the relative voltage level of the trigger breakdown compared to the rms sine wave voltage. The τ is determined for maximum and minimum conduction angles and the limits of R may be found from the equation for τ. An example will again clarify the picture. Consider the same problem as the previous example, except that the capacitor charging source is the 115 Vac, 60 Hz power line. The ratio of the trigger diode breakover voltage to the RMS charging voltage is then 8/115 = 69.6 10−3. A line drawn at 0.0696 on the ordinate of Figure 2.14(c) shows that for a conduction angle of 30°, τ = 12, and for a conduction angle of 150°, τ = 0.8. Therefore, since R = τ/(2CF) Rmax + 12 2(1.0 10 –6)60 100 k ohms, Rmin + 0.8 2(1 10–6 )60 6667 ohms. These values would require a potentiometer of 100 k in series with a 6.2 k minimum fixed resistance. The timing resistor must be capable of supplying the highest switching current allowed by the SBS specifica- tion at the switching voltage. When the conduction angle is less than 90°, triggering takes place along the back of the power line sine wave and maximum firing current thru the SBS is at the start of SBS breakover. If this current does not equal or exceed “ls” the SBS will fail to trigger and phase control will be lost. This can be prevented by selecting a lower value resistor and larger capacitor. The available current can be determined from Figure 2.14(a). The vertical line drawn from the conduction angle of 30° intersects the applied voltage curve at 0.707. The instantaneous current at breakover is then I = (0.707 115−8)/110 k = 733 μA. When the conduction angle is greater than 90°, triggering takes place before the peak of the sine wave. If the current thru the SBS does not exceed the switching current at the moment of breakover, triggering may still take place but not at the predicted time because of the additional delay for the rising line voltage to drive the SBS current up to the switching level. Usually long conduction angles are associated with low value timing resistors making this problem less likely. The SBS current at the moment of breakover can be determined by the same method described for the trailing edge. It is advisable to use a shunt gate−cathode resistor across sensitive gate SCR’s to provide a path for leakage currents and to insure that firing of the SCR causes turn−on of the trigger device and discharge of the gate circuit capacitor. TRIAC THEORY The triac is a three−terminal ac semiconductor switch which is triggered into conduction when a low−energy signal is applied to its gate. Unlike the silicon controlled rectifier or SCR, the triac will conduct current in either direction when turned on. The triac also differs from the SCR in that either a positive or negative gate signal will trigger the triac into conduction. The triac may be thought of as two complementary SCRs in parallel.
- 23. http://onsemi.com 23 The triac offers the circuit designer an economical and versatile means of accurately controlling ac power. It has several advantages over conventional mechanical switches. Since the triac has a positive “on” and a zero current “off” characteristic, it does not suffer from the contact bounce or arcing inherent in mechanical switches. The switching action of the triac is very fast compared to conventional relays, giving more accurate control. A triac can be triggered by dc, ac, rectified ac or pulses. Because of the low energy required for triggering a triac, the control circuit can use any of many low−cost solid−state devices such as transistors, bilateral switches, sensitive− gate SCRs and triacs, optically coupled drivers and integrated circuits. CHARACTERISTICS OF THE TRIAC Figure 2.15(a) shows the triac symbol and its relation- ship to a typical package. Since the triac is a bilateral device, the terms “anode” and “cathode” used for unilateral devices have no meaning. Therefore, the terminals are simply designated by MT1, MT2, and G, where MT1 and MT2 are the current−carrying terminals, and G, is the gate terminal used for triggering the triac. To avoid confusion, it has become standard practice to specify all currents and voltages using MT1 as the reference point. The basic structure of a triac is shown in Figure 2.15(b). This drawing shows why the symbol adopted for the triac consists of two complementary SCRs with a common gate. The triac is a five−layer device with the region between MT1 and MT2 being P−N−P−N switch (SCR) in parallel with a N−P−N−P switch (complementary SCR). Also, the structure gives some insight into the triac’s ability to be triggered with either a positive or negative gate signal. The region between MT1 and G consists of two complementary diodes. A positive or negative gate signal will forward−bias one of these diodes causing the same transistor action found in the SCR. This action breaks down the blocking junction regardless of the polarity of MT1. Current flow between MT2 and MT1 then causes the device to provide gate current internally. It will remain on until this current flow is interrupted. The voltage−current characteristic of the triac is shown in Figure 2.16 where, as previously stated, MT1 is used as the reference point. The first quadrant, Q−I, is the region where MT2 is positive with respect to MT1 and quadrant III is the opposite case. Several of the terms used in characterizing the triac are shown on the figure. VDRM is the breakover voltage of the device and is the highest voltage the triac may be allowed to block in either direction. If this voltage is exceeded, even transiently, the triac may go into conduction without a gate signal. Although the triac is not damaged by this action if the current is limited, this situation should be avoided because control of the triac is lost. A triac for a particular application should have VDRM at least as high as the peak of the ac waveform to be applied so reliable control can be maintained. The holding current (IH) is the minimum value of current necessary to maintain conduction. When the current goes below IH, the triac ceases to conduct and reverse to the blocking state. IDRM is the leakage current of the triac with VDRM applied from MT2 to MT1 and is several orders of magnitude smaller than the current rating of the device. The figure shows the characteristic of the triac without a gate signal applied but it should be noted that the triac can be triggered into the on state at any value of voltage up to VDRM by the application of a gate signal. This important characteristic makes the triac very useful. Since the triac will conduct in either direction and can be triggered with either a positive or negative gate signal there are four possible triggering modes (Figure 2.3): Quadrant I; MT2(+), G(+), positive voltage and positive gate current. Quadrant II; MT2(+), G(−), positive voltage and negative gate current. Quadrant III; MT2(−), G(−), negative voltage and negative gate current. Quadrant IV; MT2(−), G(+), negative voltage and positive gate current. Present triacs are most sensitive in quadrants I and III, slightly less so in quadrant II, and much less sensitive in quadrant IV. Therefore it is not recommended to use quadrant IV unless special circumstances dictate it. An important fact to remember is that since a triac can conduct current in both directions, it has only a brief interval during which the sine wave current is passing through zero to recover and revert to its blocking state. For this reason, reliable operation of present triacs is limited to 60 Hz line frequency and lower frequencies. For inductive loads, the phase−shift between the current and voltage means that at the time the current falls below IH and the triac ceases to conduct, there exists a certain voltage which must appear across the triac. If this voltage appears too rapidly, the triac will resume conduction and control is lost. In order to achieve control with certain inductive loads, the rate of rise in voltage (dv/dt) must be limited by a series RC network across the triac. The capacitor will then limit the dv/dt across the triac. The resistor is necessary to limit the surge of current from the capacitor when the triac fires, and to damp the ringing of the capacitance with the load inductance.
- 24. http://onsemi.com 24 MT2 GATE MT1 MT2 MT1 G N N NP P N (a) (b) Figure 2.16. Triac Voltage−Current Characteristic IDRM VDRM BLOCKING STATE QIII MT2ĊON−STATE IH I IH V VDRM Q1 MT2+ BLOCKING STATE IDRM ON−STATE Figure 2.15. Triac Structure and Symbol METHODS OF CONTROL AC SWITCH A useful application of triac is as a direct replacement for an ac mechanical relay. In this application, the triac furnishes on−off control and the power−regulating ability of the triac is not utilized. The control circuitry for this application is usually very simple, consisting of a source for the gate signal and some type of small current switch, either mechanical or electrical. The gate signal can be obtained from a separate source or directly from the line voltage at terminal MT2 of the triac. PHASE CONTROL An effective and widely−used method of controlling the average power to a load through the triac is by phase control. Phase control is a method of utilizing the triac to apply the ac supply to the load for a controlled fraction of each cycle. In this mode of operation, the triac is held in an off or open condition for a portion of each positive and negative cycle, and then is triggered into an on condition at a time in the half cycle determined by the control circuitry. In the on condition, the circuit current is limited only by the load — i.e., the entire line voltage (less the forward drop of the triac) is applied to the load. Figure 2.17 shows the voltage waveform along with some common terms used in describing triac operation. Delay angle is the angle, measured in electrical degrees, during which the triac is blocking the line voltage. The period during which the triac is on is called the conduction angle. It is important to note that the triac is either off (blocking voltage) or fully on (conducting). When it is in the on condition, the circuit current is determined only by the load and the power source. As one might expect, in spite of its usefulness, phase control is not without disadvantages. The main disadvan- tage of using phase control in triac applications is the generation of electro−magnetic interference (EMI). Each time the triac is fired the load current rises from zero to the load−limited current value in a very short time. The resulting di/dt generates a wide spectrum of noise which may interfere with the operation of nearby electronic equipment unless proper filtering is used. ZERO POINT SWITCHING In addition to filtering, EMI can be minimized by zero−point switching, which is often preferable. Zero− point switching is a technique whereby the control element (in this case the triac) is gated on at the instant the sine wave voltage goes through zero. This reduces, or eliminates, turn−on transients and the EMI. Power to the load is controlled by providing bursts of complete sine waves to the load as shown in Figure 2.18. Modulation can be on a random basis with an on−off control, or a proportioning basis with the proper type of proportional control. In order for zero−point switching to be effective, it must indeed be zero point switching. If a triac is turned on with as little as 10 volts across it into a load of a few−hundred watts, sufficient EMI will result to nullify the advantages of adopting zero−point switching in the first place. BASIC TRIAC AC SWITCHES Figure 2.19 shows methods of using the triac as an on−off switch. These circuits are useful in applications where simplicity and reliability are important. As pre- viously stated, there is no arcing with the triac, which can be very important in some applications. The circuits are for resistive loads as shown and require the addition of a dv/dt network across the triac for inductive loads.
- 25. http://onsemi.com 25 Figure 2.19(a) shows low−voltage control of the triac. When switch S1 is closed, gate current is supplied to the triac from the 10 volt battery. In order to reduce surge current failures during turn on (ton), this current should be 5 to 10 times the maximum gate current (IGT) required to trigger the triac. The triac turns on and remains on until S1 is opened. This circuit switches at zero current except for initial turn on. S1 can be a very−low−current switch because it carries only the triac gate current. Figure 2.19(b) shows a triac switch with the same characteristics as the circuit in Figure 2.19(a) except the need for a battery has been eliminated. The gate signal is obtained from the voltage at MT2 of the triac prior to turn on. The circuit shown in Figure 2.19(c) is a modification of Figure 2.19(b). When switch S1 is in position one, the triac receives no gate current and is non−conducting. With S1 in position two, circuit operation is the same as that for Figure 2.19(b). In position three, the triac receives gate current only on positive half cycles. Therefore, the triac conducts only on positive half cycles and the power to the load is half wave. Figure 2.19(d) shows ac control of the triac. The pulse can be transformer coupled to isolate power and control circuits. Peak current should be 10 times IGT(max) and the RC time constant should be 5 times ton(max). A high frequency pulse (1 to 5 kHz) is often used to obtain zero point switching. Figure 2.17. Sine Wave Showing Principles of Phase Control VOLTAGE APPLIED TO LOAD CONDUCTION ANGLE DELAY ANGLE ZERO POINT SWITCHING TECHNIQUES Zero−point switches are highly desirable in many applications because they do not generate electro−mag- netic interference (EMI). A zero−point switch controls sine−wave power in such a way that either complete cycles or half cycles of the power supply voltage are applied to the load as shown in Figure 2.20. This type of switching is primarily used to control power to resistive loads such as heaters. It can also be used for controlling the speed of motors if the duty cycle is modulated by having short bursts of power applied to the load and the load characteristic is primarily inertial rather than fric- tional. Modulation can be on a random basis with an on−off control, or on a proportioning basis with the proper type of proportioning control. In order for zero−point switching to be effective, it must be true zero−point switching. If an SCR is turned on with an anode voltage as low as 10 volts and a load of just a few hundred watts, sufficient EMI will result to nullify the advantages of going to zero−point switching in the first place. The thyristor to be turned on must receive gate drive exactly at the zero crossing of the applied voltage. The most successful method of zero−point thyristor control is therefore, to have the gate signal applied before the zero crossing. As soon as the zero crossing occurs, anode voltage will be supplied and the thyristor will come on. This is effectively accomplished by using a capacitor to derive a 90° leading gate signal from the power line source. However, only one thyristor can be controlled from this phase−shifted signal, and a slaving circuit is necessary to control the other SCR to get full−wave power control. These basic ideas are illustrated in Figure 2.21. The slaving circuit fires only on the half cycle after the firing of the master SCR. This guarantees that only complete cycles of power will be applied to the load. The gate signal to the master SCR receives all the control; a convenient control method is to replace the switch with a low−power transistor, which can be controlled by bridge− sensing circuits, manually controlled potentiometers, or various other techniques. Figure 2.18. Sine Wave Showing Principles of Zero−Point Switching LOAD VOLTAGE LINE VOLTAGE HALF POWER TO LOAD FULL POWER TO LOAD
- 26. http://onsemi.com 26 (a): Low Voltage Controlled Triac Switch (b): Triac ac Static Contactor (c): 3 Position Static Switch (d): AC Controlled Triac Switch Figure 2.19. Triac Switches 15 Ω LOAD 15 Ω LOAD 15 Ω LOAD 15 Ω LOAD 2N6346 2N6342 2N6342 2N6346 115 VAC 60 Hz 115 VAC 60 Hz 115 VAC 60 Hz R1 47 Ω R1 100 Ω R1 100 Ω R1 S1 3 2 1 + 10 V S1 S1 Figure 2.20. Load Voltage and Line Voltage for 25% Duty Cycle LOAD VOLTAGE LINE VOLTAGE A basic SCR is very effective and trouble free. However, it can dissipate considerable power. This must be taken into account in designing the circuit and its packaging. In the case of triacs, a slaving circuit is also usually required to furnish the gate signal for the negative half cycle. However, triacs can use slave circuits requiring less power than do SCRs as shown in Figure 2.21. Other considerations being equal, the easier slaving will some- times make the triac circuit more desirable than the SCR circuit. Besides slaving circuit power dissipation, there is another consideration which should be carefully checked when using high−power zero−point switching. Since this is on−off switching, it abruptly applies the full load to the power line every time the circuit turns on. This may cause a temporary drop in voltage which can lead to erratic operation of other electrical equipment on the line (light dimming, TV picture shrinkage, etc.). For this reason, loads with high cycling rates should not be powered from the same supply lines as lights and other voltage−sensitive devices. On the other hand, if the load cycling rate is slow, say once per half minute, the loading flicker may not be objectionable on lighting circuits. A note of caution is in order here. The full−wave zero−point switching control illustrated in Figure 2.21 should not be used as a half−wave control by removing the slave SCR. When the slave SCR in Figure 2.21 is removed, the master SCR has positive gate current flowing over approximately 1/4 of a cycle while the SCR itself is in the reverse−blocking state. This occurs during the negative half cycle of the line voltage. When this condition exists, Q1 will have a high leakage current with full voltage applied and will therefore be dissipating high power. This will cause excessive heating of the SCR and may lead to its failure. If it is desirable to use such a circuit as a half−wave control, then some means of clamping the gate signal during the negative half cycle must be devised to inhibit gate current while the SCR is reverse blocking. The circuits shown in Figures 2.23 and 2.24 do not have this disadvantage and may be used as half−wave controls.
- 27. http://onsemi.com 27 Figure 2.21. Slave and Master SCRs for Zero−Point Switching Figure 2.22. Triac Zero−Point Switch Figure 2.23. Sensitive−Gate Switch Figure 2.24. Zero−Point Switch AC LINE 150 1 W 2 μF 200 V LOAD Q2 (SLAVE) Q1 (MASTER) AC LINE 2 μF 200 V 1.2 k 7 W 150 1 W MAC210A8 LOADON−OFF CONTROL LOAD Q1 MCR22−6 D4 1N5760 C1 0.25 μF D2 1N4004 D3 1N4004 D1 1N4004AC LINE R1 3.8 k R2 8.2 k 1 W R3 1 k S1 AC LINE D1 1N4004 S1 C2 10 nF 200 V R1 3.8 k R2 8.2 k 1 W C1 0.25 μF 200 V D3 1N4004 D2 1N4004 D4 1N5760 R3 100 Q1 MCR218−4 LOAD OPERATION The zero−point switches shown in Figure 2.23 and 2.24 are used to insure that the control SCR turns on at the start of each positive alternation. In Figure 2.23 a pulse is generated before the zero crossing and provides a small amount of gate current when line voltage starts to go positive. This circuit is primarily for sensitive−gate SCRs. Less−sensitive SCRs, with their higher gate currents, normally require smaller values for R1 and R2 and the result can be high power dissipation in these resistors. The circuit of Figure 2.24 uses a capacitor, C2, to provide a low−impedance path around resistors R1 and R2 and can be used with less−sensitive, higher−current SCRs without increasing the dissipation. This circuit actually oscillates near the zero crossing point and provides a series of pulses to assure zero−point switching. The basic circuit is that shown in Figure 2.23. Operation begins when switch S1 is closed. If the positive alternation is present, nothing will happen since diode D1 is reverse biased. When the negative alternation begins, capacitor C1 will charge through resistor R2 toward the limit of voltage set by the voltage divider consisting of resistors R1 and R2. As the negative alternation reaches its peak, C1 will have charged to about 40 volts. Line voltage will decrease but C1 cannot discharge because diode D2 will be reverse biased. It can be seen that C1 and three−layer diode D4 are effectively in series with the line. When the line drops to 10 volts, C1 will still be 40 volts positive with respect to the gate of Q1. At this time D4 will see about 30 volts and will trigger. This allows C1 to discharge through D3, D4, the gate of Q1, R2, and R1. This discharge current will continue to flow as the line voltage crosses zero and will insure that Q1 turns on at the start of the positive alternation. Diode D3 prevents reverse gate−current flow and resistor R3 prevents false triggering. The circuit in Figure 2.24 operates in a similar manner up to the point where C1 starts to discharge into the gate. The discharge path will now be from C1 through D3, D4, R3, the gate of Q1, and capacitor C2. C2 will quickly charge from this high pulse of current. This reduces the voltage across D4 causing it to turn off and again revert to its blocking state. Now C2 will discharge through R1 and R2 until the voltage on D4 again becomes sufficient to cause it to break back. This repetitive exchange of charge from C1 to C2 causes a series of gate−current pulses to flow as the line voltage crosses zero. This means that Q1 will again be turned on at the start of each positive alternation as desired. Resistor R3 has been added to limit the peak gate current.
- 28. http://onsemi.com 28 AN SCR SLAVING CIRCUIT An SCR slaving circuit will provide full−wave control of an ac load when the control signal is available to only one of a pair of SCRs. An SCR slaving circuit is commonly used where the master SCR is controlled by zero−point switching. Zero−point switching causes the load to receive a full cycle of line voltage whenever the control signal is applied. The duty cycle of the control signal therefore determines the average amount of power supplied to the load. Zero−point switching is necessary for large loads such as electric heaters because conventional phase−shift techniques would generate an excessive amount of electro−magnetic interference (EMI). This particular slaving circuit has two important advantages over standard RC discharge slaving circuits. It derives these advantages with practically no increase in price by using a low−cost transistor in place of the current−limiting resistor normally used for slaving. The first advantage is that a large pulse of gate current is available at the zero−crossing point. This means that it is not necessary to select sensitive−gate SCRs for control- ling power. The second advantage is that this current pulse is reduced to zero within one alternation. This has a couple of good effects on the operation of the slaving SCR. It prevents gate drive from appearing while the SCR is reverse−biased, which would produce high power dissipation within the device. It also prevents the slaved SCR from being turned on for additional half cycles after the drive is removed from the control SCR. OPERATION The SCR slaving circuit shown in Figure 2.25 provides a single power pulse to the gate of SCR Q2 each time SCR Q1 turns on, thus turning Q2 on for the half cycle following the one during which Q1 was on. Q2 is therefore turned on only when Q1 is turned on, and the load can be controlled by a signal connected to the gate of Q1 as shown in the schematic. The control signal an be either dc or a power pulse. If the control signal is synchronized with the power line, this circuit will make an excellent zero−point switch. During the time that Q1 is on, capacitor C1 is charged through R1, D1 and Q1. While C1 is being charged, D1 reverse−biases the base−emitter junction of Q3, thereby holding it off. The charging time constant, R1, C1, is set long enough that C1 charges for practically the entire half cycle. The charging rate of C1 follows an “S” shaped curve, charging slowly at first, then faster as the supply voltage peaks, and finally slowly again as the supply voltage decreases. When the supply voltage falls below the voltage across C1, diode D1 becomes reverse biased and the base−emitter of Q3 becomes forward biased. For the values shown, this occurs approximately 6° before the end of the half cycle conduction of Q1. The base current is derived from the energy stored in C1. This turns on Q3, discharging C1 through Q3 and into the gate of Q2. As the voltage across C1 decreases, the base drive of Q3 decreases and somewhat limits the collector current. The current pulse must last until the line voltage reaches a magnitude such that latching current will exist in Q2. The values shown will deliver a current pulse which peaks at 100 mA and has a magnitude greater than 50 mA when the anode− cathode voltage of Q2 reaches plus 10 volts. This circuit completely discharges C1 during the half cycle that Q2 is on. This eliminates the possibility of Q2 being slaved for additional half cycles after the drive is removed from Q1. The peak current and the current duration are controlled by the values of R1 and C1. The values chosen provide sufficient drive for “shorted emitter” SCRs which typi- cally require 10 to 20 mA to fire. The particular SCR used must be capable of handling the maximum current requirements of the load to be driven; the 8 ampere, 200 V SCRs shown will handle a 1000 watt load. R1 1N4004 Q3 MPS 3638 Q2 2N6397 Q1 2N6397 INPUT SIGNAL 1000 W MAX 10 k 2 W 5 μF 50 V + C1 120 VAC 60 Hz Figure 2.25. SCR Slave Circuit *1000 WATT LOAD. SEE TEXT. CONTROL SCR
- 29. http://onsemi.com 29 SECTION 3 THYRISTOR DRIVERS AND TRIGGERING Edited and Updated Triggering a thyristor requires meeting its gate energy specifications and there are many ways of doing this. In general, the gate should be driven hard and fast to ensure complete gate turn on and thus minimize di/dt effects. Usually this means a gate current of at least three times the gate turn on current with a pulse rise of less than one microsecond and a pulse width greater than 10 microse- conds. The gate can also be driven by a dc source as long as the average gate power limits are met. Some of the methods of driving the gate include: 1) Direct drive from logic families of transistors 2) Opto triac drivers 3) Programmable unijunction transistors (PUTs) 4) SIDACs In this chapter we will discuss all of these, as well as some of the important design and application consider- ations in triggering thyristors in general. In the chapter on applications, we will also discuss some additional considerations relating to drivers and triggers in specific applications. PULSE TRIGGERING OF SCRs GATE TURN−ON MECHANISM The turn−on of PNPN devices has been discussed in many papers where it has been shown that the condition of switching is given by dv di = 0 (i.e., α1 + α2 = 1, where α1 and α2 are the current amplification factors of the two “transistors.’’ However, in the case of an SCR connected to a reverse gate bias, the device can have α1 + α2 = 1 and still stay in the blocking state. The condition of turn−on is actually α1 + α2 u1. The current amplification factor, α, increases with emitter current; some typical curves are shown in Figure 3.1. The monotonical increase of α with IE of the device in the blocking state makes the regeneration of current (i.e., turn−on) possible. EMITTER CURRENT DENSITY (mA/mm2) 1010−3 0.8 0.4 0.2 0 a 1.010−2 10−1 0.6 1.0 102 ,COMMONBASECURRENTGAIN W ≥ BASE WIDTH L ≥ DIFFUSION LENGTH W L + 0.1 W L + 0.5 W L + 1.0 Figure 3.1. Typical Variation of Transistor α with Emitter Current Density Using the two transistor analysis, the anode current, IA, can be expressed as a function of gate current, IG, as: IA + a2 IG ) ICS1 ) ICS2 1 * a1 * a2 (1) Definitions and derivations are given in Appendix I. Note that the anode current, IA, will increase to infinity as α1 + α2 = 1. This analysis is based upon the assumption that no majority carrier current flows out of the gate circuit. When no such assumption is made, the condition for turn−on is given by: IK I A + 1 * a1 a2 (2) which corresponds to α1 + α2 u1 (see Appendix I).
- 30. http://onsemi.com 30 P1 N1 P2 N2 J1 J2 J3 IG GATE (G) ANODE (A) CATHODE (K) IA IK Figure 3.2. Schematic Structure of an SCR, Positive Currents Are Defined as Shown by the Arrows Current regeneration starts when charge or current is introduced through the gate (Figure 3.2). Electrons are injected from the cathode across J3; they travel across the P2 “base’’ region to be swept out by the collector junction, J2, and thrown into the N1 base. The increase of majority carrier electrons in region N1 decreases the potential in region N1, so that holes from P1 are injected across the junction J1, into the N1 “base’’ region to be swept across J2, and thrown into the P2 “base’’ region. The increase in the potential of region P2 causes more electrons to be injected into P2, thereby repeating the cycle. Since α increases with the emitter current, an increase of regeneration takes place until α1 + α2 u1. Meanwhile, more carriers are collected than emitted from either of the emitters. The continuity of charge flow is violated and there is an electron build−up on the N1 side of J2, and a hole build−up on the P2 side. When the inert impurity charges are compensated for by injected majority carriers, the junction J2 becomes forward biased. The collector emits holes back to J1 and electrons to J3 until a steady state continuity of charge is established. During the regeneration process, the time it takes for a minority carrier to travel across a base region is the transit time, t, which is given approximately as: where Wi + base width (3)t1 + W2i 2Di Di + diffusion length (The subscript “i’’ can be either 1 or 2 to indicate the appropriate base.) The time taken from the start of the gate trigger to the turn−on of the device will be equal to some multiple of the transit time. CURRENT PULSE TRIGGERING Current pulse triggering is defined as supplying current through the gate to compensate for the carriers lost by recombination in order to provide enough current to sustain increasing regeneration. If the gate is triggered with a current pulse, shorter pulse widths require higher currents as shown by Figure 3.3(a). Figure 3.3(a) seems to indicate there is a constant amount of charge required to trigger on the device when IG is above a threshold level. When the charge required for turn−on plotted versus pulse current or pulse width, there is an optimum range of current levels or pulse widths for which the charge is minimum, as shown in region A of Figure 3.3(b) and (c). Region C shows that for lower current levels (i.e., longer minimum pulse widths) more charge is required to trigger on the device. Region B shows increasing charge required as the current gets higher and the pulse width smaller. t, PULSE WIDTH (ms) 1.00.05 80 40 20 0 0.50.1 0.2 60 100 2.0 i VAK = 10 V TA = 25°C 5.0 10 IG THRESHOLD HIGH UNIT LOW UNIT ,MINIMUMGATETRIGGERCURRENT(mA)G Figure 3.3(a). Typical Variation of Minimum Gate Current Required to Trigger
- 31. http://onsemi.com 31 iG, GATE CURRENT (mA) 2.0 20 5.0 2.0 1.0 5.0 10 10 100 20 Q VAK = 10 V TA = 25°C 50 100 HIGH UNITLOW UNIT ,MINIMUMTRIGGERCHARGE(nc)in 50 A ITHRESHOLDG ITHRESHOLDG C B C BA Figure 3.3(b). Variation of Charge versus Gate Current t, MINIMUM PULSE WIDTH (ms) 1.00.05 20 5.0 2.0 1.0 0.50.1 0.2 10 100 2.0 Q VAK = 10 V T = 25°C 5.0 10 HIGH UNIT LOW UNIT ,MINIMUMTRIGGERCHARGE(nc)in 50 (Q = it) CB A Figure 3.3(c). Variation of Charge versus Minimum Pulse Width The charge characteristic curves can be explained qualitatively by the variation of current amplification (αT) with respect to emitter current. A typical variation of α1 and α2 for a thyristor is shown in Figure 3.4(a). From Figure 3.4(a), it can be deduced that the total current amplification factor, αT = α1 + α2, has a characteristic curve as shown in Figure 3.4(b). (The data does not correspond to the data of Figure 3.3 — they are taken for different types of devices.) The gate current levels in region A of Figure 3.3 correspond to the emitter (or anode) currents for which the slope of the αT curve is steepest (Figure 3.4(b)). In region A the rate that αT builds up with respect to changes of IE (or IA) is high, little charge is lost by recombination, and therefore, a minimum charge is required for turn−on. In region C of Figure 3.3, lower gate current corre- sponds to small IE (or IA) for which the slope of αT, as well as αT itself, is small. It takes a large change in IE (or IA) in order to build up αT. In this region, a lot of the charge supplied through the gate is lost by recombination. The charge required for turn−on increases markedly as the gate current is decreased to the threshold level. Below this threshold, the device will not turn on regardless of how long the pulse width becomes. At this point, the slope of αT is equal to zero; all of the charge supplied is lost completely in recombination or drained out through gate−cathode shunt resistance. A qualitative analysis of variation of charge with pulse width at region A and C is discussed in Appendix II. In region B, as the gate current level gets higher and the pulse width smaller, there are two effects that contribute to an increasing charge requirement to trigger−on the device: (1) the decreasing slope of αT and, (2) the transit time effect. As mentioned previously, it takes some multiple of the transit time for turn−on. As the gate pulse width decreases to N (tN1 + tP2) or less, (where N is a positive real number, tN1 = transit time of base N1, and tP2 = transit time of base P2) the amount of current required to turn−on the device should be large enough to flood the gate to cathode junction nearly instantaneously with a charge which corresponds to IE (or IA) high enough to give αT u1.
- 32. http://onsemi.com 32 IE, EMITTER CURRENT (mA) 3000.1 0.8 0.4 0.2 0 a 1001.0 10 0.6 1.0 ,CURRENTAMPLIFICATIONFACTOR N−P−N SECTION a2 P−N−P SECTION a1 IE, EMITTER CURRENT (mA) 3000.1 0.8 0.4 0.2 0 a 1001.0 10 0.6 1.4 ,CURRENTAMPLIFICATIONFACTOR 1.0 1.2 A B C Figure 3.4(a). The Variation of α1 and α2 with Emitter Current for the Two Sections of Two Typical Silicon Controlled Rectifiers Figure 3.4(b). Typical Variation of αT versus Emitter Current CAPACITANCE CHARGE TRIGGERING Using a gate trigger circuit as shown in Figure 3.5, the charge required for turn−on increases with the value of capacitance used as shown in Figure 3.7. Two reasons may account for the increasing charge characteristics: 1) An effect due to threshold current. 2) An effect due to variation of gate spreading resistance. 0 TO COMMUTATING CIRCUIT SCR C RS DV1 Figure 3.5. Gate Circuit of Capacitance Charge Triggering Figure 3.6. Gate Current Waveform in Capacitance Charge Triggering ÇÇÇÇÇÇÇÇ ÇÇÇÇ ÉÉÉÉÉÉÉÉ ÉÉÉÉ DV1 rȀG1 ) R S DV2 rȀG2 ) R S e * * t (rȀG2 ) R S )C2 e*t (rȀG1 ) RS)C1 DV2 rȀG2 ) R S DV1 rȀG1 ) R S C1 t C2 DV1C1 + DV2C2 10% 90% |(r′G1 + RS)(C1)|(Ithr) |(r′G2 + RS)(C2) |(Ithr) tfi = 2.2 (r′G1 + RS)C1 SHADED AREA I = |(r′G1 + RS)(C1)|(Ithr) SHADED AREA II = |(r′G2 + RS)(C2)|(Ithr) PULSE WIDTH, t tf2 tf1 Ithr I II
- 33. http://onsemi.com 33 Consider the gate current waveform in Figure 3.6; the triggering pulse width is made large enough such that τuutfl; the threshold trigger current is shown as Ithr. All of the charge supplied at a transient current level less than Ithr is lost by recombination, as shown in the shaded regions. The gate spreading resistance (r′G) of the gate junction varies inversely with peak current; the higher the peak current, the smaller the gate spreading resistance. Varia- tion of gate spreading resistance measured by the method of Time Domain Reflectometry is plotted in Figure 3.8. From the data of Figure 3.7, it is clear that for larger values of capacitance a lower voltage level is required for turn−on. The peak current of the spike in Figure 3.6 is given by I pk + ΔV Rs ) r′G ; the smaller ΔV, the smaller Ipk. Smaller Ipk in turn yields large r′G, so that r′G is dependent on the value of capacitance used in capaci- tance charge triggering. This reasoning is confirmed by measuring the fall time of the gate trigger voltage and calculating the transient gate spreading resistance, r′G, from: Rs ) r′G + tf 2.2 C . Results are plotted in Figure 3.9. As expected, r′G increases with increasing values of capacitance used. Referring back to Figure 3.6, for the same amount of charge (C ΔV), the larger the (Rs + r′G)C time constant of the current spike, the more charge under the threshold level is lost in recombination. Increasing the value of C will increase the time constant more rapidly than if r′G were invariant. Therefore, increasing the value of C should increase the charge lost as shown in Figure 3.7. Note that a two order of magnitude increase in capacitance increased the charge by less than 3:1. C, CAPACITANCE (pF) 2000100 7.0 3.0 2.0 1.0 1000200 500 5.0 10 5000 ,MINIMUMTRIGGERCHARGE,Q(nc) 15 Qin 10,000 VAK = 10 V TA = −15°C HIGH UNIT LOW UNIT PULSE WIDTH = 50 ms Figure 3.7. Variation of Trigger Charge versus Capacitance Used GATE CURRENT (mA) 2000.1 3.0 0.5 0.3 0.2 10020 50 2.0 1.0 500 NORMALIZEDGATESPREADINGRESISTANCE 1000 LOW UNIT HIGH UNIT IA = 1 A TA = 25°C VAK = 10 V Z0 = 50 W 0.7 Figure 3.8. Variation of Gate Spreading Resistance versus Gate Peak Current EFFECT OF TEMPERATURE The higher the temperature, the less charge required to turn on the device, as shown in Figure 3.10. At the range of temperatures where the SCR is operated the life time of minority carriers increases with temperature; therefore less charge into the gate is lost in recombination. As analyzed in Appendix II, there are three components of charge involved in gate triggering: (1) Qr, charge lost in recombination, (2) Qdr, charge drained out through the built−in gate−cathode shunt resistance, (3) Qtr, net charge for triggering. All of them are temperature dependent. Since the temperature coefficient of voltage across a p−n junction is small, Qdr may be considered invariant of temperature. At the temperature range of operation, the temperature is too low to give rise to significant impurity gettering, lifetime increases with temperature causing Qr to decrease with increasing temperature. Also, Qtr decreases with increasing temperature because at a constant current the αT of the device in the blocking state increases with temperature;7 in other words, to attain αT = 1 at an elevated temperature, less anode current, hence gate current [see equation (3) of Appendix I], is needed; therefore, Qtr decreases. The input charge, being equal to the sum of Qtr, Qr, and Qdr, decreases with increasing temperature. The minimum current trigger charge decreases roughly exponentially with temperature. Actual data taken on an MCR729 deviate somewhat from exponential trend (Figure 3.10). At higher temperatures, the rate of decrease is less; also for different pulse widths the rates of decrease of Qin are different; for large pulse widths the recombina- tion charge becomes more significant than that of small pulse widths. As the result, it is expected and Figure 3.10 shows that Qin decreases more rapidly with temperature at high pulse widths. These effects are analyzed in
- 34. http://onsemi.com 34 Appendix II [equation (7), page 235]. The theory and experiment agree reasonably well. C, CAPACITANCE (pF) 1000200 30 10 20 0 300 500 40 2000 r VAK = 10 V T = 25°C ,GATESPREADINGRESISTANCE()G′W (RS ) rȀG ) t f 2.2C T, TEMPERATURE (°C) +65−15 10 8.0 9.0 4.0 +25 20 +105 Q VAK = 10 V t = GATE CURRENT PULSE WIDTH (Q = it) ,MINIMUMTRIGGERCHARGE(nc)in 7.0 6.0 5.0 t = 1 ms t = 500 ns t = 100 ns t = 300 ns Figure 3.9. Variation of Transient Base Spreading Resistance versus Capacitance Figure 3.10. Variation of Q versus Temperature EFFECT OF BLOCKING VOLTAGE An SCR is an avalanche mode device; the turn−on of the device is due to multiplication of carriers in the middle collector junction. The multiplication factor is given by the empirical equation M + · 1 1 * ( V VB )n (6) where M 5 Multiplication factor V 5 Voltage across the middle “collector’’ junction (voltage at which the device is blocking prior to turn−on) VB 5 Breakdown voltage of the middle “collector’’ junction n 5 Some positive number Note as V is increased, M also increases and in turn α increases (the current amplification factor α = γδβM where γ 5 Emitter efficiency, β 5 Base transport factor, and δ 5 Factor of recombination). The larger the V, the larger is α T. It would be expected for the minimum gate trigger charge to decrease with increasing V. Experimental results show this effect (see Figure 3.11). For the MCR729, the gate trigger charge is only slightly affected by the voltage at which the device is blocking prior to turn−on; this reflects that the exponent, n, in equation (6) is small. EFFECT OF GATE CIRCUIT As mentioned earlier, to turn on the device, the total amplification factor must be greater than unity. This means that if some current is being drained out of the gate which bleeds the regeneration current, turn−on will be affected. The higher the gate impedance, the less the gate trigger charge. Since the regenerative current prior to turn−on is small, the gate impedance only slightly affects the required minimum trigger charge; but in the case of over−driving the gate to achieve fast switching time, the gate circuit impedance will have noticeable effect. EFFECT OF INDUCTIVE LOAD The presence of an inductive load tends to slow down the change of anode current with time, thereby causing the required charge for triggering to increase with the value of inductance. For dc or long pulse width current triggering, the inductive load has little effect, but its effect increases markedly at short pulse widths, as shown in Figure 3.12. The increase in charge occurs because at short pulse widths, the trigger signal has decreased to a negligible value before the anode current has reached a level sufficient to sustain turn−on.
- 35. http://onsemi.com 35 VAK, ANODE VOLTAGE (V) 3010 10 8.0 9.0 4.0 20 50 Q TA = 25°C PW = 500 ns 0.05 mF CAP. DISCHARGE ,MINIMUMTRIGGERCHARGE(nc)in 7.0 6.0 5.0 2.0 3.0 1.0 100 200 500 1000 #1 #2 #3 t, MINIMUM PULSE WIDTH (ns) 30 80 40 50 Q TA = 25°C VAK = 10 V ,MINIMUMTRIGGERCHARGE(nc)in 60 20 0 100 200 500 100070 300 700 L = 100 mH L = 10 mH L = 0 mH Figure 3.11. Variation of Current Trigger Charge versus Blocking Voltage Prior to Turn−On Figure 3.12. Effect of Inductance Load on Triggering Charge USING NEGATIVE BIAS AND SHUNTING Almost all SCR’s exhibit some degree of turn−off gain. At normal values of anode current, negative gate current will not have sufficient effect upon the internal feedback loop of the device to cause any significant change in anode current. However, it does have a marked effect at low anode current levels; it can be put to advantage by using it to modify certain device parameters. Specifically, turn−off time may be reduced and hold current may be increased. Reduction of turn−off time and increase of hold current are useful in such circuits as inverters or in full−wave phase control circuits in which inductance is present. Negative gate current may, of course, be produced by use of an external bias supply. It may also be produced by taking advantage of the fact that during conduction the gate is positive with respect to the cathode and providing an external conduction path such as a gate−to−cathode resistor. All ON Semiconductor SCR’s, with the exception of sensitive gate devices, are constructed with a built in gate−to−cathode shunt, which produces the same effect as negative gate current. Further change in characteristics can be produced by use of an external shunt. Shunting does not produce as much of a change in characteristics as does negative bias, since the negative gate current, even with an external short circuit, is limited by the lateral resistance of the base layer. When using external negative bias the current must be limited, and care must be taken to avoid driving the gate into the avalanche region. The effects of negative gate current are not shown on the device specification sheets. The curves in Figure 3.13 represent measurements made on a number of SCRs, and should therefore not be considered as spec limits. They do, however, show definite trends. For example, all of the SCRs showed an improvement in turn−off time of about one−third by using negative bias up to the point where no further significant improvement was obtained. The increase in hold current by use of an external shunt resistor ranged typically between 5 and 75 percent, whereas with negative bias, the range of improvement ran typically between 2−1/2 and 7 times the open gate value. Note that the holding current curves are normalized and are referred to the open gate value.
- 36. http://onsemi.com 36 GATE−TO−CATHODE RESISTANCE (OHMS) 1.0 1.2 1.0 10010 1.6 1.4 5000 NORMALIZEDHOLDINGCURRENT 1000 SPREAD OF 5 DEVICES Figure 3.13(a). Normalized Holding Current versus Gate−to−Cathode Resistance GATE−TO−CATHODE VOLTAGE (VOLTS) 0 2.0 −4.0−2.0 6.0 4.0 −8.0 NORMALIZEDHOLDINGCURRENT −6.0 SPREAD OF 5 DEVICES −10 0 Figure 3.13(b). Normalized Holding Current versus Gate−to−Cathode Voltage GATE−TO−CATHODE VOLTAGE (VOLTS) 0 2.0 −5.0 6.0 4.0 TURN−OFFTIME(s) AVERAGE 10 DEVICES −10 0 m IF = 10 A IF = 5 A Figure 3.13(c). Turn−Off Time versus Bias REDUCING di/dt — EFFECT FAILURES Figure 3.14 shows a typical SCR structural cross section (not to scale). Note that the collector of transistor 1 and the base of transistor 2 are one and the same layer. This is also true for the collector of transistor 2 and the base of transistor 1. Although for optimum performance as an SCR the base thicknesses are great compared to a normal transistor, nevertheless, base thickness is still small compared to the lateral dimensions. When applying positive bias to the gate, the transverse base resistance, spreading resistance or rb′ will cause a lateral voltage drop which will tend to forward bias those parts of the transistor 1 emitter−junction closest to the base contact (gate) more heavily, or sooner than the portions more remote from the contact area. Regenerative action, consequently will start in an area near the gate contact, and the SCR will turn on first in this area. Once on, conduction will propagate across the entire junction. CATHODE T2 T1LAYER (C) (B) (B) (C) (E) (E) GATENO. 4 NO. 3 NO. 2 NO. 1 ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ P N N P ANODE ÉÉÉÉÉÉ Figure 3.14. Construction of Typical SCR The phenomenon of di/dt failure is related to the turn−on mechanism. Let us look at some of the external factors involved and see how they contribute. Curve 3.15(a) shows the fall of anode−to−cathode voltage with time. This fall follows a delay time after the application of the gate bias. The delay time and fall time together are called turn−on time, and, depending upon the device, will take anywhere from tens of nanoseconds up to a few microseconds. The propagation of conduction across the entire junction requires a considerably longer time. The time required for propagation or equalization of conduc- tion is represented approximately by the time required for the anode−to−cathode voltage to fall from the 10 percent point to its steady state value for the particular value of anode current under consideration (neglecting the change due to temperature effects). It is during the interval of time between the start of the fall of anode−to−cathode voltage and the final equalization of conduction that the SCR is most susceptible to damage from excessive current.
- 37. http://onsemi.com 37 Let us superimpose a current curve (b) on the anode−to− cathode voltage versus time curve to better understand this. If we allow the current to rise rapidly to a high value we find by multiplying current and voltage that the instantaneous dissipation curve (c) reaches a peak which may be hundreds of times the steady state dissipation level for the same value of current. At the same time it is important to remember that the dissipation does not take place in the entire junction, but is confined at this time to a small volume. Since temperature is related to energy per unit volume, and since the energy put into the device at high current levels may be very large while the volume in which it is concentrated is very small, very high spot temperatures may be achieved. Under such conditions, it is not difficult to attain temperatures which are sufficient to cause localized melting of the device. Even if the peak energy levels are not high enough to be destructive on a single−shot basis, it must be realized that since the power dissipation is confined to a small area, the power handling capabilities of the device are lessened. For pulse service where a significant percentage of the power per pulse is dissipated during the fall−time interval, it is not acceptable to extrapolate the steady state power dissipation capability on a duty cycle basis to obtain the allowable peak pulse power. TIME (ms) 0.1 1.0 100 50 PERCENTOFMAXIMUM(%) 0 INSTANTANEOUS POWER DISSIPATION (c) ANODE TO CATHODE VOLTAGE (a) ANODE CURRENT (b) Figure 3.15. Typical Conditions — Fast−Rise, High Current Pulse The final criterion for the limit of operation is junction temperature. For reliable operation the instantaneous junction temperature must always be kept below the maximum junction temperature as stated on the manufac- turer’s data sheet. Some SCR data sheets at present include information on how to determine the thermal response of the junction to current pulses. This informa- tion is not useful, however, for determining the limitations of the device before the entire junction is in conduction, because they are based on measurements made with the entire junction in conduction. At present, there is no known technique for making a reasonably accurate measurement of junction temperature in the time domain of interest. Even if one were to devise a method for switching a sufficiently large current in a short enough time, one would still be faced with the problem of charge storage effects in the device under test masking the thermal effects. Because of these and other problems, it becomes necessary to determine the device limitations during the turn−on interval by destructive testing. The resultant information may be published in a form such as a maximum allowable current versus time, or simply as a maximum allowable rate of rise of anode current (di/dt). Understanding the di/dt failure mechanism is part of the problem. To the user, however, a possible cure is infinitely more important. There are three approaches that should be considered. Because of the lateral base resistance the portion of the gate closest to the gate contact is the first to be turned on because it is the first to be forward biased. If the minimum gate bias to cause turn−on of the device is used, the spot in which conduction is initiated will be smallest in size. By increasing the magnitude of the gate trigger pulse to several times the minimum required, and applying it with a very fast rise time, one may considerably increase the size of the spot in which conduction starts. Figure 3.16(a) illustrates the effect of gate drive on voltage fall time and Figure 3.16(b) shows the improvement in instantaneous dissipation. We may conclude from this that overdriving the gate will improve the di/dt capabilities of the device, and we may reduce the stress on the device by doing so. t, TIME (ms) 4.00 300 100 50 0 3.52.5 3.0 250 200 4.5 ANODETOCATHODEVOLTAGE(VOLTS) 5.0 150 2.01.50.5 1.0 350 PEAK ANODE CURRENT = 500 A IGT = 2 A IGT = 17 mA Figure 3.16(a). Effect of Gate Drive on Fall Time
- 38. http://onsemi.com 38 A very straightforward approach is to simply slow down the rate of rise of anode current to insure that it stays within the device ratings. This may be done simply by adding some series inductance to the circuit. t, TIME (ms) 4.00 60 20 10 0 3.52.5 3.0 50 40 4.5 INSTANTANEOUSPOWERDISSIPATION(kW) 5.0 30 2.01.50.5 1.0 70 PEAK ANODE CURRENT = 500 A IGT = 2 A IGT = 17 mA Figure 3.16(b). Effect of Gate Drive On Turn−On Dissipation If the application should require a rate of current rise beyond the rated di/dt limit of the device, then another approach may be taken. The device may be turned on to a relatively low current level for a sufficient time for a large part of the junction to go into conduction; then the current level may be allowed to rise much more rapidly to very high levels. This might be accomplished by using a delay reactor as shown in Figure 3.17. Such a reactor would be wound on a square loop core so that it would have sharp saturation characteristic and allow a rapid current rise. It is also possible to make use of a separate saturation winding. Under these conditions, if the delay is long enough for the entire junction to go into conduction, the power handling capabilities of the device may be extrapolated on a duty cycle basis. SCR RL DELAY REACTOR + − Figure 3.17. Typical Circuit Use of a Delay Reactor WHY AND HOW TO SNUB THYRISTORS Inductive loads (motors, solenoids, etc.) present a problem for the power triac because the current is not in phase with the voltage. An important fact to remember is that since a triac can conduct current in both directions, it has only a brief interval during which the sine wave current is passing through zero to recover and revert to its blocking state. For inductive loads, the phase shift between voltage and current means that at the time the current of the power handling triac falls below the holding current and the triac ceases to conduct, there exists a certain voltage which must appear across the triac. If this voltage appears too rapidly, the triac will resume conduction and control is lost. In order to achieve control with certain inductive loads, the rate of rise in voltage (dv/dt) must be limited by a series RC network placed in parallel with the power triac as shown in Figure 3.18. The capacitor CS will limit the dv/dt across the triac. The resistor RS is necessary to limit the surge current from CS when the triac conducts and to damp the ringing of the capacitance with the load inductance LL. Such an RC network is commonly referred to as a “snubber.’’ Figure 3.19 shows current and voltage waveforms for the power triac. Commutating dv/dt for a resistive load is typically only 0.13 V/μs for a 240 V, 50 Hz line source and 0.063 V/μs for a 120 V, 60 Hz line source. For inductive loads the “turn−off’’ time and commutating dv/dt stress are more difficult to define and are affected by a number of variables such as back EMF of motors and the ratio of inductance to resistance (power factor). Although it may appear from the inductive load that the rate or rise is extremely fast, closer circuit evaluation reveals that the commutating dv/dt generated is restricted to some finite value which is a function of the load reactance LL and the device capacitance C but still may exceed the triac’s critical commutating dv/dt rating which is about 50 V/μs. It is generally good practice to use an RC snubber network across the triac to limit the rate of rise (dv/dt) to a value below the maximum allowable rating. This snubber network not only limits the voltage rise during commuta- tion but also suppresses transient voltages that may occur as a result of ac line disturbances. There are no easy methods for selecting the values for RS and CS of a snubber network. The circuit of Figure 3.18 is a damped, tuned circuit comprised of RS, CS, RL and LL, and to a minor extent the junction capacitance of the triac. When the triac ceases to conduct (this occurs every half cycle of the line voltage when the current falls below the holding current), the triac receives a step impulse of line voltage which depends on the power factor of the load. A given load fixes RL and LL; however, the circuit designer can vary RS and CS. Commutating dV/dt can be lowered by increasing CS while RS can be increased to decrease resonant “over ringing’’ of the tuned circuit.
- 39. http://onsemi.com 39 RS ZERO CROSSING CIRCUIT AC LOAD CS R LL RL 6 5 4 1 2 3 Figure 3.18. Triac Driving Circuit — with Snubber AC LINE VOLTAGE AC CURRENT VOLTAGE ACROSS POWER TRIAC IF(ON) IF(OFF) TIME t0 COMMUTATING dv/dt RESISTIVE LOAD AC LINE VOLTAGE AC CURRENT THROUGH POWER TRIAC VOLTAGE ACROSS POWER TRIAC IF(ON) IF(OFF) TIME t0 COMMUTATING dv/dt INDUCTIVE LOAD 0 d Figure 3.19. Current and Voltage Waveforms During Commutation BASIC CIRCUIT ANALYSIS Figure 3.20 shows an equivalent circuit used for analysis, in which the triac has been replaced by an ideal switch. When the triac is in the blocking or non−conduct- ing state, represented by the open switch, the circuit is a standard RLC series network driven by an ac voltage source. The following differential equation can be obtained by summing the voltage drops around the circuit; (RL ) RS) i(t) ) L di(t) dt ) qc(t) CS + VMsin(wt ) f) (2) in which i(t) is the instantaneous current after the switch opens, qc(t) is the instantaneous charge on the capacitor, VM is the peak line voltage, and φ is the phase angle by which the voltage leads the current prior to opening of the switch. After differentiation and rearrangement, the equa- tion becomes a standard second−order differential equation with constant coefficients. With the imposition of the boundary conditions that i(o) = 0 and qc(o) = 0 and with selected values for RL, L, RS and CS, the equation can be solved, generally by the use of a computer. Having determined the magnitude and time of occurrence of the peak voltage across the thyristor, it is then possible to calculate the values and times of the voltages at 10% and 63% of the peak value. This is necessary in order to compute the dv/dt stress as defined by the following equation: dv dt + V2 * V1 t2 * t1 where V1 and t1 are the voltage and time at the 10% point and V2 and t2 are the voltage and time at the 63% point. Solution of the differential equation for assumed load conditions will give the circuit designer a starting point for selecting RS and CS. Because the design of a snubber is contingent on the load, it is almost impossible to simulate and test every possible combination under actual operating conditions. It is advisable to measure the peak amplitude and rate of rise of voltage across the triac by use of an oscilloscope, then make the final selection of RS and CS experimentally. Additional comments about circuit values for SCRs and Triacs are made in Chapter 6.
- 40. http://onsemi.com 40 RS CS RLL LOAD AC POWER SOURCE Figure 3.20. Equivalent Circuit used for Analysis USING SENSITIVE GATE SCRs In applications of sensitive gate SCRs such as the ON Semiconductor 2N6237, the gate−cathode resistor, RGK (Figure 3.21) is an important factor. Its value affects, in varying degrees, such parameters as IGT, VDRM, dv/dt, IH, leakage current, and noise immunity. ANODE (A) GATE (G) CATHODE (K) RGK Figure 3.21. Gate−Cathode Resistor, RGK SCR CONSTRUCTION The initial step in making an SCR is the creation, by diffusion, of P−type layers is N−type silicon base material. Prior to the advent of the all−diffused SCR, the next step was to form the gate−cathode P−N junction by alloying in a gold−antimony foil. This produced a silicon P−N junction of the regrown type over most of the junction area. However, a resistive rather than semiconductor junction would form where the molten alloy terminated at the surface. This formed an internal RGK, looking in at the gate−cathode terminals, that reduced the “sensitivity’’ of the SCR. Modern practice is to produce the gate−cathode junction by masking and diffusing, a much more controllable process. It produces a very clean junction over the entire junction area with no unwanted resistive paths. Good dv/dt performance by larger SCRs, however, requires resistive paths distributed over the junction area. These are diffused in as emitter shorts and naturally desensitize the device. Smaller SCRs may rely on an external RGK because the lateral resistance in the gate layer is small enough to prevent leakage and dV/dt induced currents from forward biasing the cathode and triggering the SCR. Figure 3.22(a) shows the construction of a sensitive gate SCR and the path taken by leakage current flowing out through RGK. Large SCRs (Figure 3.22(b)) keep the path length small by bringing the gate layer up to contact the cathode metal. This allows the current to siphon out all−round the cathode area. When the chip dimensions are small there is little penalty in placing the resistor outside the package. This gives the circuit designer considerable freedom in tailor- ing the electrical properties of the SCR. This is a great advantage when low trigger or holding current is needed. Still, there are trade−offs in the maximum allowable junction temperature and dV/dt immunity that go with larger resistor values. Verifying that the design is adequate to prevent circuit upset by heat or noise is important. The rated value for RGK is usually 1 K Ohm. Lower values improve blocking and turn−off capability. K A G ÉÉÉÉÉÉ ÉÉÉÉÉÉCASE A P N P DIFFUSED CATHODE + − N GK ÉÉÉÉÉÉ ÉÉÉÉÉÉCASE A P N P EMITTER SHORTS N GK METAL DIFFUSED DIFFUSED BASE N N (a). SIMPLE CONSTRUCTION (b). SHORTED EMITTER CONSTRUCTION Figure 3.22. Sensitive Gate SCR Construction The sensitive gate SCR, therefore, is an all−diffused design with no emitter shorts. It has a very high impedance path in parallel with the gate−cathode P−N diode; the better the process is the higher this impedance, until a very good device cannot block voltage in the forward direction without an external RGK. This is so, because thermally generated leakage currents flowing from the anode into the gate junction are sufficient to turn on the SCR. The value for RGK is usually one kilohm and its presence and value affects many other parameters. FORWARD BLOCKING VOLTAGE AND CURRENT, VDRM AND IDRM The 2N6237 family is specified to have an IDRM, or anode−to−cathode leakage current, of less than 200 μA at maximum operating junction temperature and rated VDRM. This leakage current increases if RGK is omitted and, in fact, the device may well be able to regenerate and turn on. Tests were run on several 2N6239 devices to establish the dependency of the leakage current on RGK and to determine its relationship with junction tempera- ture, TJ, and forward voltage VAK (Figure 3.23a).
- 41. http://onsemi.com 41 Figure 3.23(a) is a plot of VAK, forward voltage, versus RGK taken at the maximum rated operating junction temperature of 110°C. With each device the leakage current, IAK, is set for a VAK of 200 V, then VAK reduced and RGK varied to re−establish the same leakage current. The plot shows that the leakage current is not strongly voltage dependent or, conversely, RGK may not be increased for derate. While the leakage current is not voltage dependent, it is very temperature dependent. The plot in Figure 3.23(b) of TJ, junction temperature, versus RGK taken at VDRM, the maximum forward blocking voltage shows this dependence. For each device (2N6329 again) the leakage current, IAK, was measured at the maximum operating junction tempera- ture of 110°C, then the junction temperature was reduced and RGK varied to re−establish that same leakage current. The plot shows that the leakage current is strongly depen- dent on junction temperature. Conversely RGK may be increased for derated temperature. A conservative rule of thumb is that leakage doubles every 10°C. If all the current flows out through RGK, triggering will not occur until the voltage across RGK reaches VGT. This implies an allowed doubling of the resistor for every 10° reduction in maximum junction temperature. However, this rule should be applied with caution. Static dV/dt may require a smaller resistor than expected. Also the leakage current does not always follow the 10° rule below 70°C because of surface effects. To summarize, the leakage current in a sensitive gate SCR is much more temperature sensitive than voltage sensitive. Operation at lower junction temperatures allows an increase in the gate−cathode resistor which makes the SCR−resistor combination more “sensitive.’’ RGK (OHMS) 0 140 120 100 3 K 180 V 160 2 K1 K 200 2N6239 TJ = 110°C IAK CONSTANT (VOLTS)AK Figure 3.23(a). VAK versus RGK (Typical) for Constant Leakage Current RGK (OHMS) 1 K 80 70 60 50 K 100 T 90 10 K5 K 110 2N6239 VAK = VDRM = 200 V IAK CONSTANT (C)J 100 K ° Figure 3.23(b). TJ versus RGK (Typical) for Constant Leakage Current RGK dv/dt CAG i RGK (W) 10 1V/ ms 10,0001,000100 MCR706−6 TJ = 110°C 400 V PEAK dv/dt,RATEOFRISEOFANODEVOLTAGE(V/s) 100,000 m 10V/ ms 1,000V/ ms 100V/ ms EXPONENTIAL METHOD IGT = 5.6 mA IGT = 27 mA Figure 3.23(c). dv/dt Firing of an SCR Figure 3.23(d). Static dv/dt as a function of Gate−Cathode Resistance on two devices with different sensitivity.
- 42. http://onsemi.com 42 RATE−OF−RISE OF ANODE VOLTAGE, dv/dt An SCR’s junctions exhibit capacitance due to the separation of charge when the device is in a blocking state. If an SCR is subjected to forward dv/dt, this capacitance can couple sufficient current into the SCR’s gate to turn it on, as shown in Figure 3.23(c). RGK acts as a diversionary path for the dv/dt current. (In larger SCRs, where the lateral gate resistance of the device limits the influence of RGK, this path is provided by the resistive emitter shorts mentioned previously.) The gate−cathode resistor, then, might be expected to have some effect on the dv/dt performance of the SCR. Figure 3.23(d) confirms this behavior. The static dV/dt for two MCR706 devices varies over several powers of ten with changes in the gate−cathode resistance. Selection of the external resistor allows the designer to trade dynamic performance with the amount of drive current provided to the resistor−SCR combination. The sensitive−gate device with low RGK provides performance approaching that of an equivalent non−sensitive SCR. This strong dependence does not exist with conventional shorted emitter SCRs because of their internal resistor. The conventional SCR cannot be made more sensitive, but the sensitive−gate device attributes can be reliably set with the resistor to any desired point along the sensitivity range. Low values of resistance make the dV/dt performance more uniform and predictable. The curves for two devices with different sensitivity diverge at high values of resistance because the device response becomes more dependent on its sensitiv- ity. The resistor is the most important factor determining the static dV/dt capability of the product. Reverse biasing the gate also improves dV/dt. A 2N6241 improved by a factor of 50 with a 1 volt bias. GATE CURRENT, IGT The total gate current that a gating circuit must supply is the sum of the current that the device itself requires to fire and the current flowing to circuit ground through RGK, as shown in Figure 3.24. IGT, the current required by the device so that it may fire, is usually specified by the device manufacturer as a maximum at some temperature (for the 2N6236 series it is 500 μA maximum at −40°C). The current flowing through RGK is defined by the resistor value and by the gate−to−cathode voltage that the SCR needs to fire. This is 1 V maximum at −40°C for the 2N6237 series, for example. RGKVGT ITOT IGT IR Figure 3.24. SCR and RGK “Gate’’ Currents GATE CURRENT, IGT(min) SCR manufacturers sometimes get requests for a sensitive−gate SCR specified with an IGT(min), that is, the maximum gate current that will not fire the device. This requirement conflicts with the basic function of a sensitive gate SCR, which is to fire at zero or very low gate current, IGT(max). Production of devices with a measurable IGT(min) is at best difficult and deliveries can be sporadic! One reason for an IGT(min) requirement might be some measurable off−state gating circuit leakage current, perhaps the collector leakage of a driving transistor. Such current can readily be bypassed by a suitably chosen RGK. The VGT of the SCR at the temperature in question can be estimated from Figure 3.25, an Ohm’s Law calculation made, and the resistor installed to define this “won’t fire’’ current. This is a repeatable design well in the control of the equipment designer. GATE TRIGGER VOLTAGE, VGT The gate−cathode junction is a p−n silicon junction. So the gate trigger voltage follows the diode law and has roughly the same temperature coefficient as a silicon diode, −2mV/C. Figure 3.25 is a plot of VGT versus temperature for typical sensitive gate SCRs. They are prone to triggering by noise coupled through the gate circuit because of their low trigger voltage. The smallest noise voltage margin occurs at maximum temperature and with the most sensitive devices. JUNCTION TEMPERATURE (°C) 110−30 0.7 0.3 0.2 0.1 9050 70 0.6 0.5 V 130 0.4 30−10 10 0.8 0.9 ,GATETRIGGERVOLTAGE(VOLTS)GT LOW UNIT HIGH UNIT IGT = 20 NA @ 300°K IGT = 200 mA @ 300°K Figure 3.25. Typical VGT vs TJ
- 43. http://onsemi.com 43 HOLDING CURRENT, IH The holding current of an SCR is the minimum anode current required to maintain the device in the on state. It is usually specified as a maximum for a series of devices (for instance, 5 mA maximum at 25°C for the 2N6237 series). A particular device will turn off somewhere between this maximum and zero anode current and there is perhaps a 20−to−1 spread in each lot of devices. Figure 3.26 shows the holding current increasing with decreasing RGK as the resistor siphons off more and more of the regeneratively produced gate current when the device is in the latched condition. Note that the gate−cathode resistor determines the holding current when it is less than 100 Ohms. SCR sensitivity is the determining factor when the resistor exceeds 1 meg Ohm. This allows the designer to set the holding current over a wide range of possible values using the resistor. Values typical of those in conventional non−sensitive devices occur when the external resistor is similar to their internal gate−cathode shorting resistance. The holding current uniformity also improves when the resistor is small. RGK, GATE−CATHODE RESISTANCE, KW 0.1 0.01 10010 1.0 I 1,000 0.1 1.0 10 ,HOLDINGCURRENT,mAH TJ = 25°C IGT = 20 NA IGT = 1.62 mA Figure 3.26. 2N5064 Holding Current NOISE IMMUNITY Changes in electromagnetic and electrostatic fields coupled into wires or printed circuit lines can trigger these sensitive devices, as can logic circuit glitches. The result is more serious than with a transistor since an SCR will latch on. Careful wire harness design (twisted pairs and adequate separation from high−power wiring) and printed circuit layout (gate and return runs adjacent to one another) can minimize potential problems. A gate cathode network consisting of a resistor and parallel capacitor also helps. The resistor provides a static short and is helpful with noise signals of any frequency. For example, with a 1,000 Ohm resistor, between 100 μA to 1 mA of noise current is necessary to generate enough voltage to fire the device. Adding a capacitor sized between 0.01 and 0.1 μF creates a noise filter and improves dV/dt by shunting dV/dt displacement current out through the gate terminal. These components must be placed as close as possible to the gate and cathode terminals to prevent lead inductance from making them ineffective. The use of the capacitor also requires the gate drive circuit to supply enough current to fire the SCR without excessive time delay. This is particularly important in applications with rapidly rising (di/dtu50 A/μs) anode current where a fast rise high amplitude gate pulse helps to prevent di/dt damage to the SCR. Reverse gate voltage can cause unwanted turn−off of the SCR. Then the SCR works like a gate turn−off thyristor. Turn−off by the gate signal is more probable with small SCRs because of the short distance between the cathode and gate regions. Whether turn−off occurs or not depends on many variables. Even if turn−off does not occur, the effect of high reverse gate current is to move the conduction away from the gate, reducing the effective cathode area and surge capability. Suppressing the reverse gate voltage is particularly important when the gate pulse duration is less than 1 microsecond. Then the part triggers by charge instead of current so halving of the gate pulse width requires double the gate current. Capacitance coupled gate drive circuits differentiate the gate pulse (Figure 3.27) leading to a reverse gate spike. The reverse gate voltage rating should not be exceeded to prevent avalanche damage. This discussion has shown that the use of RGK, the gate−cathode resistor, has many implications. Clear understanding of its need and its influence on the performance of the sensitive gate SCR will enable the designer to have better control of his circuit designs using this versatile part. OPTIONAL REVERSE GATE SUPPRESSOR DIODE Figure 3.27. Capacitance Coupled Gate Drive
- 44. http://onsemi.com 44 DRIVERS: PROGRAMMABLE UNIJUNCTION TRANSISTORS The programmable unijunction transistor (PUT) is a four layer device similar to an SCR. However, gating is with respect to the anode instead of the cathode. An external resistive voltage divider accurately sets the triggering voltage and allows its adjustment. The PUT finds limited application as a phase control element and is most often used in long duration or low battery drain timer circuits where its high sensitivity permits the use of large timing resistors and small capacitors. Like an SCR, the PUT is a conductivity modulated device capable of providing high current output pulses. OPERATION OF THE PUT The PUT has three terminals, an anode (A), gate (G), and cathode (K). The symbol and a transistor equivalent circuit are shown in Figure 3.28. As can be seen from the equivalent circuit, the device is actually an anode−gated SCR. This means that if the gate is made negative with respect to the anode, the device will switch from a blocking state to its on state. ANODE (A) (K) CATHODE GATE (G) G K A Figure 3.28(a). PUT Symbol Figure 3.28(b). Transistor Equivalent The PUT is a complementary SCR when its anode is connected like an SCR’s cathode and the circuit bias voltages are reversed. Negative resistance terminology describes the device characteristics because of the traditional application circuit. An external reference voltage must be maintained at the gate terminal. A typical relaxation type oscillator circuit is shown in Figure 3.29(a). The voltage divider shown is a typical way of obtaining the gate reference. In this circuit, the characteristic curve looking into the anode−cathode terminals would appear as shown in Figure 3.29(b). The peak and valley points are stable operating points at either end of a negative resistance region. The peak point voltage (VP) is essentially the same as the external gate reference, the only difference being the gate diode drop. Since the reference is circuit and not device dependent, it may be varied, and in this way, VP is programmable. In characterizing the PUT, it is convenient to speak of the Thevenin equivalent circuit for the external gate voltage (VS) and the equivalent gate resistance (RG). The parameters are defined in terms of the divider resistors (R1 and R2) and supply voltage as follows: VS + R1 V1ń(R1 ) R2) RG + R1 R2ń(R1 ) R2) Most device parameters are sensitive to changes in VS and RG. For example, decreasing RG will cause peak and valley currents to increase. This is easy to see since RG actually shunts the device and will cause its sensitivity to decrease. CHARACTERISTICS OF THE PUT Table 3.1 is a list of typical characteristics of ON Semiconductor’s 2N6027/2N6028 of programmable uni- junction transistors. The test circuits and test conditions shown are essentially the same as for the data sheet characteristics. The data presented here defines the static curve shown in Figure 3.29(b) for a 10 V gate reference (VS) with various gate resistances (RG). It also indicates the leakage currents of these devices and describes the output pulse. Values given are for 25°C unless otherwise noted.
- 45. http://onsemi.com 45 VS R1 R2 RT CT OUTPUT R0 V1 + − IGAO IP IV IF IA VF VV VP VS VAK PEAK POINT NEGATIVE RESISTANCE REGION VALLEY POINT Figure 3.29(a). Typical Oscillator Circuit Figure 3.29(b). Static Characteristics Table 3.1. Typical PUT Characteristics Symbol Test Circuit Figure Test Conditions 2N6027 2N6028 Unit IP 3.30 RG = 1 mΩ RG = 10 kΩ 1.25 4 0.08 0.70 μA μA IV 3.30 RG = 1 MΩ RG = 10 kΩ 18 150 18 150 μA μA VAG (See Figure 3.31) IGAO VS = 40 V (See Figure 3.32) IGKS VS = 40 V 5 5 nA VF Curve Tracer Used IF = 50 mA 0.8 0.8 V VO 3.33 11 11 V tr 3.34 40 40 ns PEAK POINT CURRENT, (IP) The peak point is indicated graphically by the static curve. Reverse anode current flows with anode voltages less than the gate voltage (VS) because of leakage from the bias network to the charging network. With currents less than IP, the device is in a blocking state. With currents above IP, the device goes through a negative resistance region to its on state. The charging current, or the current through a timing resistor, must be greater than IP at VP to insure that a device will switch from a blocking to an on state in an oscillator circuit. For this reason, maximum values of IP are given on the data sheet. These values are dependent on VS temperature, and RG. Typical curves on the data sheet indicate this dependence and must be consulted for most applications. The test circuit in Figure 3.30 is a sawtooth oscillator which uses a 0.01 μF timing capacitor, a 20 V supply, an adjustable charging current, and equal biasing resistors (R). The two biasing resistors were chosen to given an equivalent RG of 1 MΩ and 10 kΩ. The peak point current was measured with the device off just prior to oscillation as detected by the absence of an output voltage pulse. The 2N5270 held effect transistor circuit is used as a current source. A variable gate voltage supply was used to control this current. VALLEY POINT CURRENT, (IV) The valley point is indicated graphically in Figure 3.28. With currents slightly less than IV, the device is in an unstable negative resistance state. A voltage minimum occurs at IV and with higher currents, the device is in a stable on state. When the device is used as an oscillator, the charging current or the current through a timing resistor must be less than IV at the valley point voltage (VV). For this reason, minimum values for IV are given on the data sheet for RG = 10 kΩ. With RG = 1 MΩ, a reasonable “low’’ is 2 μA for all devices. When the device is used in the latching mode, the anode current must be greater than IV. Maximum values for IV are given with RG = 1 MΩ. All devices have a reasonable “high’’ of 400 μA IV with RG = 10 kΩ.
- 46. http://onsemi.com 46 PEAK POINT VOLTAGE, (VP) The unique feature of the PUT is that the peak point voltage can be determined externally. This programmable feature gives this device the ability to function in voltage controlled oscillators or similar applications. The trigger- ing or peak point voltage is approximated by VP ≈ VT ) VS, where VS is the unloaded divider voltage and VT is the offset voltage. The actual offset voltage will always be higher than the anode−gate voltage VAG, because IP flows out of the gate just prior to triggering. This makes VT = VAG + IP RG. A change in RG will affect both VAG and IP RG but in opposite ways. First, as RG increases, IP decreases and causes VAG to decrease. Second, since IP does not decrease as fast as RG increases, the IP RG product will increase and the actual VT will increase. These second order effects are difficult to predict and measure. Allowing VT to be 0.5 V as a first order approximation gives sufficiently accurate results for most applications. The peak point voltage was tested using the circuit in Figure 3.30 and a scope with 10 MΩ input impedance across the PUT. A Tektronix, Type W plug−in was used to determine this parameter. FORWARD ANODE−GATE VOLTAGE, (VAG) The forward anode−to−gate voltage drop affects the peak point voltage as was previously discussed. The drop is essentially the same as a small signal silicon diode and is plotted in Figure 3.31. The voltage decreases as current decreases, and the change in voltage with temperature is greater at low currents. At 10 nA the temperature coefficient is about −2.4 V/°C and it drops to about −1.6 mV/°C at 10 mA. This information is useful in applications where it is desirable to temperature compen- sate the effect of this diode. GATE−CATHODE LEAKAGE CURRENT, (IGKS) The gate−to−cathode leakage current is the current that flows from the gate to the cathode with the anode shorted to the cathode. It is actually the sum of the open circuit gate−anode and gate−cathode leakage currents. The shorted leakage represents current that is shunted away from the voltage divider. 20 V R R + − +− VG G RS PUT UNDER TEST S D 2N5270 IP, IV 20 0.01 mF Vp OUTPUT PULSE R = 2 RG VS = 10 V NOTES: 1) VARIOUS SENSE RESISTORS (RS) ARE USED TO KEEP THE SENSE VOLTAGE NEAR 1 Vdc. 2) THE GATE SUPPLY (VG) IS ADJUSTED FROM ABOUT −0.5 V TO +20 V. Figure 3.30. Test Circuit for IP, VP and IV GATE−ANODE LEAKAGE CURRENT, (IGAO) The gate−to−anode leakage current is the current that flows from the gate to the anode with the cathode open. It is important in long duration timers since it adds to the charging current flowing into the timing capacitor. The typical leakage currents measured at 40 V are shown in Figure 3.32. Leakage at 25°C is approxi- mately 1 nA and the current appears to double for about every 10°C rise in temperature. FORWARD VOLTAGE, (VF) The forward voltage (VF) is the voltage drop between the anode and cathode when the device is biased on. It is the sum of an offset voltage and the drop across some internal dynamic impedance which both tend to reduce the output pulse. The typical data sheet curve shows this impedance to be less than 1 ohm for up to 2 A of forward current.
- 47. http://onsemi.com 47 PEAK OUTPUT VOLTAGE, (VO) The peak output voltage is not only a function of VP, VF and dynamic impedance, but is also affected by switching speed. This is particularly true when small capacitors (less than 0.01 μF) are used for timing since they lose part of their charge during the turn on interval. The use of a relatively large capacitor (0.2 μF) in the test circuit of Figure 3.33 tends to minimize this last effect. The output voltage is measured by placing a scope across the 20 ohm resistor which is in series with the cathode lead. RISE TIME, (tr) Rise time is a useful parameter in pulse circuits that use capacitive coupling. It can be used to predict the amount of current that will flow between these circuits. Rise time is specified using a fast scope and measuring between 0.6 V and 6 V on the leading edge of the output pulse. MINIMUM AND MAXIMUM FREQUENCY In actual tests with devices whose parameters are known, it is possible to establish minimum and maximum values of timing resistors that will guarantee oscillation. The circuit under discussion is a conventional RC relaxation type oscillator. To obtain maximum frequency, it is desirable to use low values of capacitance (1000 pF) and to select devices and bias conditions to obtain high IV. It is possible to use stray capacitance but the results are generally unpredictable. The minimum value of timing resistance is obtained using the following rule of thumb: R(min) + 2(V1 * VV)ńIV where the valley voltage (VV) is often negligible. To obtain minimum frequency, it is desirable to use high values of capacitance (10 μF) and to select devices and bias conditions to obtain low IP. It is important that the capacitor leakage be quite low. Glass and mylar dielectrics are often used for these applications. The maximum timing resistor is as follows: R(max) + (VI * VP)ń2IP In a circuit with a fixed value of timing capacitance, our most sensitive PUT, the 2N6028, offers the largest dynamic frequency range. Allowing for capacitance and bias changes, the approximate frequency range of a PUT is from 0.003 Hz to 2.5 kHz. IAG (mA) 0.01 0 10010 0.7 V 1 K 0.1 1.0 0.9 (VOLTS)AG 25°C 10 K 0.3 0.5 0.1 75°C Figure 3.31. Voltage Drop of 2N6027 Series IGAO, GATE TO ANODE LEAKAGE CURRENT (nA) 20 10 40 ° 30 1.0 70 TEMPERATURE(C) 60 50 Figure 3.32. Typical Leakage Current of the 2N6027, 2N6028 Reverse Voltage Equals 40 V A 1 mF 16 k OUTPUT 27 k 20 V + − 510 k G 20 K V0 0.2 mF Figure 3.33. PUT Test Circuit for Peak Output Voltage (Vo)
- 48. http://onsemi.com 48 A 0.001 mF 16 k V1 20 V + − 510 k G 20 K 1000 pF TO TEKTRONICS TYPE 567 OR EQUIVALENT RG = 10 k 27 k 100 100 Figure 3.34. tr Test Circuit for PUTs A 1 k OUTPUT 12 V + − RT G 75 K 0.01 mF 2 k Figure 3.35. Uncompensated Oscillator TEMPERATURE COMPENSATION The PUT with its external bias network exhibits a relatively small frequency change with temperature. The uncompensated RC oscillator shown in Figure 3.35 was tested at various frequencies by changing the timing resistor RT. At discrete frequencies of 100, 200, 1000 and 2000 Hz, the ambient temperature was increased from 25° to 60°C. At these low frequencies, the negative tempera- ture coefficient of VAG predominated and caused a consistent 2% increase in frequency. At 10 kHz, the frequency remained within 1% over the same temperature range. The storage time phenomenon which increases the length of the output pulse as temperature increases is responsible for this result. Since this parameter has not been characterized, it is obvious that temperature com- pensation is more practical with relatively low frequency oscillators. Various methods of compensation are shown in Figure 3.36. In the low cost diode−resistor combination of 3.36(a), the diode current is kept small to cause its temperature coefficient to increase. In 3.36(b), the bias current through the two diodes must be large enough so that their total coefficient compensates for VAG. The transistor approach in 3.36(c) can be the most accurate since its temperature coefficient can be varied indepen- dently of bias current. R 100 k R 1 M (a) DIODE−RESISTOR (b) DUAL−DIODE (c) TRANSISTOR Figure 3.36. Temperature Compensation Techniques
- 49. http://onsemi.com 49 SECTION 4 THE SIDAC, A NEW HIGH VOLTAGE BILATERAL TRIGGER Edited and Updated The SIDAC is a high voltage bilateral trigger device that extends the trigger capabilities to significantly higher voltages and currents than have been previously obtain- able, thus permitting new, cost-effective applications. Being a bilateral device, it will switch from a blocking state to a conducting state when the applied voltage of either polarity exceeds the breakover voltage. As in other trigger devices, (SBS, Four Layer Diode), the SIDAC switches through a negative resistance region to the low voltage on-state (Figure 4.1) and will remain on until the main terminal current is interrupted or drops below the holding current. SIDAC’s are available in the large MKP3V series and economical, easy to insert, small MKP1V series axial lead packages. Breakdown voltages ranging from 104 to 280 V are available. The MKP3V devices feature bigger chips and provide much greater surge capability along with somewhat higher RMS current ratings. The high-voltage and current ratings of SIDACs make them ideal for high energy applications where other trigger devices are unable to function alone without the aid of additional power boosting components. The basic SIDAC circuit and waveforms, operating off of ac are shown in Figure 4.2. Note that once the input voltage exceeds V(BO), the device will switch on to the forward on-voltage VTM of typically 1.1 V and can conduct as much as the specified repetitive peak on-state current ITRM of 20 A (10 μs pulse, 1 kHz repetition frequency). RS + (V(BO) * VS) (IS * I(BO)) V(BO) VDRM I(BO) VS IS SLOPE = RS IDRM IH VTMITM Figure 4.1(a). Idealized SIDAC V-I Characteristics Figure 4.1(b). Actual MKP1V130 V-I Characteristic. Horizontal: 50 V/Division. Vertical: 20 mA/Division. (0,0) at Center. RL = 14 k Ohm.
- 50. http://onsemi.com 50 RS + (V(BO) * VS) (IS * I(BO)) Figure 4.2. Basic SIDAC Circuit and Waveforms RS = SIDAC SWITCHING RESISTANCE CONDUCTION ANGLE θOFFθON IT IH IH V(BO) V(BO) VIN VT RLt⎥RS⎥ V(BO) RL VIN I Operation from an AC line with a resistive load can be analyzed by superimposing a line with slope = −1/RL on the device characteristic. When the power source is AC, the load line can be visualized as making parallel translations in step with the instantaneous line voltage and frequency. This is illustrated in Figure 4.3 where v1 through v5 are the instantaneous open circuit voltages of the AC generator and i1 through i5 are the corresponding short circuit currents that would result if the SIDAC was not in the circuit. When the SIDAC is inserted in the circuit, the current that flows is determined by the intersection of the load line with the SIDAC characteris- tic. Initially the SIDAC blocks, and only a small leakage current flows at times 1 through 4. The SIDAC does not turn-on until the load line supplies the breakover current (I(BO)) at the breakover voltage (V(BO)). If the load resistance is less than the SIDAC switching resistance, the voltage across the device will drop quickly as shown in Figure 4.2. A stable operating point (VT, IT) will result if the load resistor and line voltage provide a current greater than the latching value. The SIDAC remains in an “on” condition until the generator voltage causes the current through the device to drop below the holding value (IH). At that time, the SIDAC switches to the point (Voff, Ioff) and once again only a small leakage current flows through the device. RLtȧRSȧ i + v RL Figure 4.3. Load Line for Figure 4.2. (1/2 Cycle Shown.) (VOFF, IOFF) (VT, IT) i1 IH i3 i5 RL (VBO, IBO) v v5v4v3v2v1 i i SLOPE + I RL v1, ..., v5 = INSTANTANEOUS OPEN CIRCUIT VOLTAGES AT TIME 1, ..., 5 i1, ..., i5 = INSTANTANEOUS SHORT CIRCUIT CURRENTS AT TIME 1, ..., 5
- 51. http://onsemi.com 51 Figure 4.4 illustrates the result of operating a SIDAC with a resistive load greater than the magnitude of its switching resistance. The behavior is similar to that described in Figures 4.2 and 4.3 except that the turn-on and turn-off of the SIDAC is neither fast nor complete. Stable operating points on the SIDAC characteristics between (V(BO), I(BO)) and (VS, IS) result as the generator voltage increases from v2 to v4. The voltage across the SIDAC falls only partly as the loadline sweeps through this region. Complete turn-on of the SIDAC to (VT, IT) does not occur until the load line passes through the point (VS, IS). The load line illustrated in Figure 4.4 also results in incomplete turn-off. When the current drops below IH, the operating point switches to (Voff, Ioff) as shown on the device characteristic. Figure 4.4. High Resistance Load Line with Incomplete Switching RLuȧRSȧ RS = SIDAC SWITCHING RESISTANCE (VBO, IBO) (VT, IT) IH (VS, IS) (VOFF, IOFF) v v1 Iv RL i1 i2 i3 i4 v2 v3 v4 The switching current and voltage can be 2 to 3 orders of magnitude greater than the breakover current and on-state voltage. These parameters are not as tightly specified as VBO and IBO. Consequently operation of the SIDAC in the state between fully on and fully off is undesirable because of increased power dissipation, poor efficiency, slow switching, and tolerances in timing. Figure 4.5 illustrates a technique which allows the use of the SIDAC with high impedance loads. A resistor can be placed around the load to supply the current required to latch the SIDAC. Highly inductive loads slow the current rise and the turn-on of the SIDAC because of their L/R time constant. The use of shunt resistor around the load will improve performance when the SIDAC is used with inductive loads such as small transformers and motors. The SIDAC can be used in oscillator applications. If the load line intersects the device characteristic at a point where the total resistance (RL + RS) is negative, an unstable operating condition with oscillation will result. The resistive load component determines steady-state behavior. The reactive components determine transient behavior. Figure 4.10 shows a SIDAC relaxation oscilla- tor application. The wide span between IBO and IH makes the SIDAC easy to use. Long oscillation periods can be achieved with economical capacitor sizes because of the low device I(BO). Z1 is typically a low impedance. Consequently the SIDAC’s switching resistance is not important in this application. The SIDAC will switch from a blocking to full on-state in less than a fraction of a microsecond. The timing resistor must supply sufficient current to fire the SIDAC but not enough current to hold the SIDAC in an on-state. These conditions are guaranteed when the timing resistor is selected to be between Rmax and Rmin. For a given time delay, capacitor size and cost is minimized by selecting the largest allowable timing resistor. Rmax should be determined at the lowest temperature of operation because I(BO) increases then. The load line corresponding to Rmax passes through the point (V(BO), I(BO)) allowing the timing resistor to supply the needed breakover current at the breakover voltage. The load line for a typical circuit design should enclose this point to prevent sticking in the off state. Requirements for higher oscillation frequencies and greater stored energy in the capacitor result in lower values for the timing resistor. Rmin should be deter- mined at the highest operating temperature because IH is lower then. The load line determined by R and Vin should pass below IH on the device characteristic or the SIDAC will stick in the on-state after firing once. IH is typically more than 2 orders of magnitude greater than IBO. This makes the SIDAC well suited for operation over a wide temperature span.
- 52. http://onsemi.com 52 SIDAC turn-off can be aided when the load is an under-damped oscillatory CRL circuit. In such cases, the SIDAC current is the sum of the currents from the timing resistor and the ringing decay from the load. SIDAC turn-off behavior is similar to that of a TRIAC where turn-off will not occur if the rate of current zero crossing is high. This is a result of the stored charge within the volume of the device. Consequently, a SIDAC cannot be force commuted like an SCR. The SIDAC will pass a ring wave of sufficient amplitude and frequency. Turn-off requires the device current to approach the holding current gradually. This is a complex function of junction temperature, holding current magnitude, and the current wave parameters. TYPICAL: RSL = 2.7 k OHM 10 WATT RS = 3 k OHM RSL = TURN-ON SPEED UP RESISTOR RS = SIDAC SWITCHING RESISTANCE RSLtȧRSȧ RL RSL L Figure 4.5. Inductive Load Phase Control HIGH LOW v The simple SIDAC circuit can also supply switchable load current. However, the conduction angle is not readily controllable, being a function of the peak applied voltage and the breakover voltage of the SIDAC. As an example, for peak line voltage of about 170 V, at V(BO) of 115 V and a holding current of 100 mA, the conduction angle would be about 130°. With higher peak input voltages (or lower breakdown voltages) the conduction angle would correspondingly increase. For non-critical conduction angle, 1 A rms switching applications, the SIDAC is a very cost-effec- tive device. Figure 4.7 shows an example of a SIDAC used to phase control an incandescent lamp. This is done in order to lower the RMS voltage to the filament and prolong the life of the bulb. This is particularly useful when lamps are used in hard to reach locations such as outdoor lighting in signs where replacement costs are high. Bulb life span can be extended by 1.5 to 5 times depending on the type of lamp, the amount of power reduction to the filament, and the number of times the lamp is switched on from a cold filament condition. The operating cost of the lamp is also reduced because of the lower power to the lamp; however, a higher wattage bulb is required for the same lumen output. The maximum possible energy reduction is 50% if the lamp wattage is not increased. The minimum conduction angle is 90° because the SIDAC must switch on before the peak of the line voltage. Line regulation and breakover voltage tolerances will require that a conduction angle longer than 90° be used, in order to prevent lamp turn-off under low line voltage condi- tions. Consequently, practical conduction angles will run between 110° and 130° with corresponding power reductions of 10% to 30%. In Figure 4.2 and Figure 4.7, the SIDAC switching angles are given by: qON + SIN*1 (V(BO)ńVpk) where Vpk = Maximum Instantaneous Line Voltage qOFF + 180 * SIN*1 ǒ(IH@RL) ) VT Vpk Ǔ where θON, θOFF = Switching Angles in degrees VT = 1 V = Main Terminal Voltage at IT = IH Generally the load current is much greater than the SIDAC holding current. The conduction angle then becomes 180° minus θ(on). Rectifiers have also been used in this application to supply half wave power to the lamp. SIDAC’s prevent the flicker associated with half-wave operation of the lamp. Also, full wave control prevents the introduction of a DC component into the power line and improves the color temperature of the light because the filament has less time to cool during the off time. The fast turn-on time of the SIDAC will result in the generation of RFI which may be noticeable on AM radios operated in the vicinity of the lamp. This can be prevented by the use of an RFI filter. A possible filter design is shown in Figure 4.5. This filter causes a ring wave of current through the SIDAC at turn-on time. The filter inductor must be selected for resonance at a frequency above the upper frequency limit of human hearing and as low below the start of the AM broadcast band as possible for maximum harmonic attenuation. In addition, it is important that the filter inductor be non-saturating to prevent dI/dT damage to the SIDAC. For additional information on filter design see page 92. ZL VIN SIDAC Figure 4.6. SIDAC Circuit
- 53. http://onsemi.com 53 OPTIONAL RFI FILTER 100 WATT 240 V 100 μHY PREM SPE304 RDC = 0.04 Ω (2)MKP1V130RL 400 V 0.1 μF 220 VAC Figure 4.7. Long-Life Circuit for Incandescent Lamp The sizing of the SIDAC must take into account the RMS current of the lamp, thermal properties of the SIDAC, and the cold start surge current of the lamp which is often 10 to 20 times the steady state load current. When lamps burn out, at the end of their operating life, very high surge currents which could damage the SIDAC are possible because of arcing within the bulb. The large MKP3V device is recommended if the SIDAC is not to be replaced along with the bulb. Since the MKP3V series of SIDACs have relatively tight V(BO) tolerances (104 V to 115 V for the −115 device), other possible applications are over-voltage protection (OVP) and detection circuits. An example of this, as illustrated in Figure 4.8, is the SIDAC as a transient protector in the transformer-secondary of the medium voltage power supply, replacing the two more expensive back-to-back zeners or an MOV. The device can also be used across the output of the regulator (t100 V) as a simple OVP, but for this application, the regulator must have current foldback or a circuit breaker (or fuse) to minimize the dissipation of the SIDAC. Another example of OVP is the telephony applications as illustrated in Figure 4.9. To protect the Subscriber Loop Interface Circuit (SLIC) and its associated electronics from voltage surges, two SIDACs and two rectifiers are used for secondary protection (primary protection to 1,000 V is provided by the gas discharge tube across the lines). As an example, if a high positive voltage transient appeared on the lines, rectifier D1 (with a P.I.V. of 1,000 V) would block it and SIDAC D4 would conduct the surge to ground. Conversely, rectifier D2 and SIDAC D3 would protect the SLIC for negative transients. The SIDACs will not conduct when normal signals are present. Being a negative resistance device, the SIDAC also can be used in a simple relaxation oscillator where the frequency is determined primarily by the RC time constant (Figure 4.10). Once the capacitor voltage reaches the SIDAC breakover voltage, the device will fire, dumping the charged capacitor. By placing the load in the discharge path, power control can be obtained; a typical load could be a transformer-coupled xeon flasher, as shown in Figure 4.12. z VO p 100 V REG.VIN SIDAC AS AN OVP SIDAC AS A TRANSIENT PROTECTOR Figure 4.8. Typical Application of SIDACs as a Transient Protector and OVP in a Regulated Power Supply
- 54. http://onsemi.com 54 RMAXp VIN * V(BO) I(BO) RMINq VIN * VTM IH t ^ RC Inȧȧ ȡ Ȣ I I * VBO VIN ȧȧ ȣ Ȥ TIP SENSE TIP SENSE D2D2 90 V RMS @ −48 Vdc RING GENERATOR 90 V RMS @ −48 Vdc RING GENERATOR SECONDARY PROTECTION SECONDARY PROTECTION TIP DRIVE TIP DRIVE D1D1 1N40071N4007 SLIC MC3419-1L SLIC MC3419-1L RING SENSE RING SENSE PRIMARY PROTECTION GAS DISCHARGE TUBE PRIMARY PROTECTION GAS DISCHARGE TUBE 1N40071N4007 MOC3031 RG1RG1 RG2RG2 RERE 135 V135 V RING ENABLE 0 TO + 5 V RING ENABLE 0 TO + 5 V RING DRIVE RING DRIVE GNDGND −48 V BATTERY −48 V BATTERY RPRRPR RRRR 105 V105 V RINGRING TIPTIP RPTRPT RTRT Figure 4.9. SIDACs Used for OVP in Telephony Applications t t iL VC Figure 4.10. Relaxation Oscillator Using a SIDAC C VIN u V(BO) R VC iL ZL t V(BO)
- 55. http://onsemi.com 55 SIDAC’s provide an economical means for starting high intensity high pressure gas discharge lamps. These lamps are attractive because of their long operating life and high efficiency. They are widely used in outdoor lighting for these reasons. Figure 4.13 illustrates how SIDAC’s can be used in sodium vapor lamp starters. In these circuits, the SIDAC is used to generate a short duration (1 to 20 μs) high-voltage pulse of several KV or more which is timed by means of the RC network across the line to occur near the peak of the AC input line voltage. The high voltage pulse strikes the arc which lights the lamp. In these circuits, an inductive ballast is required to provide a stable operating point for the lamp. The lamp is a negative resistance device whose impedance changes with current, temperature, and time over the first few minutes of operation. Initially, before the lamp begins to conduct, the lamp impedance is high and the full line voltage appears across it. This allows C to charge to the breakover voltage of the SIDAC, which then turns on discharging the capacitor through a step-up transformer generating the high voltage pulse. When the arc strikes, the voltage across the lamp falls reducing the available charging voltage across RC to the point where VC no longer exceeds V(BO) and the SIDAC remains off. The low duty cycle lowers average junction temperature improving SIDAC reliability. Normal operation approxi- mates non-repetitive conditions. However, if the lamp fails or is removed during replacement, operation of the SIDAC will be at the 60 Hz line frequency. The design of the circuit should take into account the resulting steady state power dissipation. 4 kV PULSE TRANSFORMER RS-272-1146 560 k 2 W 1 μF 200 V + VIN ≈ 300 V 125 V + 1 M 2 W 220 2 W 2 kW XEON TUBE RS-272-1145 20 μF 400 V Figure 4.11. Typical Capacitor Discharge SIDAC Circuit Figure 4.12. Xeon Flasher Using a SIDAC HVVIN Figure 4.13. Sodium Vapor Lamp Starter Circuits (b). H.V. Auto-Transformer (a). Conventional HV Transformer C1 C R vac (c). Tapped Ballast Auto Transformer LB vac vac LB LB C C R R Figure 4.14 illustrates a solid state fluorescent lamp starter using the SIDAC. In this circuit the ballast is identical to that used with the conventional glow-tube starter shown in Figure 4.15. The glow tube starter consists of a bimetallic switch placed in series with the tube filaments which closes to energize the filaments and then opens to interrupt the current flowing through the ballast inductor thereby generating the high-voltage pulse necessary for starting. The mechanical glow-tube starter is the circuit component most likely to cause unreliable starting.
- 56. http://onsemi.com 56 Figure 4.14. Fluorescent Starter Using SIDAC L PTC R D2 D1 LB 115 VAC LB UNIVERSAL MFG CORP CAT200-H2 14-15-20-22 WATT BALLAST 325 mHY 28.9 Ω DCR D1 1N4005 RECTIFIER D2 (2) MKP1V130RL SIDAC C 3 VFD 400 V R 68 k OHMS 112 WATT PTC KEYSTONE CARBON COMPANY RL3006-50-40-25-PTO 50 OHMS/25°C L MICROTRAN QIL 50-F 50 mHY 11 OHMS SYLVANIA F15T8/CW The heating of the filaments causes thermonic emission of electrons from them. These electrons are accelerated along the length of the tube causing ionization of the argon gas within the tube. The heat generated by the starting current flow through the tube vaporizes the mercury droplets within the tube which then become ionized themselves causing the resistance and voltage across the tube to drop significantly. The drop in voltage across the tube is used to turn off the starting circuit and prevent filament current after the lamp is lit. The SIDAC can be used to construct a reliable starter circuit providing fast, positive lamp ignition. The starter shown in Figure 4.14 generates high voltage by means of a series CRL charging circuit. The circuit is roughly analogous to a TRIAC snubber used with an inductive load, except for a lower damping factor and higher Q. The size of C determines the amount of filament heating current by setting the impedance in the filament circuit before ionization of the tube. The evolution of this circuit can be understood by first considering an impractical circuit (Figure 4.16). If LB and C are adjusted for resonance near 60 Hz, the application of the AC line voltage will result in a charging current that heats the filaments and a voltage across the capacitor and tube that grows with each half-cycle of the AC line until the tube ionizes. Unfortunately, C is a large capacitor which can suddenly discharge through the tube causing high current pulses capable of destroying the tube filament. Also C provides a permanent path for filament current after starting. These factors cause short tube operating life and poor efficiency because of filament power losses. The impractical circuit must be modified to: (1) Switch off the filament current after starting. (2) Limit capacitor discharge current spikes. In Figure 4.14 a parallel connected rectifier and SIDAC have been added in series with the capacitor C. The breakover voltage of the SIDAC is higher than the peak of the line voltage. Diode D1 is therefore necessary to provide a current path for charging C. On the first half-cycle, C resonant charges through diode D1 to a peak voltage of about 210 V, and remains at that value because of the blocking action of the rectifier and SIDAC. During this time, the bleeder resistor R has negligible effect on the voltage across C because the RC time constant is long in comparison to the line period. When the line reverses, the capacitor voltage boosts the voltage across the SIDAC until breakover results. This results in a sudden step of voltage across the inductor L, causing resonant charging of the capacitor to a higher voltage on the 2nd half-cycle. BALLAST INDUCTOR FLUORESCENT COATING NEON GAS (ARGON GAS) VAC MERCURY DROPLETS STARTER COATED FILAMENT Figure 4.15. Fluorescent Lamp with Glow Tube Starter
- 57. http://onsemi.com 57 Q + XLB RTOTAL fo + 1 2a LCǸ + 60 Hz BALLAST CHOKE Figure 4.16. Impractical Starter Circuit VSTART t VMAX −VSTART LBRB V C VAC Vmax + Q VAC 2Ǹ Figure 4.17. Starting Voltage Across Fluorescent Tube 100 V/DIV 0 V AT CENTER VLine = 110 V (a). 5 ms/DIVISION (b). 100 ms/DIVISION Several cycles of operation are necessary to approach steady state operating conditions. Figure 4.17 shows the starting voltage waveform across the tube. The components R, PTC, and L serve the dual role of guarantying SIDAC turn-off and preventing capacitor discharge currents through the tube. SIDAC’s can also be used with auto-transformer ballasts. The high voltage necessary for starting is generated by the leakage autotransformer. The SIDAC is used to turn-on the filament transformer initially and turn it off after ionization causes the voltage across the tube to drop. Figure 4.18 illustrates this concept. The resistor R can be added to aid turn-off of the SIDAC by providing a small idle current resulting in a voltage drop across the impedance Z. The impedance Z could be a saturable reactor and or positive temperature coefficient thermistor. These components help to insure stability of the system comprised of the negative resistance SIDAC and negative resistance tube during starting, and promote turn off of the SIDAC. The techniques illustrated in Figure 4.13 are also possible methods for generation of the necessary high- voltage required in fluorescent starting. The circuits must be modified to allow heating of the fluorescent tube cathodes if starting is to simulate the conditions existing when a glow tube is used.
- 58. http://onsemi.com 58 VBO t VSTART VBO u VOPERATING Figure 4.18. Fluorescent Starter Using SIDAC and Autotransformer Ballast V Z C VAC R Table 4.1. Possible Sources for Thermistor Devices Fenwal Electronics, 63 Fountain Street Framingham MA 01701 Keystone Carbon Company, Thermistor Division St. Marys, PA 15857 Thermometrics, 808 U.S. Highway 1 Edison, N.J. 08817 Therm-O-Disc, Inc. Micro Devices Product Group 1320 South Main Street, Mansfield, OH 44907 Midwest Components Inc., P.O Box 787 1981 Port City Boulevard, Muskegon, MI 49443 Nichicon (America) Corp., Dept. G 927 E. State Pkwy, Schaumburg, IL 60195 Thermistors are useful in delaying the turn-on or insuring the turn-off of SIDAC devices. Table 4.1 shows possible sources of thermistor devices. Other high voltage nominal current trigger applications are: • Gas or oil igniters • Electric fences • HV electrostatic air filters • Capacitor Discharge ignitions Note that all these applications use similar circuits where a charged capacitor is dumped to generate a high transformer secondary voltage (Figure 4.11). In many cases, the SIDAC current wave can be approxi- mated by an exponential or quasi-exponential current wave (such as that resulting from a critically damped or slightly underdamped CRL discharge circuit). The ques- tion then becomes; how much “real world” surge current can the SIDAC sustain? The data sheet defines an ITSM of 20 A, but this is for a 60 Hz, one cycle, peak sine wave whereas the capacitor discharge current waveform has a fast-rise time with an exponential fall time. To generate the surge current curve of peak current versus exponential discharge pulse width, the test circuit of Figure 4.19 was implemented. It simulates the topology of many applications whereby a charged capacitor is dumped by means of a turned-on SIDAC to produce a current pulse. Timing for this circuit is derived from the nonsymmetrical CMOS astable multivibrator (M.V.) gates G1 and G2. With the component values shown, an approximate 20 second positive-going output pulse is fed to the base of the NPN small-signal high voltage transistor Q1, turning it on. The following high voltage PNP transistor is consequently turned on, allowing capacitor C1 to be charged through limiting resistor R1 in about 16 seconds. The astable M.V. then changes state for about 1.5 seconds with the positive going pulse from Gate 1 fed through integrator R2-C2 to Gate 3 and then Gate 4. The net result of about a 100 μs time delay from G4 is to ensure non-coincident timing conditions. This positive going output is then differentiated by C3-R3 to produce an approximate 1 ms, leading edge, positive going pulse which turns on NPN transistor Q3 and the following PNP transistor Q4. Thus, an approximate 15 mA, 1 ms pulse is generated for turning on SCR Q5 about 100 μs after capacitor charging transistor Q2 is turned off. The SCR now fires, discharging C1 through the current limiting resistor R4 and the SIDAC Device Under Test (D.U.T.). The peak current and its duration is set by the voltage VC across capacitor C1 and current limiting resistor R4. The circuit has about a 240 V capability limited by C1, Q1 and Q2 (250 V, 300 V and 300 V respectively).
- 59. http://onsemi.com 59 1N 4003 Q1 MPS A42 R1 4 k 5 W 1N914 R3 10 k 3.3 Ω 2 W 10 k 22 k MCR 6507 C3 0.1 μF 1 k 1 k 10 k +15 V 2N3906 Q4 Q5 LED 39 k 2 W C1 80 μF 250 V R4 0.47 μF 1N914 22 k Q2 MJ4646 R2 100 k 10 k VCC p 240 V 0.001 μF 4 6 5 31 2 C2 MC14011 47 k11 14 +15 V +15 V +15 V +15 V 22 M Q3 2N3904 7 22 M G2 13 12 108 9 G1 Figure 4.19. SIDAC Surge Tester 2.2 M G3 G4 SIDAC DUT The SCR is required to fire the SIDAC, rather than the breakover voltage, so that the energy to the D.U.T. can be predictably controlled. By varying VC, C1 and R4, the surge current curve of Figure 4.20 was derived. Extensive life testing and adequate derating ensure that the SIDAC, when properly used, will reliably operate in the various applications. I,SURGECURRENT(AMPS)pk tw Figure 4.20. Exponential Surge Current Capability of the MKP3V SIDAC. Pulse Width versus Peak Current 10% Ipk 0.3 100 tw, PULSE WIDTH (ms) 3 30 10 101 1 30 100 3003
- 60. http://onsemi.com 60 SECTION 5 SCR CHARACTERISTICS Edited and Updated SCR TURN−OFF CHARACTERISTICS In addition to their traditional role of power control devices, SCRs are being used in a wide variety of other applications in which the SCR’s turn−off characteristics are important. As in example — reliable high frequency inverters and converter designs (t20 kHz) require a known and controlled circuit−commutated turn−off time (tq). Unfor- tunately, it is usually difficult to find the turn−off time of a particular SCR for a given set of circuit conditions. This section discusses tq in general and describes a circuit capable of measuring tq. Moreover, it provides data and curves that illustrate the effect on tq when other parameters are varied, to optimize circuit performance. SCR TURN−OFF MECHANISM The SCR, being a four layer device (P−N−P−N), is represented by the two interconnected transistors, as shown in Figure 5.1. This regenerative configuration allows the device to turn on and remain on when the gate trigger is removed, as long as the loop gain criteria is satisfied; i.e., when the sum of the common base current gains (α) of both the equivalent NPN transistor and PNP transistor, exceed one. To turn off the SCR, the loop gain must be brought below unity, whereby the on−state principal current (anode current iT) limited by the external circuit impedance, is reduced below the holding current (IH). For ac line applications, this occurs automatically during the negative going portion of the waveform. However, for dc applications (inverters, as an example), the anode current must be interrupted or diverted; (diversion of the anode current is the technique used in the tq test fixture described later in this application note). SCR TURN−OFF TIME tq Once the anode current in the SCR ceases, a period of time must elapse before the SCR can again block a forward voltage. This period is the SCR’s turn−off time, tq, and is dependent on temperature, forward current, and other parameters. The turn−off time phenomenon can be understood by considering the three junctions that make up the SCR. When the SCR is in the conducting state, each of the three junctions is forward biased and the N and P regions (base regions) on either side of J2 are heavily saturated with holes and electrons (stored charge). In order to turn off the SCR in a minimum amount of time, it is necessary to apply a negative (reverse) voltage to the device anode, causing the holes and electrons near the two end junctions, J1 and J3, to diffuse to these junctions. This causes a reverse current to flow through the SCR. When the holes and electrons near junctions J1 and J3 have been removed, the reverse current will cease and junctions J1 and J3 will assume a blocking state. However, this does not complete the recovery of the SCR since a high concentration of holes and electrons still exist near the center junction, J2. This concentration decreases by the recombination process and is largely independent of the external circuit. When the hole and electron concentration near junction J2 has reached some low value, junction J2 will assume its blocking condition and a forward voltage can, after this time, be applied without the SCR switching back to the conduction state. Figure 5.1. Two Transistor Analogy of an SCR TWO TRANSISTOR MODEL IB1 = IC2Q1 GATE Q2 ITM P P P N N GATE IC1 = IB2 N P−N−P−N STRUCTURE J1 P N N P GATE CATHODE ANODE ANODE GATE CATHODE J2 J3 CATHODE CATHODE ANODE ANODE
- 61. http://onsemi.com 61 tq MEASUREMENT When measuring SCR turn−off time, tq, it is first necessary to establish a forward current for a period of time long enough to ensure carrier equilibrium. This must be specified, since ITM has a strong effect on the turn−off time of the device. Then, the SCR current is reversed at a specified di/dt rate, usually by shunting the SCR anode to some negative voltage through an inductor. The SCR will then display a “reverse recovery current,” which is the charge clearing away from the junctions. A further waiting time must then elapse while charges recombine, before a forward voltage can be applied. This forward voltage is ramped up a specified dv/dt rate. The dv/dt delay time is reduced until a critical point is reached where the SCR can no longer block the forward applied voltage ramp. In effect, the SCR turns on and conse- quently, the ramp voltage collapses. The elapsed time between this critical point and the point at which the forward SCR current passes through zero and starts to go negative (reverse recovery phase), is the tq of the SCR. This is illustrated by the waveforms shown in Figure 5.2. tq GENERAL TEST FIXTURE The simplified circuit for generating these waveforms is schematically illustrated in Figure 5.3. This circuit is implemented with as many as eight transformers includ- ing variacs, and in addition to being very bulky, has been known to be troublesome to operate. However, the configuration is relevent and, in fact, is the basis for the design, as described in the following paragraphs. tq TEST FIXTURE BLOCK DIAGRAMS AND WAVEFORMS The block diagram of the tq Test Fixture, illustrated in Figure 5.4, consists of four basic blocks: A Line Synchronized Pulse Generator establishes system timing; a Constant Current Generator (variable in amplitude) powers the Device Under Test (DUT); a di/dt Circuit controls the rate of change of the SCR turn−off current; and the dv/dt Circuit reapplies a controlled forward blocking voltage. Note from the waveforms illustrated that the di/dt circuit, in parallel with the DUT, diverts the constant current from the DUT to produce the described anode current ITM. tq TEST FIXTURE CHARACTERISTICS The complete schematic of the tq Test Fixture and the important waveforms are shown in Figures 5.5 and 5.6, respectively. A CMOS Gate is used as the Line Synchronized Pulse Generator, configured as a wave shaping Schmitt trigger, clocking two cascaded monostable multivibrators for delay and pulse width settings (Gates 1C to 1F). The result is a pulse generated every half cycle whose width and position (where on the cycle it triggers) are adjustable by means of potentiometers R2 and R3, respectively. The output pulse is normally set to straddle the peak of the ac line, which not only makes the power supplies more efficient, but also allows a more consistent oscilloscope display. This pulse shown in waveform A of Figure 5.6 initiates the tq test, which requires approximately 0.5 ms to assure the device a complete turn on. A fairly low duty cycle results, (approxi- mately 5%) which is important in minimizing temperature effects. The repetitive nature of this test permits easy oscillo- scope viewing and allows one to readily “walk in” the dv/dt ramp. This is accomplished by adjusting the appropriate potentiometer (R7) which, every 8.33 ms (every half cycle) will apply the dv/dt ramp at a controlled time delay. Figure 5.2. SCR Current and Voltage Waveforms During Circuit−Commutated Turn−Off VT IDX ITM 50% IRM IRM di/dt dv/dt trr tq VDX 50% ITM
- 62. http://onsemi.com 62 Figure 5.3. Simplified tq Test Circuit V2 IT I1 V1 S2 IT S1 dv/dt DUT di/dt L1 R2S3 V3 R1 C1 D3 S4 D2 D1 To generate the appropriate system timing delays, four RC integrating network/comparators are used, consisting of op−amps U2, U5 and U6. Op−amp U2A, along with transistor Q2, opto−coupler U4 and the following transistors Q6 and Q7, provide the gate drive pulse to the DUT (see waveforms B, C and D of Figure 5.6). The resulting gate current pulse is about 50 μs wide and can be selected, by means of switch S2, for an IGT of from about 1 mA to 90 mA. Opto−coupler U4, as well as U1 in the Constant Current Circuit, provide electrical isolation between the power circuitry and the low level circuitry. The Constant Current Circuit consists of an NPN Darling- ton Q3, connected as a constant current source driving a PNP tri−Darlington (Darlington Q4, Bipolar Q5). By vary- ing the base voltage of Q3 (with Current Control potentiom- eter R4), the collector current of Q3 and thus the base voltage of Q4 will also vary. The PNP output transistor Q5 (MJ14003) (rated at 70 A), is also configured as a constant current source with four, parallel connected emitter resistors (approximately 0.04 ohms, 200 W), thus providing as much as 60 A test current. Very briefly, the circuit operates as follows: — CMOS Gate 1E is clocked high, turning on, in order, a) NPN transistor Q16, b) PNP transistor Q1, c) optocoupler U3, and d) transistors Q3, Q4 and Q5. The board mounted Current Set potentiometer R5, sets the maximum output current and R4, the Current Control, is a front panel, multiturn potentiometer. Figure 5.4. Block Diagram of the tq Test Fixture and Waveforms 0 V1 dv/dt IT di/dt CONSTANT CURRENT di/dt dv/dt IT D1 DUT IGT LINE SYNC PULSE GENERATOR CONSTANT CURRENT GENERATOR dv dt CIRCUIT di dt CIRCUIT
- 63. 63 http://onsemi.com 47 2 W 0.1 μF 50 μF 20 V LM317T U7 − + 25 V 16 20,000 μF 25 V − + 100 1 W −V1 −18 V TYP Figure 5.5. tq Test Fixture 120 V 60 Hz POWER ON 2 A S.B. 0.1 μF 200 V 0.1 μF, 200 V + 20 V (UNLOADED) + 12 V (LOADED) STANCOR P6337 SW S1 1 4N35 U4 2 GATE CURRENT SW S2 150 150 k IT DUT − 5 VSW.53 OFF BIAS 1 k 8.2 k 820 330 160 120 82 Q6 10 k 2N 4919 Q7 1 W 20 2N3904 1 k 1 k 4 1 k 1N4740 10 V, 1 W 100 μF 20 V0.1 μF + 1N4733 5.1 V, 1 W 1N 914 − 10 V 1 k + 10 V 5 + 10 V − V1 MPS A13 CURRENT SET R5 1 k CURRENT CONTROL R4 100 1W 4 100 1/2 W Q3 (4) 0.15 Ω, 50 W + 50,000 μF 25 V 1.2 k 2 W 0.1 μF 100 1 W 2N6042 Q4 MJ 14003 Q5 L1 D1 * (3) MTM15N06E 100 k MR856 − V2 1N 5370A 56 V 5 W 1N 5932A 560 2 W Q10 μF 0.001 μF 560 2 W Q12 0.001 μF Q11 .001 1N 5932A 20 V 1.5 W 0.002 μF 1N 5932A MJE254 Q9 470 56 2 W 10 k 0.001 μF 1 k 470 1N 914 SYNC OUT 2N4401 Q8 10 k + V1R1 I1 MTM2N90 Q15 C1 + 10 V 0.1 μF 1N 4747 1 k 2 W 1N4728 100 + (1/2) MC1458 U5 U56 7 4 0.1 μF + 10 V 8 MJE 250 Q14 5 − 10 V 1 k 10 k 1N4728 0.1 μF tq TIME CONTROL R7 R6 ON TIME CONTROL 150 k, 10 T 10 k 0.002 μF 1.8 k 0.1 μF 3.3 V − 10 V 39 k 7 6 4 1 k U62 3 + 10 V (1/2) MC1458− 7 U2B + 6 5 0.001 μF 0.02 μF 0.1 μF 4.7 k 50 k VREF + 10 V 3.3 k 2N3904 Q2 2 3.3 V 4N35 U3 3.3 k1N4728 0.1 μF − U2A + 2 3 (1/2) MC1458 820 pF + 10 V12 k 510 k 5 + 10 V 10 k 430 2 W 2N3904 Q16 10 k 47 k CONSTANT CURRENT CIRCUIT 4.7 k 25 k R3 PULSE WIDTH CONTROL 11 1F 12 1E 13 15 14 0.001 μF 9 100 k + 10 V R2 PULSE DELAY CONTROL 1D + 10 V 10 150 k 0.01 μF 1M 1C 5 U1 MC14572 7 1 k Q1 2N 3906 + 10 V 100 k 220 pF + 10 V 1B 38 1 4 220 k 1 A 222 k + 10 V 1 k 10 k + + 10 V 1.8 k 2 2401 + 3 1N4001 2000 μF 330 1 W −5 V + 1 k1/2 W 90 mA 70 30 50 10 U6 MC1741 o o o − V1 − 18 V o 10 μF 15 V 2N3904 Q13 TRIAD F93X 1N914 10 V + 10 V 1.5 k 1 mA V A 1000 di dt CIRCUIT 560 2 W 1 K 2 W 1 K 2 W dv dt CIRCUIT 6 1.2 K 2 W LINE SYNCHRONIZED PULSE GENERATOR 120V SWD L1: 0 μH (TYP) *DIODE REQUIRED WITH L1 D1: MR506 FOR 3 A, HIGH tq DUTS MR856 FOR 3 A, LOW tq DUTS (DIODE IF SCALED TO DUT IA) I1: ≈ 50 mA FOR HIGH tq DUTS V1 R1 50 V 1 k (TYP) ≈ 1 A FOR LOW tq V1 R1 50 V 50 (TYP) C1: DETERMINED BY SPEC dv/dt − V2: − 12 V (TYP), t − 50 V
- 64. http://onsemi.com 64 Time delay for the di/dt Circuit is derived from cascaded op−amps U2B and U5 (waveforms F and G of Figure 5.6). The output gate, in turn, drives NPN transistor Q8, followed by PNP transistor Q9, whose output provides the gate drive for the three parallel connected N−channel power MOSFET transistors Q10−Q12 (waveforms H of Figure 5.6). These three FETs (MTM15N06), are rated at 15 A continuous drain current and 40 A pulsed current and thus can readily divert the maximum 60 A constant current that the Fixture can generate. The results of this diversion from the DUT is described by waveforms E, H and I of Figure 5.6, with the di/dt of of ITM dictated by the series inductance L1. For all subsequent testing, the inductor was a shorting bar, resulting in very little inductance and consequently, the highest di/dt (limited primarily by wiring inductance). When a physical inductor L1 is used, a clamp diode, scaled to the diverted current, should be placed across L1 to limit “inductive kicks.” dv/dt CIRCUIT The last major portion of the Fixture, the dv/dt Circuit, is variable time delayed by the multi−turn, front panel tq Time Control potentiometer R7, operating as part of an integrator on the input of comparator U6. Its output (waveform J of Figure 5.6) is used to turn−off, in order, a) normally on NPN transistor Q13, b) PNP transistor Q14 and c) N−channel power MOSFET Q15 (waveform L of Figure 5.6). This FET is placed across ramp generating capacitor C1, and when unclamped (turned off), the capacitor is allowed to charge through resistor R1 to the supply voltage +V1. Thus, the voltage appearing on the drain will be an exponentially rising voltage with a dv/dt dictated by R1, C1, whose position in time can be advanced or delayed. This waveform is then applied through a blocking diode to the anode of the DUT for the forward blocking voltage test. Another blocking diode, D1, also plays an important role in tq measurements and must be properly selected. Its purpose is to prevent the dv/dt ramp from feeding back into the Current Source and di/dt Circuit and also to momentarily apply a reverse blocking voltage (a function of −V2 of the di/dt circuit) to the DUT. Consequently, D1 must have a reverse recovery time trr greater than the DUT, but less than the tq time. When measuring standard recovery SCRs, its selection — fast recovery rectifiers or standard recovery — is not that critical, however, for fast recovery, low tq SCRs, the diode must be tailored to the DUT to produce accurate results. Also, the current rating of the diode must be compatible with the DUT test current. These effects are illustrated in the waveforms shown in Figure 5.7 where both a fast recovery rectifier and standard recovery rectifier were used in measuring tq of a standard 2N6508 SCR. Although the di/dt’s were the same, the reverse recovery current IRM and trr were greater with the standard recovery rectifier, resulting in a somewhat shorter tq (59 μs versus 63 μs). In fact, tq is affected by the initial conditions (ITM, di/dt, IRM, dv/dt, etc.) and these conditions should be specified to maintain measurement repeatability. This is later described in the published curves and tables. Finally, the resistor R1 and the resultant current I1 in the dv/dt circuit must meet certain criteria: I1 should be greater than the SCR holding current so that when the DUT does indicate tq limitation, it latches up, thus suppressing the dv/dt ramp voltage; and, for fast SCRs (low tq), I1 should be large enough to ensure measurement repeatability. Typical values of I1 for standard and fast SCRs may be 50 mA and 500 mA, respectively. Obviously, for high forward blocking voltage + V1 tests, the power requirements must be met. EFFECTS OF GATE BIAS ON tq Examples of the effects of I1 on tq are listed in Table 5.III whereby standard and fast SCRs were tested with about 50 mA and 1 A, respectively. Note that the low tq SCR’s required fast recovery diodes and high I1 current. TEST FIXTURE POWER SUPPLIES Most of the power supplies for the system are self contained, including the +12 V supply for the Constant Current Circuit. This simple, unregulated supply furnishes up to 60 A peak pulsed current, primarily due to the line synchronized operation of the system. Power supplies +V1 and −V2, for this exercise, were external supplies, since they are variable, but they can be incorporated in the system. The reverse blocking voltage to the DUT is supplied by − V2 and is typically set for about −10 V to −20 V, being limited to the breakdown voltage of the diverting power MOSFETS (VDSS = 60 V). The +12 V unregulated supply can be as high as +20 V when unloaded; therefore, −V2 (MAX), in theory, would be −40 V but should be limited to less than −36 V due to the 56 V protective Zener across the drain−source of the FETs. Also, −V2 must be capable of handling the peak 60 A, diverting current, if so required. The reapplied forward blocking voltage power supply +V1, may be as high as the DUT VDRM which conceivably can be 600 V, 1,000 V or greater and, since this supply is on most of the time, must be able to supply the required I1. Due to the sometimes high power requirements, +V1 test conditions may have to be reduced for extremely fast SCRs.
- 65. http://onsemi.com 65 PARAMETERS AFFECTING tq To see how the various circuit parameters can affect tq, one condition at a time is varied while the others are held constant. The parameters to be investigated are a) forward current magnitude (ITM), b) forward current duration, c) rate of change of turn−off current (di/dt), d) reverse− current magnitude (IRM), e) reverse voltage (VRM), f) rate of reapplied forward voltage (dv/dt), g) magnitude limit of reapplied voltage, h) gate−cathode resistance and i) gate drive magnitude (IGT). Typical data of this kind, taken for a variety of SCRs, including standard SCRs, high speed SCRs, is con- densed and shown in Table 5.1. The data consists of the different conditions which the particular SCR types were subjected to; ten SCRs of each type were serialized and tested to each condition and the ten tq’s were averaged to yield a “typical tq.” The conditions listed in Column A in Table 5.1, are typical conditions that might be found in circuit opera- tion. Columns B through J in Table 5.1, are in order of increasing tq; the conditions listed in these columns are only the conditions that were modified from those in Column A and if a parameter is not listed, it is the same as in Column A. Figure 5.6. tq Test Fixture System Waveforms U6, P6 dv/dt CIRCUIT Q15 GATE dv/dt U5, P7 Q1 COL. U2, P7 IT DUT IGT t, TIME (μs) Q15 DRAIN dv/dt OUTPUT U2, P1 U4, P4 Q9 COL. Q10−Q12 di/dt CIRCUIT CONSTANT CURRENT GEN. Q5 COL. A B C D E F G H I J K L 8006004002000
- 66. http://onsemi.com 66 tq = 59 μs Figure 5.7. The Effects of Blocking Diode D1 on tq of a 2N6508 SCR D1 = MR856, FAST RECOVERY RECTIFIER D1 = 1N5402, STANDARD RECOVERY RECTIFIER I = 2 A/Div 0 A V = 10 V/Div tq = 63 μs 0 V I = 2 A/Div 0 A V = 10 V/Div 0 V t = 50 μs/Div t = 50 μs/Div t = 1 μs/Div t = 1 μs/Div
- 67. http://onsemi.com 1.5-67 Table 5.1. Parameters Affecting tq Device A B C D E F G H I 2N6508 25 A 600 V RGK = 1 k dv/dt = 15 V/μs ITM = 25 A IRM = 14 A di/dt = −100 A/μs ITM duration = 275 μs IGT = 30 mA RGK = 100 dv/dt = 2.4 V/μs ITM = 1 A IRM = 1.8 A di/dt = 32 A/μs RGK = 100 dv/dt = 2.4 V/μs ITM = 2 A IRM = 50 mA di/dt = 0.5 μs RGK = 100 dv/dt = 2.4 V/μs IRM = 50 mA di/dt = 0.45 A/μs RGK = 100 dv/dt = 2.4 V/μs RGK = 1 dv/dt = 2.4 V/μs RGK = 100 dv/dt = 2.4 V/μs ITM = 37 A RGK = 100 IGT = 90 mA typ tq = 68 μs typ tq = 42 μs typ tq = 45 μs typ tq = 49 μs typ tq = 60 μs typ tq = 64 μs typ tq = 64 μs typ tq = 65 μs typ tq = 68 μs 2N6399 12 A RGK = 1 k dv/dt = 90 V/μs ITM = 12 A IRM = 11 A di/dt = −100 A/μs ITM duration = 275 μs IGT = 30 mA RGK = 100 dv/dt = 2.5 V/μs ITM = 1 A IRM = 50 mA di/dt = −0.5 A/μs RGK = 100 dv/dt = 2.5 V/μs ITM = 1 A IRM = 2.7 A di/dt = 56 A/μs RGK = 100 dv/dt = 2.5 V/μs IRM = 50 mA di/dt = 32 A/μs RGK = 100 dv/dt = 2.5 V/μs ITM = 18 A IRM = 50 mA di/dt = 0.3 A/μs RGK = 1 dv/dt = 2.5 V/μs IRM = 50 mA di/dt = 0.35 A/μs RGK = 100 IGT = 90 mA typ tq = 48 μs typ tq = 30 μs typ tq = 31 μs typ tq = 32 μs typ tq = 33 μs typ tq = 35.5 μs typ tq = 45 μs typ tq = 48 μs
- 68. http://onsemi.com 1.5-68 Table 5.1. Continued Device A B C D E F G H I C106B 4 A IGT = 1 mA RGK = 1 k dv/dt = 5 V/ms ITM = 4A IRM = 4A di/dt = 50 A/ms ITM duration = 275 ms VDX = 50 V ITM = 2 A IRM = 2.5 A di/dt = −30 A/ms VDX = 50 V ITM = 6 A IRM = −1 A/ms di/dt = −1 A/ms VDX = 150 V ITM = 6 A IRM = 0.1 A di/dt = −1 A/ms VDX = 50 V dv/dt = 1.4 V/ms ITM = 2 A IRM = 0.2 A di/dt = −1.4 A/ms −V2 = 35 V IRM = 0.2 A di/dt = −1.4 A/ms IRM = 0.15 A −V2 = 4 V di/dt = −1.4 A/ms dv/dt = 1.4 V/ms IRM = 0.15 A di/dt = 1.4 A/ms IGT = 90 mA dv/dt = 1.4 V/ms IRM = 2 A di/dt = −1.4 A/ms typ tq = 28 ms typ tq = 25 ms typ tq = 26 ms typ tq = 26 ms typ tq = 26 ms typ tq = 27 ms typ tq = 27 ms typ tq = 27 ms typ tq = 27 ms 2N6240 4 A RGK = 1 k dv/dt = 40 V/ms ITM = 4 A IRM = 4 A di/dt = 50 A/ms ITM duration = 275 ms IGT = 1 mA VDX = 50 V RGK = 100 dv/dt = 1.3 V/ms ITM = 1 A IRM = 50 mA di/dt = −0.5 A/ms IGT = 90 mA VDX = 150 V RGK = 100 dv/dt = 1.75 V/ms ITM = 1 A IRM = 50 mA di/dt = −0.5 A/ms IGT = 90 mA RGK = 100 dv/dt = 1.75 V/ms IRM = 50 mA di/dt = −0.5 A/ms IGT = 90 mA dv/dt = 1.75 V/ms RGK = 100 ITM = 6 A IRM = 50 mA di/dt = −0.5 A/ms IGT = 90 mA RGK = 100 IRM = 50 mA di/dt = −0.5 A/ms IGT = 90 mA RGK = 100 IGT = 900 mA RGK = 1 dv/dt = 1.75 V/ms ITM = 1 A IRM = 50 mA di/dt = −0.5 A/ms IGT = 90 mA IGT = 90 mA typ tq = 44.8 ms typ tq = 26 ms typ tq = 26.2 ms typ tq = 27.7 ms typ tq = 28.6 ms typ tq = 30 ms typ tq = 32.7 ms typ tq = 37.2 ms typ tq = 41.4 ms MCR100−6 0.8 A RGK = 1 k dv/dt = 160 V/ms ITM = 0.8 A IRM = 0.8 A di/dt = 12 A/ms VDX = 50 V ITM duration = 275 ms dv/dt = 30 V/ms ITM = 0.25 A IRM = 40 mA di/dt = −0.6 A/ms dv/dt = 30 V/ms Ir = 40 mA di/dt = −0.8 A/ms −V2 = 9 V IRM = 20 mA di/dt = −0.4 A/ms −V2 = 1 V Ir = 40 mA di/dt = −0.8 A/ms dv/dt = 30 V/ms ITM = 1.12 A IRM = 40 mA di/dt = −0.8 A/ms dv/dt = 30 V/ms ITM = 1.12 A IRM = 40 mA di/dt = −0.8 A/ms VDX = 100 V typ tq = 14.4 ms typ tq = 12.7 ms typ tq = 13.5 ms typ tq = 13.7 ms typ tq = 13.9 ms typ tq = 14.4 ms typ tq = 14.4 ms 2N5064 0.8 A RGK = 1 k dv/dt = 30 V/ms ITM = 0.8 A IRM = 0.8 A di/dt = 12 A/ms ITM duration = 275 ms VDX = 50 V dv/dt = 5 V/ms ITM = 0.2 A IRM = 50 mA di/dt = −0.6 A/ms dv/dt = 5 V/ms IRM = 50 mA di/dt = −0.8 A/ms dv/dt = 5 V/ms ITM = 1.12 A IRM = 50 mA di/dt = −0.8 A/ms IRM = 40 mA −V2 = 9 V di/dt = −0.45 A/ms IRM = 40 mA −V2 = 1 V di/dt = −0.8 A/ms VDX = 100 V dv/dt = 5 V/ms ITM = 1.12 A IRM = 50 mA di/dt = −0.8 A typ tq = 28.9 ms typ tq = 27/ms typ tq = 30/ms typ tq = 31 ms typ tq = 31.2 ms typ tq = 31.4 ms typ tq = 31.7 ms 2N5061 0.8 A dv/dt = 10 V/ms ITM = 0.8 A IRM = 0.8 A di/dt = 18 A/ms ITM duration = 275 ms RGK = 1 k VDX = 30 V dv/dt = 3.5 V/ms ITM = 0.25 A IRM = 40 mA di/dt = −0.7 A/ms dv/dt = −3.5 V/ms IRM = 40 mA di/dt = −0.8 A/ms dv/dt = 3.5 V/ms ITM = 1.12 A IRM = 40 mA di/dt = −0.8 A/ms VDX = 60 V dv/dt = 3.58/ms ITM = 1.12 A IRM = 40 mA di/dt = −0.7 A/ms −V2 = 4 V IRM = 20 mA di/dt = −0.2 A/ms −V2 = 1 V IRM = 40 mA di/dt = −0.8 A/ms typ tq = 31.7 ms typ tq = 19.1 ms typ tq = 19/ms typ tq = 19.8 ms typ tq = 20.2 ms typ tq = 30 ms typ tq = 30.2 ms
- 69. http://onsemi.com 69 Table 5.2 is a condensed summary of Table 5.1 and shows what happens to the tq of the different devices when a parameter is varied in one direction or the other. THE EFFECT OF CHANGING PARAMETERS ON tq From Tables 5.1 and 5.2, it is clear that some parameters affect tq more than others. The following discussion describes the effect on tq of the various parameters. FORWARD CURRENT MAGNITUDE (ITM) Of the parameters that were investigated, forward−cur- rent magnitude and the di/dt rate have the strongest effect on tq. Varying the ITM magnitude over a realistic range of ITM conditions can change the measured tq by about 30%. The change in tq is attributed to varying current densities (stored charge) present in the SCR’s junctions as the ITM magnitude is changed. Thus, if a large SCR must have a short tq when a low ITM is present, a large gate trigger pulse (IGT magnitude) would be advantageous. This turns on a large portion of the SCR to minimize the high current densities that exists if only a small portion of the SCR were turned on (by a weak gate pulse) and the low ITM did not fully extend the turned on region. In general, the SCR will exhibit longer tq times with increasing ITM. Increasing temperature also increases the tq time. di/dt RATE Varying the turn−off rate of change of anode current di/dt does have some effect on the tq of SCRs. Although the increase in tq versus increasing di/dt was nominal for the SCRs illustrated, the percentage change for the fast SCRs was fairly high (about 30−40%). REVERSE CURRENT MAGNITUDE (IRM) The reverse current is actually due to the stored charge clearing out of the SCR’s junctions when a negative voltage is applied to the SCR anode. IRM is very closely related to the di/dt rate; an increasing di/dt rate causing an increase of IRM and a decreasing di/dt rate causing a lower IRM. Parameter Changed Device Columns 1st (μs) 2nd (μs) IGT Increase 2N6508 2N6399 2N6240 C106F AI AG AI HI 68 48 44.8 27 68 48 41.4 27 Decrease RGK 1 k to 100 ohms 2N6508 2N6399 2N6240 AH AG GI 68 48 41.4 65 45 32.7 Increase RGK 1 k to R 2N6508 2N6399 2N6240 EF DF CH 60 32 26.2 64 35.5 37.2 VDX C106F 2N6240 MCR100−6 2N5064 2N5061 DC BC FG DG DE 26 26.2 14.4 31 20.2 26 26 14.4 31.7 19.8 Decrease dv/dt Rate 2N6508 C106F 2N6240 EH HJ DF 65 29 30 60 27 27.7 Increase ITM 2N6508 2N6399 C106F 2N6240 MCR100−6 2N5064 2N5061 EG DE EH DC DE CE CF CD BE 60 32 26 26.2 27.7 26.2 13.5 30.7 19.1 64 33 27 27.7 28.6 28.6 14.4 31 20.7 Table 5.2. The Effects of Changing Parameters on tq By using different series inductors and changing the negative anode turn−off voltage, it is possible to keep the di/dt rate constant while changing IRM. It was found that IRM has little or no effect on tq when it is the only variable changed (see Table 5.1 C106F, Columns F and G, for example). REVERSE ANODE VOLTAGE (VRM) Reverse anode voltage has a strong effect on the IRM magnitude and the di/dt rate, but when VRM alone is varied, with IRM and di/dt held constant, little or no change in tq time was noticed. VRM must always be within the reverse voltage of the device.
- 70. http://onsemi.com 70 Device Gate Bias Conditions + V1 RI dv/dt (v/μs) 0V − 5 V − V2 = −10 V, IF = 3 A 50 V 1 k/50 2.5/50 tq 1 tq 2 Diode DI dv/dt (V/μs) Remarks 2N6508 40 μs 30 μs Slow MR502 2.5 Slow diode faster than fast diode, (lower tq) 2N6240 16 μs 9 μs Slow 2.5 Slow diode faster. 2.5 V/μs faster than 50 V/μs 2N6399 30 μs 25 μs Slow 2.5 Tested slow diode only C106F 13 μs 8 μs Slow 2.5 Tested slow diode only Table 5.3 The Effects of Gate Bias on tq Figure 5.8. Standard SCR Turn−Off Time tq as a Function of Anode Current ITM C106 : 5 A/μs dv/dt : 45 V/μs RGK : 100 Ω TA : 25°C ITM, ANODE CURRENT (AMPS) di/dt C106F STANDARD SCR 25 20 15 10 5 0 502010521 t,TURN-OFFTIME(s)qμ REAPPLIED dv/dt RATE Varying the reapplied dv/dt rate across the range of dv/dt’s commonly encountered can vary the tq of a given SCR by more than 10%. The effect of the dv/dt rate on tq is due to the Anode−Gate capacitance. The dv/dt applied at the SCR anode injects current into the gate through this capacitance (iGT = C dv/dt). As the dv/dt rate increased, the gate current also increases and can trigger the SCR on. To complicate matters, this injected current also adds to the current due to leakage or stored charge left in the junctions just after turn−off. The stored charge remaining in the center junction is the main reason for long tq times and, for the most part, the charge is removed by the recombination process. If the reapplied dv/dt rate is high, more charge is injected into this junction and prevents it from returning to the blocking state, as soon as if it were a slow dv/dt rate. The higher the dv/dt rate, the longer the tq times will be. MAGNITUDE LIMIT OF REAPPLIED dv/dt (VDX) Changing the magnitude limit of the reapplied dv/dt voltage has little or no effect on a given SCR’s tq time when the maximum applied voltage is well below the voltage breakdown of the SCR. The tq times will lengthen if the SCR is being used near its voltage breakdown, since the leakage present near breakdown is higher than at lower voltage levels. The leakage will lengthen the time it takes for the charge to be swept out of the SCR’s center junction, thus lengthening the time it takes for this junction to return to the blocking state. GATE CATHODE RESISTANCE (RGK) In general, the lower the RGK is, the shorter the tq time will be for a given SCR. This is because low RGK aids in the removal of stored charge in the SCR’s junctions. An approximate 15% change in the tq time is seen by changing RGK from 100 ohms to 1000 ohms for the DUTs. GATE DRIVE MAGNITUDE (IGT) Changing the gate drive magnitude has little effect on a SCR’s tq time unless it is grossly overdriven or underdri- ven. When it is overdriven, there is an unnecessary large amount of charge in SCR’s junction. When underdriven, it is possible that only a small portion of the chip at the gate region turns on. If the anode current is not large enough to spread the small turned on region, there is a high current and charge density in this region that consequently lengthens the tq time. FORWARD CURRENT DURATION Forward current duration had no measurable effect on tq time when varied from 100 μs to 300 μs, which were the limits of the ON Semiconductor tq Tester. Longer ITM durations heat up the SCR which causes temperature effects; very short ITM durations affect the tq time due to the lack of time for the charges in the SCR’s junctions to reach equilibrium, but these effects were not seen in the range tested.
- 71. http://onsemi.com 71 REVERSE GATE BIAS VOLTAGE As in transistor operation, reverse biasing the gate of the SCR decreases the turn−off time, due to the rapid “sweeping out” of the stored charge. The reduction in tq for standard SCRs is quite pronounced, approaching perhaps 50% in some cases; for fast SCRs, only nominal improvement might result. Table 5.3 shows this effect on six SCRs where the gate bias was set for 0 V and − 5 V, respectively (the 1 k gate resistor of the DUT was either grounded or returned to − 5 V). Due to the internal, monolithic resistor of most SCRs, the actual reverse bias voltage between the gate−cathode is less than the reverse bias supply. CHARACTERIZING SCRs FOR CROWBAR APPLICATIONS The use of a crowbar to protect sensitive loads from power supply overvoltage is quite common and, at the first glance, the design of these crowbars seems like a straightforward, relatively simple task. The crowbar SCR is selected so as to handle the overvoltage condition and a fuse is chosen at 125 to 250% of the supply’s rated full−load line current. However, upon further investiga- tion, other questions and problems are encountered. How much overvoltage and for how long (energy) can the load take this overvoltage? Will the crowbar respond too slowly and thus not protect the load or too fast resulting in false, nuisance triggering? How much energy can the crowbar thyristor (SCR) take and will it survive until the fuse opens or the circuit breaker opens? How fast will the fuse open, and at what energy level? Can the fuse adequately differentiate between normal current levels — including surge currents — and crowbar short circuit conditions? It is the attempt of this section to answer these questions — to characterize the load, crowbar, and fuse and thus to match their characteristics to each other. The type of regulator of most concern is the low voltage, series pass regulator where the filter capacitors to be crowbarred, due to 60 Hz operation, are relatively large and the charge and energy stored correspondingly large. On the other hand, switching regulators operating at about 20 kHz require smaller capacitors and thus have lower crowbar constraints. These regulators are quite often line−operated using a high voltage, two−transistor inverter, half bridge or full bridge, driving an output step−down transformer. If a transistor were to fail, the regulator−transformed power would be less and the output voltage would drop, not rise, as is the case for the linear series regulator with a shorted pass transistor. Thus, the need for overvoltage protection of these types of switching regulators is minimized. This premise, however, does not consider the case of the lower power series switching regulator where a shorted transistor would cause the output voltage to rise. Nor does it take into account overvoltage due to transients on the output bus or accidental power supply hookup. For these types of operations, the crowbar SCR should be considered. HOW MUCH OVERVOLTAGE CAN THE LOAD TAKE? Crowbar protection is most often needed when ICs are used, particularly those requiring a critical supply voltage such as TTL or expensive LSI memories and MPUs. If the load is 5 V TTL, the maximum specified continuous voltage is 7 V. (CMOS, with its wide power supply range of 3 to 18 V, is quite immune to most overvoltage conditions.) But, can the TTL sustain 8 V or 10 V or 15 V and, if so, for how long and for how many power cycles? Safe Operating Area (SOA) of the TTL must be known. Unfortunately, this information is not readily available and has to be generated. 20 PULSE WIDTH (ms) VCC TJ ≈ 85°C, DUTY CYCLE = 10% PULSE WIDTH 12 14 16 18 5003001 105 10030 50 10 V,SUPPLYVOLTAGE(VOLTS) CC Figure 5.9. Pulsed Supply Voltage versus Pulse Width 5 V Using the test circuit illustrated in Appendix III, a quasi−SOA curve for a typical TTL gate was generated (Figure 5.9). Knowing the overvoltage−time limit, the crowbar and fuse energy ratings can be determined. The two possible configurations are illustrated in Figure 5.10, the first case shows the crowbar SCR across the input of the regulator and the second, across the output. For both configurations, the overvoltage compara- tor senses the load voltage at the remote load terminals, particularly when the IR drop of the supply leads can be appreciable. As long as the output voltage is less than that of the comparator reference, the crowbar SCR will be in an off state and draw no supply current. When an over−voltage condition occurs, the comparator will pro- duce a gate trigger to the SCR, firing it, and thus clamping the regulator input, as in the first case — to the SCRs on−state drop of about 1 to 1.5 V, thereby protecting the load.
- 72. http://onsemi.com 72 Figure 5.10. Typical Crowbar Configurations *NEEDED IF SUPPLY NOT CURRENT LIMITED (b). SCR Across Output of Regulator * vO Vin vO CoCin D1 F (a). SCR Across Input of Regulator Vin SERIES REGULATOR REGULATOR OVERVOLTAGE SENSE OVERVOLTAGE SENSE Placing the crowbar across the input filter capacitors, although effectively clamping the output, has several disadvantages. 1. There is a stress placed on the input rectifiers during the crowbarring short circuit time before the line fuse opens, particularly under repeated operation. 2. Under low line conditions, the minimum short circuit current can be of the same magnitude as the maximum primary line current at high line, high load, making the proper fuse selection a difficult choice. 3. The capacitive energy to be crowbarred (input and output capacitor through rectifier D1) can be high. When the SCR crowbar and the fuse are placed in the dc load circuit, the above problems are minimized. If crowbarring occurs due to an external transient on the line and the regulator’s current limiting is working properly, the SCR only has to crowbar the generally smaller output filter capacitor and sustain the limited regulator current. If the series pass devices were to fail (short), even with current limiting or foldback disabled, the crowbarred energy would generally be less than of the previous case. This is due to the higher impedance of the shorted regulator (due to emitter sharing and current sensing resistors) relative to that of rectifier D1. Fuse selection is much easier as a fault will now give a greater percentage increase in dc load current than when measuring transformer primary or secondary rms current. The disadvantage, however, of placing the fuse in the dc load is that there is no protection for the input rectifier, capacitor, and transformer, if one of these components were to fail (short). Secondly, the one fuse must protect not only the load and regulator, but also have adequate clearing time to protect the SCR, a situation which is not always readily accomplished. The input circuitry can be protected with the addition of a primary fuse or a circuit breaker. HOW MUCH ENERGY HAS TO BE CROWBARRED? This is dictated by the power supply filter capacitors, which are a function of output current. A survey of several linear power supply manufacturers showed the output filter capacitor size to be from about 100 to 400 microfarads per ampere with about 200 μF/A being typical. A 30 A regulator might therefore have a 6000 μF output filter capacitor.
- 73. http://onsemi.com 73 Additionally, the usually much larger input filter capacitor will have to be dumped if the regulator were to short, although that energy to be dissipated will be dependent on the total resistance in the circuit between that capacitor and the SCR crowbar. The charge to be crowbarred would be Q + CV + IT, the energy, E + 1ń2 CV2 and the peak surge current ipk + VC RT When the SCR crowbars the capacitor, the current waveform will be similar to that of Figure 5.11, with the peak surge current, ipk, being a function of the total impedance in the circuit (Figure 5.12) and will thus be limited by the Equivalent Series Resistance (ESR) and inductance (ESL) of the capacitor plus the dynamic impedance of the SCR, any external current limiting resistance, (and inductance) of the interconnecting wires and circuit board conductors. The ESR of computer grade capacitors, depending on the capacitor size and working voltage, might vary from 10 to 1000 milliohms (mΩ). Those used in this study were in the 25 to 50 mΩ range. The dynamic impedance of the SCR (the slope of the on−state voltage, on−state current curve), at high currents, might be in the 10 to 20 mΩ range. As an example, from the on−state characteristics of the MCR70, 35 A rms SCR, the dynamic impedance is rd + DVF DIF + (4.5 * 3.4)V (300 * 200)A + 1.1 V 100 A `11 mΩ. The interconnecting wire might offer an additional 5 mΩ (#20 solid copper wire ` 20 mΩ/ft) so that the total circuit resistance, without additional current limiting, might be in the 40 to 70 mΩ range. The circuit inductance was considered low enough to ignore so far as ipk is concerned for this exercise, being in hundreds of nano- henry range (ESL ` 3 nH, L wire ` 500 nH/ft). However, di/dt will be affected by the inductance. HOW MUCH ENERGY CAN THE CROWBAR SCR SUSTAIN? There are several factors which contribute to possible SCR failures or degradation — the peak surge current, di/dt, and a measure of the device’s energy capability, I2t. If the peak current and/or duration of the surge is large, destruction of the device due to excessive dissipation can occur. Obviously, the ipk can be reduced by inserting additional impedance in the crowbar path, at an increase in dump time. However, this time, which is a measure of how long the overvoltage is present, should be within the SOA of the load. The energy stored in the capacitor being a constant for a particular voltage would suggest that the I2t integral for any limiting resistance is also a constant. In reality, this is not the case as the thermal response of the device must be taken into consideration. It has been shown that the dissipation capability of a device varies as to the tǸ for the first tens of milliseconds of the thermal response and, in effect, the measure of a device’s energy capability would be closer to i2 tǸ . This effect is subsequently illustrated in the empirically derived ipk versus time derating curves being a non−linear function. However, for comparison with fuses, which are rated in I2t, the linear time base, “t,” will be used. The di/dt of the current surge pulse is also a critical parameter and should not exceed the device’s ratings (typically about 200 A/μs for 50 A or less SCRs). The magnitude of di/dt that the SCR can sustain is controlled by the device construction and, to some extent, the gate drive conditions. When the SCR gate region is driven on, conduction across the junction starts in a small region and progressively propagates across the total junction. Anode current will initially be concentrated in this small conducting area, causing high current densities which can degrade and ultimately destroy the device. To minimize this di/dt effect, the gate should be turned on hard and fast such that the area turned on is initially maximized. This can be accomplished with a gate current pulse approach- ing five times the maximum specified continuous gate current, Igt, and with a fast rise time ( 1 μs). The gate current pulse width should be greater than the propagation time; a figure of 10 μs minimum should satisfy most SCRs with average current ratings under 50 A or so. The wiring inductance alone is generally large enough to limit the di/dt. Since most SCRs are good for over 100 A/μs, this effect is not too large a problem. However, if the di/dt is found excessive, it can be reduced by placing an inductance in the loop; but, again, this increases the circuit’s response time to an overvoltage and the trade−off should be considered.
- 74. http://onsemi.com 74 Figure 5.11. Typical SCR Crowbar Waveform CROWBAR CURRENT TERMS di/dt I t2.3 τ 10% 10% 50% ipk 5 τ tW tW I = 200 A/Div RS = 0 MCR69 VC = 30 V C = 22,000 μF IGT = 200 mA 0 t = 0.5 ms/Div 0 t = 10 μs/Div Figure 5.12. Circuit Elements Affecting SCR Surge Current RW, LW: INTERCONNECTING WIRE IMPEDANCE RS, LS: CURRENT LIMITING IMPEDANCE ESL LS RS RW ESR LW Since many SCR applications are for 60 Hz line operation, the specified peak non−repetitive surge current ITSM and circuit fusing I2t are based on 1/2 cycle (8.3 ms) conditions. For some SCRs, a derating curve based on up to 60 or 100 cycles of operation is also published. This rating, however, does not relate to crowbar applications. To fully evaluate a crowbar system, the SCR must be characterized with the capacitor dump exponential surge current pulse. A simple test circuit for deriving this pulse is shown in Figure 5.13, whereby a capacitor is charged through a limiting resistor to the supply voltage, V, and then the charge is dumped by the SCR device under test (DUT). The SCR gate pulse can be varied in magnitude, pulse width, and rise time to produce the various IGT conditions. An estimate of the crowbar energy capability of the DUT is determined by first dumping the capacitor charged to low voltage and then progressively increasing the voltage until the DUT fails. This is repeated for several devices to establish an average and minimum value of the failure points cluster.
- 75. http://onsemi.com 75 Figure 5.13 V EXTERNAL TRIGGER 5022,000 μF 100 DUT H.P. 214A PULSE GENERATOR This procedure was used to test several different SCRs of which the following Table 5.4 describes several of the pertinent energy specifications and also the measured crowbar surge current at the point of device failure. This one−shot destruct test was run with a gate current of five IGT(MAX) and a 22,000 μF capacitor whose ESR produced the exponentially decaying current pulse about 1.5 ms wide at its 10% point. Based on an appropriate derating, ten devices of each line where then successfully tested under the following conditions. Device VC ipk t 2N6397 12 V 250 A 1.5 ms 2N6507 30 V 800 A 1.5 ms To determine the effect of gate drive on the SCRs, three devices from each line were characterized at non−destruct levels using three different capacitors (200, 6,000, and 22,000 μF), three different capacitor voltages (10, 20, and 30 V), and three different gate drives (IGT(MAX), 5 IGT(MAX), and a ramp IGT(MAX) with a di/dt of about 1 mA/μs). Due to its energy limitations, the MCR68 was tested with only 10 V across the larger capacitors. The slow ramp, IGT, was used to simulate overvoltage sense applications where the gate trigger rise time can be slow such as with a coupling zener diode. No difference in SCR current characteristics were noted with the different gate current drive conditions; the peak currents were a function of capacitor voltage and circuit impedance, the fall times related to RTC, and the rise times, tr, and di/dt, were more circuit dependent (wiring inductance) and less device dependent (SCR turn−on time, ton). Since the wiring inductance limits, tr, the effect of various IGTs was masked, resulting in virtually identical waveforms. The derated surge current, derived from a single (or low number) pulse test, does not truly reflect what a power supply crowbar SCR might have to see over the life of the supply. Life testing over many cycles have to be performed; thus, the circuit described in Appendix IV was developed. This life test fixture can simultaneously test ten SCRs under various crowbar energy and gate drive conditions. Table 5.4. Specified and Measured Current Characteristics of Three SCRs Device Case Maximum Specified Values Measured Crowbar Surge Current Ipk IT(rms) (A) IT(AV) (A) ITSM* (A) I2t (A2s) IGT(Max) (mA) Min (A) Max (A) Ave (A) 2N6397 TO−220 12 8 100 40 30 380 750 480 2N6507 TO−220 25 16 300 375 40 1050 1250 1100 * ITSM = Peak Non−Repetitive Surge Current, 1/2 cycle sine wave, 8.3 ms. Each of the illustrated SCRs of Figure 5.14(a) were tested with as many as four limiting resistors (0, 50, 100, and 240 mΩ) and run for 1000 cycles at a nominal energy level. If no failures occurred, the peak current was progressively increased until a failure(s) resulted. Then the current was reduced by 10% and ten new devices were tested for 2000 cycles (about six hours at 350 cycles/hour). If this test proved successful, the data was further derated by 20% and plotted as shown on log−log paper with a slope of − 1/4. This theoretical slope, due to the I2 tǸ one−dimensional heat−flow relationship (see Appendix VI), closely follows the empiri- cal results. Of particular interest is that although the peak current increases with decreasing time, as expected, the I2t actually decreases.
- 76. http://onsemi.com 76 Figure 5.14(a). Peak Surge Current versus Pulse Width tW, BASE PULSE WIDTH (ms) 2N6507 0.5 1000.1 5 10 100 300 1000 3000 1 30 50 2N6397 I,PEAKCURRENT(AMPS)pk tW 5 TC C = 8400 μF TA = 25°C ESR ≈ 25 mΩ N = 2000 PULSES VC p 60 V f = 3 PULSES/MIN. Ipk (b). Peak Surge Current versus Ambient Temperature TC, AMBIENT TEMPERATURE (°C) 0.2 0 1 0.8 0.6 0.4 125100755025 N = 2000 PULSES NORMALIZEDPEAKSURGECURRENT Figure 5.14(b) shows the effect of elevated ambient temperature on the peak current capability of the illustrated SCRs. FUSE CHARACTERISTICS SCRs, like rectifiers, are generally rated in terms of average forward current, IT(AV), due to their half−wave operation. Additionally, an rms forward current, IT(rms), a peak forward surge current, ITSM, and a circuit−fusing energy limit, I2t, may be shown. However, these specifi- cations, which are based one−half cycle 60 Hz operation, are not related to the crowbar current pulse and some means must be established to define their relationship. Also, fuses which must ultimately match the SCR and the load, are rated in rms currents. The crowbar energy curves are based on an exponen- tially decaying surge current waveform. This can be converted* to Irms by the equation. Irms + 0.316 ipk which now allows relating the SCR to the fuse. *See Appendix V The logic load has its own overvoltage SOA as a function of time (Figure 5.9). The crowbar SCR must clamp the overvoltage within a specified time, and still be within its own energy rating; thus, the series−limiting resistance, RS, in the crowbar path must satisfy both the load and SCR energy limitations. The overvoltage response time is set by the total limitations. The overvoltage response time is set by the total limiting resistance and dumped capacitor(s) time constant. Since the SOA of the TTL used in this exercise was derived by a rectangular overvoltage pulse (in effect, over−energy), the energy equivalent of the real−world exponentially falling voltage waveform must be made. An approximation can be made by using an equivalent rectangular pulse of 0.7 times the peak power and 0.7 times the base time. Once an overvoltage is detected and the crowbar is enabled, in addition to sustaining the peak current, the SCR must handle the regulator short−circuit current for the time it takes to open the fuse. Thus, all three elements are tied together — the load can take just so much overvoltage (over−energy) and the crowbar SCR must repeatedly sustain for the life of the equipment an rms equivalent current pulse that lasts for the fuse response time. It would seem that the matching of the fuse to the SCR would be straightforward — simply ensure that the fuse rms current rating never exceed the SCR rms current rating (Figure 5.15), but still be sufficient to handle steady−state and normal overload currents. The more exact relationship would involve the energy dissipated in the system ∫I2Rdt, which on a comparative basis, can be reduced to I2t. Thus, the “let−through” I2t of the fuse should not exceed I2t capability of the SCR under all operating conditions. These conditions are many, consist- ing of “available fault current,” power factor of the load, supply voltage, supply frequency, ambient temperature, and various fuse factors affecting the I2t. There has been much detailed information published on fuse characteristics and, rather than repeat the text which would take many pages, the reader is referred to those sources. Instead, the fuse basics will be defined and an example of matching the fuse to the SCR will be shown. In addition to interrupting high current, the fuse should limit the current, thermal energy, and overvoltage due to the high current. Figure 5.16 illustrates the condition of the fuse at the moment the over−current starts. The peak let−through current can be assumed triangular in shape for a first−order approximation, lasting for the clearing time of the fuse. This time consists of the melting or pre−arcing time and the arcing time. The melting time is an inverse function of over−current and, at the time that the fuse element is opened, an arc will be formed causing the peak arc voltage. This arc voltage is both fuse and circuit dependent and under certain conditions can exceed the
- 77. http://onsemi.com 77 peak line voltage, a condition the user should ensure does not overstress the electronics. The available short−circuit current is the maximum current the circuit is capable of delivering and is generally limited by the input transformer copper loss and reactance when the crowbar SCR is placed at the input to the regulator or the regulator current limiting when placed at the output. For a fuse to safely protect the circuit, it should limit the peak let−through current and clear the fault in a short time, usually less than 10 ms. Figure 5.15. Time−Current Characteristic Curves of a Crowbar SCR and a Fuse TIME t (LOG) 10 ms LIMITED BY FUSE Irms (max) FUSE CHARACTERISTIC SCR CHARACTERISTICS 4 HRS CURRENTI(LOG)rms Figure 5.16. Typical Fuse Timing Waveforms During Short Circuit PEAK ARC VOLTAGE INSTANT OF SHORT SUPPLY VOLTAGE PEAK ASYMMETRICAL FAULT CURRENT CLEARING TIME FUSE VOLTAGE ARCING TIME MELTING TIME PEAK FUSE CURRENT IPLT FUSE CURRENT Fuse manufacturers publish several curves for charac- terizing their products. The current−time plot, which describes current versus melting time (minimum time being 10 ms), is used in general industrial applications, but is not adequate for protecting semiconductors where the clearing time must be in the subcycle range. Where protection is required for normal multicycle overloads, this curve is useful. Two other useful curves, the total clearing I2t character- istic and the peak let−through current IPLT characteristic, are illustrated in Figures 5.17 and 5.18 respectively. Some vendors also show total clearing time curves (overlayed on Figure 5.17 as dotted lines) which then allows direct comparison with the SCR energy limits. When this clearing time information is not shown, then the designer should determine the IPLT and I2t from the respective curves and then solve for the clearing time from the approximate equation relating these two parameters. Assuming a triangular waveform for IPLT, the total clearing time, tc, would then approximately be tc ≈ 3 I2t IPLT2 Once tc of the fuse is known, the comparison with the SCR can readily be made. As long as the I2t of the fuse is less than the I2t of the SCR, the SCR is protected. It should be pointed out that these calculations are predi- cated on a known value of available fault current. By inspection of Figure 5.18, it can be seen that IPLT can vary greatly with available fault current, which could have a marked effect on the degree of protection. Also, the illustrated curves are for particular operating conditions; the curves will vary somewhat with applied voltage and frequency, initial loading, load power factor, and ambient temperature. Therefore, the reader is referred to the manufacturer’s data sheet in those cases where extrapola- tion will be required for other operating conditions. The final proof is obtained by testing the fuse in the actual circuit under worst−case conditions. CROWBAR EXAMPLE To illustrate the proper matching of the crowbar SCR to the load and the fuse, consider the following example. A 50 A TTL load, powered by a 60 A current limited series regulator, has to be protected from transients on the supply bus by crowbarring the regulator output. The output filter capacitor of 10,000 μF (200 μF/A) contrib- utes most of the energy to be crowbarred (the input capacitor is current limited by the regulator). The transients can reach 18 V for periods 100 ms. Referring to Figure 5.9, it is seen that this transient exceeds the empirically derived SOA. To ensure safe operation, the overvoltage transient must be crowbarred within 5 ms. Since the TTL SOA is based on a rectangular power pulse even though plotted in terms of voltage, the equivalent crowbarred energy pulse should also be derived. Thus, the exponentially decaying voltage wave- form should be multiplied by the exponentially decaying current to result in an energy waveform proportional to e−2x. The rectangular equivalent will have to be deter- mined and then compared with the TTL SOA. However, for simplicity, by using the crowbarred exponential waveform, a conservative rating will result.
- 78. http://onsemi.com 78 Figure 5.17. Maximum Clearing I2t Characteristics for 10 to 20 A Fuses SF 13X SERIES 130 Vrms, 60 Hz TA = 25°C POWER FACTOR p 15% 4 10 4 102 2 ms 1.5 ms TOTAL CLEARING TIME 10 A 105 5 ms 4 4102 4103 104 AVAILABLE FAULT CURRENT (SYMMETRICAL rms AMPS) 15 A 10 20 A 4 4 1 LET-THROUGHIt(AS)22 To protect the SCR, a fuse must be chosen that will open before the SCR’s I2t is exceeded, the current being the regulator limiting current which will also be the available fault current to the fuse. The fuse could be eliminated by using a 60 A SCR, but the cost versus convenience trade−off of not replacing the fuse is not warranted for this example. A second fuse or circuit breaker will protect the rectifiers and regulator for internal faults (shorts), but its selection, which is based on the respective energy limits of those components, is not part of this exercise. If a crowbar discharge time of 3 ms were chosen, it would not only be within the rectangular pulsed SOA, but also be well within the derived equivalent rectangular model of the exponential waveform. It would also require about 1.3 time constants for the overvoltage to decay from 18 V to 5 V; thus, the RC time constant would be 3 ms/1.3 or 2.3 ms. The limiting resistance, RS would simply be RS + 2.3 ms 10,000 mF + 0.23 W ` 0.2 W Figure 5.18. Peak Let−Through Current versus Fault Current for 10 to 20 A Fuses 15 A AVAILABLE FAULT CURRENT (SYMMETRICAL rms AMPS) MAX PEAK AVAILABLE CURRENT (2.35 x SYMMETRICAL rms AMPERES) 10 A 20 A 1054 4102 4103 10410 4 10 4 102 4 103 INSTANTANEOUSPEAKLET-THROUGHCURRENT(AMPS SF 13X SERIES 130 Vrms, 60 Hz POWER FACTOR p 15%
- 79. http://onsemi.com 79 Since the capacitor quickly charges up to the over−voltages VCC1 of 18 V, the peak capacitor discharge current would be Ipk + VCC1 RS + 18 V 0.2 W + 90 A The rms current equivalent for this exponentially decay- ing pulse would be Irms + 0.316 Ipk + 0.316(90) + 28.4 A rms Now referring to the SCR peak current energy curves (Figure 5.14), it is seen that the MCR68 can sustain 210 A peak for a base time of 3 ms. This 12 A SCR must also sustain the 60 A regulator limited current for the time required to open the fuse. The MCR68 has a specified peak forward surge current rating of 100 A (1/2 cycle, sine wave, 60 Hz, non−repetitive) and a circuit fusing rating of 40 A2s. The non−repetitive rating implies that the device can sustain 100 occurrences of this 1/2 cycle surge over the life of the device; the SCR crowbar surge current curves were based on 2000 cycles. For the 3 ms time frame, the I1 2t1 for the exponential waveform is I1 2 t1 + (28.4 A)2(3 ms) + 2.4 A2s Assuming that the fuse will open within 6 ms, the approximate energy that the SCR must sustain would be 60 A for an additional 3 ms. By superposition, this would amount to I2 2 t2 + (60 A)2(6 ms) + 21.6 A2s which , when added to the exponential energy, would result in 24 A2. The MCR68 has a 40 A2s rating based on a 1/2 cycle of 8.3 ms. Due to the one−dimensional heat flow in the device, the energy capability is not linearly related to time, but varies as to the tǸ . Therefore, with a 6 ms 1/2−cycle sine wave, the 40 A2t rating would now decrease to approximately (see Appendix VI for derivation). I2 2 t2 + I1 2 t1ǒt2 t1 Ǔ 1ń2 + 40 A2s ǒ 6 ms 8.3 ms Ǔ 1ń2 + 34 A2s Although the 1/2 cycle extrapolated rating is greater than the actual crowbar energy, it is only characterized for 100 cycles of operation. To ensure 2000 cycles of operation, at a somewhat higher cost, the 25 A MCR69 could be chosen. Its exponential peak current capability, at 3 ms, is about 560 A and has a specified ITSM of 300 A for 8.3 ms. The I2t rating is not specified, but can be calculated from the equation I2t + (ITSM)2 2 t + (300 A)2 2 (8.3 ms) + 375 A2s Extrapolating to 6 ms results in about 318 A2s, an I2t rating much greater than the circuit 24 A2s value. The circuit designer can then make the cost/perfor- mance trade−offs. All of these ratings are predicated on the fuse operating within 6 ms. With an available fault current of 60 A, Figure 5.17 shows that a 10 A (SF13X series) fuse will have a let−through I2t of about 10 A2s and a total clearing time of about 6 ms, satisfying the SCR requirements, that is, I2t fuse t I2t SCR tc p 6 ms Figure 5.18 illustrates that for the same conditions, instantaneous peak let−through current of about 70 A would result. For fuse manufacturers that don’t show the clearing time information, the approximate time can be calculated from the triangular model, as follows tc + 3 I2t IPLT2 + 3(10) (70)2 + 6.1 ms The fuse is now matched to the SCR which is matched to the logic load. Other types of loads can be similarly matched, if the load energy characteristics are known. CHARACTERIZING SWITCHES AS LINE−TYPE MODULATORS In the past, hydrogen thyratrons have been used extensively as discharge switches for line type modula- tors. In general, such devices have been highly satisfac- tory from an electrical performance standpoint, but they have some major drawbacks including relatively large size and weight, low efficiency (due to filament power requirements), and short life expectancy compared with semiconductor devices, now can be eliminated through the use of silicon controlled rectifiers. A line type modulator is a modulator whose output− pulse characteristics are determined by a lumped− constant transmission line (pulse forming network) and by the proper match of the line impedance (PFN) to the load impedance. A switch for this type modulator should only initiate conduction and should have no effect on pulse character- istics. This is in contrast to a hard switch modulator where output pulse characteristics are determined by the “hard” relationship of grid (base) control of conduction through a vacuum tube (transistor) switch. Referring to the schematic (Figure 5.25), when the power supply is first turned on, no charge exists in the PFN, and energy is transferred from the power supply to the PFN via the resonant circuit comprising the charging choke and PFN capacitors. At the time that the voltage
- 80. http://onsemi.com 80 across the PFN capacitors reaches twice the power supply voltage, current through the charging choke tries to reverse and the power supply is disconnected due to the back biased impedance of the hold−off diode. If we assume this diode to be perfect, the energy remains stored in the PFN until the discharge switch is triggered to its on state. When this occurs, assuming that the pulse trans- former has been designed to match the load impedance to the PFN impedance, all energy stored in the PFN reactance will be transferred to the load if we neglect switch losses. Upon completion of the transfer of energy the switch must return to its off condition before allowing transfer of energy once again from the power supply to the PFN storage element. OPTIMUM SWITCH CHARACTERISTICS FORWARD BREAKOVER VOLTAGE Device manufacturers normally apply the variable− amplitude output of a half−wave rectifier across the SCR. Thus, forward voltage is applied to the device for only a half cycle and the rated voltage is applied only as an ac peak. While this produces a satisfactory rating for ac applications, it does not hold for dc. An estimated 90% of devices tested for minimum breakover voltage (VBO) in a dc circuit will not meet the data sheet performance specifications. A switch designed for the pulse modulator application should therefore specify a minimum continuous forward breakover voltage at rated maximum leakage current for maximum device temperatures. THE OFF SWITCH The maximum forward leakage current of the SCR must be limited to a low value at maximum device temperature. During the period of device nonconduction it is desired that the switch offer an off impedance in the range of megohms to hundreds of megohms. This is required for two reasons: (1) to prevent diminishing the efficiency of recharge by an effective shunt path across the PFN, and (2) to prevent the bleeding off of PFN charge during the interpulse period. This second factor is especially important in the design of radar tansponders wherein the period between interrogations is variable. Change of the PFN voltage during the interpulse period could result in frequency shift, pulse instabilities, and loss of power from the transmitter being modulated. THE ON SWITCH At present, SCR design is more limited in the achievable maximum forward sustaining voltage than in the current that the device will conduct. For this reason modulators utilizing SCRs can be operated at lower impedance levels than comparable thyratron circuits of yesterday. It is not uncommon for the characteristic impedance of the pulse forming network to be in the order of 5 to 10 ohms or less. Operating the SCR at higher current to switch the same equivalent pulse power as a thyratron requires the SCR on impedance to be much lower so that the I2R loss is a reasonable value, in order to maintain circuit efficiency. Low switch loss, moreover, is mandatory because internal power dissipation can be directly translated into junction−temperature−rise and associated leakage current increase which, if excessive, could result in thermal runaway. TURN−ON TIME In radar circuits the pulse−power handling capability of an SCR, rather than the normally specified average− power capability, is of primary importance. For short pulses at high PRFs the major portion of semiconductor dissipation occurs during the initial turn−on during the time that the anode rises from its forward leakage value to its maximum value. It is necessary, therefore, that turn−on time be as short as possible to prevent excessive power dissipation. The function of radar is to provide distance information measured as a function of time. It is important, therefore, that any delay introduced by a component be fixed in relation to some variable parameter such as signal strength or temperature. For radar pulse modulator applications, a minimal delay variation versus tempera- ture is required and any such variation must be repetitive from SCR to SCR, in production lots, so that adequate circuit compensation may be provided. PULSE GATE CURRENT TO FIRE The time of delay, the time of rise, and the delay variation versus temperature associated with SCR turn−on are functions of the gate triggering current available and the trigger pulse duration. In order to predict pulse circuit operation of the SCR, the pulse gate current required to turn the device on when switching the low−impedance modulator should be specified and the limits of turn−on− time variation for the specified pulse trigger current and collector load should be given at the high and low operating temperature extremes. RECOVERY TIME After the cessation of forward conducting current in the on device, a time of SCR circuit isolation must be provided to allow the semiconductor to return to its off state. Recovery time cannot be given as an independent parameter of device operation, but must include factors as determined by the external circuit, such as: (1) pulse current and rate of decay; (2) availability of an inverse voltage immediately following pulse−current conduction; (3) level of base bias following pulse current conduction; (4) rate of rise of reapplied positive voltage and its amplitude in relation to SCR breakover voltage; and (5) maximum circuit ambient temperature.
- 81. http://onsemi.com 81 In the reverse direction the controlled rectifier behaves like a conventional silicon diode. Under worst circuit conditions, if an inverse voltage is generated through the existence of a load short circuit, the current available will be limited only by the impedance of the pulse forming network and SCR inverse characteristics. The reverse current is able to sweep out some of the carriers from the SCR junctions. Intentional design of the load impedance to something less than the network impedance allows development of an inverse voltage across the SCR immediately after pulse conduction, enhancing switch turn−off time. Careful use of a fast clamp diode in series with a fast zener diode, the two in shunt across the SCR, allows application of a safe value of circuit−inverse−volt- age without preventing the initial useful reverse current. Availability of a negative base−bias following pulse current conduction provides a similar enhancement of switch turn−off time. If removal of carriers from the SCR junction enables a faster switch recovery time, then, conversely, operation of the SCR at high temperatures with large forward currents and with slow rate of current decay all increase device recovery time. HOLDING CURRENT One of the anomalies that exist in the design of a pulse SCR is the requirement for a high holding current. This need can be determined by examining the isolation component that disconnects the power supply from the discharge circuit during the time that PFN energy is being transferred to the transmitter and during the recovery time of the discharge switch. An inductance resonating with the PFN capacitance at twice the time of recharge is normally used for power supply isolation. Resonant charging restricts the initial flow of current from the power supply, thereby maximizing the time at which power supply current flow will exceed the holding current of the SCR. If the PFN recharge current from the power supply exceeds the holding current of the SCR before it has recovered, the SCR will again conduct without the application of a trigger pulse. As a result continuous conduction occurs from the power supply through the low impedance path of the charging choke and on switch. This lock−on condition can completely disable the equipment employing the SCR switch. The charging current passed by the inductance is given as (the PFN inductance is considered negligible): ic(t) + Ebb * Vn(0) LcńCnǸ ȧȧ ȡ Ȣ cos Tr*2t 2 LcCnǸ sin Tr 2 LcCnǸ ȧȧ ȣ Ȥ Where Ebb = power supply voltage Vn(0) = 0 volts if the PFN employs a clamp diode or is matched to the load Tr = time of resonant recharge and is usually equal to 1 PRF Lc = value of charging inductance Cn = value of total PFN capacity For a given radar pulse modulator design, the values of power supply voltage, time of resonant recharge, charging choke inductance, and PFN capacitance are established. If the time (t) represents the recovery time of the SCR being used as the discharge switch, ic then represents the minimum value of holding current required by the SCR to prevent power supply lock−on. Conversely, if the modula- tor design is about an existing SCR where holding current, recovery time, and forward breakover voltage are known, the charge parameters can be derived by rewriting the above formula as follows: iH + VBO * Vn(0) LcńCnǸ ȧȧ ȡ Ȣ cos Tr*2(recovery time) 2 Lc CnǸ sin Tr 2 Lc CnǸ ȧȧ ȣ Ȥ The designer may find that for the chosen SCR the desired characteristics of modulator pulse width and pulse repetition frequency are not obtainable. One means of increasing the effective holding current of an SCR is for the semiconductor to exhibit some turn−off gain characteristic for the residual current flow at the end of the modulator pulse. The circuit designer then can provide turn−off base current, making the SCR more effective as a pulse circuit element. THE SCR AS A UNIDIRECTIONAL SWITCH When triggered to its on state, the SCR, like the hydrogen thyratron, is capable of conducting current in one direction. A load short circuit could result in an inverse voltage across the SCR due to the reflection of voltage from the pulse forming network. The circuit designer may wish to provide an intentional load−to−PFN mismatch such that some inverse voltage is generated across the SCR to enhance its turn−off characteristics. Nevertheless, since the normal circuit application is unidirectional, the semiconductor device designer could take advantage of this fact in restricting the inverse−volt- age rating that the SCR must withstand. The circuit designer, in turn, can accommodate this lack of peak− inverse−voltage rating by use of a suitable diode clamp across the PFN or across the SCR.
- 82. http://onsemi.com 82 SCRs TESTS FOR PULSE CIRCUIT APPLICATION The suitability for pulse circuit applications of SCRs not specifically characterized for such purposes can be determined from measurements carried out with relatively simple test circuits under controlled conditions. Applica- ble test circuits and procedures are outlined in the following section. FORWARD BLOCKING VOLTAGE AND LEAKAGE CURRENT Mount the SCRs to a heat sink and connect the units to be tested as shown in Figure 5.21. Place the assembly in an oven and stabilize at maximum SCR rated tempera- ture. Turn on the power supply and raise the voltage to rated VBO. Allow units to remain with the voltage applied for minimum of four hours. At the end of the temperature soak, determine if any units exhibit thermal runaway by checking for blown fuses (without removing the power). Reject any units which have blown circuit fuses. The forward leakage current, ILF, of the remaining units may be calculated after measuring the voltage VL, across resistor R2. Any units with a leakage current greater than manufacturer’s rating should be rejected. Figure 5.20. Vertical Set to 4 cm, Horizontal 0.2 μs/cm. Detected RF Magnetron Pulse TURN−ON TIME, VARIATION AND ON IMPEDANCE This circuit assumes that the pulse gate current required to switch a given modulator load current is specified by the manufacturer or that the designer is able to specify the operating conditions. Typical operating values might be: Time of trigger pulse t = 1 μs Pulse gate current IG = 200 mA Forward blocking voltage VBO = 400 V Load current ILoad = 30 A To measure turn−on time using a Tektronix 545 oscilloscope (or equivalent) with a dual trace type CA plug−in, connect probes of Channels A and B to Test Points A and B. Place the Mode selector switch in the Added Algebraically position and the Channel B Polarity switch in the Inverted position. Adjust the HR212A pulse generator to give a positive pulse 1 μs wide (100 pps) as viewed at Test Point A. Adjust the amplitude of the “added” voltage across the 100−ohm base resistor for the specified pulse gate current (200 mA in this example). Switch the Mode selector knob to the alternate position. Connect Channel A to Test Point D. Leave the oscillo- scope probe, Channel B, at Test Point B, thereby displaying the input trigger waveform. Measure the time between the 50 percent voltage amplitudes of the two waveforms. This is the Turn−On Time (tD + tR). To measure turn−on time versus temperature, place the device to be tested on a suitable heat sink and place the assembly in a temperature chamber. Stabilize the chamber at minimum rated (cold) temperature. Repeat the above measurements. Raise the chamber temperature to maxi- mum rated (hot) temperature and stabilize. Repeat the measurements above. RESISTOR R1 IS USED ONLY IF MANUFACTURER CALLS FOR BIAS RESISTOR BETWEEN GATE AND CATHODE. RESISTOR R2 CAN HAVE ANY SMALL VALUE WHICH, WHEN MULTIPLIED BY MAXIMUM ALLOWABLE LEAKAGE CURRENT, WILL PROVIDE A CONVENIENT READING OF VOLTAGE VL. Figure 5.21. Test Setup for SCR Forward Blocking Voltage and Leakage Current Measurements ADDITIONAL UNITS MAY BE CONNECTED IN PARALLEL R1 GATE ANODE − REGULATED POWER SUPPLY + 1/16 A R2VL CATHODE
- 83. http://onsemi.com 83 To measure the turn−on impedance for the specified current load, the on impedance can be measured as an SCR forward voltage drop. The point in time of measurement shall be half the output pulse width. For a 1 μs output pulse, the measurement procedure would be: Connect the oscilloscope probe, Channel B, to Point D shown in Figure 5.22. Use the oscilloscope controls Time/CM and Multiplier to a setting of 0.5 μs per centimeter or faster. With the Amplitude Control set to view 100 volts per centimeter (to prevent amplifier overloading) measure the amplitude of the voltage drop, VF, across the SCR 0.5 μs after the PFN voltage waveform has dropped to half amplitude. It may be necessary to check ground reference several times during this test to provide the needed accuracy of measurement. Figure 5.22. Suggested Test Circuit for SCR “On” Measurements VBO 2 HP 212A B t = AS SPECIFIED VBOE = VBO C 100 k 0 V IC = AS SPECIFIED t = AS SPECIFIED D WHERE ILOAD = AS SPECIFIED zO = R 100 A 1:1 51 Von 1 2 R + VBO 2 : 1 LOAD HOLDING CURRENT The SCR holding current can be measured with or without a gate turn−off current, according to the position of switch S2. The ON Semiconductor Trigger Pulse Generator is a transistor circuit capable of generating a 1.5 μs turn−on pulse followed by a variable−duration turn−off pulse. Measurements should be made at the maximum expected temperature of operation. Resistor R1 should be chosen to allow an initial magnitude of current flow at the device pulse current rating. To measure holding current, connect the SCRs under test as illustrated in Figure 5.23. Place SCRs in oven and stabilize at maximum expected operating temperature. View the waveform across R1 by connecting the oscillo- scope probe (Tektronix 2465) Channel A to Point A, and Channel B to Point B. Place the Mode Selector switch in the Added Algebraically position. Place the Polarity swich of Channel B in the Inverted position. Adjust both Volts/CM switches to the same scale factor, making sure that each Variable knob is in its Calibrated position. Adjust pulse generator for a positive pulse, 1 μs wide, and 1,000 pps pulse repetition frequency. Adjust power supply voltage to rated VBO. Adjust input pulse amplitude until unit fully triggers. Measure amplitude of voltage drop across R1, V(A − B), and calculate holding current in mA from the equation mA + V(A * B) R1 ) VBO 100 k W Any unit which turns on but does not turn off has a holding current of less than VBO V 100 kW The approximate voltage setting to view the amplitude of the holding current will be 10 or 20 volts per centimeter. The approximate sweep speed will be 2 to 5 μs per centimeter. These settings will, of course, vary, depending upon the holding current of the unit under test. SCR recovery time is greatly dependent upon the circuit in which the device is used. However, any test of SCR recovery time should suffice to compare devices of various manufacturers, as long as the test procedure is standardized. Further evaluation of the selected devices could be made in an actual modulator circuit tester wherein techniques conducive to SCR turn−off are used. The circuit setup shown in Figures 5.24 and 5.25 can be employed for such tests. A slight load to PFN mismatch is called for to generate an inverse voltage across the SCR at the termination of the output pulse. An SCR gate turn−off pulse is used. The recharge component is a charging choke, providing optimized conditions of reapplied voltage to the PFN (and across the SCR). Adequate heat sinking of the SCR should be provided.
- 84. http://onsemi.com 84 Figure 5.23. Test Setup for Measuring Holding Current ON SEMI− CONDUCTOR TRIGGER PULSE GEN HARRISON 800 A P.S. NOTE: ADDITIONAL UNITS MAY BE TESTED BY SWITCHING THE ANODE AND GATE CONNECTIONS TO SIMILARLY MOUNTED SCRs. SHORT LEAD LENGTHS ARE DESIRABLE. +12 IH VOLTAGE LEVEL FROM WHICH TO CALCULATE HOLDING CURRENT TIME AT WHICH TO MEASURE IN 2 W 100k − + B R1 S1A REGULATED POWER SUPPLY C1 7500 fd. CATHODE GATE ANODE S2 S1B R2 HP212 PULSE GEN. A −12 R3 R4 51 Ω Figure 5.24. Modulator Circuit for SCR Tests HARRISON 800 A HOLD OFF DIODE CATH- ODE ON SEMI− CONDUCTOR TRIGGER PULSE GEN CANODE R GATE HP212A PULSE GEN zO q RLOAD PFN B REGULATED POWER SUPPLY A CHARGING CHOKE RLOAD +12 −12
- 85. http://onsemi.com 85 Figure 5.25. Radar Modulator, Resonant Line Type TRIGGER IN SIMPLIFIED SCHEMATIC SCR LOAD HOLD OFF DIODE CHARGING CHOKE PFN BLOCK DIAGRAM; DISC SWITCH ENERGY STORE POWER SUPPLY CHARGE IMPEDANCE LOAD PULSE TRANSFORMER Es PARALLEL CONNECTED SCRs When an application requires current capability in excess of a single economical SCR, it can be worthwhile to consider paralleling two or more devices. To help determine if two or more SCRs in parallel are more cost effective than one high current SCR, some of the advantages and disadvantages are listed for parallel devices. Advantages 1. Less expensive to purchase 2. Less expensive to mount 3. Less expensive to replace, in case of failure 4. Ease of mounting 5. Ease of isolation from sink Disadvantages 1. Increased SCR count 2. Selected or matched devices 3. Increased component count 4. Greater R D effort There are several factors to keep in mind in paralleling and many are pertinent for single SCR operations as well. GATE DRIVE The required gate current (IGT) amplitude can vary greatly and can depend upon SCR type and load being switched. As a general rule for parallel SCRs, IGT should be at least two or three times the IGT(MAX) specification on the data sheet and ideally close to, but never exceeding, the maximum specified gate power dissipation or peak current. Adequate gate current is necessary for rapid turn−on of all the parallel SCRs and to ensure simultaneous turn−on without excessive current crowding across any of the individual die. The rise time of the gate drive pulse should be fast, ideally p 100 ns. Each gate should be driven from a good current source and through its own resistor, even if transformer drive is used. Gate pulse width requirements vary but should be of sufficient width to ensure simultaneous turn−on and last well beyond the turn−on delay of the slowest device, as well as beyond the time required for latching of all devices. Ideally, gate current would flow for the entire conduction period to ensure latching under all operating conditions. With low voltage switching, which includes conduction angles near 180° and near zero degrees, the gate drive requirements can be more critical and special emphasis may be required of gate pulse amplitude and width. PARAMETER MATCHING For reliable current sharing with parallel SCRs, there are certain device parameters that should be matched or held within close tolerances. The degree of matching required varies and can be affected by type of load (resistive, inductive, incandescent lamp or phase con- trolled loads) being switched.
- 86. http://onsemi.com 86 The most common device parameters that can effect current sharing are: 1. td — turn−on delay time 2. tr — turn−on rise time of anode current 3. VA(MIN) — minimum anode voltage at which device will turn on 4. Static on−state voltage and current 5. IL — Latching current The four parameters shown in Table 5.6 were measured with a curve tracer and are: IL, latching current; VTM, on−state voltage; IGT and VGT, minimum gate current and voltage for turn on. Of the four parameters, IL and VTM can greatly affect current sharing. The latching current of each SCR is important at turn−on to ensure each device turns on and will stay on for the entire conduction period. On−state voltage determines how well the SCRs share current when cathode ballasting is not used. Table 5.5 gives turn−on delay time (td) and turn−on rise time (tr) of the anode−cathode voltage and the minimum forward anode voltage for turn−on. These parameters were measured in the circuits shown in Figures 5.28 and 5.29. One SCR at a time was used in the circuit shown in Figure 5.28. Turn−on delay on twenty−five SCRs was measured (only ten are shown in Table 5.5) and they could be from one or more production lots. The variation in td was slight and ranged from 35 to 44 ns but could vary considerably on other production lots and this possible variation in td would have to be considered in a parallel application. Waveforms for minimum forward anode voltage for turn−on are shown in Figure 5.26. The trailing edge of the gate current pulse is phase delayed (R3) so that the SCR is not turned on. The width of the gate current pulse is now increased (R5) until the SCR turns on and the forward anode voltage switches to the on−state at about 0.73 V. This is the minimum voltage at which this SCR will turn on with the circuit conditions shown in Figure 5.28. For dynamic turn−on current sharing, td, tr and VA(MIN) are very important. As an example, with a high wattage incandescent lamp load, it is very important that the inrush current of the cold filament be equally shared by the parallel SCRs. The minimum anode voltage at which a device turns on is also very important. If one of the parallel devices turns on before the other devices and its on−state voltage is lower than the required minimum anode voltage for turn−on of the unfired devices, they therefore cannot turn on. This would overload the device which turned on, probably causing failure from over−current and excessive junction temperature. Table 5.5. MCR12D Turn−On Delay, Rise Time and Minimum Forward Anode Voltage For Turn−On Device Turn−On Delay and Rise Time Off−State Voltage = 8 V Peak RL = 10 Ohms, IA ^ 6.5 A Peak IG = 100 mA (PW = 100 μs) Conduction Angle 90 Degrees Minimum Anode Voltage For Turn−On Off−State Voltage = 4 V Peak RL = 0.5 Ohm IA = 5A IG = 100 mA td(ns) tr(μs) (Volts) 1 2 3 4 5 6 7 8 9 10 35 38 45 44 44 43 38 38 38 37 0.80 0.95 1 1 0.90 0.85 1.30 1.25 1 0.82 0.70 0.81 0.75 0.75 0.75 0.75 0.75 0.70 0.75 0.70 Figure 5.26. Minimum Anode Voltage For Turn−On Off−State Voltage = 4 V Peak, RL = 0.5 Ohm, IA ≈ 5 A, IG = 75 mA OFF−STATE ANODE−CATHODE VOLTAGE 0.2 V/Div ON−STATE 00 100 μs/Div 1 mA/Div IG = 50 Turn−off time — tq is important in higher frequency applications which require the SCR to recover from the forward conduction period and be able to block the next cycle of forward voltage. Thus, tq matching for high frequency operation can be as important as td, tr and VA(MIN) matching for equal turn−on current sharing. Due to the variable in tq measurement, no further attempt will be made here to discuss this parameter and the reader is referred to Application Note AN914. The need for on−state matching of current and voltage is important, especially in unforced current sharing circuits.
- 87. http://onsemi.com 87 UNFORCED CURRENT SHARING When operating parallel SCRs without forced current sharing, such as without cathode ballasting using resistors or inductors, it is very important that the device parameters be closely matched. This includes td, tr, minimum forward anode voltage for turn−on and on−state voltage matching. The degree of matching determines the success of the circuit. In circuits without ballasting, it is especially important that physical layout, mounting of devices and resistance paths be identical for good current sharing, even with on−state matched devices. Figure 5.27 shows how anode current can vary on devices closely matched for on−state voltage (1, 3 and 4) and a mismatched device (2). Without resistance ballast- ing, the matched devices share peak current within one ampere and device 2 is passing only nine amps, seven amps lower than device 1. Table 5.6 shows the degree of match or mismatch of VTM of the four SCRs. With unforced current sharing (RK = 0), there was a greater tendency for one device (1) to turn−on, preventing the others from turning on when low anode switching voltage (p 10 V rms) was tried. Table 5.5 shows that the minimum anode voltage for turn−on is from 7 to 14% lower for device 1 than on 2, 3 and 4. Also, device 1 turn−on delay is 35 ns versus 38, 45 and 44 ns for devices 2, 3 and 4. The tendency for device 1 to turn on, preventing the other three from turning on, is most probably due to its lower minimum anode voltage requirement and shorter turn on delay. The remedy would be closer matching of the minimum anode voltage for turn−on and driving the gates hard (but less than the gate power specifications) and increasing the width of the gate current pulse. FORCED CURRENT SHARING Cathode ballast elements can be used to help ensure good static on−state current sharing. Either inductors or resistors can be used and each has advantages and disadvantages. This section discuses resistive ballasting, but it should be kept in mind that the inductor method is usually better suited for the higher current levels. Although they are more expensive and difficult to design, there is less power loss with inductor ballasting as well as other benefits. The degree of peak current sharing is shown in Figure 5.27 for four parallel MCR12D SCRs using cathode resistor ballasting with an inductive anode load. With devices 1, 3 and 4, on−state voltage is matched within 10 mV at an anode current of 15 A (See Table 5.6) and are within 1A of each other in Figure 5.27, with cathode resistance (RK) equal to zero. As RK increases, the current sharing becomes even closer. The unmatched device 2, with a VTM of 1.41 V (Table 5.6), is not carrying its share of current (Figure 5.29) with RK equal zero. As RK increases, device 2 takes a greater share of the total current and with RK around 0.25 ohm, the four SCRs are sharing peak current quite well. The value of RK depends on how close the on−state voltage is matched on the SCRs and the degree of current sharing desired, as well as the permissible power dissipation in RK. Figure 5.27. Effects Of Cathode Resistor On Anode Current Sharing #2 #3 IG = 400 mA PW = 400 μs OFF−STATE VOLTAGE = 26 V (rms) INDUCTIVE LOAD CONDUCTION ANGLE = 120° RK, CATHODE RESISTORS (MILLIOHMS) SCR #1 #4 7 17 15 13 50 11 2502001500 9 100 I,PEAKANODECURRENT(AMPS)A(pk) Table 5.6. MCR12D Parameters Measured On Curve Tracer, TC = 25°C Device # IL, Latching Current VD = 12 Vdc IG = 100 mA VTM, On−State Voltage IA = 15 A PW = 300 μs Minimum Gate Current Voltage for Turn−On VD = 12 Vdc, RL = 140 Ω IGT VGT 1 2 3 4 5 6 7 8 9 10 13 mA 27 28 23 23 23 18 19 19 16 1.25 V 1.41 1.26 1.26 1.28 1.26 1.25 1.25 1.25 1.25 5.6 mA 8.8 12 9.6 9.4 9.6 7.1 7 8.4 6.9 0.615 V 0.679 0.658 0.649 0.659 0.645 0.690 0.687 0.694 0.679 LINE SYNCHRONIZED DRIVE CIRCUIT Gate drive for phase control of the four parallel SCRs is accomplished with one complementary MOS hex gate, MC14572, and two bipolar transistors (Figure 5.28). This adjustable line−synchronized driver permits SCR conduc- tion from near zero to 180 degrees. A Schmitt trigger clocks a delay monostable multivibrator that is followed by a pulse−width monostable multivibrator.
- 88. http://onsemi.com 88 Line synchronization is achieved through the half− wave section of the secondary winding of the full−wave, center−tapped transformer (A). This winding also supplies power to the circuit through rectifiers D1 and D2. The full−wave signal is clipped by diode D5, referenced to a + 15 volt supply, so that the input limit of the CMOS chip is not exceeded. The waveform is then shaped by the Schmitt trigger, which is composed of inverters U1−a and U1−b. A fast switching output signal B results. The positive−going edge of this pulse is differentiated by the capacitive−resistive network of C1 and R2 and triggers the delay multivibrator that is composed of U1−c and U1−d. As a result, the normally high output is switched low. The trailing edge of this pulse (C) then triggers the following multivibrator, which is composed of NAND gate U1−e and inverter U1−f. The positive going output pulse (waveform D) of this multivibrator, whose width is set by potentiometer R6, turns on transistors Q1 and Q2, which drives the gates of the four SCRs. Transistor Q2 supplies about 400 mA drive current to each gate through 100 ohm resistors and has a rise time of p100 ns. B D A A Figure 5.28. Line−Synchronized Gate Driver + 15 V τ2 0 15 V τ1 TRIAD F90X 1N914 120 V 60 Hz D3 HALF − WAVE D4 S1 FULL− WAVE 0 kΩ 22 kΩ1 kΩ1N914 D1 D2 1N914 D5 100 Ω, 1 W 250 μF 25 V 1N5352 5 V, 5 W + 15 V + 40 V 10 k Q2 MJE253 1 k TO GATES RESISTORS 0.005 TIP122 10 k 14 1315 U1−−e R5 100 kΩ 0.01 μF U1−f 8 11 16 12 0.01 μF 10 k0.001 4.7 kΩ R6 25 kΩ U1−a R1 220 kΩ C1 0.01 μF 150 kΩ 4 R4 + 15 V R2 100 kΩ SCHMITT TRIGGER R3 1 mΩ 2 D C B 30 μs t τ2 200 μs PULSE−WIDTH MULTIVIBRATOR 1 3 0.7 ms t τ1 t 6 rms DELAY MULTIVIBRATOR 7 9 U1−d 100.01 μF 5 U1−b 5.30(b) 5.30(a) U1t 0 15 V 0 15 V 0 15 V 6 PARALLEL SCR CIRCUIT The four SCRs are MCR12Ds, housed in the TO−220 package, rated at 12 A rms, 50 V and are shown schematically in Figure 5.29. Due to line power limita- tions, it was decided to use a voltage step down transformer and not try working directly from the 120 V line. Also, line isolation was desirable in an experiment of this type. The step down transformer ratings were 120 V rms primary, 26 V rms secondary, rated at 100 A, and was used with a variable transformer for anode voltage adjustment. The inductive load consisted of four filter chokes in parallel (Stancor #C−2688 with each rated at 10 mH, 12.5 Adc and 0.11 ohm). For good current sharing with parallel SCRs, symmetry in layout and mounting is of primary importance. The four SCRs were mounted on a natural finish aluminum heat sink and torqued to specification which is 8 inch pounds. Cathode leads and wiring were identical, and when used, the cathode resistors RK were matched within 1%. An RC snubber network (R7 and C2) was connected across the anodes−cathodes to slow down the rate−of−rise of the off−state voltage, preventing unwanted turn−on.
- 89. http://onsemi.com 89 Figure 5.29. Parallel Thyristors LOAD: FOUR STANCOR FILTER CHOKES (#C−2688) IN PARALLEL EACH RATED AT: 10 mH @ 12.5 Adc AND 0.11 OHMS ALL ANODES COMMON TO HEAT SINK Q3−Q6, MCR12D 120 V rms 60 Hz 26 V rms 1 k 100 100 100 Q6 100 R7 100 SNUBBER 0.25 C2 Q4 RK Q3 Q5 1 k 1 k 1 k RK RK RK CHARACTERIZING RFI SUPPRESSION IN THYRISTOR CIRCUITS In order to understand the measures for suppression of EMI, characteristics of the interference must be explored first. To have interference at all, we must have a transmitter, or creator of interference, and a receiver, a device affected by the interference. Neither the transmitter nor the receiver need be related in any way to those circuits commonly referred to as radio−frequency circuits. Common transmit- ters are opening and closing of a switch or relay contacts, electric motors with commutators, all forms of electric arcs, and electronic circuits with rapidly changing voltages and currents. Receivers are generally electronic circuits, both low and high impedance which are sensitive to pulse or high frequency energy. Often the very circuits creating the interference are sensitive to similar interference from other circuits nearby or on the same power line. EMI can generally be separated into two categories — radiated and conducted. Radiated interference travels by way of electro−magnetic waves just as desirable RF energy does. Conducted interference travels on power, communications, or control wires. Although this separa- tion and nomenclature might seem to indicate two neat little packages, independently controllable, such is not the case. The two are very often interdependent such that in some cases control of one form may completely eliminate the other. In any case, both interference forms must be considered when interference elimination steps are taken. Phase control circuits using thyristors (SCRs, triacs, etc.) for controlling motor speed or resistive lighting and heating loads are particularly offensive in creating interference. They can completely obliterate most stations on any AM radio nearby and will play havoc with another control on the same power line. These controls are generally connected in one of the two ways shown in the block diagrams of Figure 5.30. A common example of the connection of 5.30(a) is the wall mounted light dimmer controlling a ceiling mounted lamp. A motorized appliance with a built−in control such as a food mixer is an example of the connection shown in 5.30(b). Figure 5.30(a) may be re−drawn as shown in Figure 5.31, illustrating the complete circuit for RF energy. The switch in the control box represents the thyristor, shown in its blocking state. In phase control operation, this switch is open at the beginning of each half cycle of the power line alternations. After a delay determined by the remainder of the control circuitry, the switch is closed and remains that way until the instantaneous current drops to zero. This switch is the source from which the RF energy flows down the power lines and through the various capacitors to ground. LINE CONTROL LOAD LOAD CONTROL LINE (b). Control and Load in the Same Enclosure (a). Separately Mounted Control Figure 5.30. Block Diagram of Control Connections
- 90. http://onsemi.com 90 If the load is passive, such as a lamp or a motor which does not generate interference, it may be considered as an impedance bypassed with the wire−to−wire capacitance of its leads. If it is another RF energy source, however, such as a motor with a commutator, it must be treated separately to reduce interference from that source. The power supply may be considered as dc since the interference pulse is extremely short (10 μs) compared to the period of the power line frequency (16 ms for 60 Hz). The inductance associated with the power source comes from two separate phenomena. First is the leakage impedance of the supply transformer, and second is the self−inductance of the wires between the power line transformer and the load. One of the most difficult parameters to pin down in the system is the effect of grounding. Most industrial and commercial wiring and many homes use a grounded conduit system which provides excellent shielding of radiated energy emanating from the wiring. However, a large number of homes are being wired with two to three wire insulated cable without conduit. In three−wire systems, one wire is grounded independently of the power system even though one of the power lines is already grounded. The capacitances to ground shown in Figure 5.31 will be greatly affected by the type of grounding used. Of course, in any home appliance, filtering must be provided suitable for all three different systems. Before the switch in the control is closed, the system is in a steady−state condition with the upper line of the power line at the system voltage and the bottom line and the load at ground potential. When the switch is closed, the upper line potential instantaneously falls due to the line and source inductance, then it rises back to its original value as the line inductance is charged. While the upper line is rising, the line from the control to the load also rises in potential. The effect of both of these lines increasing in potential together causes an electro− static field change which radiates energy. In addition, any other loads connected across the power lines at point A, for example, would be affected by a temporary loss of voltage created by the closing of the switch and by the line and source inductance. This is a form of conducted interference. A second form of radiated interference is inductive coupling in which the power line and ground form a one−turn primary of an air core transformer. In this mode, an unbalanced transient current flows down the power lines with the difference current flowing to ground through the various capacitive paths available. The secondary is the radio antenna or the circuit being affected. This type of interference is a problem only when the receiver is within about one wavelength of the transmitter at the offending frequency. Radiated interference from the control circuit proper is of little consequence due to several factors. The lead lengths in general are so short compared to the wave- lengths in question that they make extremely poor antenna. In addition, most of these control circuits are mounted in metal enclosures which provide shielding for radiated energy generated within the control circuitry. A steel box will absorb radiated energy at 150 kHz such that any signal inside the box is reduced 12.9 dB per mil of thickness of the box. In other words, a 1/16 inch thick steel box will attenuate radiated interference by over 800 dB! A similar aluminum box will attenuate 1 dB per mil or 62.5 dB total. Thus, even in an aluminum box, the control circuitry will radiate very little energy. Both forms of radiated interference which are a problem are a result of conducted interference on the power lines which is in turn caused by a rapid rise in current. Thus, if this current rise is slowed, all forms of interference will be reduced. RFI SOLUTIONS Since the switch in Figure 5.31, when it closes, provides a very low impedance path, a capacitor in parallel with it will show little benefit in slowing down the rise of current. The capacitor will be charged to a voltage determined by the circuit constants and the phase angle of the line voltage just before the switch closes. When the switch closes, the capacitor will discharge quickly, its current limited only by its own resistance and the resistance of the switch. However, a series inductor will slow down the current rise in the load and thus reduce the voltage transient on all lines. A capacitor connected as shown in Figure 5.32 will also help slow down the current rise since the inductor will now limit the current out of the capacitor. Thus, the capacitor voltage will drop slowly and correspondingly the load voltage will increase slowly. Although this circuit will be effective in many cases, the filter is unbalanced, providing an RF current path through the capacitances to ground. It has, therefore, been found advantageous to divide the inductor into two parts and to put half in each line to the control. Figure 5.33 illustrates this circuit showing the polarity marks of two coils which are wound on the same core. A capacitor at point A will help reduce interference further. This circuit is particularly effective when used with the connection of Figure 5.30(b) where the load is not always on the grounded side of the power line. In this case, the two halves of the inductor would be located in the power line leads, between the controlled circuit and the power source.
- 91. http://onsemi.com 91 Figure 5.31. RF Circuit for Figure 5.30(a) LOAD CONTROL A Figure 5.32. One Possible EMI Reduction Circuit LOAD 8A CONTROL 10 A TRIAC 100 μH0.1 μF Where the control circuit is sensitive to fast rising line transients, a capacitor at point B will do much to eliminate this problem. The capacitor must charge through the impedance of the inductor, thus limiting the rate of voltage change (dv/dt) applied to the thyristor while it is in the blocking state. DESIGN CRITERIA Design equations for the split inductor have been developed based on parameters which should be known before attempting a design. The most difficult to determine is tr, the minimum allowable current rise time which will not cause objectionable interference. The value of this parameter must be determined empirically in each situation if complete interference reduction is needed. ON Semiconductor has conducted extensive tests using an AM radio as a receiver and a 600 Watt thyristor lamp dimmer as a transmitter. A rate of about 0.35 Amp per μs seems to be effective in eliminating objectionable interference as well as materially reducing false triggering of the thyristor due to line transients. The value of tr may be calculated by dividing the peak current anticipated by the allowable rate of current rise. Ferrite core inductors have proved to be the most practical physical configuration. Most ferrites are effec- tive; those with highest permeability and saturation flux density are preferred. Those specifically designed as high frequency types are not necessarily desirable. Laminated iron cores may also be used; however, they require a capacitor at point A in Figure 5.33 to be at all effective. At these switching speeds, the iron requires considerable current in the windings before any flux change can take place. We have found currents rising to half their peak value in less than one μs before the inductance begins to slow down the rise. The capacitor supplies this current for the short period without dropping in voltage, thus eliminating the pulse on the power line. Once a core material has been selected, wire size is the next decision in the design problems. Due to the small number of turns involved (generally a single layer) smaller sizes than normally used in transformers may be chosen safely. Generally, 500 to 800 circular mills per ampere is acceptable, depending on the enclosure of the filter and the maximum ambient temperature expected. An idea of the size of the core needed may be determined from the equation: (1) AcAw + 26 Awire Erms tr BMAX where: Ac = the effective cross−sectional area of the core in in2 Aw = available core window area in in2 Awire = wire cross section in circular mils BMAX = core saturation flux density in gauss tr = allowable current rise time in seconds Erms = line voltage (A factor of 3 has been included in this equation to allow for winding space factor.) Once a tentative core selection has been made, the number of turns required may be found from the equation: (2) N + 11 Erms tr 106 BMAXAc where: N = the total number of turns on the core The next step is to check how well the required number of turns will fit onto the core. If the fit is satisfactory, the core design is complete; if not, some trade−offs will have to be made.
- 92. http://onsemi.com 92 Figure 5.33. Split Inductor Circuit LOAD CONTROL 10 A TRIAC A120 Vac 240 μH 240 μH5A B In most cases, the inductor as designed at this point will have far too much inductance. It will support the entire peak line voltage for the time selected as tr and will then saturate quickly, giving much too fast a current rise. The required inductance should be calculated from the allowable rise time and load resistance, making the rise time equal to two time constants. Thus: (3) 2L R + tr or L + R tr 2 Paper or other insulating material should be inserted between the core halves to obtain the required inductance by the equation: (4) Ig + 3.19 N2 Ac 10*8 L * Ic m where: Ig = total length of air gap in inches μ = effective ac permeability of the core material at the power line frequency Ic = effective magnetic path length of the core in inches Ac = effective cross sectional area of the core in square inches L = inductance in henries DESIGN EXAMPLE Consider a 600 watt, 120 Volt lamp dimmer using an ON Semiconductor 2N6348A triac. Line current is 600 120 = 5 amperes. #16 wire will provide about 516 circular mils per ampere. For core material, type 3C5 of Ferroxcube Corporation of America, Saugerties, New York, has a high Bmax and μ. The company specifies BMAX = 3800 gauss and μ = 1900 for material. As was previously mentioned, a current rise rate of about 0.35 ampere per μs has been found to be acceptable for interference problems with ac−dc radios in most wiring situations. With 5 amperes rms, 7 amperes peak, tr + 7 0.35 + 20 ms Then the equation (1): AcAw + 26 2580 120 20 10*6 3800 gauss + 0.044 Core part number 1F30 of the same company in a U−1 configuration has an AcAw product of 0.0386, which should be close enough. N + 10.93 120 20 10*6 106 3800 0.137 + 42 turns Two coils of 21 turns each should be wound on either one or two legs and be connected as shown in Figure 5.33. The required inductance of the coil is found from equation (3). L + R tr 2 + Erated Irated tr 2 +120 5 20 2 10–6+ 240 10–6 L + 240 mH To obtain this inductance, the air gap should be Ig+3.19 422 0.137 10–8 240 10–6 – 3.33 1900 + 0.0321–0.00175 Ig+0.03035 Thus, 15 mils of insulating material in each leg will provide the necessary inductance. If a problem still exists with false triggering of the thyristor due to conducted interference, a capacitor at point B in Figure 5.33 will probably remedy the situation.
- 93. http://onsemi.com 93 SECTION 6 APPLICATIONS Edited and Updated Because they are reliable solid state switches, thyristors have many applications, especially as controls. One of the most common uses for thyristors is to control ac loads such as electric motors. This can be done either by controlling the part of each ac cycle when the circuit conducts current (phase control) or by controlling the number of cycles per time period when current is con- ducted (cycle control). In addition, thyristors can serve as the basis of relaxation oscillators for timers and other applications. Most of the devices covered in this book have control applications. PHASE CONTROL WITH THYRISTORS The most common method of electronic ac power control is called phase control. Figure 6.1 illustrates this concept. During the first portion of each half-cycle of the ac sine wave, an electronic switch is opened to prevent the current flow. At some specific phase angle, α, this switch is closed to allow the full line voltage to be applied to the load for the remainder of that half-cycle. Varying α will control the portion of the total sine wave that is applied to the load (shaded area), and thereby regulate the power flow to the load. The simplest circuit for accomplishing phase control is shown in Figure 6.2. The electronic switch in this case is a triac (Q) which can be turned on by a small current pulse to its gate. The TRIAC turns off automatically when the current through it passes through zero. In the circuit shown, capacitor CT is charged during each half-cycle by the current flowing through resistor RT and the load. The fact that the load is in series with RT during this portion of the cycle is of little consequence since the resistance of RT is many times greater than that of the load. When the voltage across CT reaches the breakdown voltage of the DIAC bilateral trigger (D), the energy stored in capacitor CT is released. This energy produces a current pulse in the DIAC, which flows through the gate of the TRIAC and turns it on. Since both the DIAC and the TRIAC are bidirectional devices, the values of RT and CT will determine the phase angle at which the TRIAC will be triggered in both the positive and negative half-cycles of the ac sine wave. PORTION OF WAVEFORM APPLIED TO LOAD α Figure 6.1. Phase Control of AC Waveform α AC LINE VOLTAGE CT LOAD RT D Q Figure 6.2. Simplest Circuit for Phase Control α = 150° APPLIED SINE WAVE α = 90° α = 90° α = 150° Figure 6.3. Waveforms of Capacitor Voltage at Two Phase Angles
- 94. http://onsemi.com 94 The waveform of the voltage across the capacitor for two typical control conditions (α = 90° and 150°) is shown in Figure 6.3. If a silicon controlled rectifier is used in this circuit in place of the TRIAC, only one half-cycle of the waveform will be controlled. The other half-cycle will be blocked, resulting in a pulsing dc output whose average value can be varied by adjusting RT. CONTROL OF INDUCTION MOTORS Shaded-pole motors driving low-starting-torque loads such as fans and blowers may readily be controlled using any of the previously described full-wave circuits. One needs only to substitute the winding of the shaded-pole motor for the load resistor shown in the circuit diagrams. Constant-torque loads or high-starting-torque loads are difficult, if not impossible, to control using the voltage controls described here. Figure 6.4 shows the effect of varying voltage on the speed-torque curve of a typical shaded-pole motor. A typical fan-load curve and a constant-torque-load curve have been superimposed upon this graph. It is not difficult to see that the torque developed by the motor is equal to the load torque at two different points on the constant-torque-load curve, giving two points of equilibrium and thus an ambiguity to the speed control. The equilibrium point at the lower speed is a condition of high motor current because of low counter EMF and would result in burnout of the motor winding if the motor were left in this condition for any length of time. By contrast, the fan speed-torque curve crosses each of the motor speed- torque curve crosses each of the motor speed-torque curves at only one point, therefore causing no ambiguities. In addition, the low-speed point is one of low voltage well within the motor winding’s current-carrying capabilities. Permanent-split-capacitor motors can also be controlled by any of these circuits, but more effective control is achieved if the motor is connected as shown in Figure 6.5. Here only the main winding is controlled and the capacitor winding is continuously connected to the entire ac line voltage. This connection maintains the phase shift between the windings, which is lost if the capacitor phase is also controlled. Figure 6.6(a) shows the effect of voltage on the speed-torque characteristics of this motor and a superim- posed fan-load curve. 3/4 VR TORQUE 1/4 VR CONSTANT TORQUE LOAD 1/2 VR VR = FULL RATED VOLTAGE TYPICAL FAN LOAD VR SPEED Figure 6.4. Characteristics of Shaded-Pole Motors at Several Voltages CONTROL CIRCUIT AC LINE VOLTAGE MOT Figure 6.5. Connection Diagram for Permanent-Split-Capacitor Motors Not all induction motors of either the shaded-pole or the permanent-split-capacitor types can be controlled effectively using these techniques, even with the proper loads. Motors designed for the highest efficiencies and, therefore, low slip also have a very low starting torque and may, under certain conditions, have a speed-torque characteristic that could be crossed twice by a specific fan-load speed-torque characteristic. Figure 6.6(b) shows motor torque-speed characteristic curves upon which has been superimposed the curve of a fan with high starting torque. It is therefore desirable to use a motor whose squirrel-cage rotor is designed for medium-to-high imped- ance levels and, therefore, has a high starting torque. The slight loss in efficiency of such a motor at full rated speed and load is a small price to pay for the advantage of speed control prevents the TRIAC from turning on due to line transients and inductive switching transients.
- 95. http://onsemi.com 95 (a). High-Starting-Torque Motor (b). High-Efficiency Motor VR = FULL RATED VOLTAGE TORQUE TYPICAL FAN LOAD 1/4 VR 1/2 VR 3/4 VR VR SPEED TORQUE 1/4 VR 1/2 VR 3/4 VR VR HIGH-STARTING- TORQUE FAN LOAD SPEED Figure 6.6. Speed−Torque Curves for a Permanent−Split−Capacitor Motors at Various Applied Voltages A unique circuit for use with capacitor-start motors in explosive or highly corrosive atmospheres, in which the arcing or the corrosion of switch contacts is severe and undesirable, is shown in Figure 6.7. Resistor R1 is connected in series with the main running winding and is of such a resistance that the voltage drop under normal full-load conditions is approximately 0.2 V peak. Since starting currents on these motors are quite high, this peak voltage drop will exceed 1 V during starting conditions, triggering the TRIAC, which will cause current to flow in the capacitor winding. When full speed is reached, the current through the main winding will decrease to about 0.2 V, which is insufficient to trigger the TRIAC — thus the capacitor winding will no longer be energized. Resistor R2 and capacitor C2 form a dv/dt suppression network; this prevents the TRIAC from turning on due to line transients and inductive switching transients. CONTROL OF UNIVERSAL MOTORS Any of the half-wave or full-wave controls described previously can be used to control universal motors. Non- feedback, manual controls, such as those shown in Figure 6.2, are simple and inexpensive, but they provide very little torque at low speeds. A comparison of typical speed-torque curves using a control of this type with those of feedback control is shown in Figure 6.8. These motors have some unique characteristics which allow their speed to be controlled very easily and efficiently with a feedback circuit such as that shown in Figure 6.9. This circuit provides phase-controlled half- wave power to the motor; that is, on the negative half-cycle, the SCR blocks current flow in the negative direction causing the motor to be driven by a pulsating direct current whose amplitude is dependent on the phase control of the SCR. Figure 6.7. Circuit Diagram for Capacitor-Start Motor AC LINE VOLTAGE R1 MOT C1 R2 C2 Figure 6.8. Comparison of Feedback Control with Non-Feedback Control 1/2 VR 3/4 VR VR TORQUE (B) FEEDBACK CONTROL 1/4 VR 1/2 VR 3/4 VR VR VR = FULL RATED VOLTAGE TORQUE (A) NON-FEEDBACK CONTROL SPEED SPEED
- 96. http://onsemi.com 96 The theory of operation of this control circuit is not at all difficult to understand. Assuming that the motor has been running, the voltage at point A in the circuit diagram must be larger than the forward drop of Diode D1, the gate-to-cathode drop of the SCR, and the EMF generated by the residual MMF in the motor, to get sufficient current flow to trigger the SCR. The waveform at point A (VA) for one positive half-cycle is shown in 6.9(b), along with the voltage levels of the SCR gate (VSCR), the diode drop (VD), and the motor-generated EMF (VM). The phase angle (α) at which the SCR would trigger is shown by the vertical dotted line. Should the motor for any reason speed up so that the generated motor voltage would increase, the trigger point would move upward and to the right along the curve so that the SCR would trigger later in the half-cycle and thus provide less power to the motor, causing it to slow down again. Similarly, if the motor speed decreased, the trigger point would move to the left and down the curve, causing the TRIAC to trigger earlier in the half-cycle providing more power to the motor, thereby speeding it up. Resistors R1, R2, and R3, along with diode D2 and capacitor C1 form the ramp-generator section of the circuit. Capacitor C1 is changed by the voltage divider R1, R2, and R3 during the positive half-cycle. Diode D2 prevents negative current flow during the negative half-cycle, therefore C1 discharges through only R2 and R3 during that half-cycle. Adjustment of R3 controls the amount by which C1 discharges during the negative half-cycle. Because the resistance of R1 is very much larger than the ac impedance of capacitor C1, the voltage waveform on C1 approaches that of a perfect cosine wave with a dc component. As potentiometer R2 is varied, both the dc and the ac voltages are divided, giving a family of curves as shown in 6.9(c). Figure 6.9. (a). Speed-Control Scheme for Universal Motors AC LINE VOLTAGE C1 R2 D2 R3 R1 A C2 MOT D1 The gain of the system, that is, the ratio of the change of effective SCR output voltage to the change in generator EMF, is considerably greater at low speed settings than it is at high speed settings. This high gain coupled with a motor with a very low residual EMF will cause a condition sometimes known as cycle skipping. In this mode of operation, the motor speed is controlled by skipping entire cycles or groups of cycles, then triggering one or two cycles early in the period to compensate for the loss in speed. Loading the motor would eliminate this condition; however, the undesirable sound and vibration of the motor necessitate that this condition be eliminated. This can be done in two ways. The first method is used if the motor design is fixed and cannot be changed. In this case, the impedance level of the voltage divider R1, R2 and R3 can be lowered so that C1 will charge more rapidly, thus increasing the slope of the ramp and lowering the system gain. The second method, which will provide an overall benefit in improved circuit performance, involves a redesign of the motor so that the residual EMF becomes greater. In general, this means using a lower grade of magnetic steel for the laminations. As a matter of fact, some people have found that ordinary cold-rolled steel used as rotor laminations makes a motor ideally suited for this type of electronic control. Another common problem encountered with this circuit is that of thermal runaway. With the speed control set at low or medium speed, at high ambient temperatures the speed may increase uncontrollably to its maximum value. This phenomenon is caused by an excessive impedance in the voltage-divider string for the SCR being triggered. If the voltage-divider current is too low, current will flow into the gate of the SCR without turning it on, causing the waveform at point A to be as shown in 6.9(d). The flat portion of the waveform in the early part of the half-cycle is caused by the SCR gate current loading the voltage divider before the SCR is triggered. After the SCR is triggered, diode D1 is back-biased and a load is no longer on the voltage divider so that it jumps up to its unloaded voltage. As the ambient temperature increases, the SCR becomes more sensitive, thereby requiring less gate current to trigger, and is triggered earlier in the half-cycle.This early triggering causes increased current in the SCR, thereby heating the junction still further and increasing still further the sensitivity of the SCR until maximum speed has been reached. The solutions to this problem are the use of the most sensitive SCR practical and a voltage divider network of sufficiently low impedance. As a rough rule of thumb, the average current through the voltage divider during the positive half-cycle should be approximately three times the current necessary to trigger the lowest-sensitivity (highest gate current) SCR being used.
- 97. http://onsemi.com 97 (b). Waveform for One Positive Half-Cycle of Circuit (c). Voltage Waveform at Point “A” for Three Settings of Potentiometer R2 (d). Point “A” Voltage with Excessive Resistance R1 α2 α α3α1 VM VA R2 (R2)″ (R2)′ VD PHASE ANGLE VM VSCR VA VA PHASE ANGLE UNLOADED WAVEFORM ACTUAL WAVEFORM TRIGGER POINT In addition to the type of steel used in the motor laminations, consideration should also be given to the design of motors used in this half-wave speed control. Since the maximum rms voltage available to the motor under half-wave conditions is 85 V, the motor should be designed for use at that voltage to obtain maximum speed. However, U.L. requirements state that semiconductor devices used in appliance control systems must be able to be short-circuited without causing danger. Many designers have found it advantageous, therefore, to use 115 V motors with this system and provide a switch to apply full-wave voltage to the motor for high-speed operation. Figure 6.10 shows the proper connection for this switch. If one were to simply short-circuit the SCR for full-speed operation, a problem could arise. If the motor were operating at full speed with the switch closed, and the switch were then opened during the negative half-cycle, the current flowing in the inductive field of the motor could then break down the SCR in the negative direction and destroy the control. With the circuit as shown, the energy stored in the field of the motor is dissipated in the arc of the switch before the SCR is connected into the circuit. Figure 6.10. Switching Scheme for Full-Wave Operation CONTROL CIRCUIT MOT ACLINEVOLTAGE CONTROL OF PERMANENT-MAGNET MOTORS As a result of recent developments in ceramic perma- nent-magnet materials that can be easily molded into complex shapes at low cost, the permanent-magnet motor has become increasingly attractive as an appliance compo- nent. Electronic control of this type of motor can be easily achieved using techniques similar to those just described for the universal motor. Figure 6.11 is a circuit diagram of a control system that we have developed and tested successfully to control permanent-magnet motors presently being used in blenders. Potentiometer R3 and diode D1 form a dc charging path for capacitor C1; variable resistor R1 and resistor R2 form an ac charging path which creates the ramp voltage on the capacitor. Resistor R4 and diode D2 serve to isolate the motor control circuit from the ramp generator during the positive and negative half-cycles, respectively.
- 98. http://onsemi.com 98 Figure 6.11. Circuit Diagram for Controlling Permanent-Magnet Motors R3 D1 R4 D2 C1 R2 R1 MOT ACLINEVOLTAGE A small amount of cycle skipping can be experienced at low speeds using this control, but not enough to necessitate further development work. Since the voltage generated during off time is very high, the thermal runaway problem does not appear at all. Typical speed-torque curves for motors of this type are shown in Figure 6.12. Figure 6.12. Speed-Torque Characteristic of Permanent-Magnet Motors at Various Applied Voltages 3/4 VR 1/4 VR VR VR = FULL RATED VOLTAGE TORQUE 1/2 VR SPEED MOTOR SPEED CONTROL WITH FEEDBACK While many motor speed control circuits have used SCRs, the TRIAC has not been very popular in this application. At first glance, it would appear that the TRIAC would be perfect for speed control because of its bilateral characteristics. There are a couple of reasons why this is not true. The major difficulty is the TRIAC’s dv/dt charac- teristic. Another reason is the difficulty of obtaining a feed- back signal because of the TRIAC’s bilatera nature. While the TRIAC has its disadvantages, it does offer some advantages. In a SCR speed control either two SCRs must be used, or the line voltage must be full-wave rectified using relatively high current rectifiers, or the control must be limited to half-wave. The TRIAC elimi- nates all these difficulties. By using a TRIAC the part count, package size, and cost can be reduced. Figure 6.13 shows a TRIAC motor speed control circuit that derives its feedback from the load current and does not require separate connections to the motor field and armature windings. Therefore, this circuit can be conveniently built into an appliance or used as a separate control. The circuit operates as follows: When the TRIAC conducts, the normal line voltage, less the drop across the TRIAC and resistor R5, is applied to the motor. By delaying the firing of the TRIAC until a later portion of the cycle, the rms voltage applied to the motor is reduced and its speed is reduced proportionally. The use of feedback maintains torque at reduced speeds. Diodes D1 through D4 form a bridge which applies full-wave rectified voltage to the phase-control cir- cuit. Phase control of the TRIAC is obtained by the charging of capacitor C1 through resistors R2 and R3 from the voltage level established by zener diode D5. When C1 charges to the firing voltage of PUT Q1, the TRIAC triggers by transformer T1. C1 discharges through the emitter of Q1. While the TRIAC is conducting, the voltage drop between points A and B falls below the breakdown voltage of D5. Therefore, during the conduction period, the voltage on C1 is determined by the voltage drop from A to B and by resistors R1, R2, and R3. Since the voltage between A and B is a function of motor current due to resistor R5, C1 is charged during the conduction period to a value which is proportional to the motor current. The value of R5 is chosen so that C1 cannot charge to a high enough voltage to fire Q1 during the conduction period. However, the amount of charging required to fire Q1 has been decreased by an amount proportional to the motor current. Therefore, the firing angle at which Q1 will fire has been advanced in proportion to the motor current. As the motor is loaded and draws more current, the firing angle of Q1 is advanced even more, causing a proportionate increase in the rms voltage applied to the motor, and a consequent increase in its available torque. Since the firing voltage of Q1 depends on the voltage from base one to base two, it is necessary to support the base two voltage during the conduction portion of the cycle to prevent the feedback voltage from firing Q1. D6 and C2 perform this function. Because the motor is an inductive load, it is necessary to limit the commutation dv/dt for reliable circuit operation. R6 and C3 perform this function.
- 99. http://onsemi.com 99 Figure 6.13. Motor Speed Control with Feedback B MOTOR 115 VAC 60 Hz A IN4006(4) D4 D3 D1 D2 18 k 2 W R1 D5 ZENER 9.1 V R3 50 k R2 27 k C1 0.1 μF Q1 2N6027 D6 1N4001 T1 DALE PT-50 ORIGIN R4 16 k R7 27 k C2 10 μF 10 V Q2 MAC9D R6 100 Ω C3 0.1 μF R5 SEE TABLE 6.5 3 2 Motor Rating (Amperes) 0.32 0.67 1 OHMS 15 10 5 Watts R5 NOMINAL R5 VALUES IM = Max. Rated Motor Current (RMS) R5 + 2 IM Nominal values for R5 can be obtained from the table or they can be calculated from the equation given. Exact values for R5 depend somewhat on the motor characteris- tics. Therefore, it is suggested that R5 be an adjustable wirewound resistor which can be calibrated in terms of motor current, and the speed control can be adapted to many different motors. If the value of R5 is too high, feedback will be excessive and surging or loss of control will result. If the value is too low, a loss of torque will result. The maximum motor current flows through R5, and its wattage must be determined accordingly. This circuit has been operated successfully with 2 and 3 ampere 1/4-inch drills and has satisfactorily controlled motor speeds down to 1/3 or less of maximum speed with good torque characteristics. to the motor, and a consequent increase in its available torque. AN INTEGRATED CIRCUIT FEEDBACK CONTROL The TDA1185A TRIAC phase angle controller (Figure 6.14) generates controlled triac triggering pulses and applies positive current feedback to stabilize the speed of universal motors. A ramp voltage synchronized to the ac line half cycle and compared to an external set voltage determines the firing angle. Negative gate pulses drive the triac in quadrants two and three. Because the speed of a universal motor decreases as torque increases, the TDA1185A lengthens the triac conduction angle in proportion to the motor current, sensed through resistor R9. The TDA1185A is the best solution for low cost applications tolerating 5% motor speed variation. Open loop systems do not have a tachometer or negative feedback and consequently cannot provide perfect speed compensation. CONSTANT SPEED MOTOR CONTROL USING TACHOMETER FEEDBACK Tachometer feedback sensing rotor speed provides excellent performance with electric motors. The principal advantages to be gained from tachometer feedback are the ability to apply feedback control to shaded-pole motors, and better brush life in universal motors used in feedback circuits. This latter advantage results from the use of full-wave rather than half-wave control, reducing the peak currents for similar power levels.
- 100. dφ dt http://onsemi.com 100 Figure 6.14. TDA 1185-A Universal Motor Speed Control — Internal Block Diagram/Pin Assignment − + + + 100 μF C8 8 1.0 μF R12 SET 12 120 k MAIN LINE VOLTAGE COMPENSATION RCOMPENSATION +C13 SOFT START PROGRAMMING PIN 13 FULL-WAVE R10 10 C4 4 SAWTOOTH GENERATOR FULL-WAVE TRIGGER PULSE GENERATOR MONITORING POSITIVE FEEDBACK R9 0.05 100 MAC8D 14 9 2 M CURRENT SYNCHRO 820 k6 1 7 18 k 2.0 W −VCC 820 k VOLTAGE SYNCHRO 1N4005 THE TACHOMETER The heart of this system is, of course, the speed-sensing tachometer itself. Economy being one of the principal goals of the design, it was decided to use a simple magnetic tachometer incorporating the existing motor fan as an integral part of the magnetic circuit. The generator consists of a coil wound on a permanent magnet which is placed so that the moving fan blades provide a magnetic path of varying reluctance as they move past the poles of the magnet. Several possible configurations of the magnetic system are shown in Figure 6.15. Flux in a magnetic circuit can be found from the “magnetic Ohm’s law”: φ + MMF R , where φ = the flux, MMF = the magnetomotive force (strength of the magnet), and R = the reluctance of the magnetic path. Assuming the MMF of the permanent magnet to be constant, it is readily apparent that variations in reluctance will directly affect the flux. The steel fan blades provide a low-reluctance path for the flux once it crosses the air gap between them and the poles of the magnet. If the magnet used has a horseshoe or U shape, and is placed so that adjacent fan blades are directly opposite each pole in one position of the motor armature, the magnetic path will be of relatively low reluctance; then as the motor turns the reluctance will increase until one fan blade is precisely centered between the poles of the magnet. As rotation continues, the reluctance will then alternately increase and decrease as the fan blades pass the poles of the magnet. If a bar- or L-shaped magnet is used so that one pole is close to the shaft or the frame of the motor and the other is near the fan blades, the magnetic path reluctance will vary as each blade passes the magnet pole near the fan. In either case the varying reluctance causes variations in the circuit flux and a voltage is generated in the coil wound around the magnet. The voltage is given by the equation: e + –N dφ dt x10–8, where e = the coil voltage in volts, N = the number of turns in the coil, and = the rate of change of flux in lines per second. In a practical case, a typical small horseshoe magnet wound with 1000 turns of wire generated a voltage of about 0.5 volts/1000 rpm when mounted in a blender. Since both generated voltage and frequency are directly proportional to the motor speed, either parameter can be used as the feedback signal. However, circuits using voltage sensing are less complex and therefore less expensive. Only that system will be discussed here.
- 101. http://onsemi.com 101 Figure 6.15. (a). Locations for Magnetic Sensing Tachometer Generator Using a Horseshoe Magnet (b). Locations for Magnetic Sensing Tachometer Generator Using an “L” or Bar Magnet POSSIBLE MAGNET SHAPES AND LOCATIONS FERROUS MOTOR HOUSING FAN MOTOR FAN MAGNET COIL WIRES MOTOR ARMATURE MAGNET COIL WIRES SIDE VIEW MOTOR FAN TOP VIEW MOTOR ARMATURE MOTOR ARMATURE THE ELECTRONICS In one basic circuit, which is shown in Figure 6.16, the generator output is rectified by rectifier D1, then filtered and applied between the positive supply voltage and the base of the detector transistor Q1. This provides a negative voltage which reduces the base-voltage on Q1 when the speed increases. The emitter of the detector transistor is connected to a voltage divider which is adjusted to the desired tachometer output voltage. In normal operation, if the tachometer voltage is less than desired, the detector transistor, Q1, is turned on by current through R1 into its base. Q1 then turns on Q2 which causes the timing capacitor for programmable unijunction transistor Q3 to charge quickly. As the tachometer output approaches the voltage desired, the base-emitter voltage of Q1 is reduced to the point at which Q1 is almost cut off. Thereby, the collector current of Q2, which charges the PUT timing capacitor, reduces, causing it to charge slowly and trigger the thyristor later in the half cycle. In this manner, the average power to the motor is reduced until just enough power to maintain the desired motor speed is allowed to flow. Input circuit variations are used when the tachometer output voltage is too low to give a usable signal with a silicon rectifier. In the variation shown in Figure 6.16(b), the tachometer is connected between a voltage divider and the base of the amplifier transistor. The voltage divider is set so that with no tachometer output the transistor is just barely in conduction. As the tachometer output increases, QT is cut off on negative half cycles and conducts on positive half cycles. Resistors R9 and R10 provide a fixed gain for this amplifier stage, providing the hFE of QT is much greater than the ratio of R9 to R10. Thus the output of the amplifier is a fixed multiple of the positive values of the tachometer waveform. The rectifier diode D1 prevents C1 from discharging through R9 on negative half cycles of the tachometer. The remainder of the filter and control circuitry is the same as the basic circuit. In the second variation, shown in 6.16(c), R8 has been replaced by a semiconductor diode, D2. Since the voltage and temperature characteristics more closely match those of the transistor base-to-emitter junction, this circuit is easier to design and needs no initial adjustments as does the circuit in 6.16(b). The remainder of this circuit is identical to that of Figure 6.15. In the second basic circuit, which is shown in Figure 6.17, the rectified and filtered tachometer voltage is added to the output voltage of the voltage divider formed by R1 and R2. If the sum of the two voltages is less than V1 − VBE Q1 (where VBE Q1 is the base-emitter voltage of Q1), Q1 will conduct a current proportional to V1 − VBE Q1, charging capacitor C. If the sum of the two voltages is greater than V1 − VBE Q1, Q1 will be cut off and no current will flow into the capacitor. The operation of the remainder of the circuit is the same as the previously described circuits.
- 102. http://onsemi.com 102 Figure 6.16. (a). Basic Tachometer Control Circuit (b). Variation Used when the Tachometer Output is Too Low for Adequate Control (c). Variation Providing Better Temperature Tracking and Easier Initial Adjustment DETECTOR AND POWER CONTROL CIRCUIT INPUT CIRCUIT TACHOMETER GENERATOR D1 C1 R1 R2 R5 R3 Q1 R4 C2 R6 Q2 +V2 120 V AC LOAD (PULSING dc) (PURE dc) R9 R1C1 D1QT R10 TACH R8 R7 D2 TACH R7 R10 D1 QT R9 C1 R1 +V 1 PHASE CONTROL WITH TRIGGER DEVICES Phase control using thyristors is one of the most common means of controlling the flow of power to electric motors, lamps, and heaters. With an ac voltage applied to the circuit, the gated thyristor (SCR, TRIAC, etc.) remains in its off-state for the first portion of each half cycle of the power line, then, at a time (phase angle) determined by the control circuit, the thyristor switches on for the remainder of the half cycle. By controlling the phase angle at which the thyristor is switched on, the relative power in the load may be controlled. PHASE CONTROL WITH PROGRAMMABLE UNIJUNCTION TRANSISTORS PUTs provide a simple, convenient means for obtaining the thyristor trigger pulse synchronized to the ac line at a controlled phase angle. Figure 6.17. Another Basic Tachometer Circuit +V1 (PURE dc) +V2 PULSATING dc LOAD 120 VAC Q1 C R1 TACH R2 These circuits are all based on the simple relaxation oscillator circuit of Figure 6.18. RT and CT in the figure form the timing network which determines the time between the application of voltage to the circuit (repre- sented by the closing of S1) and the initiation of the pulse. In the case of the circuit shown, with Vs pure dc, the oscillator is free running, RT and CT determine the frequency of oscillation. The peak of the output pulse voltage is clipped by the forward conduction voltage of the gate to cathode diode in the thyristor. The principal waveforms associated with the circuit are shown in Figure 6.18(b). Operation of the circuit may best be described by referring to the capacitor voltage waveform. Following power application, CT charges at the rate determined by its own capacitance and the value of RT until its voltage reaches the peak point voltage of the PUT. Then the PUT switches into conduction, discharging CT through RGK and the gate of the thyristor. With Vs pure dc, the cycle then repeats immediately; however, in many cases Vs is derived from the anode voltage of the thyristor so that the timing cycle cannot start again until the thyristor is blocking forward voltage and once again provides Vs.
- 103. http://onsemi.com 103 Figure 6.18. Basic Relaxation Oscillator Circuit (a) and Waveforms (b) 0 IBBRB1 VCG RGK Von Voff RB1 RB2 K G A CT RT LOAD VS V V CAPACITOR VOLTAGE CT V OUTPUTVOLTAGE RB1 (a) (b) It is often necessary to synchronize the timing of the output pulses to the power line voltage zero-crossing points. One simple method of accomplishing synchroniza- tion is shown in Figure 6.19. Zener diode D1 clips the rectified supply voltage resulting in a Vs as shown in 6.19(b). Since VS, and therefore the peak point voltage of the PUT drops to zero each time the line voltage crosses zero, CT discharges at the end of every half cycle and begins each half cycle in the discharged state. Thus, even if the PUT has not triggered during one half cycle, the capacitor begins the next half cycle discharged. Conse- quently, the values of RT and CT directly control the phase angle at which the pulse occurs on each half cycle. The zener diode also provides voltage stabilization for the timing circuit giving the same pulse phase angle regardless of normal line voltage fluctuations. APPLICATIONS The most elementary application of the PUT trigger circuit, shown in Figure 6.20, is a half-wave control circuit. In this circuit, RD is selected to limit the current through D1 so that the diode dissipation capability is not exceeded. Dividing the allowable diode dissipation by one-half the zener voltage will give the allowable positive current in the diode since it is conducting in the voltage regulating mode only during positive half cycles. Once the positive half- cycle current is found, the resistor value may be calculated by subtracting 0.7 times the zener voltage from the rms line voltage and dividing the result by the positive current: RD + Erms * 0.7 Vz Ipositive The power rating of RD must be calculated on the basis of full wave conduction as D1 is conducting on the negative half cycle acting as a shunt rectifier as well as providing Vs on the positive half cycle. LINE D1 CT R3 R2 VS R1RT RD RECTIFIED SINE WAVEVS (a) Figure 6.19. Control Circuit (a) with Zener Clipped, Rectified Voltage (b) (b) AC LINE D1 1N5250 A CT 0.1 μF 2N6027 R3 100 k R2 10 k MCR8D 100 k RT 6.8 k 2 W R1 5.1 k RD600 W LOAD Figure 6.20. Half Wave Control Circuit with Typical Values for a 600 Watt Resistive Load
- 104. http://onsemi.com 104 The thyristor is acting both as a power control device and a rectifier, providing variable power to the load during the positive half cycle and no power to the load during the negative half cycle. The circuit is designed to be a two terminal control which can be inserted in place of a switch. If full wave power is desired as the upper extreme of this control, a switch can be added which will short circuit the SCR when RT is turned to its maximum power position. The switch may be placed in parallel with the SCR if the load is resistive; however, if the load is inductive, the load must be transferred from the SCR to the direct line as shown in Figure 6.21. Figure 6.21. Half Wave Controls with Switching for Full Wave Operation (a). Resistive Load (b). Inductive Load CONTROL CIRCUIT CONTROL CIRCUIT Figure 6.22. A Simple Full Wave Trigger Circuit with Typical Values for a 900 Watt Resistive Load 900 W LOAD LINE MDA920A4 1N5250 A 6.8 k 2 W RD RT D1 2N6027 100 k R1 5.1 k 10 k R2 CT 0.1 μF DALE PT50 (OR EQUIVALENT) R3 100 k MAC12D Full wave control may be realized by the addition of a bridge rectifier, a pulse transformer, and by changing the thyristor from an SCR to a TRIAC, shown in Figure 6.22. Occasionally a circuit is required which will provide constant output voltage regardless of line voltage changes. Adding potentiometer P1, as shown in Figure 6.23, to the circuits of Figures 6.20 and 6.22, will provide an approxi- mate solution to this problem. The potentiometer is adjusted to provide reasonably constant output over the desired range of line voltage. As the line voltage increases, so does the voltage on the wiper of P1 increasing VS and thus the peak point voltage of the PUT. The increased peak point voltage results in CT charging to a higher voltage and thus taking more time to trigger. The additional delay reduces the thyristor conduction angle and maintains the average voltage at a reasonably constant value. FEEDBACK CIRCUITS The circuits described so far have been manual control circuits; i.e., the power output is controlled by a potentiometer turned by hand. Simple feedback circuits may be constructed by replacing RT with heat or light-dependent sensing resistors; however, these circuits have no means of adjusting the operating levels. The addition of a transistor to the circuits of Figures 6.20 and 6.22 allows complete control. Figure 6.23. Circuit for Line Voltage Compensation RECTIFIED LINE (FULL OR HALF WAVE) CT 0.1 μF D1 1N5250A 6.8 k RD 500 P1 RT 100 100 k 2N6027 RG1 RGK RG2 5.1 k 10 k TO THYRISTOR GATE-CATHODE Figure 6.24. Feedback Control Circuit Rs* *Rs SHOULD BE SELECTED TO BE ABOUT 3 k TO 5 k OHMS AT THE DESIRED OUTPUT LEVEL RECTIFIED LINE (FULL OR HALF WAVE) RD 6.8 k Rc 100 k 1N5250A D1 Q1 CT 0.1 μF 2N6027 MPS6512 10 k RT(MIN) 10 k 100 5.1 k TO THYRISTOR GATE-CATHODE
- 105. http://onsemi.com 105 Figure 6.24 shows a feedback control using a sensing resistor for feedback. The sensing resistor may respond to any one of many stimuli such as heat, light, moisture, pressure, or magnetic field. Rs is the sensing resistor and Rc is the control resistor that establishes the desired operating point. Transistor Q1 is connected as an emitter follower such that an increase in the resistance of Rs decreases the voltage on the base of Q1, causing more current to flow. Current through Q1 charges CT, triggering the PUT at a delayed phase angle. As Rs becomes larger, more charging current flows, causing the capacitor voltage to increase more rapidly. This triggers the PUT with less phase delay, boosting power to the load. When Rs decreases, less power is applied to the load. Thus, this circuit is for a sensing resistor which decreases in response to too much power in the load. If the sensing resistor increases with load power, then Rs and Rc should be interchanged. If the quantity to be sensed can be fed back to the circuit in the form of an isolated, varying dc voltage such as the output of a tachometer, it may be inserted between the voltage divider and the base of Q1 with the proper polarity. In this case, the voltage divider would be a potentiometer to adjust the operating point. Such a circuit is shown in Figure 6.25. Figure 6.25. Voltage Feedback Circuit es 6.8 k R1 MPS6512 CT 100 10 k TO THYRISTOR GATE- CATHODE 5.1 k 2N6027 RT(MIN)10 k Rc 100 k1N5250A RECTIFIED LINE 0.1 μF In some cases, average load voltage is the desired feedback variable. In a half wave circuit this type of feedback usually requires the addition of a pulse transform- er, shown in Figure 6.26. The RC network, R1, R2, C1, averages load voltage so that it may be compared with the set point on Rs by Q1. Full wave operation of this type of circuit requires dc in the load as well as the control circuit. Figure 6.27 is one method of obtaining this full wave control. Each SCR conducts on alternate half-cycles and supplies pulsating dc to the load. The resistors (Rg) insure sharing of the gate current between the simultaneously driven SCRs. Each SCR is gated while blocking the line voltage every other half cycle. This momentarily increases reverse blocking leakage and power dissipation. However, the leakage power loss is negligible due to the low line voltage and duty cycle of the gate pulse. There are, of course, many more sophisticated circuits which can be derived from the basic circuits discussed here. If, for example, very close temperature control is desired, the circuit of Figure 6.24 might not have sufficient gain. To solve this problem a dc amplifier could be inserted between the voltage divider and the control transistor gate to provide as close a control as desired. Other modifica- tions to add multiple inputs, switched gains, ramp and pedestal control, etc., are all simple additions to add sophistication. Figure 6.26. Half Wave, Average Voltage Feedback DC LOAD 600 W R2 30 k C1 10 μF 2N6028 CT 0.1 μF T 1N5250A RC 1 k 2 k MPS6512 Q1 T DALE PT50 (OR EQUIVALENT) MCR218-4 6.8 kRD AC LINE R1 100 k 3.9k Figure 6.27. Full Wave, Average Voltage Feedback Control MCR218-4 (2) RG 10 AC LINE 1N4721 (2) 1N4003 (2) DALE PT50 (OR EQUIVALENT) D1 1N5250A T 10 μF C1 CT 0.1 μF 2N6028 DC LOAD R2 30 k R1 100 k MPS6512 Q1 2 k 6.8 k 2 WRD RG T 3.9k 10 CLOSED LOOP UNIVERSAL MOTOR SPEED CONTROL Figure 6.28 illustrates a typical tachometer stabilized closed feedback loop control using the TDA1285A inte- grated circuit. This circuit operates off the ac line and generates a phase angle varied trigger pulse to control the triac. It uses inductive or hall effect speed sensors, controls motor starting acceleration and current, and provides a 1 to 2% speed variation for temperature and load variations. CYCLE CONTROL WITH OPTICALLY ISOLATED TRIAC DRIVERS In addition to the phase control circuits, TRIAC drivers can also be used for ac power control by on-off or burst control, of a number of ac cycles. This form of power control allows logic circuits and microprocessors to easily control ac power with TRIAC drivers of both the zero- crossing and non zero-crossing varieties.
- 106. http://onsemi.com 106 NOTES: Frequency to Voltage converter —Max. motor speed 30,000 rpm —Tachogenerator 4 pairs of poles: max. frequency = —C11 = 680 pF. R4 adjusted to obtain VPin 4 = 12 V at max. speed: 68 kΩ —Power Supply with Vmains = 120 Vac, R1 = 4.7 kΩ. Perfect operation will occur down to 80 Vac. 30, 000 60 x 4 + 2 kHz TDA1285A 126 C5 10 NF C4 100 nF R4 1.0 MΩ 1.5 μF 220 nF 220 k 330 nF C14 47 nF + VCC 47 μF 0.1 μF 22 k 0.1 μF R3 2.2 k 220 nF1.0 μF C7 C11 R1 10 k 1N4005 820 k 820 k Inductive TACHOM 3 220 V 13 1291410 126711854 16 TDA1285A 47 k HALL- EFFECT SENSOR M Figure 6.28. (a). Motor Control Circuit (b). Circuit Modifications to Connect a Hall-Effect Sensor USING NON-ZERO CROSSING OPTICALLY ISOLATED TRIAC DRIVERS USING THE MOC3011 ON 240 VAC LINES The rated voltage of a MOC3011 is not sufficiently high for it to be used directly on 240 V line; however, the designer may stack two of them in series. When used this way, two resistors are required to equalize the voltage dropped across them as shown in Figure 6.29. REMOTE CONTROL OF AC VOLTAGE Local building codes frequently require all 115 V light switch wiring to be enclosed in conduit. By using a MOC3011, a TRIAC, and a low voltage source, it is possible to control a large lighting load from a long distance through low voltage signal wiring which is completely isolated from the ac line. Such wiring usually is not required to be put in conduit, so the cost savings in installing a lighting system in commercial or residential buildings can be considerable. An example is shown in Figure 6.29. Naturally, the load could also be a motor, fan, pool pump, etc. LOAD MOC3011 MOC3011 150 + 5 V l l 1 M 1 M 1 k 240 Vac 180 Figure 6.29. Two MOC3011 TRIAC Drivers in Series to Drive 240 V TRIAC
- 107. http://onsemi.com 107 λ NON-CONDUIT #22 WIRE 5 V 360 MOC3011 180 115 V 2N6342A Figure 6.30. Remote Control of AC Loads Through Low Voltage Non-Conduit Cable SOLID STATE RELAY Figure 6.30 shows a complete general purpose, solid state relay snubbed for inductive loads with input protec- tion. When the designer has more control of the input and output conditions, he can eliminate those components which are not needed for his particular application to make the circuit more cost effective. INTERFACING MICROPROCESSORS TO 115 VAC PERIPHERALS The output of a typical microcomputer input-output (I/O) port is a TTL-compatible terminal capable of driving one or two TTL loads. This is not quite enough to drive the MOC3011, nor can it be connected directly to an SCR or TRIAC, because computer common is not normally referenced to one side of the ac supply. Standard 7400 series gates can provide an input compatible with the output of an MC6821, MC6846 or similar peripheral interface adaptor and can directly drive the MOC3011. If the second input of a 2 input gate is tied to a simple timing circuit, it will also provide energization of the TRIAC only at the zero crossing of the ac line voltage as shown in Figure 6.32. This technique extends the life of incandes- cent lamps, reduces the surge current strains on the TRIAC, and reduces EMI generated by load switching. Of course, zero crossing can be generated within the microcomputer itself, but this requires considerable software overhead and usually just as much hardware to generate the zero-crossing timing signals. APPLICATIONS USING THE ZERO CROSSING TRIAC DRIVER For applications where EMI induced, non-zero crossing- load switching is a problem, the zero crossing TRIAC driver is the answer. This TRIAC driver can greatly simplify the suppression of EMI for only a nominal increased cost. Examples of several applications using the MOC3031, 41 follows. 115 V 2N6071B 10 k 0.1 μF 2.4 k180 47 MOC3011 2N3904 2 W 1N4002 150 λ Figure 6.31. Solid-State Relay
- 108. http://onsemi.com 108 Figure 6.32. Interfacing an M6800 Microcomputer System to 115 Vac Loads 115 V (RESISTIVE LOAD) +5 V 200 W 115 V (INDUCTIVE LOAD) 2N6071 2N6071B MOTOR 0.1 μF 2.4 k 180 180 ADDRESS DATA MC6800 OR MC6802 MPU MC6820 OR MC6821 OR MC6846 I/O 115 V 6.3 V 3 k 100 k 2N3904 1 k 5 V OPTIONAL ZERO-CROSSING CIRCUITRY 7400 +5 V 300 300 OPTO TRIAC DRIVERS MOC3011 MOC3011 MATRIX SWITCHING Matrix, or point-to-point switching, represents a method of controlling many loads using a minimum number of components. On the 115 V line, the MOC3031 is ideal for this application; refer to Figure 6.33. The large static dv/dt rating of the MOC3031 prevents unwanted loads from being triggered on. This might occur, in the case of non-zero crossing TRIAC drivers, when a TRIAC driver on a vertical line was subjected to a large voltage ramp due to a TRIAC on a horizontal line being switched on. Since non-zero crossing TRIAC drivers have lower static dv/dt ratings, this ramp would be sufficiently large to trigger the device on. R is determined as before: R(min) + Vin(pk) ITSM + 170 V 1.2 A + 150 ohms CONTROL BUS 150 Ω MOC 3031 LOAD LOAD LOAD 150 Ω MOC 3031 LOAD LOAD LOAD 150 Ω MOC 3031 115 V 150 Ω MOC 3031 LOAD 150 Ω MOC 3031 LOAD 150 Ω LOAD MOC 3031 Figure 6.33. Matrix Switching
- 109. http://onsemi.com 109 POWER RELAY (230 VAC COIL) 300 Ω MOC 3041 CONTROL 230 VAC LOAD LOAD LOAD LOAD Figure 6.34. Power Relay Control POWER RELAYS The use of high-power relays to control the application of ac power to various loads is a very widespread practice. Their low contact resistance causes very little power loss and many options in power control are possible due to their multipole-multithrow capability. The MOC3041 is well suited to the use of power relays on the 230 Vac line; refer to Figure 6.34. The large static dv/dt of this device makes a snubber network unnecessary, thus reducing component count and the amount of printed circuit board space required. A non-zero crossing TRAIC driver (MOC3021) could be used in this application, but its lower static dv/dt rating would necessitate a snubber network. MICROCOMPUTER INTERFACE The output of most microcomputer input/output (I/O) ports is a TTL signal capable of driving several TTL gates. This is insufficient to drive a zero-crossing TRIAC driver. In addition, it cannot be used to drive an SCR or TRIAC directly, because computer common is not usually refer- enced to one side of the ac supply. However, standard 7400 NAND gates can be used as buffers to accept the output of the I/O port and in turn, drive the MOC3031 and/or MOC3041; refer to Figure 6.35. The zero-crossing feature of these devices extends the life of incandescent lamps, reduces inrush currents and minimizes EMI generated by load switching. AC MOTORS The large static dv/dt rating of the zero-crossing TRIAC drivers make them ideal when controlling ac motors. Figure 6.36 shows a circuit for reversing a two phase motor using the MOC3041. The higher voltage MOC3041 is required, even on the 115 Vac line, due to the mutual and self-inductance of each of the motor windings, which may cause a voltage much higher than 115 Vac to appear across the winding which is not conducting current. DETERMINING LIMITING RESISTOR R FOR A HIGH-WATTAGE INCANDESCENT LAMP Many high-wattage incandescent lamps suffer shortened lifetimes when switched on at ac line voltages other than zero. This is due to a large inrush current destroying the filament. A simple solution to this problem is the use of the MOC3041 as shown in Figure 6.37. The MOC3041 may be controlled from a switch or some form of digital logic. 1 kΩ MC6820 OR MC6821 OR MC6846 I/O +5 V 7400 +5 V 300 300 MOC 3041 MOC 3031 230 V (INDUCTIVE LOAD) 115 V (RESISTIVE LOAD) 150 Ω 300 Ω 2N6073 MOTOR 2N6071 200 W +5 V MC68000 MPU DATA ADDRESS Figure 6.35. M68000 Microcomputer Interface
- 110. http://onsemi.com 110 OPTIONAL CURRENT LIMITING RESISTOR MOC 3041 300 C R MOTOR 300 MOC 3041 115 V Figure 6.36. Reversing Motor Circuit The minimum value of R is determined by the maximum surge current rating of the MOC3041 (ITSM): R(min) + Vin(pk) ITSM + Vin(pk) 1.2 A (10) On a 230 Vac Line: R(min) + 340 V 1.2 A + 283 ohms (11) In reality, this would be a 300 ohm resistor. AC POWER CONTROL WITH SOLID-STATE RELAYS The Solid-State Relay (SSR) as described below, is a relay function with: a. Four Terminals (Two Input, Two Output) b. DC or AC Input c. Optical Isolation Between Input and Output d. Thyristor (SCR or TRIAC) Output e. Zero Voltage Switching Output (Will Only Turn On Close to Zero Volts) f. AC Output (50 or 60 Hz) Figure 6.38 shows the general format and waveforms of the SSR. The input on/off signal is conditioned (perhaps only by a resistor) and fed to the Light-Emitting-Diode (LED) of an optoelectronic-coupler. This is ANDed with a go signal that is generated close to the zero-crossing of the line, typically p 10 Volts. Thus, the output is not gated on via the amplifier except at the zero-crossing of the line voltage. The SSR output is then re-gated on at the beginning of every half-cycle until the input on signal is removed. When this happens, the thyristor output stays on until the load current reaches zero, and then turns off. ADVANTAGES AND DISADVANTAGES OF SSRs The SSR has several advantages that make it an attractive choice over its progenitor, the Electromechanical Relay (EMR) although the SSR generally costs more than its electromechanical counterpart. These advantages are: 300 R LAMP 230 VSWITCH OR DIGITAL LOGIC MOC 3041 Figure 6.37. High-Wattage Lamp Control
- 111. http://onsemi.com 111 LINE LOAD POWER SWITCH AMPL AND GO/NO GO ZERO CROSS DETECTOR ON/OFF INPUT LED Figure 6.38. SSR Block Diagram NO GO LINE 0 GO ON OFF OUTPUT 1. No Moving Parts — the SSR is all solid-state. There are no bearing surfaces to wear, springs to fatigue, assemblies to pick up dust and rust. This leads to sev- eral other advantages. 2. No Contact Bounce — this in turn means no contact wear, arcing, or Electromagnetic Interference (EMI) associated with contact bounce. 3. Fast Operation — usually less than 10 μs. Fast turn-on time allows the SSR to be easily synchronized with line zero-crossing. This also minimizes EMI and can greatly increase the lifetime of tungsten lamps, of con- siderable value in applications such as traffic signals. 4. Shock and Vibration Resistance — the solid-state con- tact cannot be “shaken open” as easily as the EMR contact. 5. Absence of Audible Noise — this devolves from the lack of moving mechanical parts. 6. Output Contact Latching — the thyristor is a latching device, and turns off only at the load current zero- crossing, minimizing EMI. 7. High Sensitivity — the SSR can readily be designed to interface directly with TTL and CMOS logic, simplify- ing circuit design. 8. Very Low Coupling Capacitance Between Input and Output. This is a characteristic inherent in the optoelec- tronic-coupler used in the SSR, and can be useful in areas such as medical electronics where the reduction of stray leakage paths is important. This list of advantages is impressive, but of course, the designer has to consider the following disadvantages: 1. Voltage Transient Resistance — the ac line is not the clean sine wave obtainable from a signal generator. Superimposed on the line are voltage spikes from motors, solenoids, EMRs (ironical), lightning, etc. The solid-state components in the SSR have a finite voltage rating and must be protected from such spikes, either with RC networks (snubbing), zener diodes, MOVs or selenium voltage clippers. If not done, the thyristors will turn on for part of a half cycle, and at worst, they will be permanently damaged, and fail to block volt- age. For critical applications a safety margin on voltage of 2 to 1 or better should be sought. The voltage transient has at least two facets — the first is the sheer amplitude, already discussed. The second is its frequency, or rate-of-rise of voltage (dv/dt). All thyris- tors are sensitive to dv/dt to some extent, and the transient must be snubbed, or “soaked up,” to below this level with an RC network.(1) Typically this rating (“critical” or “static” dv/dt) is 50 to 100 V/μs at maximum tempera- ture. Again the failure mode is to let through, to a half- cycle of the line, though a high energy transient can cause permanent damage. Table 6.1 gives some starting points for snubbing circuit values. The component values required depend on the characteristics of the transient, which are usually difficult to quantify. Snubbing across the line as well as across the SSR will also help. Table 6.1. Typical Snubbing Values Load Current A rms Resistance Ω Capacitance μF 5 47 0.047 10 33 0.1 25 10 0.22 40 22 0.47 1. For a more thorough discussion of snubbers, see page 38.
- 112. http://onsemi.com 112 Q2 INPUT AND CONTROL CIRCUIT TRIAC POWER CIRCUIT LINE R12 TR11 C11 R13 LOAD R11 BR 11 + − R4 R6 SCR1 D2 R7 R5C2 Q1 R3 R2C1 OC1 − + INPUT D1 R1 Figure 6.39 (a). TRIAC SSR Circuit 2. Voltage Drop — The SSR output contact has some offset voltage — approximately 1 V, depending on cur- rent, causing dissipation. As the thyristor has an operat- ing temperature limit of +125°C, this heat must be removed, usually by conduction to air via a heat sink or the chassis. 3. Leakage Current — When an EMR is open, no current can flow. When an SSR is open however, it does not have as definite an off condition. There is always some current leakage through the output power switching thyristor, the control circuitry, and the snubbing net- work. The total of this leakage is usually 1 to 10 mA rms — three or four orders of magnitude less than the on-state current rating. 4. Multiple Poles — are costly to obtain in SSRs, and three phase applications may be difficult to implement. 5. Nuclear Radiation — SSRs will be damaged by nuclear radiation. TRIAC SSR CIRCUIT Many SSR circuits use a TRIAC as the output switching device. Figure 6.39(a) shows a typical TRIAC SSR circuit. The control circuit is used in the SCR relay as well, and is defined separately. The input circuit is TTL compatible. Output snubbing for inductive loads will be described later. A sensitive-gate SCR (SCR1) is used to gate the power TRIAC, and a transistor amplifier is used as an interface between the optoelectronic-coupler and SCR1. (A sensi- tive-gate SCR and a diode bridge are used in preference to a sensitive gate TRIAC because of the higher sensitivity of the SCR.) CONTROL CIRCUIT OPERATION The operation of the control circuit is straightforward. The AND function of Figure 6.38 is performed by the wired-NOR collector configuration of the small-signal transistors Q1 and Q2. Q1 clamps the gate of SCR1 if optoelectronic-coupler OC1 is off. Q2 clamps the gate if there is sufficient voltage at the junction of the potential divider R4,R5 to overcome the VBE of Q2. By judicious selection of R4 and R5, Q2 will clamp SCR1’s gate if more than approximately 5 Volts appear at the anode of SCR1; i.e., Q2 is the zero-crossing detector. Table 6.2. Control Circuit Parts List Line Voltage Part 120 V rms 240 V rms C1 C2 D1 D2 OC1 Q1 Q2 R1 R2 R3 R4 R5 R6 R7 SCR1 220 pF, 20%, 200 Vdc 0.022 μF, 20%, 50 Vdc 1N4001 1N4001 MOC1005 MPS5172 MPS5172 1 kΩ, 10%, 1 W 47 kΩ, 5%, 1/2 W 1 MΩ, 10%, 1/4 W 110 kΩ, 5%, 1/2 W 15 kΩ, 5%, 1/4 W 33 kΩ, 10%, 1/2 W 10 kΩ, 10%, 1/4 W 2N5064 100 pF, 20%, 400 Vdc 0.022 μF, 20%, 50 Vdc 1N4001 1N4001 MOC1005 MPS5172 MPS5172 1 kΩ, 10%, 1 W 100 kΩ, 5%, 1 W 1 MΩ, 10%, 1/4 W 220 kΩ, 5%, 1/2 W 15 kΩ, 5%, 1/4 W 68 kΩ, 10%, 1 W 10 kΩ, 10%, 1/4 W 2N6240 If OC1 is on, Q1 is clamped off, and SCR1 can be turned on by current flowing down R6, only if Q2 is also off — which it is only at zero crossing.
- 113. http://onsemi.com 113 FIRING WINDOW FIRING WINDOW WITH C1 AND C2 (d) FIRING WINDOW WITHOUT C1 AND C2 (c) FIRING WINDOW ZERO VOLTAGE FIRING LEVEL (b) VSCR1 E Figure 6.39. Firing Windows LINEZERO CROSSING The capacitors are added to eliminate circuit race conditions and spurious firing, time ambiguities in operation. Figure 6.39(b) shows the full-wave rectified line that appears across the control circuit. The zero voltage firing level is shown in 6.39(b) and 6.39(c), expanded in time and voltage. A race condition exists on the up-slope of the second half-cycle in that SCR1 may be triggered via R6 before Q1 has enough base current via R2 to clamp SCR1’s gate. C1 provides current by virtue of the rate of change of the supply voltage, and Q1 is turned on firmly as the supply voltage starts to rise, eliminating any possibility of unwanted firing of the SSR; thus eliminating the race condition. This leaves the possibility of unwanted firing of the SSR on the down-slope of the first half cycle shown. C2 provides a phase shift to the zero voltage potential divider, and Q2 is held on through the real zero-cross- ing. The resultant window is shown in 6.39(d). CONTROL CIRCUIT COMPONENTS The parts list for the control circuit at two line voltages is shown in Table 6.2. R1 limits the current in the input LED of OC1. The input circuit will function over the range of 3 to 33 Vdc. D1 provides reverse voltage protection for the input of OC1.
- 114. http://onsemi.com 114 D2 allows the gate of SCR1 to be reverse biased, providing better noise immunity and dv/dt performance. R7 eliminates pickup on SCR1’s gate through the zero-crossing interval. SCR1 is a sensitive gate SCR; the 2N5064 is a TO-92 device, the 2N6240 is a Case 77 device. Alternatives to the simple series resistor (R1) input circuit will be described later. POWER CIRCUIT COMPONENTS The parts list for the TRIAC power circuit in Figure 6.39(a) is shown in Table 6.3 for several rms current ratings, and two line voltages. The metal TRIACs are in the half-inch pressfit package in the isolated stud configuration; the plastic TRIACs are in the TO-220 Thermowatt package. R12 is chosen by calculating the peak control circuit off-state leakage current and ensuring that the voltage drop across R12 is less than the VGT(MIN) of the TRIAC. C11 must be an ac rated capacitor, and with R13 provides some snubbing for the TRIAC. The values shown for this network are intended more for inductive load commutating dv/dt snubbing than for voltage transient suppression. Consult the individual data sheets for the dissipation, temperature, and surge current limits of the TRIACs. Table 6.3. TRIAC Power Circuit Parts List Voltage 120 V rms 240 V rms rms Current Amperes 8 12 25 40 8 12 25 40 BR11 IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) IN4004(4) C11, μF (10%, line voltage ac rated) 0.047 0.047 0.1 0.1 0.047 0.047 0.1 0.1 R11 (10%, 1 W) 39 39 39 39 39 39 39 39 R12 (10%, 1/2 W) 18 18 18 18 18 18 18 18 R13 (10%, 1/2 W) 620 620 330 330 620 620 330 330 TR11 Plastic 2N6344 2N6344A — — 2N6344 2N6344A — — TRIACs AND INDUCTIVE LOADS The TRIAC is a single device which to some extent is the equivalent of two SCRs inverse parallel connected; cer- tainly this is so for resistive loads. Inductive loads however, can cause problems for TRIACs, especially at turn-off. A TRIAC turns off every line half-cycle when the line current goes through zero. With a resistive load, this coincides with the line voltage also going through zero. The TRIAC must regain blocking-state before there are more than 1 or 2 Volts of the reverse polarity across it — at 120 V rms, 60 Hz line this is approximately 30 μs. The TRIAC has not completely regained its off-state character- istics, but does so as the line voltage increases at the 60 Hz rate. Figure 6.40 indicates what happens with an inductive or lagging load. The on signal is removed asynchronously and the TRIAC, a latching device, stays on until the next current zero. As the current is lagging the applied voltage, the line voltage at that instant appears across the TRIAC. It is this rate-of-rise of voltage, the commutating dv/dt, that must be limited in TRIAC circuits, usually to a few volts per microsecond. This is normally done by use of a snubber network RS and CS as shown in Figure 6.41. SCRs have less trouble as each device has a full half-cycle to turn off and, once off, can resist dv/dt to the critical value of 50 to 100 V/μs. CHOOSING THE SNUBBING COMPONENTS(1) There are no easy methods for selecting the values of RS and CS in Figure 6.41 required to limit commutating dv/dt. The circuit is a damped tuned circuit comprised by RS, CS, RL and LL, and to a minor extent the junction capacitance of the TRIAC. At turn-off this circuit receives a step impulse of line voltage which depends on the power factor of the load. Assuming the load is fixed, which is normally the case, the designer can vary RS and CS. CS can be increased to decrease the commutating dv/dt; RS can be increased to decrease the resonant over-ring of the tuned circuit — to increase damping. This can be done empiri- cally, beginning with the values for C11 and R13 given in Table 6.3, and aiming at close to critical damping and the data sheet value for commutating dv/dt. Reduced tempera- tures, voltages, and off-going di/dt (rate-of-change of current at turn-off) will give some safety margin. 1. For a more thorough discussion of snubbers, see page 38.
- 115. http://onsemi.com 115 TRIAC VOLTAGE 0 0 OFF ON dv/dtLINE VOLTAGE LINE AND TRIAC VOLTAGE LOAD CURRENT ON/OFF SIGNAL (LAGGING LOAD) Figure 6.40. Commutating dv/dt Table 6.4. SCR Power Circuit Parts List Voltage 120 V rms 240 V rms rms Current Amperes 5 11 22 49 5 11 22 49 C21 (10%, line voltage ac rated) SEE TEXT D21-24 1N4003 1N4003 1N4003 1N4003 1N4004 1N4004 1N4004 1N4004 R21 (10%, 1 W) 39 39 39 39 39 39 39 39 R22, 23 (10%, 1/2 W) 18 18 18 18 18 18 18 18 R24 SEE TEXT SCR21, 22 Plastic 2N6240 2N6397 2N6402 — 2N6240 2N6397 2N6403 — CS RS RL LOADLL Figure 6.41. TRIAC with Snubber Network SCR SSR CIRCUIT The inverse parallel connected Silicon Controlled Recti- fier (SCR) pair (shown in Figure 6.42) is less sensitive to commutating dv/dt. Other advantages are the improved thermal and surge characteristics of having two devices; the disadvantage is increased cost. The SCR power circuit can use the same control circuit as the TRIAC Circuit shown in Figure 6.39(a). In Figure 6.42, for positive load terminal and when the control circuit is gated on, current flows through the load, D21, R21, SCR1, D22, the gate of SCR21 and back to the line, thus turning on SCR21. Operation is similar for the other line polarity. R22 and R23 provide a path for the off-state leakage of the control circuit and are chosen so that the voltage dropped across them is less than the VGT(MIN) of the particular SCR. R24 and C21 provide snubbing and line transient suppres- sion, and may be chosen from Table 6.4 or from the C11, R13 rows of Table 6.3. The latter values will provide less transient protection but also less off-state current, with the capacitor being smaller. Other circuit values are shown in Table 6.46.
- 116. http://onsemi.com 116 CONTROL CIRCUIT (SEE FIGURE 6.39(a) AND TABLE 6.II) R21 LINE LOAD SCR22 SCR21 D21 D24 D22 D23 R22 R24 C21 + + − R23 − INPUT Figure 6.42. SCR SSR Circuit Consult the individual data sheets for packages and dissipation, temperature, and surge current limits. While the SCRs have much higher dv/dt commutation ability, with inductive loads, attention should be paid to maintaining the dv/dt below data sheet levels. ALTERNATE INPUT CIRCUITS CMOS COMPATIBLE The 1 kΩ resistor, R1, shown in Figure 6.39(a) and Table 6.2, provide an input that is compatible with the current that a TTL gate output can sink. The resistor R1 must be changed for CMOS compatibility, aiming at 2 mA in the LED for adequate performance to 100°C. At 2 mA do not use the CMOS output for any other function, as a LOGIC 0 or 1 may not be guaranteed. Assume a forward voltage drop of 1.1 V for the LED, and then make the Ohm’s Law calculation for the system dc supply voltage, thus defining a new value for R1. TTL/CMOS COMPATIBLE To be TTL compatible at 5 Volts and CMOS compatible over 3 to 15 Volts, a constant current circuit is required, such as the one in Figure 6.43. The current is set by the VBE of Q31 and the resistance of the R32, R33, and thermistor TH31 network, and is between 1 and 2 mA, higher at high temperatures to compensate for the reduced transmission efficiency of optoelectronic-couplers at higher tempera- ture. The circuit of Figure 6.43 gives an equivalent impedance of approximately 50 kΩ. The circuit performs adequately over 3 to 33 Vdc and −40 to +100°C. Note that though the SSR is protected against damage from improp- erly connected inputs, the external circuit is not, as D31 acts as a bypass for a wrongly connected input driver. R31 330 k TH31 WESTERN THERMISTOR CORP., CURVE 2, 650 Ω ± 10% @ 25°C P/N2C6500 OR EQUIVALENT 2N6427 R32 330 OC1 Q32 Q31 MPS5172 D31 1N4001 + INPUT TH31 R33 180 − Figure 6.43. TTL/CMOS Compatible Input
- 117. http://onsemi.com 117 AC LINE COMPATIBLE To use SSRs as logic switching elements is inefficient, considering the availability and versatility of logic families such as CMOS. When it is convenient to trigger from ac, a circuit such as shown in Figure 6.44 may be used. The capacitor C41 is required to provide current to the LED of OC1 through the zero-crossing time. An in-phase input voltage gives the worst case condition. The circuit gives 2 mA minimum LED current at 75% of nominal line voltage. INVERSE PARALLEL SCRs FOR POWER CONTROL TRIACs are very useful devices. They end up in solid state relays, lamp drivers, motor controls, sensing and detection circuits; just about any industrial full-wave application. But in high-frequency applications or those requiring high voltage or current, their role is limited by their present physical characteristics, and they become very expensive at current levels above 40 amperes rms. SCRs can be used in an inverse-parallel connection to bypass the limitations of a TRIAC. A simple scheme for doing this is shown in Figure 6.45. The control device can take any of many forms, shown is the reed relay (Fig- ure 6.45). TRIACs and Opto couplers can be inserted at point A−A to replace the reed relay. 2 μF 10% 50 V 2 kΩ, 10% 1/2 W 47 kΩ, 10%, 2 W 22 kΩ, 10%, 1 W 240 V 120 V R42 R41 OC1 INPUT AC C41 BR41 R41 Figure 6.44. AC Compatible Input Compared to a TRIAC, an inverse-parallel configuration has distinct advantages. Voltage and current capabilities are dependent solely on SCR characteristics with ratings today of over a thousand volts and several hundred amps. Because each SCR operates only on a half-wave basis, the system’s rms current rating is 2Ǹ times the SCR’s rms current rating (see Suggested SCR chart). The system has the same surge current rating as the SCRs do. Operation at 400 Hz is also no problem. While turn-off time and dv/dt limits control TRIAC operating speed, the recovery characteristics of an SCR need only be better than the appropriate half-wave period. ILa FLOATING LOAD RL ba 2V SCR1 OR ILb 2 IG1 1 IG R AA CONTROL DEVICE (CLOSED RESISTANCE) RC IG2GROUNDED LOAD RL WHERE IGP IS PEAK GATE CURRENT RATING OF SCR SCR2 R q 2 VǸ IGP * (RL ) RC) Figure 6.45. Use of Inverse Parallel SCRs
- 118. http://onsemi.com 118 With inductive loads you no longer need to worry about commutating dv/dt, either. SCRs only need to withstand static dv/dt, for which they are typically rated an order of magnitude greater than TRIACs are for commutating dv/dt. Better reliability can be achieved by replacing the reed relay with a low current TRIAC to drive the SCRs, although some of its limitations come with it. In the preferred circuit of Figure 6.46(b), the main requirements of the TRIAC are that it be able to block the peak system voltage and that it have a surge current rating compatible with the gate current require-ments of the SCRs. This is normally so small that a TO-92 cased device is adequate to drive the largest SCRs. In circuits like Figure 6.45, the control devices alternately pass the gate currents IG1 and IG2 during the “a” and “b” half cycles, respectively. ILa and ILb are the load currents during the corresponding half cycles. Each SCR then gets the other half cycle for recovery time. Heat sinking can also be done more efficiently, since power is being dissipated in two packages, rather than all in one. The load can either be floated or grounded. the SCRs are not of the shunted-gate variety, a gate-cathode resistance should be added to shunt the leakage current at higher temperatures. The diodes act as steering diodes so the gate-cathode junctions are not avalanched. The blocking capability of the diodes need only be as high as the VGT of the SCRs. A snubber can also be used if conditions dictate. A A GATE CONTROL A AAA GATE CONTROL GATE CONTROL (FLOATING) Figure 6.46. Control Devices (a). Reed Relay (b). Low-Current TRIAC (c). Optically Coupled TRIAC Driver This circuit offers several benefits. One is a considerable increase in gain. This permits driving the TRIAC with almost any other semiconductors such as linear ICs, photosensitive devices and logic, including MOS. If necessary, it can use an optically coupled TRIAC driver to isolate (up to 7500 V isolation) delicate logic circuits from the power circuit (see Figure 6.46(c)). Table 6.6. lists suggested components. Another benefit is being able to gate the TRIAC with a supply of either polarity. Probably the most important benefit of the TRIAC/SCR combination is its ability to handle variable-phase applications — nearly impossible for non solid-state control devices. Table 6.6. Driver TRIACs Line Voltage Gate Negative Or In Phase With Line Voltage Gate Positive Optically Coupled 120 220 MAC97A4 MAC97A6 MAC97A4 MAC97A6 MOC3030*, 3011 MOC3020, MOC3021 *Includes inhibit circuit for zero crossover firing. INTERFACING DIGITAL CIRCUITS TO THYRISTOR CONTROLLED AC LOADS Because they are bidirectional devices, TRIACs are the most common thyristor for controlling ac loads. A TRIAC can be triggered by either a positive or negative gate signal on either the positive or negative half-cycle of applied MT2 voltage, producing four quadrants of operation. However, the TRIAC’s trigger sensitivity varies with the quadrant, with quadrants II and III (gate signal negative and MT2 either positive or negative) being the most sensitive and quadrant IV (gate positive, MT2 negative) the least sensitive. For driving a TRIAC with IC logic, quadrants II and III are particularly desirable, not only because less gate trigger current is required, but also because IC power dissipation is reduced since the TRIAC can be triggered by an “active low” output from the IC.
- 119. http://onsemi.com 119 There are other advantages to operating in quadrants II and III. Since the rate of rise of on-state current of a TRIAC (di/dt) is a function of how hard the TRIAC’s gate is turned on, a given IC output in quadrants II and III will produce a greater di/dt capability than in the less sensitive quadrant IV. Moreover, harder gate turn-on could reduce di/dt failure. One additional advantage of quadrant II and III operation is that devices specified in all four quadrants are generally more expensive than devices specified in quad- rants I, II and III, due to the additional testing involved and the resulting lower yields. USING TRIACs Two important thyristor parameters are gate trigger current (IGT) and gate trigger voltage (VGT). IGT (Gate Trigger Current) is the amount of gate trigger current required to turn the device on. IGT has a negative temperature coefficient — that is, the trigger current required to turn the device on increases with decreasing temperature. If the TRIAC must operate over a wide temperature range, its IGT requirement could double at the low temperature extreme from that of its 25°C rating. It is good practice, if possible, to trigger the thyristor with three to ten times the IGT rating for the device. This increases its di/dt capability and ensures adequate gate trigger current at low temperatures. VGT (Gate Trigger Voltage) is the voltage the thyristor gate needs to ensure triggering the device on. This voltage is needed to overcome the input threshold voltage of the device. To prevent thyristor triggering, gate voltage should be kept to approximately 0.4 V or less. Like IGT, VGT increases with decreasing temperature. INDUCTIVE LOAD SWITCHING Switching of inductive loads, using TRIACs, may require special consideration in order to avoid false triggering. This false-trigger mechanism is illustrated in Figure 6.47 which shows an inductive circuit together with the accompanying waveforms. As shown, the TRIAC is triggered on, at t1, by the positive gate current (IGT). At that point, TRIAC current flows and the voltage across the TRIAC is quite low since the TRIAC resistance, during conduction, is very low. From point t1 to t2 the applied IGT keeps the TRIAC in a conductive condition, resulting in a continuous sinusoidal current flow that leads the applied voltage by 90° for this pure inductive load. At t2, IGT is turned off, but TRIAC current continues to flow until it reaches a value that is less than the sustaining current (IH), at point A. At that point, TRIAC current is cut off and TRIAC voltage is at a maximum. Some of that voltage is fed back to the gate via the internal capacitance (from MT2 to gate) of the TRIAC. TTL-TO-THYRISTOR INTERFACE The subject of interfacing requires a knowledge of the output characteristics of the driving stages as well as the input requirements of the load. This section describes the driving capabilities of some of the more popular TTL circuits and matches these to the input demands of thyristors under various practical operating conditions. CHANGE IN TRIAC VOLTAGE DURING TURN-OFF (dv) UNDESIRED TRIGGERING DUE TO FEEDBACK TRIAC VOLTAGE WITH SNUBBER NETWORK toff(dt) IGT A TRIAC CURRENT GATE MT1 60 Hz LINE VOLTAGE APPLIED TO TERMINALS A AND B MT2 LOAD B A t2t1 TRIAC VOLTAGE WITH SNUBBER NETWORK Figure 6.47. Inductive Load TRIAC Circuit and Equivalent Waveforms
- 120. http://onsemi.com 120 TTL CIRCUITS WITH TOTEM-POLE OUTPUTS (e.g. 5400 SERIES) The configuration of a typical totem-pole connected TTL output stage is illustrated in Figure 6.48(a). This stage is capable of “sourcing” current to a load, when the load is connected from Vout to ground, and of “sinking” current from the load when the latter is connected from Vout to VCC. If the load happens to be the input circuit of a TRIAC (gate to MT1), the TRIAC will be operating in quadrants I and IV (gate goes positive) when connected from Vout to ground, and of “sinking” II and III (gate goes negative) when connected from Vout to VCC. QUADRANT I-IV OPERATION Considering first the gate-positive condition, Figure 6.48(b), the operation of the circuit is as follows: When Vin to the TTL output stage is low (logical “zero”), transistors Q1 and Q3 of that stage are cut off, and Q2 is conducting. Therefore, Q2 sources current to the thyristor, and the thyristor would be triggered on during the Vin = 0 condition. When Vin goes high (logical “one”), transistors Q1 and Q3 are on and Q2 is off. In this condition depicted by the equivalent circuit transistor Q3 is turned on and its collector voltage is, essentially, VCE(sat). As a result, the TRIAC is clamped off by the low internal resistance of Q3. QUADRANT II-III OPERATION When the TRIAC is to be operated in the more sensitive quadrants II and III (negative-gate turn-on), the circuit in Figure 6.49(a) may be employed. With Q3 in saturation, as shown in the equivalent circuit of 6.49(b), its saturation voltage is quite small, leaving virtually the entire −VEE voltage available for thyristor turn-on. This could result in a TRIAC gate current that exceeds the current limit of Q3, requiring a current-limiting series resistor, (R(Iim)). When the Vout level goes high, Q3 is turned off and Q2 becomes conductive. Under those conditions, the TRIAC gate voltage is below VGT and the TRIAC is turned off. DIRECT-DRIVE LIMITATIONS With sensitive-gate TRIACs, the direct connection of a TRIAC to a TTL circuit may sometimes be practical. However, the limitations of such circuits must be recognized. For example: For TTL circuits, the “high” logic level is specified as 2.4 volts. In the circuit of Figure 6.48(a), transistor Q2 is capable of supplying a short-circuit output current (ISC) of 20 to 55 mA (depending on the tolerances of R1 and R2, and on the hFE of Q2). Although this is adequate to turn a sensitive-gate TRIAC on, the specified 2.4 volt (high) logic level can only be maintained if the sourcing current is held to a maximum of 0.4 mA — far less than the current required to turn on any thyristor. Thus, the direct connec- tion is useful only if the driver need not activate other logic circuits in addition to a TRIAC. TRIAC LOAD 60 Hz Vout Q3 1 k Q1 R1 MT1 GATE 60 Hz Vout TRIAC LOAD Q2 R2 Vout VCC SINK CURRENT SOURCE CURRENT R1 Vin Vin TTL GATE 1 k LOAD CONNECTION FOR CURRENT SOURCE CONDITION Q3 VoutQ1 R1 1.4 k Q2 R2 100 LOAD CONNECTION FOR CURRENT SINK CONDITION VCCVCC SOURCE CURRENT SINK CURRENT (a) (b) (c) Figure 6.48. Totem-Pole Output Circuit TTL Logic, Together with Voltage and Current Waveforms, (b) Equivalent Circuit for Triggering TRIAC with a Positive Voltage — TRIAC-On Condition, (c) TRIAC-Off Condition
- 121. http://onsemi.com 121 A similar limiting condition exists in the Logic “0” condition of the output, when the thyristor is to be clamped off. In this condition, Q3 is conducting and Vout equals the saturation voltage (VCE(sat)) of Q3. TTL specifications indicate that the low logic level (logic “0”) may not exceed 0.4 volts, and that the sink current must be limited to 16 mA in order not to exceed this value. A higher value of sink current would cause (VCE(sat)) to rise, and could trigger the thyristor on. CIRCUIT DESIGN CONSIDERATIONS Where a 5400-type TTL circuit is used solely for controlling a TRIAC, with positive-gate turn-on (quadrants I-IV), a sensitive gate TRIAC may be directly coupled to the logic output, as in Figure 6.48. If the correct logic levels must be maintained, however, a couple of resistors must be added to the circuit, as in Figure 6.50(a). In this diagram, R1 is a pull-up which allows the circuit to source more current during a high logical output. Its value must be large enough, however, to limit the sinking current below the 16 mA maximum when Vout goes low so that the logical zero level of 0.4 volts is not exceeded. Resistor R2, a voltage divider in conjunction with R1, insures VOH (the “high” output voltage) to be 2.4 V or greater. For a supply voltage of 5 V and a maximum sinking current of 16 mA R1 q V CC ń16 mA q 5ń0.016 q 312 W Thus, 330 Ω, 1/4 W resistor may be used. Assuming R1 to be 330 Ω and a thyristor gate on voltage (VGT) of 1 V, the equivalent circuit of Figure 6.49(b) exists during the log- ical “1” output level. Since the logical “1” level must be maintaned at 2.4 volts, the voltage drop across R2 must be 1.4 V. Therefore, R2+ 1.4ńI R + 1.4ńV R 1 ńR 2 + 1.4ń(2.6ń3.30) ` 175 W A 180 Ω resistor may be used for R2. If the VGT is less than 1 volt, R2 may need to be larger. The MAC97A and 2N6071A TRIACs are compatible devices for this circuit arrangement, since they are guaranteed to be triggered on by 5 mA, whereas the current through the circuit of Figure 6.50(b) is approximately 8 mA, When the TRIAC is to be turned on by a negative gate voltage, as in Figure 6.49(b), the purpose of the limiting resistor R(Iim) is to hold the current through transistor Q3 to 16 mA. With a 5 V supply, a TRIAC VGT of 1 V and a maximum sink current of 16 mA R (lim) + (V CC –V GT )ńI sink + (5–1)(0.016q250 W In practice, a 270 Ω, 1/4 W resistor may be used. 60 Hz LINE LOAD MT2 MT1R(lim) LOGIC CIRCUIT − 5 V R1 Isink Vout MT1 Q1 1 k − 5 V Q3 R(lim) VEE(sat) 0.4 V MAX 60 Hz LINE MT2 LOAD (a) (b) Figure 6.49. TTL Circuit for Quadrant II and III TRIAC Operation Requiring Negative VGT, (b) Schematic Illustrates TRIAC Turn-On Condition, Vout = Logical “0” G = 1 V LOGIC CIRCUIT R2 Vout = 2.4 V R1 60 Hz LINE MT2 MT1 R2 R1 Vout LOAD VCC VCC Figure 6.50. Practical Direct-Coupled TTL TRIAC Circuit, (b) Equivalent Circuit Used for Calculation of Resistor Values (a) (b) (VR 1 ńR1).
- 122. http://onsemi.com 122 OPEN COLLECTOR TTL CIRCUIT The output section of an open-collector TTL gate is shown in Figure 6.51(a). A typical logic gate of this kind is the 5401 type Q2-input NAND gate circuit. This logic gate also has a maximum sink current of 16 mA (VOL = 0.4 V max.) because of the Q1 (sat) limitations. If this logic gate is to source any current, a pull-up-collector resistor, R1 (6.51b) is needed. When this TTL gate is used to trigger a thyristor, R1 should be chosen to supply the maximum trigger current available from the TTL circuit ([ 16 mA, in this case). The value of R1 is calculated in the same way and for the same reasons as in Figure 6.50. If a logical “1” level must be maintained at the TTL output (2.4 V min.), the entire circuit of Figure 6.50 should be used. For direct drive (logical “0”) quadrants II and III triggering, the open collector, negative supplied (−5 V) TTL circuit of Figure 6.52 can be used. Resistor R1 can have a value of 270 Ω, as in Figure 6.49. Resistor R2 ensures that the TRIAC gate is referenced to MT1 when the TTL gate goes high (off), thus preventing unwanted turn-on. An R2 value of about 1 k should be adequate for sensitive gate TRIACs and still draw minimal current. 5 V LOAD MT2 R1 Vout LOGIC CIRCUIT MT1 G 1 k Q1 Vout 1.4 k TTL GATE VCC 60 Hz LINE (a) (b) Figure 6.51. Output Section of Open-Collector TTL, (b) For Current Sourcing, A Pull-up Resistor, R1, Must Be Added Circuits utilizing Schottky TTL are generally designed in the same way as TTL circuits, although the current source/sink capabilities may be slightly different. − 5 V LOAD MT2 MT1G R2 R1 LOGIC CIRCUIT 60 Hz LINE Figure 6.52. Negative-Supplied ( −5 V) TTL Gate Permits TRIAC Operation in Quadrants II and III TRIGGERING THYRISTORS FROM LOGIC GATES USING INTERFACE TRANSISTORS For applications requiring thyristors that demand more gate current than a direct-coupled logic circuit can supply, an interface device is needed. This device can be a small-signal transistor or an opto coupler. The transistor circuits can take several different configu- rations, depending on whether a series or shunt switch design is chosen, and whether gate-current sourcing (quadrants I and IV) or sinking (quadrants II and III) is selected. An example of a series switch, high output (logic 1) activation, is shown in Figure 6.53. Any logic family can be used as long as the output characteristics are known. The NPN interface transistor, Q1, is configured in the common-emitter mode — the simplest approach — with the emitter connected directly to the gate of the thyristor. LOGIC GATE R3 Q1 R5 LOAD G MT1 MT2 60 Hz LINE R4 R2 R1 VCC Figure 6.53. Series Switch, High Output (Logic “1”)
- 123. http://onsemi.com 123 Depending on the logic family used, resistor R1 (pull-up resistor) and R3 (base-emitter leakage resistor) may or may not be required. If, for example, the logic is a typical TTL totem-pole output gate that must supply 5 mA to the base of the NPN transistor and still maintain a “high” (2.4 V) logic output, then R1 and R2 are required. If the “high” logic level is not required, then the TTL circuit can directly source the base current, limited by resistor R2. To illustrate this circuit, consider the case where the selected TRIAC requires a positive-gate current of 100 mA. The interface transistor, a popular 2N4401, has a specified minimum hFE (at a collector current of 150 mA) of 100. To ensure that this transistor is driven hard into saturation, under “worse case” (low temperature) condi- tions, a forced hFE of 20 is chosen — thus, 5 mA of base current. For this example, the collector supply is chosen to be the same as the logic supply (+5 V); but for the circuit configuration, it could be a different supply, if required. The collector-resistor, R4, is simply R4 + (VCC * VCE(sat) * VGT(typ))ńIGT + (5 * 1 * 0.9)ń100 mA + 40 W A 39 ohm, 1 W resistor is then chosen, since its actual dissipation is about 0.4 W. If the “logic 1” output level is not important, then the base limiting resistor R2 is required, and the pull-up resistor R1 is not. Since the collector resistor of the TTL upper totem-pole transistor, Q2, is about 100 Ω, this resistor plus R2 should limit the base current to 5 mA. Thus R2 calculates to R2 + [(VCC * VBE * VGT)ń5 mA] * 100 W + [(5 * 0.7 * 0.9)ń0.005] 100 W [ 560 W (specified) When the TTL output is low, the lower transistor of the totem-pole, Q3, is a clamp, through the 560 Ω resistor, across the 2N4401; and, since the 560 Ω resistor is relatively low, no leakage-current shunting resistor, R3, is required. In a similar manner, if the TTL output must remain at “logic 1” level, the resistor R1 can be calculated as described earlier (R3 may or may not be required). For low-logic activation (logic “0”), the circuit of Figure 6.54 can be used. In this example, the PNP-interface transistor 2N4403, when turned on, will supply positive- gate current to the thyristor. To ensure that the high logic level will keep the thyristor off, the logic gate and the transistor emitter must be supplied with the same power supply. The base resistors, as in the previous example, are dictated by the output characteristics of the logic family used. Thus if a TTL gate circuit is used, it must be able to sink the base current of the PNP transistor (IOL(MAX) = 16 mA). When thyristor operation in quadrants II and III is desired, the circuits of Figures 6.55 and 6.56 can be used; Figure 6.55 is for high logic output activation and Figure 6.56 is for low. Both circuits are similar to those on Figures 6.53 and 6.54, but with the transistor polarity and power supplies reversed. + 5 V LOGIC GATE R1 R2 Q1 G R4 R3 MT2 MT1 60 Hz LINE LOAD Figure 6.54. Low-Logic Activation with Interface Transistor LOGIC GATE R3 R1 R2 Q1 R4 R5 LOAD G MT1 MT2 60 Hz LINE − VEE Figure 6.55. High-Logic Output Activation Figure 6.55 sinks current from the thyristor gate through a switched NPN transistor whose emitter is referenced to a negative supply. The logic circuit must also be referenced to this negative supply to ensure that transistor Q1 is turned off when required; thus, for TTL gates, VEE would be −5 V. In Figure 6.56, the logic-high bus, which is now ground, is the common ground for both the logic, and the thyristor and the load. As in the first example (Figure 6.53), the negative supply for the logic circuit (−VEE) and the collector supply for the PNP transistor need not be the same supply. If, for power-supply current limitations, the collector supply is chosen to be another supply (−VCC), it must be within the VCEO ratings of the PNP transistor. Also, the power dissipation of collector resistor, R3, is a function of −VCC — the lower −VCC, the lower the power rating.
- 124. http://onsemi.com 124 − VEE LOGIC GATE R3 LOAD MT2 MT1 G R4 R1 R2 60 Hz LINE Figure 6.56. Low-Logic Output Activation + 5 V LOGIC GATE R2 R1 Q1 R3 LOAD G MT1 MT2 60 Hz LINE Figure 6.57. Shunt-Interface Circuit (High-Logic Output) R2 R1 LOGIC GATE R3 LOAD G MT2 MT1 − VEE 60 Hz LINE Figure 6.58. Shunt-Interface Circuit (Quadrants I and III Operation) The four examples shown use gate-series switching to activate the thyristor and load (when the interface transistor is off, the load is off). Shunt-switching can also be used if the converse is required, as shown in Figures 6.57 and 6.58. In Figure 6.57, when the logic output is high, NPN transistor, Q1, is turned on, thus clamping the gate of the thyristor off. To activate the load, the logic output goes low, turning off Q1 and allowing positive gate current, as set by resistor R3, to turn on the thyristor. In a similar manner, quadrant’s II and III operation is derived from the shunt interface circuit of Figure 6.58. OPTICAL ISOLATORS/COUPLERS An Optoelectronic isolator combines a light-emitting device and a photo detector in the same opaque package that provides ambient light protection. Since there is no electrical connection between input and output, and the emitter and detector cannot reverse their roles, a signal can pass through the coupler in one direction only. Since the opto-coupler provides input circuitry protec- tion and isolation from output-circuit conditions, ground- loop prevention, dc level shifting, and logic control of high voltage power circuitry are typical areas where opto- couplers are useful. Figure 6.59 shows a photo-TRIAC used as a driver for a higher-power TRIAC. The photo-TRIAC is light sensitive and is turned on by a certain specified light density (H), which is a function of the LED current. With dark conditions (LED current = 0) the photo-TRIAC is not turned on, so that the only output current from the coupler is leakage current, called peak-blocking current (IDRM). The coupler is bilateral and designed to switch ac signals. The photo-TRIAC output current capability is, typically, 100 mA, continuous, or 1 A peak. LED OPTO COUPLER PHOTO TRIAC H I LOAD G R MT2 MT1 60 Hz LINE Figure 6.59. Optically-Coupled TRIAC Driver is Used to Drive a Higher-Power TRIAC
- 125. http://onsemi.com 125 Any Opto TRIAC can be used in the circuit of Figure 6.59 by using Table 6.8. The value of R is based on the photo-TRIAC’s current-handling capability. For example, when the MOC3011 operates with a 120 V line voltage (approximately 175 V peak), a peak IGT current of 175 V/180 ohm (approximately 1 A) flows when the line voltage is at its maximum. If less than 1 A of IGT is needed, R can be increased. Circuit operation is as follows: Table 6.8. Specifications for Typical Optically Coupled TRIAC Drivers Device Type Maximum Required LED Trigger Current (mA) Peak Blocking Voltage R(Ohms) MOC3011 MOC3011 MOC3021 MOC3031 15 10 15 15 250 250 400 250 180 180 360 51 When an op-amp, logic gate, transistor or any other appropriate device turns on the LED, the emitted light triggers the photo-TRIAC. Since, at this time, the main TRIAC is not on, MT2-to-gate is an open circuit. The 60 Hz line can now cause a current flow via R, the photo-TRIAC, Gate-MT1 junction and load. This Gate-MT1 current triggers the main TRIAC, which then shorts and turns off the photo-TRIAC. The process repeats itself every half cycle until the LED is turned off. Triggering the main TRIAC is thus accomplished by turning on the LED with the required LED-trigger current indicated in Table 6.7. MICROPROCESSORS Microprocessor systems are also capable of controlling ac power loads when interfaced with thyristors. Commonly, the output of the MPU drives a PIA (peripheral interface adaptor) which then drives the next stage. The PIA Output Port generally has a TTL compatible output with significant- ly less current source and sink capability than standard TTL. (MPUs and PIAs are sometimes constructed together on the same chip and called microcontrollers.) When switching ac loads from microcomputers, it is good practice to optically isolate them from unexpected load or ac line phenomena to protect the computer system from possible damage. In addition, optical isolation will make UL recognition possible. A typical TTL-compatible microcontroller, such as the MC3870P offers the following specifications: IOH + 300 mA (VOH + 2.4 V) IOL + 1.8 mA (VOL + 0.4 V) VCC + 5 V Since this is not adequate for driving the optocoupler directly (10 mA for the MOC3011), an interface transistor is necessary. The circuit of Figure 6.60 may be used for thyristor triggering from the 3870 logical “1.” MC3870 MT1 MT2 R G LOAD Q1 R2 R1 R3 + 5 V Figure 6.60. Logical “1” Activation from MC3870P Microcomputer 60 Hz LINE The interface transistor, again, can be the 2N4401. With 10 mA of collector current (for the MOC3011) and a base current of 0.75 mA, the VCE(sat) will be approximately 0.1 V. R1 can be calculated as in a previous example. Specifically: 1.8 mA (maximum IOL for the 3870) u 5 VńR1; R1 u 2.77 k R1 can be 3 k, 1ń4 W With a base current of 0.75 mA, R1 will drop (0.75 mA) (3 k) or 2.25 V. This causes a VOH of 2.75 V, which is within the logical “1” range. R2 + [2.75 V–VBE(on)]ńIB + (2.75–0.75)ń0.75 + 2.66 k R2 can be a 2.7 k, 1ń4 W resistor.. R3 must limit IC to 10 mA : R3 + [5 V–VCE(sat) – VF(diode)ń10 mA] + (5–0.1–1.2)ń10 mA + 370 W Since R3 is relatively small, no base-emitter leakage resistor is required.
- 126. http://onsemi.com 126 Figure 6.61 shows logical “0” activation. Resistor values are calculated in a similar way. MC3870P Q1 R1 R2 + 5 V R3 G LOAD MT1 60 Hz LINE MT2 R Figure 6.61. Logical “0” Activation D S D P-CHANNEL rDS(on)P-CHANNEL S N-CHANNEL RL Vout RL VDD Vin VDDVDD Vout Vout N-CHANNEL rDS(on) Figure 6.62. Output Section of a Typical CMOS Gate, (b) Equivalent Current-Sourcing Circuit is Activated when Vin goes Low, Turning the P-Channel Device Fully On, (c) Equivalent Current Sinking Circuit is Activated when the Input Goes High and Turns the N-Channel Device On (a) (b) (c) THE CMOS INTERFACE Another popular logic family, CMOS, can also be used to drive thyristors. As shown in Figure 6.62(a), the output stage of a typical CMOS Gate consists of a P-channel MOS device con- nected in series with an N-channel device (drain-to-drain), with the gates tied together and driven from a common input signal. When the input signal goes high, logical 1, the P-channel device is essentially off and conducts only leakage current (IDSS), on the order of pico-amps. The N-channel unit is forward-biased and, although it has a relatively high on resistance (rDS(on)), the drain-to-source voltage of the N-channel device (VDS) is very low (essentially zero) because of the very low drain current (VDSS) flowing through the device. Conversely, when the input goes low (zero), the P-channel device is turned fully on, the N-channel device is off and the output voltage will be very near VDD. When interfacing with transistors or thyristors, the CMOS Gate is current-limited mainly by its relatively high on resistance, the dc resistance between drain and source, when the device is turned on. The equivalent circuits for sourcing and sinking current into an external load is shown in Figures 6.62(b) and 6.62(c). Normally, when interfacing CMOS to CMOS, the logic outputs will be very near their absolute maximum states (VDD or 0 V) because of the extremely small load currents. With other types of loads (e.g. TRIACs), the current, and the resulting output voltage, is dictated by the simple voltage divider of rDS(on) and the load resistor RL, where rDS(on) is the total series and/or parallel resistance of the devices comprising the NOR and NAND function. Interfacing CMOS gates with thyristors requires a knowledge of the on resistance of the gate in the source and sink conditions. The on-resistance of CMOS devices is not normally specified on data sheets. It can easily be calculated, however, from the output drive currents, which are specified. The drive (source/sink) currents of typical CMOS gates at various supply voltages are shown in Table 6.9. From this information, the on resistance for worst case design is calculated as follows: For the source condition rDS(on)(MAX) + (V DD * V OH )ńI OH(MIN) Similarly, for the sink current condition rDS(on)(MAX) + VOLńIOL(MIN) Values of rDS(on) for the various condition shown in Table 6.9 are tabulated in Table 6.10. Specified source/sink currents to maintain logical “1” and logical “0” levels for various power-supply (VDD) voltages. The IOH and IOL values are used to calculate the “on” resistance of the CMOS output.
- 127. http://onsemi.com 127 Table 6.9. CMOS Characteristics Output Drive Current CMOS AL Series mA, dc CMOSCL/CP Series mA, dc Min Typ Min Typ I(source) − IOH VDD = 5 V; VOH = 2.5 V VDD = 10 V; VOH = 9.5 V VDD = 15 V; VOH = 13.5 V − 0.5 − 0.5 − 1.7 − 0.9 − 3.5 − 0.2 − 0.2 − 1.7 − 0.9 − 3.5 I(sink) − IOL VDD = 5 V; VOL= 0.4 V VDD = 10 V; VOL = 0.5 V VDD = 15 V; VOL = 1.5 V 0.4 0.9 7.8 2 7.8 0.2 0.5 7.8 2 7.8 Table 6.10. Calculated CMOS On Resistance Values For Current Sourcing and Sinking at Various VDD Options Operating Conditions Output Resistance, rDS(on) Ohms Typical Maximum Source Condition VDD = 5 V 10 V 15 V 1.7 k 500 430 12.5 k 2.5 k — Sink Condition VDD = 5 V 10 V 15 V 500 420 190 2 k 1 k — It is apparent from this table that the on resistance decreases with increasing supply voltage. Although the minimum currents are now shown on the data sheet for the 15 V case, the maximum on resistance can be no greater than the 10 V example and, therefore, can be assumed for worst case approximation to be 1 and 2.5 kohms for sink-and-source current cases, respectively. The sourcing on resistance is greater than the sinking case because the difference in carrier mobilities of the two channel types. Since rDS(on) for both source and sink conditions varies with supply voltage (VDD), there are certain drive limitations. The relative high rDS(on) of the P-channel transistor could possibly limit the direct thyristor drive capability; and, in a like manner, the N-channel rDS(on) might limit its clamping capability. With a 10 or 15 V supply, the device may be capable of supplying more than 10 mA, but should be limited to that current, with an external limiting resistor, to avoid exceeding the reliable limits of the unit metalization. DC MOTOR CONTROL WITH THYRISTORS In order to control the speed of a dc series field motor at different required torque levels, it is necessary to adjust the voltage applied to the motor. For any particular applied voltage the motor speed is determined solely by the torque requirements and top speed is reached under minimum torque conditions. When a series motor is used as a traction drive for vehicles, it is desirable to control the voltage to the motor to fit the various torque requirements of grades, speed and load. The common method of varying the speed of the motor is by inserting resistance in series with the motor to reduce the supplied voltage. This type of motor speed control is very inefficient due to the I2R loss, especially under high current and torque conditions. A much more efficient method of controlling the voltage applied to the motor is the pulse width modulation method shown in Figure 6.63. In this method, a variable width pulse of voltage is applied to the motor at the same rate to proportionally vary the average voltage applied to the motor. A diode is placed in parallel with the inductive motor path to provide a circuit for the inductive motor current and prevent abrupt motor current change. Abrupt current changes would cause high induced voltage across the switching device. VM = BACK EMF OF MOTOR LM = MOTOR INDUCTANCE RM = MOTOR RESISTANCE VM LM RM BATTERY− BATTERY CURRENT + MOTOR CURRENT DIODE CURRENT APPLIED BATTERY VOLTAGE AVERAGE − + AVERAGE AVERAGE AVERAGE Figure 6.63. Basic Pulse Width Modulated Motor Speed Control The circulating current through the diode decreases only in response to motor and diode loss. With reference to Figure 6.63, it can be seen that the circulating diode current causes more average current to flow through the motor than is taken from the battery. However, the power taken from the battery is approximately equal to the power delivered to the motor, indicating that energy is stored in the motor inductance at the battery voltage level and is delivered to the motor at the approximate current level when the battery is disconnected.
- 128. http://onsemi.com 128 To provide smooth and quiet motor operation, the current variations through the motor should be kept to a minimum during the switching cycle. There are limitations on the amount of energy that can be stored in the motor inductance, which, in turn, limits the power delivered to the motor during the off time; thus the off time must be short. To operate the motor at low speeds, the on time must be approximately 10 percent of the off time and therefore, a rapid switching rate is required that is generally beyond the capabilities of mechanical switches. Practical solutions can be found by the use of semiconductor devices for fast, reliable and efficient switching operations. SCR DC MOTOR CONTROL SCRs offer several advantages over power transistors as semiconductor switches. They require less driver power, are less susceptible to damage by overload currents and can handle more voltage and current. Their disadvantages are that they have a higher power dissipation due to higher voltage drops and the difficulty in commutating to the off condition. The SCR must be turned off by either interrupting the current through the anode-cathode circuit or by forcing current through the SCR in the reverse direction so that the net flow of forward current is below the holding current long enough for the SCR to recover blocking ability. Commutation of the SCR in high current motor control circuits is generally accomplished by discharging a capaci- tor through the SCR in the reverse direction. The value of this capacitor is determined approximately from the following equation: Cc + Tq I A Vc Where: Cc = value of necessary commutating capacitance Tq = turn-off time of the SCR IA = value of anode current before commutation Vc = voltage of Cc before commutation This relationship shows that to reduce the size of Cc, the capacitor should be charged to as high a voltage as possible and the SCR should be selected with as low a turn-off time as possible. If a 20 microsecond turn-off time SCR is commutated by a capacitor charged to 36 volts, it would take over 110 μF to turn off 200 amperes in the RC commutating circuit of Figure 6.64. If a 50 cycle switching frequency is desired, the value of R1 would be approximately 5 ohms to allow charging time with an on duty cycle of 10 percent. The value of this resistor would give approximately 260 watts dissipa- tion in the charging circuit with 90 percent off duty cycle. If the resonant charging commutating circuitry of Figure 6.65 is used, the capacitor is reduced to approxi- mately 55 μF. In this circuit, SCR3 is gated on at the same time as SCR1 and allows the resonant charging of Cc through Lc to twice the supply voltage. SCR3 is then turned off by the reversal of voltage in the resonant circuit before SCR2 is gated on. It is apparent that there is very little power loss in the charge circuit depending upon the voltage drop across SCR3 and the resistance in Lc. SCR1 TRIGGER CIRCUIT SCR2 Cc R1 Figure 6.64. Speed Control with Resistive Charging SCR1 SCR2 Cc Lc SCR3 TRIGGER CIRCUIT Figure 6.65. Speed Control with Inductive Charging TRIGGER CIRCUIT SCR1 SCR2 D1 D2 Figure 6.66. SCR Motor Control with Transformer Charging
- 129. http://onsemi.com 129 If the commutating capacitor is to be reduced further, it is necessary to use a transformer to charge the capacitor to more than twice the supply voltage. This type of circuit is illustrated by the transformer charge circuit shown in Figure 6.66. In this circuit the capacitor can be charged to several times the supply voltage by transformer action through diode D1 before commutating SCR1. The disad- vantage of this circuit is in the high motor current that flows through the transformer primary winding. HEAVY DUTY MOTOR CONTROL WITH SCRs Another advantage of SCRs is their high surge current capabilities, demonstrated in the motor drive portion of the golf cart controller shown in Figure 6.67. Germanium power transistors were used because of the low saturation voltages and resulting low static power loss. However, since switching speeds are slow and leakage currents are high, additional circuit techniques are required to ensure reliable operation: 1. The faster turn-on time of the SCR (Q9) over that of the germanium transistors shapes the turn-on load line. 2. The parallelled output transistors (Q3-Q8) require a 6 V reverse bias. 3. The driver transistor Q2 obtains reverse bias by means of diode D4. To obtain the 6 V bias, the 36 V string of 6 V batteries are tapped, as shown in the schematic. Thus, the motor is powered from 30 V and the collector supply for Q2 is 24 V, minimizing the dissipation in colllector load resistor R1. Total switching loss in switchmode applications is the result of the static (on-state) loss, dynamic (switching) loss and leakage current (off-state) loss. The low saturation voltage of germanium transistors produces low static loss. However, switching speeds of the germanium transistors are low and leakage currents are high. Loss due to leakage current can be reduced with off bias, and load line shaping can minimize switching loss. The turn-off switching loss was reduced with a standard snubber network (D5, C1, R2) see Figure 6.67. Turn-on loss was uniquely and substantially reduced by using a parallel connected SCR (across the germanium transistors) the MCR265-4 (55 A rms, 550 A surge). This faster switching device diverts the initial turn-on motor load current from the germanium output transistors, reducing both system turn-on loss and transistor SOA stress. The main point of interest is the power switching portion of the PWM motor controller. Most of the readily available PWM ICs can be used (MC3420, MC34060, TL494, SG1525A, UA78S40, etc.), as they can source at least a 10 mA, +15 V pulse for driving the following power MOSFET. PWM + 15 V +10 μF 25 V 0.01 μF 1 k 10 k MTP12N10E Q1 20 50 W R1 27 0.6 200 W 1N1183 D4 Q2 1 μF 1N914 D3 (2) D2 330 D1 1N914 (6) MATCHED Q8 Q3 6 25 W OFF BIAS UTC H51 SENSE CURRENT TO PWM 0.001 dc MOTOR 2 HP FORWARD Q9 MCR 265-4 1N4744 D5 1N1183 1 R2 700 μF C1 + 18 V 470 + 24 V + 15 V + 30 V + 36 V REVERSE Figure 6.67. PWM DC Motor Controller Using SCR Turn-On Feature
- 130. http://onsemi.com 130 Due to the extremely high input impedance of the power MOSFET, the PWM output can be directly connected to the FET gate, requiring no active interface circuitry. The positive going output of the PWM is power gained and inverted by the TMOS FET Q1 to supply the negative going base drive to PNP transistor Q2. Diode D1 provides off-bias to this paraphase amplifier, the negative going pulse from the emitter furnishing base drive to the six parallel connected output transistors and the positive going collector output pulse supplying the SCR gate trigger coupled through transformer T1. Since the faster turn-on SCR is triggered on first, it will carry the high, initial turn-on motor current. Then the slower turn-on germanium transistors will conduct clamp- ing off the SCR, and carry the full motor current. For the illustrated 2HP motor and semiconductors, a peak expo- nentially rising and falling SCR current pulse of 120 A lasting for about 60 μs was measured. This current is well within the rating of the SCR. Thus, the high turn-on stresses are removed from the transistors providing a much more reliable and efficient motor controller while using only a few additional components. DIRECTION AND SPEED CONTROL FOR MOTORS For a shunt motor, a constant voltage should be applied to the shunt field to maintain constant field flux so that the armature reaction has negligible effect. When constant voltage is applied to the shunt field, the speed is a direct function of the armature voltage and the armature current. If the field is weak, then the armature reaction may counterbalance the voltage drop due to the brushes, windings and armature resistances, with the net result of a rising speed-load characteristic. The speed of a shunt-wound motor can be controlled with a variable resistance in series with the field or the armature. Varying the field current for small motor provides a wide range of speeds with good speed regula- tion. However, if the field becomes extremely weak, a rising speed-load characteristic results. This method cannot provide control below the design motor speed. Varying the resistance in series with the armature results in speeds less than the designed motor speed; however, this method yields poor speed regulation, especially at low speed settings. This method of control also increases power dissipation and reduces efficiency and the torque since the maximum armature current is reduced. Neither type of resistive speed control is very satisfactory. Thyristor drive controls, on the other hand, provide continuous control through the range of speed desired, do not have the power losses inherent in resistive circuits, and do not compromise the torque characteristics of motors. Although a series-wound motor can be used with either dc or ac excitation, dc operation provides superior perfor- mance. A universal motor is a small series-wound motor designed to operate from either a dc or an ac supply of the same voltage. In the small motors used as universal motors, the winding inductance is not large enough to produce sufficient current through transformer action to create excessive commutation problems. Also, high-resistance brushes are used to aid commutation. The characteristics of a universal motor operated from alternating current closely approximate those obtained for a dc power source up to full load; however, above full load the ac and dc characteristics differ. For a series motor that was not designed as a universal motor, the speed-torque characteristic with ac rather than dc is not as good as that for the universal motor. At eight loads, the speed for ac operation may be greater than for dc since the effective ac field strength is smaller than that obtained on direct current. At any rate, a series motor should not be operated in a no-load condition unless precaution is are taken to limit the maximum speed. SERIES-WOUND MOTORS The circuit shown in Figure 6.68 can be used to control the speed and direction of rotation of a series-wound dc motor. Silicon controlled rectifiers Q1-Q4, which are connected in a bridge arrangement, are triggered in diagonal pairs. Which pair is turned on is controlled by switch S1 since it connects either coupling transformer T1 or coupling transformer T2 to a pulsing circuit. The current in the field can be reversed by selecting either SCRs Q2 and Q3 for conduction, or SCRs Q1 and Q4 for conduction. Since the armature current is always in the same direction, the field current reverses in relation to the armature current, thus reversing the direction of rotation of the motor. A pulse circuit is used to drive the SCRs through either transformer T1 or T2. The pulse required to fire the SCR is obtained from the energy stored in capacitor C1. This capacitor charges to the breakdown voltage of zener diode D5 through potentiometer R1 and resistor R2. As the capacitor voltage exceeds the zener voltage, the zener conducts, delivering current to the gate of SCR Q5. This turns Q5 on, which discharges C1 through either T1 or T2 depending on the position of S1. This creates the desired triggering pulse. Once Q5 is on, it remains on for the duration of the half cycle. This clamps the voltage across C1 to the forward voltage drop of Q5. When the supply voltage drops to zero, Q5 turns off, permitting C1 to begin charging when the supply voltage begins to increase.
- 131. http://onsemi.com 131 R3 1 k D5 1N5262 Q5 2N5062 R2, 4.7 k 5 W R1 20 k 5 W D3 D1 D4 D2 (4) 1N4722 OR MDA2503AC LINE (2) SPRAGUE 11Z13 T2T1 S1 C1 + 5 μF 75 V MCR12D Q3 T2 MCR12D Q1 T1 FIELD MCR12D Q4 MCR12D Q2 ARMATURE T1 T2 Figure 6.68. Direction and Speed Control for Series-Wound or Universal Motor Q5 2N5062 R3 1 k D5 1N5262 T1 C1 ac LINE R2, 4.7 k 5 W R1 20 k 5 W D3 D1 D4 D2 (4) 1N4722 + 5 μF 75 V T1 AND T2 ARE SPRAGUE 11Z13 Q1 THRU Q4 Ċ MCR12D T2 FIELD Q3 T2 T1 Q4 ARMATURE Q2 T2 T1 Q1 Figure 6.69. Direction and Speed Control for Shunt-Wound Motor The speed of the motor can be controlled by potentiome- ter R1. The larger the resistance in the circuit, the longer required to charge C1 to the breakdown voltage of zener D5. This determines the conduction angle of either Q1 and Q4, or Q2 and Q3, thus setting the average motor voltage and thereby the speed. SHUNT-WOUND MOTORS If a shunt-wound motor is to be used, then the circuit in Figure 6.69 is required. This circuit operates like the one shown in Figure 6.68. The only differences are that the field is placed across the rectified supply and the armature is placed in the SCR bridge. Thus the field current is unidirectional but armature current is reversible; conse- quently the motor’s direction of rotation is reversible. Potentiometer R1 controls the speed as explained previously.
- 132. http://onsemi.com 132 RESULTS Excellent results were obtained when these circuits were used to control 1/15 hp, 115 V, 5,000 r/min motors. This circuit will control larger, fractional-horsepower motors provided the motor current requirements are within the semiconductor ratings. Higher current devices will permit control of even larger motors, but the operation of the motor under worst case must not cause anode currents to exceed the ratings of the semiconductor. PUT APPLICATIONS PUTs are negative resistance devices and are often used in relaxation oscillator applications and as triggers for controlling thyristors. Due to their low leakage current, they are useful for high-impedance circuits such as long-duration timers and comparators. TYPICAL CIRCUITS The following circuits show a few of the many ways in which the PUT can be used. The circuits are not optimized even though performance data is shown. In several of the circuit examples, the versatility of the PUT has been hidden in the design. By this it is meant that in designing the circuit, the circuit designer was able to select a particular intrinsic standoff ratio or he could select a particular RG (gate resistance) that would provide a maximum or minimum valley and peak current. This makes the PUT very versatile and very easy to design with. LOW VOLTAGE LAMP FLASHER The PUT operates very well at low supply voltages because of its low on-state voltage drop. A circuit using the PUT in a low voltage application is shown in Figure 6.70 where a supply voltage of 3 volts is used. The circuit is a low voltage lamp flasher composed of a relaxation oscillator formed by Q1 and an SCR flip flop formed by Q2 and Q3. R2 910 C1 10 μF Q1 2N6027 R1 100 k R3 1 k R4 2 k R5 1 k 0.01 μF C2 Q2 2N5060 R6 51 k C3 0.01 μF (SEE TEXT) −+ C4 4 μF R7 1 k Q3 2N5060 GE NO. 14 + 3 V Figure 6.70. Low Voltage Lamp Flasher With the supply voltage applied to the circuit, the timing capacitor C1 charges to the firing point of the PUT, 2 volts plus a diode drop. The output of the PUT is coupled through two 0.01 μF capacitors to the gate of Q2 and Q3. To clarify operation, assume that Q3 is on and capacitor C4 is charged plus to minus as shown in the figure. The next pulse from the PUT oscillator turns Q2 on. This places the voltage on C4 across Q3 which momentarily reverse biases Q3. This reverse voltage turns Q3 off. After discharging, C4 then charges with its polarity reversed to that shown. The next pulse from Q1 turns Q3 on and Q2 off. Note that C4 is a non-polarized capacitor. For the component values shown, the lamp is on for about 1/2 second and off the same amount of time. 2 19 876543 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 1 C = 0.0047 μF C = 0.01 μF DURATION TIME (ms) V(VOLTS)in (b). Voltage versus Ramp Duration Time of VCRG 5 to 20 V C1 R2 20 k −40 V + R1 10 k Q1 MPS6516 R3 510 k R4 100 2N6027 R5 100 k RAMP OUT + Figure 6.71. (a). Voltage Controlled Ramp Generator (VCRG)
- 133. http://onsemi.com 133 VOLTAGE CONTROLLED RAMP GENERATOR The PUT provides a simple approach to a voltage controlled ramp generator, VCRG, as shown in Figure 6.71(a). The current source formed by Q1 in conjuction with capacitor C1 set the duration time of the ramp. As the positive dc voltage at the gate is changed, the peak point firing voltage of the PUT is changed which changes the duration time, i.e., increasing the supply voltage increases the peak point firing voltage causing the duration time to increase. Figure 6.71(b) shows a plot of voltage-versus-ramp duration time for a 0.0047 μF and a 0.01 μF timing capacitor. The figure indicates that it is possible to have a change in frequency of 3 ms and 5.4 ms for the 0.0047 μF and the 0.01 μF capacitor respectively as the control voltage is varied from 5 to 20 volts. LOW FREQUENCY DIVIDER The circuit shown in Figure 6.72 is a frequency divider with the ratio of capacitors C1 and C2 determining division. With a positive pulse applied to the base of Q1, assume that C1 = C2 and that C1 and C2 are discharged. When Q1 turns off, both C1 and C2 charge to 10 volts each through R3. On the next pulse to the base of Q1, C1 is again discharged but C2 remains charged to 10 volts. As Q1 turns off this time, C1 and C2 again charge. This time C2 charges to the peak point firing voltage of the PUT causing it to fire. This discharges capacitor C2 and allows capacitor C1 to charge to the line voltage. As soon as C2 discharges and C1 charges, the PUT turns off. The next cycle begins with another positive pulse on the base of Q1 which again discharges C1. The input and output frequency can be approximated by the equation fin [ (C1 ) C2) C1 fout For a 10 kHz input frequency with an amplitude of 3 volts, Table 6.11 shows the values for C1 and C2 needed to divide by 2 to 11. This division range can be changed by utilizing the programmable aspect of the PUT and changing the voltage on the gate by changing the ratio R6/(R6+ R5). Decreasing the ratio with a given C1 and C2 decreases the division range and increasing the ratio increases the division range. The circuit works very well and is fairly insensitive to the amplitude, pulse width, rise and fall times of the incoming pulses. R2 2.2 k 3 V R1 3.9 k Q1 MPS6512 R3 1 k C1 D1 1N4001 C2 D2 1N4001 + 20 Vdc Q2 2N6027 R4 100 R6 5.1 k 8 VR5 5.1 k OUT 0.01 μF 0.01 μF 0.01 μF 0.01 μF 0.01 μF 0.01 μF 0.01 μF 0.01 μF 0.01 μF 0.01 μF C1 C2 Division 0.01 μF 0.02 μF 0.03 μF 0.04 μF 0.05 μF 0.06 μF 0.07 μF 0.08 μF 0.09 μF 0.1 μF 2 3 4 5 6 7 8 9 10 11 Table 6.11 Figure 6.72. Low Frequency Divider PUT LONG DURATION TIMER A long duration timer circuit that can provide a time delay of up to 20 minutes is shown in Figure 6.73. The circuit is a standard relaxation oscillator with a FET current source in which resistor R1 is used to provide reverse bias on the gate-to-source of the JFET. This turns the JFET off and increases the charging time of C1. C1 should be a low leakage capacitor such as a mylar type. The source resistor of the current source can be computed using the following equation: VGS + VP (1 * IOńIDSSǸ ) NR1 + VGS IO where IO is the current out of the current source. VP is the pinch off voltage, VGS is the voltage gate-to-source and, IDSS is the current, drain-to-source, with the gate shorted to the source.
- 134. http://onsemi.com 134 The time needed to charge C1 to the peak point firing voltage of Q2 can be approximated by the following equation: t + CDV I , where t is time in seconds C is capacitance in μF, ΔV is the change in voltage across capacitor C1, and I is the constant current used to charge C1. Maximum time delay of the circuit is limited by the peak point firing current, lP, needed to fire Q2. For charging currents below IP, there is not enough current available from the current source to fire Q2, causing the circuit to lock up. Thus PUTs are attractive for long duration timing circuits because of their low peak point current. This current becomes very small when RG (the equivalent parallel resistance of R3 and R4) is made large. For example, the 2N6028 has IP guaranteed to be less than 0.15 μA at RG = 1 M Ohm as shown in Figure 6.73. + 20 Vdc R3 2 M C1 10 μF MYLAR Q1 2N5457 R1 22 M R2 100 Q2 2N6028 OUTPUT R4 2 M Figure 6.73. 20-Minute, Long Duration Timer PHASE CONTROL Figure 6.74 shows a circuit using a PUT for phase control of an SCR. The relaxation oscillator formed by Q2 provides conduction control of Q1 from 1 to 7.8 millisec- onds or 21.6° to 168.5°. This constitutes control of over 97% of the power available to the load. Only one SCR is needed to provide phase control of both the positive and negative portion of the sine wave byputting the SCR across the bridge composed of diodes D1 through D4. 115 V rms 60 Hz LOAD 100 Ω Q1 2N6402 D4 D2 D1 D3 D5 1N4114 20 V R2 250 k C1 0.1 μF Q2 2N6027 R4 1 k R3 1 k 15 k 2 WATT R1 Figure 6.74. SCR Phase Control BATTERY CHARGER USING A PUT A short circuit proof battery charger is shown in Figure 6.75 which will provide an average charging current of about 8 amperes to a 12 volt lead acid storage battery. The charger circuit has an additional advantage in that it will not function nor will it be damaged by improperly connecting the battery to the circuit. With 115 volts at the input, the circuit commences to function when the battery is properly attached. The battery provides the current to charge the timing capacitor C1 used in the PUT relaxation oscillator. When C1 charges to the peak point voltage of the PUT, the PUT fires turning the SCR on, which in turn applies charging current to the battery. As the battery charges, the battery voltage increases slightly which increases the peak point voltage of the PUT. This means that C1 has to charge to a slightly higher voltage to fire the PUT. The voltage on C1 increases until the zener voltage of D1 is reached which clamps the voltage on C1 and thus prevents the PUT oscillator from oscillating and charging ceases. The maximum battery voltage is set by potentiometer R2 which sets the peak point firing voltage of the PUT.
- 135. http://onsemi.com 135 In the circuit shown, the charging voltage can be set from 10 V to 14 V, the lower limit being set by D1 and the upper limit by T1. Lower charging voltages can be obtained by reducing the reference voltage (reducing the value of zener diode D1) and limiting the charging current (using either a lower voltage transformer, T1, or adding resistance in series with the SCR). Resistor R4 is used to prevent the PUT from being destroyed if R2 were turned all the way up. Figure 6.75(b) shows a plot of the charging characteris- tics of the battery charger. 115 V rms 14 V rms T1 D1 1N5240 10 V R1 10 k C1 0.1 μF DALE PT50 T2 11Z12 1:1 PUT SCR 2N6027 B R3 47 k R2 50 k R4 1 k A 12 V − + Figure 6.75. (a). 12-Volt Battery Charger 1200 CHARGING CURRENT versus TIME 2 4 5 6 7 987654321 1150 8 0 SPECIFIC GRAVITY OF ELECTROLYTE versus TIME TIME (HR) 1250 3 SPECIFICGRAVITY CURRENT(AMPS) Figure 6.75 (b) Charging Characteristics of Battery Charger 90 V rms VOLTAGE REGULATOR USING A PUT The circuit of Figure 6.76 is an open loop rms voltage regulator that will provide 500 watts of power at 90 V rms with good regulation for an input voltage range of 110 −130 V rms. With the input voltage applied, capacitor C1 charges until the firing point of Q3 is reached causing it to fire. This turns Q5 on which allows current to flow through the load. As the input voltage increases, the voltage across R10 increases which increases the firing point of Q3. This delays the firing of Q3 because C1 now has to charge to a higher voltage before the peak-point voltage is reached. Thus the output voltage is held fairly constant by delaying the firing of Q5 as the input voltage increases. For a decrease in the input voltage, the reverse occurs. Another means of providing compensation for increased input voltage is achieved by Q2 and the resistive divider formed by R6 and R7. As input voltage increases, the voltage at the base of Q2 increases causing Q2 to turn on harder which decreases the charging rate of C1 and further delays the firing of Q5. To prevent the circuit from latching up at the beginning of each charging cycle, a delay network consisting of Q1 and its associated circuitry is used to prevent the current source from turning on until the trigger voltage has reached a sufficiently high level. This is achieved in the following way: Prior to the conduction of D2, the voltage on the base of Q1 is set by the voltage divider (R4 + R5)/(R1 + R3 + R4 + R5). This causes the base of Q1 to be more positive than the emitter and thus prevents Q1 from conducting until the voltage across R3 is sufficient to forward bias the base-emitter junction of Q1. This occurs when the line voltage has increased to about 15 volts. The circuit can be operated over a different voltage range by changing resistors R6 and/or R4 which change the charging rate of C1.
- 136. http://onsemi.com 136 Figure 6.76(b) provides a plot of output voltage and conduction angle versus input voltage for the regulator. As the figure indicates, good regulation can be obtained between the input voltage range of 110 to 130 volts. LOAD 500 W 90 V ± 2 110-130 V rms D1 D2 1N4747 20 V R5 6.8 k R4 10 k 1 k R3 1 k R2 R1 10 k C1 0.1 μF 100 V R7 4.7 k R8 10 k R10 6.8 k Q2 2N3903 Q1 2N3906 R6 300 k Q3 2N6027 Q5 MCR16M R9 100 k Figure 6.76. (a). rms Voltage Regulator 90 90 100 110 120 130 140 150 160 6 2 3 4 5 80 50 60 70 80 170 7 INPUT VOLTAGE (V rms) 100 OUTPUTVOLTAGE(Vrms) CONDUCTIONANGLE(ms) CONDUCTION TIME OUTPUT VOLTAGE (b). Output Voltage and Conduction Angle versus Input Voltage TRIAC ZERO-POINT SWITCH APPLICATIONS BASIC TRIAC ZERO-POINT SWITCH Figure 6.77 shows a manually controlled zero-point switch useful in power control for resistive loads. Opera- tion of the circuit is as follows. On the initial part of the positive half cycle, the voltage is changing rapidly from zero causing a large current flow into capacitor C2. The current through C2 flows through R4, D3, and D4 into the gate of the TRIAC Q2 causing it to turn on very close to zero voltage. Once Q2 turns on, capacitor C3 charges to the peak of the line voltage through D5. When the line voltage passes through the peak, D5 becomes reverse-biased and C3 begins to discharge through D4 and the gate of Q2. At this time the voltage on C3 lags the line voltage. When the line voltage goes through zero there is still some charge on C3 so that when the line voltage starts negative C3 is still discharging into the gate of Q2. Thus Q2 is also turned on near zero on the negative half cycle. This operation continues for each cycle until switch S1 is closed, at which time SCR Q1 is turned on. Q1 shunts the gate current away from Q2 during each positive half cycle keeping Q2 from turning on. Q2 cannot turn on during the negative cycle because C3 cannot charge unless Q2 is on during the positive half cycle. If S1 is initially closed during a positive half cycle, SCR Q1 turns on but circuit operation continues for the rest of the complete cycle and then turns off. If S1 is closed during a negative half cycle, Q1 does not turn on because it is reverse biased. Q1 then turns on at the beginning of the positive half cycle and Q2 turns off. Zero-point switching when S1 is opened is ensured by the characteristic of SCR Q1. If S1 is opened during the positive half cycle, Q1 continues to conduct for the entire half cycle and TRIAC Q2 cannot turn on in the middle of the positive half cycle. Q2 does not turn on during the negative half cycle because C3 was unable to charge during the positive half cycle. Q2 starts to conduct at the first complete positive half cycle. If S1 is opened during the negative half cycle, Q2 again cannot turn on until the beginning of the positive half cycle because C3 is uncharged. A 3-volt gate signal for SCR Q1 is obtained from D1, R1, C1, and D6.
- 137. http://onsemi.com 137 115 VAC 60 Hz C3 1 μF 200 V R5 1 k 2 W C2 2 μF 200 V D4 1N4001 LOAD + Q2 2N6346 + S1 R3 1.2 k 7 W + D6 1N4372 R2 10 k D1 1N4003 R1 12 k 2 W D3 1N4003 Q1 MCR1906-4 D2 1N4003 D5 1N4003 R4 150 Ω 1 W C1 10 μF 5 V Figure 6.77. Zero-Point Switch AN INTEGRATED CIRCUIT ZERO VOLTAGE SWITCH A single CA3059/79 integrated circuit operating directly off the ac line provides the same function as the discrete circuit shown in Figure 6.77. Figure 6.78 shows its block diagram. The circuit operates a power triac in quadrants one and four, providing gate pulses synchronized to the zero voltage point of the ac cycle. This eliminates the RFI resulting from the control of resistive loads like heaters and flashing lamps. Table 6.12 specifies the value of the input series resistor for the operating line voltage. Figure 6.79 shows the pin connection for a typical application. RX − + 15 V ON/OFF SENSING AMP 100 μF AC INPUT 12 ZERO CROSSING DETECTOR 5RS 11 CURRENT BOOST LIMITER 10 9 13 POWER SUPPLY VCC TRIAC DRIVE DC MODE or 400 Hz INPUT VCC RL MT2 AC INPUT VOLT- AGE 3 4 GATE 2 GND + 7 8 1 INHIBIT EXTERNAL TRIGGER *NTC SENSOR VCC MT1 6 14 − PROTECTION CIRCUIT RP Figure 6.78. Functional Block Diagram *
- 138. http://onsemi.com 138 R1 5 k R2 5 k + 120 Vrms 60 Hz 100 μf 15 V RL CA3059 RS 10 k T2800D ON OFF 2 3 8 11109 13 14 4 5 7 Figure 6.79. Zero Voltage Switch Using CA3059 Integrated Circuit Table 6.12. AC Input Voltage (50/60 Hz) vac Input Series Resistor (RS) kΩ Dissipation Rating for RS W 24 120 208/230 277 2.0 10 20 25 0.5 2.0 4.0 5.0 TEMPERATURE CONTROL WITH ZERO-POINT SWITCHING ZERO VOLTAGE SWITCH PROPORTIONAL BAND TEMPERATURE CONTROLLER Figure 6.80 shows the block diagram for the UAA1016B integrated circuit temperature controller. Figure 6.81 shows a typical application circuit. This device drives triacs with a zero voltage full wave technique allowing RFI free power regulation of resistive loads and adjustable burst frequency to comply with standards. It operates directly off the ac line triggers the triac in Q2 and Q3, is sensor fail-safe, and provides proportional temperature control over an adjust- able band. Consult the device data sheet (DS9641) for detailed information. LOAD 220 VAC 8 220 VAC 2 CPin RSYNC2 − 6 + + R4 1.0 M VREF 5 − VCC 1 (NTC) TEMP. SENSOR RL 180 k 4 FAIL-SAFETEMP. SET 3 R2R1 R3 7 MAC224-8 PULSE AMPLIFIER SAMPLING FULL WAVE LOGIC SAWTOOTH GENERATOR COMPARATOR UAA1016B SYNCHRO- NIZATION POWER SUPPLY R2 R3 Figure 6.80. UA1016B Block Diagram and Pin Assignment DVREF + DVPin 1 R4 R2 || R3 ) 1 Design Notes: 1. Let R4 q 5RL 2. Select Ratio for a symmetrical reference deviation centered about Pin 1 output swing, R2 will be slightly greater than R3. 3. Select R2 and R3 values for the desired reference deviation where
- 139. http://onsemi.com 139 6.8 k RT : NTC R @ 25°C = 22 k 10% B = 3700 MOV: 250 VAC VARISTOR 220 VAC 100 Ω 0.1 μF 50 k 22 k 6.8 k 3 RT R4 RL 47 μF 8.0 V + 2 HEATER 2.0 kW + 100 μF 7 UAA1016B 100 k 18 k 1N4005 6 MAC224-8 2.0 W 58 1 4 Figure 6.81. Application Circuit — Electric Radiator with Proportional Band Thermostat, Proportional Band 1°C at 25°C MOV TRIAC RELAY-CONTACT PROTECTION A common problem in contact switching high current is arcing which causes erosion of the contacts. A solution to this problem is illustrated in Figure 6.82. This circuit can be used to prevent relay contact arcing for loads up to 50 amperes. There is some delay between the time a relay coil is energized and the time the contacts close. There is also a delay between the time the coil is de-energized and the time the contacts open. For the relay used in this circuit both times are about 15 ms. The TRIAC across the relay contacts will turn on as soon as sufficient gate current is present to fire it. This occurs after switch S1 is closed but before the relay contacts close. When the contacts close, the load current passes through them, rather than through the TRIAC, even though the TRIAC is receiving gate current. If S1 should be closed during the negative half cycle of the ac line, the TRIAC will not turn on immediately but will wait until the voltage begins to go positive, at which time diode D1 conducts providing gate current through R1. The maximum time that could elapse before the TRIAC turns on is 8-1/3 ms for the 60 Hz supply. This is adequate to ensure that the TRIAC will be on before the relay contact closes. During the positive half cycle, capacitor C1 is charged through D1 and R2. This stores energy in the capacitor so that it can be used to keep the TRIAC on after switch S1 has been opened. The time constant of R1 plus R2 and C1 is set so that sufficient gate current is present at the time of relay drop-out after the opening of S1, to assure that the TRIAC will still be on. For the relay used, this time is 15 ms. The TRIAC therefore limits the maximum voltage, across the relay contacts upon dropout to the TRIAC’s voltage drop of about 1 volt. The TRIAC will conduct until its gate current falls below the threshold level, after which it will turn off when the anode current goes to zero. The TRIAC will conduct for several cycles after the relay contacts open. This circuit not only reduces contact bounce and arcing but also reduces the physical size of the relay. Since the relay is not required to interrupt the load current, its rating can be based on two factors: the first is the rms rating of the current-carrying metal, and the second is the contact area. This means that many well-designed 5 ampere relays can be used in a 50 ampere load circuit. Because the size of the relay has been reduced, so will the noise on closing. Another advantage of this circuit is that the life of the relay will be increased since it will not be subjected to contact burning, welding, etc. The RC circuit shown across the contact and TRIAC (R3 and C2) is to reduce dv/dt if any other switching element is used in the line.
- 140. http://onsemi.com 140 115 VAC 60 Hz R1 1.5 k 10 W C1 20 μF 250 V + 115 V RELAY WITH PICK- UP AND DROP-OUT TIMES OF 10-20 ms 50 AMP LOAD D1 1N4004 MAC210A8 47 R2 10 10 W R3 S1 C2 0.1 μF Figure 6.82. TRIAC Prevents Relay Contact Arcing AN AUTOMATIC AC LINE VOLTAGE SELECTOR USING THE MC34161 AND A TRIAC Line operated switching regulators run off of 120 or 240 VAC by configuring the main reservoir input capacitor filter as a full-wave doubler or full-wave bridge. This integrated circuit provides the control signals and trigger- ing for a TRIAC to automatically provide this function. Channel 1 senses the negative half cycles of the AC line voltage. If the line voltage is less than 150 V, the circuit will switch from bridge mode to voltage doubling mode after a preset time delay. The delay is controlled by the 100 kΩ resistor and the 10 μF capacitor. If the line voltage is greater than 150 V, the circuit will immediately return to fullwave bridge mode. 1N 4742 0.6 V 4 10 k 3 W MAC 228A6FP 10 47 + + T 2.54 V REFERENCE 3.0 A MR506 10 k 1.2 k 220 250 V B+ + 75 k 220 250 V RTN 75 k INPUT 92 TO 276 VAC +8 100 k 1.6 M 10 k 1.27 V 1.27 V 6 1 7 2 3 + − + + + − 5 + + + − − 2.8 V + Figure 6.83. Automatic AC Line Voltage Selector
- 141. © Semiconductor Components Industries, LLC, 1999 August, 1999 − Rev. 2 141 Publication Order Number: AN1045/D AN1045/D Series Triacs In AC High Voltage Switching Circuits By George Templeton Thyristor Applications Engineer INTRODUCTION Edited and Updated This paper describes the series connection of triacs to create a high voltage switch suitable for operation at volt- ages up to 2000 Volts. They can replace electromechanical contactors or extend their current rating and lifetime. Motor starters and controllers operating at line voltages of 240 Volts or more require high-voltage switches. Transformer action and resonant snubber charging result in voltages much greater than the peak of the line. Triacs can be sub- jected to both commutating and static dV/dt when multiple switching devices are present in the circuit. Snubber designs to prevent static dV/dt turn-on result in higher volt- ages at turn-off. Variable load impedances also raise volt- age requirements. The benefits of series operation include: higher blocking voltage, reduced leakage, better thermal stability, higher dV/dt capability, reduced snubber costs, possible snubber- less operation, and greater latitude in snubber design. The advantages of triacs as replacements for relays include: • Small size and light weight • Safety — freedom from arcing and spark initiated explosions • Long lifespan — contact bounce and burning eliminated • Fast operation — turn-on in microseconds and turn-off in milliseconds • Quiet operation Triacs can be used to replace the centrifugal switch in capacitor start motors. The blocking voltage required of the triac can be much greater than the line voltage would sug- gest. It must block the vector sum of the line, auxiliary winding, and start capacitor voltage. This voltage increases when triac turn-off occurs at higher rpm. TRIGGERING Figure 1 illustrates a series thyristor switching circuit. In this circuit, the top triac triggers in Quadrant 1 when the bottom triac triggers in Quadrant 3. When the optocoupler turns on, gate current flows until the triacs latch. At that time, the voltage between the gate terminals drops to about 0.6 Volts stopping the gate current. This process repeats each half cycle. The power rating of the gate resistor can be small because of the short duration of the gate current. Optocoupler surge or triac gate ratings determine the mini- mum resistance value. For example, when the maximum optocoupler ITSM rating is 1 A: Rg u+ VpeakńImax (1.0) Rg + 750 Vń1 A + 750 Ohm The triacs retrigger every half cycle as soon as the line voltage rises to the value necessary to force the trigger cur- rent. The instantaneous line voltage V is V + IGT Rg ) 2 VGT ) 2 VTM (1.1) where VGT, IGT are data book specifications for the triac and VTM is the on-voltage specification for the optocoupler. The phase delay angle is qd + SIN*1ƪ V 2Ǹ VLINE ƫ (1.2) http://onsemi.com APPLICATION NOTE
- 142. AN1045/D http://onsemi.com 142 ΔI 3 σ 6 σ 3 σ 6 σ DESIGN CAPABILITY PROCESS WIDTH MEAN MT1 MT1 MT2 MT2 IG RG G IL G Figure 6.1. Series Switch Figure 6.2. Designing for Probable Leakage STATIC VOLTAGE SHARING Maximum blocking voltage capability results when the triacs share voltage equally. The blocking voltage can be dc or ac. A combination of both results when the triac switches the start winding in capacitor start motors. In the simple series connection, both triacs operate with an identical leak- age current which is less than that of either part operated alone at the same voltage. The voltages across the devices are the same only when their leakage resistances are identi- cal. Dividing the voltage by the leakage current gives the leakage resistance. It can range from 200 kohm to 2000 megohm depending on device characteristics, temperature, and applied voltage. Drawing a line corresponding to the measured series leakage on each device’s characteristic curve locates its operating point. Figure 3a shows the highest and lowest leakage units from a sample of 100 units. At room tempera- ture, a leakage of 350 nA results at 920 Volts. The lowest leakage unit blocks at the maximum specified value of 600 Volts, while the highest blocks 320 Volts. A 50 percent boost results. Figure 3b shows the same two triacs at rated TJmax. The magnitude of their leakage increased by a factor of about 1000. Matching between the devices improved, allowing operation to 1100 Volts without exceeding the 600 Volt rat- ing of either device. Identical case temperatures are necessary to achieve good matching. Mounting the devices closely together on a common heatsink helps. A stable blocking condition for operation of a single triac with no other components on the heatsink results when dIMT dTJ @ dTJ dPJ @ dPJ dIMT t 1 (2.0) Thermal run-away is a regenerative process which occurs whenever the loop gain in the thermal feedback circuit reaches unity. An increase in junction temperature causes increased leakage current and higher power dissipation. Higher power causes higher junction temperature which in turn leads to greater leakage. If the rate of heat release at the junction exceeds the rate of removal as temperature increases, this process repeats until the leakage current is sufficient to trigger the thyristor on. DC blocking simplifies analysis. A design providing stable dc operation guarantees ac performance. AC opera- tion allows smaller heatsinks. The last term in the stability equation is the applied volt- age when the load resistance is low and the leakage causes negligible voltage drop across it. The second term is the thermal resistance from junction to ambient. The first term describes the behavior of leakage at the operating condi- tions. For example, if leakage doubles every 10°C, a triac operating with 2 mA of leakage at 800 Vdc with a 6°C/W thermal resistance is stable because 2 mA 10°C @6°C W @800 V + 0.96 Operating two triacs in series improves thermal stability. When two devices have matched leakages, each device sees half the voltage and current or 1/4 of the power in a single triac. The total leakage dissipation will approach half that of a single device operated at the same voltage. The addi- tional voltage margin resulting from the higher total block- ing voltage reduces the chance that either device will oper- ate near its breakdown voltage where the leakage current increases rapidly with small increments in voltage. Higher voltage devices have lower leakage currents when operated near breakdown. Consequently, the highest breakover volt- age unit in the pair will carry the greatest proportion of the burden. If the leakage current is large enough to cause sig- nificant changes in junction temperature, (ΔTJ = φJC PD), the effect will tend to balance the voltage division between the two by lowering the leakage resistance of the hotter unit. If the leakage mismatch between the two is large, nearly all the voltage will drop across one device. As a result there will be little benefit connecting two in series. Series blocking voltage depends on leakage matching. Blocking stability depends on predictable changes in leak- age with temperature. Leakage has three components.
- 143. AN1045/D http://onsemi.com 143 (a) (b) HIGH ΔIL LOW HIGH LOW 100 V/ 100 nA/ 25°C 100 V/ 100 μA/ 125°C Figure 6.3. Leakage Matching versus Temperature Surface Leakage Passivation technique, junction design, and cleanliness determine the size of this component. It tends to be small and not very dependent on temperature. Diffusion Leakage Measurements with 1 volt reverse bias show that this component is less than 10 percent of the total leakage for allowed junction temperatures. It follows an equation of the form: I T e*(qvńkT) (2.1) and doubles about every 10°C. Its value can be estimated by extrapolating backward from high temperature data points. Depletion Layer Charge Generation This component is a result of carriers liberated from within the blocking junction depletion layer. It grows with the square root of the applied voltage. The slope of the leak- age versus applied voltage is the mechanism allowing for series operation with less than perfect leakage matching. Predictable diffusion processes determine this leakage. At temperatures between 70 and 150°C it is given by: i T e * E kT (2.2) where E = 1.1 eV, k = 8.62E − 5 eV/k, T = degrees Kelvin, and k = 8.62 x 10−5 eV/k. It is useful to calculate the percentage change in leakage current with temperature: A + 1 i di dTJ + E kT2 + 0.08 + 8% °C The coefficient A was evaluated on 3 different die size triacs by curve fitting to leakage measurements every 10° from 70 to 150°C. Actual values measured 0.064 at 125° and 0.057 at 150°. Deviations from this behavior will result at voltages and temperatures where leakage magnitude, current gain, and avalanche multiplication aid unwanted turn-on. Sensitive gate triacs are not recommended for this reason. DERATING AND LEAKAGE MATCHING Operation near breakdown increases leakage mismatch because of the effects of avalanche multiplication. For series operation, devices should be operated at least 100 Volts below their rating. 18 1.61.51.41.31.21.110.80.7 0.9 2 4 6 8 10 12 16 14 0.6 20 550 V TJ = 25°C 650 V PERCENT(SAMPLESIZE=100) Figure 6.4. Normalized Leakage (Mean = 1.0) Figure 4 shows the leakage histogram for a triac sample operated at two different voltages. The skewedness in the high-voltage distribution is a consequence of some of the sample operating near breakdown.
- 144. AN1045/D http://onsemi.com 144 HEATSINK SELECTION Solving equations (2.0) and (2.3) for the thermal resis- tance required to prevent runaway gives: θJA t 1 A@V@i (3.0) where θJA is thermal resistance, junction to ambient, in °C/W, A = 0.08 at TJ = 125°C, V = rated VDRM, and i = rated IDRM. θJA must be low enough to remove the heat resulting from conduction losses and insure blocking stability. The latter can be the limiting factor when circuit voltages are high. For example, consider a triac operated at 8 amps (rms) and 8 Watts. The allowed case temperature rise at 25° ambient is 85°C giving a required θCA (thermal resistance, case to ambient) of 10.6°C/W. Allowing 1°C/W for θCHS (thermal resistance, case to heatsink) leaves 9.6°C/W for θSA (thermal resistance, heatsink to ambient). However, thermal stability at 600 V and 2 mA IDRM requires θJA = 10.4°C/W. A heatsink with θSA less than 7.4°C/W is needed, given a junction to case thermal resistance of 2°C/W. The operation of devices in series does not change the coefficient A. When matching and thermal tracking is per- fect, both devices block half the voltage. The leakage cur- rent and power divide by half and the allowed θJA for blocking stability increases by 4. Low duty cycles allow the reduction of the heatsink size. The thermal capacitance of the heatsink keeps the junction temperature within specification. The package time constant (Cpkg RθJA) is long in comparison with the thermal response time of the die, causing the instantaneous TJ to rise above the case as it would were the semiconductor mounted on an infinite heatsink. Heatsink design requires estimation of the peak case temperature and the use of the thermal derating curves on the data sheet. The simplest model applies to a very small heatsink which could be the semicondutor package itself. When θSA is large in compari- son with θCHS, it is sufficient to lump both the package and heatsink capacitances together and treat them as a single quantity. The models provide good results when the heat- sink is small and the thermal paths are short. Model C, Figure 5 is a useful simplification for low duty cycle applications. Increasing heatsink mass adds thermal capacitance and reduces peak junction temperature. Heat- sink thermal resistance is proportional to surface area and determines the average temperature. qSA + 32.6 A(*0.47) (3.1) where A = total surface area in square inches, θSA = thermal resistance sink to ambient in °C/W. Analysis of heatsink thermal response to a train of peri- odic pulses can be treated using the methods in ON Semiconductor application note AN569 and Figure 6. For example:
- 145. AN1045/D http://onsemi.com 145 In Circuit (B): The steady state case temperature is given by To account for thermal capacity, a time dependent factor r(t) is applied to the steady state case-to-ambient thermal resis- tance. The package thermal resistance, at a given on-time, is called transient thermal resistance and is given by: In terms of measurable temperatures: In model (b.) this is Use simplified model C when (5.2) DTCpk + DTCSS(1 * e*tonńt) where DTCpk + TCpk * TA DTCSS + TCSS * TA (5.3) r(ton) + DTCpk DTCSS (5.5) CPKG + * ton (θCA In (1 * r(ton)) ton tt t DTCpk tt DTCSS (5.6) TC + Pd ton CPKG ) TA (5.0) TCSS + Pd qCA ) TA in °C (5.1) t + qCA CPKG, seconds where Pd = Applied average power, watts θCA = Case to ambient thermal resistance, °C/W TA = ambient temperature, °C The package rises toward the steady state temperature expo- nentially with time constant where Cpkg = HM, Joules/°C H = Specific heat, calories/(gm S °C) M = Mass in grams and 1 Calorie = 4.184 Joule 1 Joule = 1 Watt S Sec The case temperature rise above ambient at the end of power pulse is: RqCA (ton) + r(ton) qCA where r(ton) = Unitless transient thermal impedance coefficient. (5.4) r(ton) + (1 * e *tonńt) ton Pd CPKG θCA TC TA (a.) Standard Thermal Analogue For a Thyristor in Free Air (b.) Equivalent Circuit For (a) θCA Pd θCA TA CPKG TC (c.) Simplified Model Pd CPKG TC TA Solving 5-4 for the package capacitance gives Figure 6.5. Transient Thermal Response For a Single Power Pulse
- 146. AN1045/D http://onsemi.com 146 Assume the case temperature changes by 40°C for a single power pulse of 66.67 W and 3 s duration. Then from equation (5.6): Cpkg + (66.7 Watts) (3 seconds) 40°C + 5 Joules °C The heatsink thermal resistance can be determined by applying dc power, measuring the final case temperature, and using equation (5.0). TC * TA PD + 175-25 5 + 30°CńW The application requires a 3 s on-time and 180 s period at 66.7 W. Then Pavg + (66.7 W) (3ń180) + 1.111 W Where Δ TC (N + 1) = maximum rise above ambient Pd = applied average power within a pulse PAV G = average power within a period r(ton + tp) = time dependent factor for sum of ton and tp r(ton) = time dependent factor for ton r(tp) = time dependent factor for tp DTC (N ) 1) + [PAVG ) (Pd * PAVG) r(ton ) tp) ) Pd r(ton) * Pd r(tp)]qCA tp PAVG ton Nth PULSE N + 1 PULSE Pd 0 Figure 6.6. Steady State Peak Case Temperature Rise Using equation (5.3), the theoretical steady state case temperature rise is: TCSS * TA + (66.7 W) (30°CńW) + 2000°C and R(ton) + R (3 s) + (40°C measured rise)ń2000+ 0.02 From equation (5.4) and (5.1): R (Tp) + (1 * e*180ń150) + .6988 R (ton ) Tp) + (1 * 1*183ń150) + .7047 Then from Figure 6: delta TC = (1.111 + 46.225 + 1.333 − 46.61) 30 = 61.8°C If the ambient temperature is 25°C, TC = 87°C. COMPENSATING FOR MAXIMUM SPECIFIED LEAKAGE Identical value parallel resistors around each triac will prevent breakdown resulting from mismatched leakages. Figure 7 derives the method for selecting the maximum allowed resistor size. A worst case design assumes that the series pair will operate at maximum TJ and that one of the triacs leaks at the full specified value while the other has no leakage at all. A conservative design results when the toler- ances in the shunt resistors place the highest possible resis- tor across the low leakage unit and the lowest possible resistor around the high leakage unit. This method does not necessarily provide equal voltage balancing. It prevents triac breakover. Perfect voltage shar- ing requires expensive high-wattage resistors to provide large bleeder currents. V1 + VSR1 R1 ) R2 ) DILR1R2 R1 ) R2 Let R1 = R (1 + p) and R2 = R (1−p) where R = Nominal resistor value p = 0.05 for 5% tolerance, etc. R x 2 VDRM * VS (1 ) p) DIL (1 * p2) Worst case becomes: and IDRM (T1) = 0; IDRM (T2) = Spec. max. value ΔIL = Spec. Max. Value IDRM (T2) IDRM (T1) R1 T1 ΔIL T2 VS I1 R2 I2 V1 Figure 6.7. Maximum Allowed Resistor for Static Voltage Sharing
- 147. AN1045/D http://onsemi.com 147 COMPENSATION FOR PROBABLE LEAKAGE Real triacs have a leakage current greater than zero and less than the specified value. Knowledge of the leakage distribu- tion can be used to reduce resistor power requirements. The first step is to statistically characterize the product at maxi- mum temperature. Careful control of the temperature is criti- cal because leakage depends strongly on it. The process width is the leakage span at plus or minus 3 standard deviations (sigma) from the mean. To minimize the probability of out of spec parts, use a design capability index (Cp) of 2.0. Cp + (design DI)ń(process width) (4.0) Cp + (12 sigma)ń(6 sigma) Figure 2 and Figure 7 describe this. Substituting delta IL at 6 sigma in Figure 7 gives the resistor value. The required power drops by about 4. Theoretically there would be no more than 3.4 triacs per million exceeding the design tolerance even if the mean value of the leakage shifted by plus or minus 1.5 sigma. SELECTING RESISTORS Small resistors have low voltage ratings which can impose a lower constraint on maximum voltage than the triac. A common voltage rating for carbon resistors is: Rated Power (W) Maximum Voltage (V) 1/4 Watt 250 Volts 1/2 350 1 500 2 750 Series resistors are used for higher voltage. Let VDRM + E Rmax Rmax ) Rmin E + VDRM ǒ1 ) Imin Imax Ǔ Rmax + VDRM Imin Rmin + VDRM Imax (8.0) ACTUAL TRIACI E Rmin Rmax (a) Equivalent Circuit (b) Model VDRM VMT2 − 1 MODEL TRIAC IDRM Figure 6.8. Maximum Voltage Sharing Without Shunt Resistor OPERATION WITHOUT RESISTORS Figure 8 derives the method for calculating maximum operating voltage. The voltage boost depends on the values of Imin and Imax. For example : ǒ1 ) 131 mA 683 mA Ǔ+ 1.19 A 19 percent voltage boost is possible with the 6 sigma design. Testing to the measured maximum and minimum of the sample allows the boost to approach the values given in Table 1. (1 ) 0.835ń1.228) + 1.68 Table 1. Normalized leakage and voltage boost factor. (Mean = 1.0) Voltage (V) 550 650 550 550 550 550 550 TJ (°C) 25 25 100 125 125 150 150 Rshunt — — — — 1.5M 1.5M 510K Sample Size 100 100 16 16 16 16 16 Maximum 1.31 5 1.59 1 1.18 7 1.22 8 1.12 3 1.34 6 1.18 6 Minimum 0.72 9 0.68 1 0.84 0 0.83 5 0.92 0 0.82 0 0.87 7 Sigma 0.116 0.17 2 0.10 6 0.113 0.05 5 0.13 2 0.08 4 Sample Boost 1.55 1.43 1.71 1.68 1.82 1.61 1.74 6 Sigma Boost 1.18 1.00 1.22 1.19 1.50 1.12 1.33
- 148. AN1045/D http://onsemi.com 148 COMPENSATING FOR SURFACE LEAKAGE A small low power shunt resistance will provide nearly per- fect low temperature voltage sharing and will improve high temperature performance. It defines the minimum leakage current of the parallel triac-resistor combination. The design method in Figure 8 can be used by adding the resistor current to the measured maximum and minimum leakage currents of the triac sample. This is described in Table 1. SERIES ǒdV dt Ǔ s The series connection will provide twice the ǒdV dt Ǔ s capability of the lowest device in the pair (Figure 9). Dynamic matching without a snubber network depends on equality of the thyristor self capacitance. There is little variation in junction capacitance. Device gain variations introduce most of the spread in triac performance. The blocking junction capacitance of a thyristor is a declining function of dc bias voltage. Mismatch in static blocking voltage will contribute to unequal capacitances. However, this effect is small at voltages beyond a few volts. The attachment of a heatsink at the high-impedance node formed by connection of the triac main-terminals can also contribute to imbalance by introducing stray capacitance to ground. This can be made insignificant by adding small capacitors in parallel with the triacs. Snubbers will serve the same purpose. 100 1 R = 270 kΩ C = 1000 pF Vpk = 1000 V R C 135 2 2 3 4 5 6 7 8 8 9 1 1000 2 3 4 5 6 7 9 0 10,000 453015 60 75 90 105 150120 JUNCTION TEMPERATURE (TJ) °C R C EXPONENTIALSTATICdv/dtS(V/s)μ Figure 6.9. Exponential Static dV/dt, Series MAC15-8 Triacs Triacs can tolerate very high rates of voltage rise when the peak voltage magnitude is below the threshold needed to trigger the device on. This behavior is a consequence of the voltage divider action between the device collector and gate-cathode junction capacitances. If the rise-time is made short in comparison with minority carrier lifetime, voltage and displaced charge determine whether the device triggers on or not. Series operation will extend the range of voltage and load conditions where a static dV dt snubber is not needed. Figure 10 graphs the results of measurements on two series connected triacs operated without snubbers. The series connection doubled the allowed step voltage. How- ever, this voltage remained far below the combined 1200 V breakover voltage of the pair. TJ (°C) 700 600 500 400 300 200 100 0 800 0 16014012010020 40 60 80 V dV dt u 10 kVńms MAXIMUMSTEPVOLTAGE(V) f = 10 Hz pw = 100 μs Figure 6.10. Step Blocking Voltage VS TJ (Unsnubbed Series Triacs) Exponential ǒdV dt Ǔ s tests performed at 1000 V and less than 2 kV/μs showed that turn-on of the series pair can occur because of breakdown or dV dt . The former was the limiting factor at junction temperatures below 100°C. Per- formance improved with temperature because device gain aided voltage sharing. The triac with the highest current gain in the pair is most likely to turn-on. However, this device has the largest effective capacitance. Consequently it is exposed to less voltage and dV dt . At higher tempera- tures, rate effects dominated over voltage magnitudes, and the capability of the series pair fell. dV dt performance of the series devices was always better than that of a single triac alone. TURNOFF Process tolerances cause small variations in triac turn-off time. Series operation will allow most of the reapplied blocking voltage to appear across the faster triac when a dynamic voltage sharing network is not used.
- 149. AN1045/D http://onsemi.com 149 Figure 11 describes the circuit used to investigate this behavior. It is a capacitor discharge circuit with the load series resonant at 60 Hz. This method of testing is desirable because of the reduced burn and shock hazard resulting from the limited energy storage in the load capacitor. The triacs were mounted on a temperature controlled hotplate. The single pulse non-repetitive test aids junction temperature control and allows the use of lower power rated components in the snubber and load circuit. CL 15K + (b) Optocoupler Gate Circuit S1 = GORDES MR988 REED WOUND WITH 1 LAYER AWG #18 LL = 320 MHY CL = 24 μFD, NON-POLAR REVERSE S4 AND VCC TO CHECK OPPOSITE POLARITY. MT1, T1 510 S4B S4A 15K 2W MOC3081 1N4001 G1 2.2 Meg 2.2 Meg G2 910 510 CL 2W PEARSON 301X 1−PROBE G1 MT1 MT2 T1 T2MT2 G2 MT1 LL S2 Hg RELAY (c) Load Circuit CL 270K 2W VCC 1.5 kV S3 (a) Triac Gate Circuit G1 13K G2 S1 910 1/2W 11 Ω 2W PUSH TO TEST − 100 V + S1 20 μF 200 V MOC3081 270K 2W Rs Cs Cs Rs MT1, T2 TRIADC30X50H,3500Ω Figure 6.11. Test CircuitǒdV dt Ǔc Snubberless turn-off at 1200 V and 320 milli-henry resulted in 800 V peak and 100 V/μs. Although this test exceeded the ratings of the triacs, they turned off success- fully. Snubberless operation is allowable when: 1. The total transient voltage across both triacs does not exceed the rating for a single device. This voltage depends on the load phase angle, self capacitance of the load and triac, damping constant, and natural res- onance of the circuit. 2. The total ǒdV dt Ǔ c across the series combination does not exceed the capability of a single device. Maximum turn-off voltage capability and tolerance for variable loads requires the use of a snubber network to pro- vide equal dynamic voltage sharing. Figure 12 and Figure 13 derives the minimum size snubber capacitor allowed. It is determined by the recovery charge of the triac. Measurements in fast current crossing applications suggest that the reverse recovery charge is less than 2 micro-coulombs. Recovery currents cannot be much greater than IH or IGT, or the triac would never turn-off. Recovery can be forward, reverse, or near zero current depending on conditions. Snubber design for the series switch has the following objectives: • Controlling the voltage peak. Resonant charging will magnify the turn-off voltage. • Controlling the voltage rate. Peak voltage trades with voltage rate. • Equalizing the voltage across the series devices by providing for imbalance in turn-off charge. Designs that satisfy the first two objectives will usually provide capacitor values above the minimum size. Select the snubber for a satisfactory compromise between voltage and dV dt . Then check the capacitor to insure that it is suffi- ciently large.
- 150. AN1045/D http://onsemi.com 150 where C = Nominal value of capacitor and p = 0.1 for 10% tolerance, etc. ΔQ = Reverse recovery charge Note that T1 has no charge while T2 carries full recovery charge. For the model shown above, VS + Q1 C1 ) Q2 C2 + Q1 C(1 * p) ) Q1 * DQ C(1 ) p) C y DQ 2 VDRM * VS(1 ) p) Worst case: C2 + C(1 ) p); C1 + C(1 * p); Q1 + 0; Q2 + DQ t (dv/dt)c VMT2-1 AND IMT2 φ VMT2-1 ΔQ IRRM ΔQ Q+ Δ Q Q1 VDRM V2 Q2 C2 C1 Q T1 T2 VS ǒdI dt Ǔc Figure 6.12. Minimum Capacitor Size for Dynamic Voltage Sharing Snubber designs for static, commutating, and combined dV dt stress are shown in Table 2. Circuits switching the line or a charged capacitor across a blocking triac require the addition of a series snubber inductor. The snubber must be designed for maximum dV dt with the minimum circuit inductance. This contraint increases the required triac blocking voltage. Table 2. Snubber Designs Type ǒdV dt Ǔ c ǒdV dt Ǔ s Both L (mh) 320 0.4 320 RL Ohm 8 0 8 Rs Ohm 1820 48 48 Cs (μf) 0.5 0.5 0.5 Damping Ratio 1.14 0.85 .035 Vstep (V) 1200 1200 750 Vpk (V) 1332 1400 1423 tpk (μs) 768 29.8 1230 (V/μs)dV dt 4.6 103 1.3 Note: Divide Rs and by 2, multiply Cs by 2 for each triac.dV dt dl dt CAPABILITY The hazard of thyristor damage by dl dt overstress is greater when circuit operating voltages are high because dl dt is proportional to voltage. Damage by short duration tran- sients is possible even though the pulse is undetectable when observed with non-storage oscilloscopes. This type of damage can be consequence of snubber design, tran- sients, or parasitic capacitances. A thyristor can be triggered on by gate current, exceeding its breakdown voltage, or by exceeding its ǒdV dt Ǔ s capabili- ty. In the latter case, a trigger current is generated by charg- ing of the internal depletion layer capacitance in the device. This effect aids turn-on current spreading, although dam- age can still occur if the rate of follow on dl dt is high. Repeti- tive operation off the ac line at voltages above breakdown is a worst case condition. Quadrant 3 has a slightly slower gated turn-on time, increasing the chance of damage in this direction. Higher operating voltages raise power density and local heating, increasing the possibility of die damage due to hot-spots and thermal run-away. 1K 2W CARBON PEARSON 411I PROBE MT1 MT2 MT2 MT1 G *S1 G L T106-6 QTY = 6 TO 16 MKP1V130 C NON-INDUCTIVE 0−6 kV 1/2A 60 Hz RRE1 5K 200W Vci V C μFD L μHY R Ω dl/dt A/μs Rejects Tested 1000 4.06 3.4 5.7 100 0/100 1900* 1.05 7.9 5.7 179 0/195 1500 0.002 0.3 10 3000 3/10 * Open S1 to test breakover dl/dt Figure 6.13. dl/dt Test Circuit
- 151. AN1045/D http://onsemi.com 151 Ideally, turn-on speed mismatch should not be allowed to force the slower thyristor into breakdown. An RC snubber across each thyristor prevents this. In the worst case, one device turns on instantly while the other switches at the slowest possible turn-on time. The rate of voltage rise at the slower device is roughly dV dt + VIRs 2L , where VI is the maxi- mum voltage across L. This rate should not allow the volt- age to exceed VDRM in less than Tgt to prevent breakover. But what if the thyristors are operated without a snubber, or if avalanche occurs because of a transient overvoltage condition? The circuit in Figure 13 was constructed to investigate this behavior. The capacitor, resistor, and inductor create a pulse forming network to shape the current wave. The ini- tial voltage on the capacitor was set by a series string of sidac bidirectional breakover devices. Test results showed that operation of the triac switch was safe as long as the rate of current rise was below 200 A/μs. This was true even when the devices turned on because of breakover. However, a 0.002 μf capacitor with no series limiting impedance was sufficient to cause damage in the Q3 firing polarity. Circuit malfunctions because of breakover will be tem- porary if the triac is not damaged. Test results suggest that there will be no damage when the series inductance is suffi- cient to hold dl/dt to acceptable values. Highly energetic transients such as those resulting from lightning strikes can cause damage to the thyristor by I2t surge overstress. Device survival requires the use of voltage limiting devices in the circuit and dV dt limiting snubbers to prevent unwanted turn-on. Alternatively, a large triac capable of surviving the surge can be used. DQ for turn-off at I H DQ + ŕ t2 t1 Ipk SINwt dt + Ipk w (cos wt1 * cos wt2) IH1 + Ipk Sinwt1 thus t1 + 1 w Sin*1 IH1 Ipk Worst case : IH2 + 0; f2 + wt2 + p DQ + Ipk w (1 ) cos[SIN*1 IH1 Ipk ]) DQ + Ipk wȧ ȡ Ȣ 1 ) I * ǒIH1 Ipk Ǔ 2 Ǹ ȧ ȣ Ȥ IH2 T1 ΔQ T2 IH1 ωt = 0 t1 t2 lpk Δ Q Figure 6.14. Forward Recovery Charge for Turn-Off at lH
- 152. © Semiconductor Components Industries, LLC, 1999 August, 1999 − Rev. 2 152 Publication Order Number: AN1048/D AN1048/D RC Snubber Networks For Thyristor Power Control and Transient Suppression By George Templeton Thyristor Applications Engineer INTRODUCTION Edited and Updated RC networks are used to control voltage transients that could falsely turn-on a thyristor. These networks are called snubbers. The simple snubber consists of a series resistor and capacitor placed around the thyristor. These components along with the load inductance form a series CRL circuit. Snubber theory follows from the solution of the circuit’s differential equation. Many RC combinations are capable of providing accept- able performance. However, improperly used snubbers can cause unreliable circuit operation and damage to the semi- conductor device. Both turn-on and turn-off protection may be necessary for reliability. Sometimes the thyristor must function with a range of load values. The type of thyristors used, circuit configuration, and load characteristics are influential. Snubber design involves compromises. They include cost, voltage rate, peak voltage, and turn-on stress. Practi- cal solutions depend on device and circuit physics. STATIC dV dt WHAT IS STATIC dV dt ? Static dV dt is a measure of the ability of a thyristor to retain a blocking state under the influence of a voltage transient. ǒdV dt Ǔ s DEVICE PHYSICS Static dV dt turn-on is a consequence of the Miller effect and regeneration (Figure 1). A change in voltage across the junction capacitance induces a current through it. This cur- rent is proportional to the rate of voltage change ǒdV dt Ǔ. It triggers the device on when it becomes large enough to raise the sum of the NPN and PNP transistor alphas to unity. Figure 6.1. ModelǒdV dt Ǔ s IA + CJ dV dt 1 * (aN ) ap) CEFF+ CJ 1*(aN)ap) IBP IJ IJ IK IBN ICN I1 I2 ICP IA TWO TRANSISTOR MODEL OF SCR CJN CJP PNP A C G CJ NE PB NB PE V tGNPN INTEGRATED STRUCTURE K A K dv dt http://onsemi.com APPLICATION NOTE
- 153. AN1048/D http://onsemi.com 153 CONDITIONS INFLUENCING ǒdV dt Ǔ s Transients occurring at line crossing or when there is no initial voltage across the thyristor are worst case. The col- lector junction capacitance is greatest then because the depletion layer widens at higher voltage. Small transients are incapable of charging the self- capacitance of the gate layer to its forward biased threshold voltage (Figure 2). Capacitance voltage divider action between the collector and gate-cathode junctions and built- in resistors that shunt current away from the cathode emit- ter are responsible for this effect. PEAK MAIN TERMINAL VOLTAGE (VOLTS) 700 800 80 60 MAC 228A10 TRIAC TJ = 110°C 600500400300200 100 120 140 160 20 1000 180 40 STATIC(V/s)μdV dt Figure 6.2. Exponential versus Peak VoltageǒdV dt Ǔ s Static dV dt does not depend strongly on voltage for opera- tion below the maximum voltage and temperature rating. Avalanche multiplication will increase leakage current and reduce dV dt capability if a transient is within roughly 50 volts of the actual device breakover voltage. A higher rated voltage device guarantees increased dV dt at lower voltage. This is a consequence of the exponential rat- ing method where a 400 V device rated at 50 V/μs has a higher dV dt to 200 V than a 200 V device with an identical rating. However, the same diffusion recipe usually applies for all voltages. So actual capabilities of the product are not much different. Heat increases current gain and leakage, lowering ǒdV dt Ǔ s , the gate trigger voltage and noise immunity (Figure 3). Figure 6.3. Exponential versus TemperatureǒdV dt Ǔ s STATIC(V/s)μdV dt 170 150 130 110 30 50 70 90 100 115 130 14585705540 MAC 228A10 VPK = 800 V TJ, JUNCTION TEMPERATURE (°C) 25 10 ǒdV dt Ǔ s FAILURE MODE Occasional unwanted turn-on by a transient may be acceptable in a heater circuit but isn’t in a fire prevention sprinkler system or for the control of a large motor. Turn-on is destructive when the follow-on current amplitude or rate is excessive. If the thyristor shorts the power line or a charged capacitor, it will be damaged. Static dV dt turn-on is non-destructive when series imped- ance limits the surge. The thyristor turns off after a half- cycle of conduction. High dV dt aids current spreading in the thyristor, improving its ability to withstand dI dt . Breakdown turn-on does not have this benefit and should be prevented. Figure 6.4. Exponential versus Gate to MT1 Resistance ǒdV dt Ǔ s STATIC(V/s)μdV dt 20 100 1000 0 10 10,000 GATE-MT1 RESISTANCE (OHMS) MAC 228A10 800 V 110°C 40 60 80 100 120 140 RINTERNAL = 600 Ω
- 154. AN1048/D http://onsemi.com 154 IMPROVING ǒdV dt Ǔ s Static dV dt can be improved by adding an external resistor from the gate to MT1 (Figure 4). The resistor provides a path for leakage and dV dt induced currents that originate in the drive circuit or the thyristor itself. Non-sensitive devices (Figure 5) have internal shorting resistors dispersed throughout the chip’s cathode area. This design feature improves noise immunity and high tempera- ture blocking stability at the expense of increased trigger and holding current. External resistors are optional for non- sensitive SCRs and TRIACs. They should be comparable in size to the internal shorting resistance of the device (20 to 100 ohms) to provide maximum improvement. The internal resistance of the thyristor should be measured with an ohm- meter that does not forward bias a diode junction. Figure 6.5. Exponential versus Junction Temperature ǒdV dt Ǔ s STATIC(V/s)μdV dt 800 1000 1200 1400 130120110100 2000 2200 1800 1600 9080706050 600 TJ, JUNCTION TEMPERATURE (°C) MAC 15-8 VPK = 600 V Sensitive gate TRIACs run 100 to 1000 ohms. With an external resistor, their dV dt capability remains inferior to non-sensitive devices because lateral resistance within the gate layer reduces its benefit. Sensitive gate SCRs (IGT t 200 μA) have no built-in resistor. They should be used with an external resistor. The recommended value of the resistor is 1000 ohms. Higher values reduce maximum operating temperature and ǒdV dt Ǔ s (Figure 6). The capability of these parts varies by more than 100 to 1 depending on gate-cathode termination. GATE-CATHODERESISTANCE(OHMS) Figure 6.6. Exponential versus Gate-Cathode Resistance ǒdV dt Ǔ s 10 MEG 1 MEG 100 K 0.01 10010 10K 0.1 1 MCR22-006 TA = 65°C 0.001 K G A 10 V STATIC dV dt (Vńms) A gate-cathode capacitor (Figure 7) provides a shunt path for transient currents in the same manner as the resis- tor. It also filters noise currents from the drive circuit and enhances the built-in gate-cathode capacitance voltage divider effect. The gate drive circuit needs to be able to charge the capacitor without excessive delay, but it does not need to supply continuous current as it would for a resistor that increases dV dt the same amount. However, the capacitor does not enhance static thermal stability. Figure 6.7. Exponential versus Gate to MT1 Capacitance ǒdV dt Ǔ s STATIC(V/s)μdV dt GATE TO MT1 CAPACITANCE (μF) 130 120 110 100 90 80 70 60 MAC 228A10 800 V 110°C 10.10.010.001 The maximum ǒdV dt Ǔ s improvement occurs with a short. Actual improvement stops before this because of spreading resistance in the thyristor. An external capacitor of about 0.1 μF allows the maximum enhancement at a higher value of RGK.
- 155. AN1048/D http://onsemi.com 155 One should keep the thyristor cool for the highest ǒdV dt Ǔ s . Also devices should be tested in the application circuit at the highest possible temperature using thyristors with the lowest measured trigger current. TRIAC COMMUTATING dV dt WHAT IS COMMUTATING dV dt ? The commutating dV dt rating applies when a TRIAC has been conducting and attempts to turn-off with an inductive load. The current and voltage are out of phase (Figure 8). The TRIAC attempts to turn-off as the current drops below the holding value. Now the line voltage is high and in the opposite polarity to the direction of conduction. Successful turn-off requires the voltage across the TRIAC to rise to the instantaneous line voltage at a rate slow enough to prevent retriggering of the device. TIMEΦ i PHASE ANGLE i VLINE G 1 2 R L TIME VLINE MT2-1V VOLTAGE/CURRENT Figure 6.8. TRIAC Inductive Load Turn-Off ǒdV dt Ǔ c ǒdI dt Ǔ c ǒdV dt Ǔ c VMT2-1 ǒdV dt Ǔ c DEVICE PHYSICS A TRIAC functions like two SCRs connected in inverse- parallel. So, a transient of either polarity turns it on. There is charge within the crystal’s volume because of prior conduction (Figure 9). The charge at the boundaries of the collector junction depletion layer responsible for ǒdV dt Ǔ s is also present. TRIACs have lower ǒdV dt Ǔ c than ǒdV dt Ǔ s because of this additional charge. The volume charge storage within the TRIAC depends on the peak current before turn-off and its rate of zero crossing ǒdI dt Ǔ c . In the classic circuit, the load impedance and line frequency determine ǒdI dt Ǔ c . The rate of crossing for sinusoidal currents is given by the slope of the secant line between the 50% and 0% levels as: ǒdI dt Ǔ c + 6 fITM 1000 Ańms where f = line frequency and ITM = maximum on-state cur- rent in the TRIAC. Turn-off depends on both the Miller effect displacement current generated by dV dt across the collector capacitance and the currents resulting from internal charge storage within the volume of the device (Figure 10). If the reverse recovery current resulting from both these components is high, the lateral IR drop within the TRIAC base layer will forward bias the emitter and turn the TRIAC on. Commu- tating dV dt capability is lower when turning off from the pos- itive direction of current conduction because of device geometry. The gate is on the top of the die and obstructs current flow. Recombination takes place throughout the conduction period and along the back side of the current wave as it declines to zero. Turn-off capability depends on its shape. If the current amplitude is small and its zero crossing ǒdI dt Ǔ c is low, there is little volume charge storage and turn-off becomes limited by ǒdV dt Ǔ s . At moderate current amplitudes, the volume charge begins to influence turn-off, requiring a larger snubber. When the current is large or has rapid zero crossing, ǒdV dt Ǔ c has little influence. Commutating dI dt and delay time to voltage reapplication determine whether turn- off will be successful or not (Figures 11, 12). STORED CHARGE FROM POSITIVE CONDUCTION Previously Conducting Side N P + − LATERAL VOLTAGE DROP REVERSE RECOVERY CURRENT PATH G MT1 TOP MT2 N N N N N N N Figure 6.9. TRIAC Structure and Current Flow at Commutation
- 156. AN1048/D http://onsemi.com 156 CHARGE DUE TO dV/dt Figure 6.10. TRIAC Current and Voltage at Commutation ǒdi dt Ǔ c ǒdV dt Ǔ c TIME IRRM VOLUME STORAGE CHARGE VMT2-1 0 VOLTAGE/CURRENT MAINTERMINALVOLTAGE(V) Figure 6.11. Snubber Delay Time E td0 VT TIME E V NORMALIZEDDELAYTIME Figure 6.12. Delay Time To Normalized Voltage 0.2 DAMPING FACTOR 0.02 0.03 0.05 0.1 0.2 0.5 10.50.30.001 0.002 0.005 0.01 0.02 0.2 0.1 0.05 0.02 0.01 0.05 0.1 (t*=Wd0 0.005 V T E RL = 0 M = 1 IRRM = 0 td) CONDITIONS INFLUENCING ǒdV dt Ǔ c Commutating dV dt depends on charge storage and recov- ery dynamics in addition to the variables influencing static dV dt . High temperatures increase minority carrier life-time and the size of recovery currents, making turn-off more dif- ficult. Loads that slow the rate of current zero-crossing aid turn-off. Those with harmonic content hinder turn-off. Circuit Examples Figure 13 shows a TRIAC controlling an inductive load in a bridge. The inductive load has a time constant longer than the line period. This causes the load current to remain constant and the TRIAC current to switch rapidly as the line voltage reverses. This application is notorious for causing TRIAC turn-off difficulty because of high ǒdI dt Ǔ c . Figure 6.13. Phase Controlling a Motor in a Bridge ǒL R u8.3 msǓ + t i CRS 60 Hz LS − R L DC MOTOR i ǒdI dt Ǔc High currents lead to high junction temperatures and rates of current crossing. Motors can have 5 to 6 times the normal current amplitude at start-up. This increases both junction temperature and the rate of current crossing, lead- ing to turn-off problems. The line frequency causes high rates of current crossing in 400 Hz applications. Resonant transformer circuits are doubly periodic and have current harmonics at both the pri- mary and secondary resonance. Non-sinusoidal currents can lead to turn-off difficulty even if the current amplitude is low before zero-crossing. ǒdV dt Ǔ c FAILURE MODE ǒdV dt Ǔ c failure causes a loss of phase control. Temporary turn-on or total turn-off failure is possible. This can be destructive if the TRIAC conducts asymmetrically causing a dc current component and magnetic saturation. The winding resistance limits the current. Failure results because of excessive surge current and junction temperature.
- 157. AN1048/D http://onsemi.com 157 IMPROVING ǒdV dt Ǔ c The same steps that improve ǒdV dt Ǔ s aid ǒdV dt Ǔ c except when stored charge dominates turn-off. Steps that reduce the stored charge or soften the commutation are necessary then. Larger TRIACs have better turn-off capability than smaller ones with a given load. The current density is lower in the larger device allowing recombination to claim a greater proportion of the internal charge. Also junction temperatures are lower. TRIACs with high gate trigger currents have greater turn-off ability because of lower spreading resistance in the gate layer, reduced Miller effect, or shorter lifetime. The rate of current crossing can be adjusted by adding a commutation softening inductor in series with the load. Small high permeability “square loop” inductors saturate causing no significant disturbance to the load current. The inductor resets as the current crosses zero introducing a large inductance into the snubber circuit at that time. This slows the current crossing and delays the reapplication of blocking voltage aiding turn-off. The commutation inductor is a circuit element that introduces time delay, as opposed to inductance, into the circuit. It will have little influence on observed dV dt at the device. The following example illustrates the improvement resulting from the addition of an inductor constructed by winding 33 turns of number 18 wire on a tape wound core (52000-1A). This core is very small having an outside diameter of 3/4 inch and a thickness of 1/8 inch. The delay time can be calculated from: ts + (N A B 10*8) E where: ts = time delay to saturation in seconds. B = saturating flux density in Gauss A = effective core cross sectional area in cm2 N = number of turns. For the described inductor: ts + (33 turns) (0.076 cm2) (28000 Gauss) (1 10–8) ń (175 V) + 4.0 ms. The saturation current of the inductor does not need to be much larger than the TRIAC trigger current. Turn-off fail- ure will result before recovery currents become greater than this value. This criterion allows sizing the inductor with the following equation: Is + Hs ML 0.4 p N where : Hs = MMF to saturate = 0.5 Oersted ML = mean magnetic path length = 4.99 cm. Is + (.5) (4.99) .4 p 33 + 60 mA. SNUBBER PHYSICS UNDAMPED NATURAL RESONANCE w0 + I LCǸ Radiansńsecond Resonance determines dV dt and boosts the peak capacitor voltage when the snubber resistor is small. C and L are related to one another by ω0 2. dV dt scales linearly with ω0 when the damping factor is held constant. A ten to one reduction in dV dt requires a 100 to 1 increase in either component. DAMPING FACTOR ρ + R 2 C L Ǹ The damping factor is proportional to the ratio of the circuit loss and its surge impedance. It determines the trade off between dV dt and peak voltage. Damping factors between 0.01 and 1.0 are recommended. The Snubber Resistor Damping and dV dt When ρ t 0.5, the snubber resistor is small, and dV dt depends mostly on resonance. There is little improvement in dV dt for damping factors less than 0.3, but peak voltage and snubber discharge current increase. The voltage wave has a 1-COS (θ) shape with overshoot and ringing. Maxi- mum dV dt occurs at a time later than t = 0. There is a time delay before the voltage rise, and the peak voltage almost doubles. When ρ u 0.5, the voltage wave is nearly exponential in shape. The maximum instantaneous dV dt occurs at t = 0. There is little time delay and moderate voltage overshoot. When ρ u 1.0, the snubber resistor is large and dV dt depends mostly on its value. There is some overshoot even through the circuit is overdamped. High load inductance requires large snubber resistors and small snubber capacitors. Low inductances imply small resistors and large capacitors.
- 158. AN1048/D http://onsemi.com 158 Damping and Transient Voltages Figure 14 shows a series inductor and filter capacitor connected across the ac main line. The peak to peak voltage of a transient disturbance increases by nearly four times. Also the duration of the disturbance spreads because of ringing, increasing the chance of malfunction or damage to the voltage sensitive circuit. Closing a switch causes this behavior. The problem can be reduced by adding a damping resistor in series with the capacitor. V(VOLTS) Figure 6.14. Undamped LC Filter Magnifies and Lengthens a Transient V 0.1 μF 100 μH 0.05 0 10 μs 340 V VOLTAGE SENSITIVE CIRCUIT 0 + 700 −700 TIME (μs) 0 2010 dI dt Non-Inductive Resistor The snubber resistor limits the capacitor discharge current and reduces dI dt stress. High dI dt destroys the thyristor even though the pulse duration is very short. The rate of current rise is directly proportional to circuit voltage and inversely proportional to series inductance. The snubber is often the major offender because of its low inductance and close proximity to the thyristor. With no transient suppressor, breakdown of the thyristor sets the maximum voltage on the capacitor. It is possible to exceed the highest rated voltage in the device series because high voltage devices are often used to supply low voltage specifications. The minimum value of the snubber resistor depends on the type of thyristor, triggering quadrants, gate current amplitude, voltage, repetitive or non-repetitive operation, and required life expectancy. There is no simple way to pre- dict the rate of current rise because it depends on turn-on speed of the thyristor, circuit layout, type and size of snub- ber capacitor, and inductance in the snubber resistor. The equations in Appendix D describe the circuit. However, the values required for the model are not easily obtained except by testing. Therefore, reliability should be verified in the actual application circuit. Table 1 shows suggested minimum resistor values esti- mated (Appendix A) by testing a 20 piece sample from the four different TRIAC die sizes. Table 1. Minimum Non-inductive Snubber Resistor for Four Quadrant Triggering. TRIAC Type Peak VC Volts Rs Ohms dI dt A/μs Non-Sensitive Gate (IGT u 10 mA) 8 to 40 A(RMS) 200 300 400 600 800 3.3 6.8 11 39 51 170 250 308 400 400 Reducing dI dt TRIAC dI dt can be improved by avoiding quadrant 4 triggering. Most optocoupler circuits operate the TRIAC in quadrants 1 and 3. Integrated circuit drivers use quadrants 2 and 3. Zero crossing trigger devices are helpful because they prohibit triggering when the voltage is high. Driving the gate with a high amplitude fast rise pulse increases dI dt capability. The gate ratings section defines the maximum allowed current. Inductance in series with the snubber capacitor reduces dI dt . It should not be more than five percent of the load inductance to prevent degradation of the snubber’s dV dt suppression capability. Wirewound snubber resistors sometimes serve this purpose. Alternatively, a separate inductor can be added in series with the snubber capacitor. It can be small because it does not need to carry the load current. For example, 18 turns of AWG No. 20 wire on a T50-3 (1/2 inch) powdered iron core creates a non-saturat- ing 6.0 μH inductor. A 10 ohm, 0.33 μF snubber charged to 650 volts resulted in a 1000 A/μs dI dt . Replacement of the non-inductive snub- ber resistor with a 20 watt wirewound unit lowered the rate of rise to a non-destructive 170 A/μs at 800 V. The inductor gave an 80 A/μs rise at 800 V with the non−inductive resistor. The Snubber Capacitor A damping factor of 0.3 minimizes the size of the snub- ber capacitor for a given value of dV dt . This reduces the cost and physical dimensions of the capacitor. However, it raises voltage causing a counter balancing cost increase. Snubber operation relies on the charging of the snubber capacitor. Turn-off snubbers need a minimum conduction angle long enough to discharge the capacitor. It should be at least several time constants (RS CS).
- 159. AN1048/D http://onsemi.com 159 STORED ENERGY Inductive Switching Transients E + 1 2 L I0 2 Watt-seconds or Joules I0 = current in Amperes flowing in the inductor at t = 0. Resonant charging cannot boost the supply voltage at turn-off by more than 2. If there is an initial current flowing in the load inductance at turn-off, much higher voltages are possible. Energy storage is negligible when a TRIAC turns off because of its low holding or recovery current. The presence of an additional switch such as a relay, ther- mostat or breaker allows the interruption of load current and the generation of high spike voltages at switch opening. The energy in the inductance transfers into the circuit capacitance and determines the peak voltage (Figure 15). dV dt + I C VPK + I L C Ǹ Figure 6.15. Interrupting Inductive Load Current VPK C L I FAST SLOW (b.) Unprotected Circuit(a.) Protected Circuit OPTIONAL R Capacitor Discharge The energy stored in the snubber capacitor ǒEc + 1 2 CV2Ǔ transfers to the snubber resistor and thyristor every time it turns on. The power loss is propor- tional to frequency (PAV = 120 Ec @ 60 Hz). CURRENT DIVERSION The current flowing in the load inductor cannot change instantly. This current diverts through the snubber resistor causing a spike of theoretically infinite dV dt with magnitude equal to (IRRM R) or (IH R). LOAD PHASE ANGLE Highly inductive loads cause increased voltage and ǒdV dt Ǔ c at turn-off. However, they help to protect the thyristor from transients and ǒdV dt Ǔ s . The load serves as the snubber inductor and limits the rate of inrush current if the device does turn on. Resistance in the load lowers dV dt and VPK (Figure 16). dV dt M = 0.25 M = 0.5 M = 0.75 VPK 1.3 E 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 0.9 1 1.1 1.2 1.4 1.5 1.6 1.7 1.4 1.2 1 0.8 0.6 2.2 2.1 2 1.9 1.8 DAMPING FACTOR M = 0 M = RS / (RL + RS) M = 1 dV dt()0 NORMALIZEDdV dt ǒM + RESISTIVE DIVISION RATIO + RS RL ) RS Ǔ I RRM + 0 Figure 6.16. 0 To 63% dV dt /(EW) NORMALIZEDPEAKVOLTAGE V/EPK CHARACTERISTIC VOLTAGE WAVES Damping factor and reverse recovery current determine the shape of the voltage wave. It is not exponential when the snubber damping factor is less than 0.5 (Figure 17) or when significant recovery currents are present. V(VOLTS)MT2-1 ƪ0*63% ǒdV dt Ǔ s + 100 Vńms, E + 250 V,ƫ R L + 0, IRRM + 0 Figure 6.17. Voltage Waves For Different Damping Factors ρ = 0 1 TIME (μs) 0.3 0.1 0 ρ = 0.1 ρ = 0.3 ρ = 1 3.52.82.1 4.2 4.9 5.6 6.30.7 0 100 200 300 400 500 1.4 70
- 160. AN1048/D http://onsemi.com 160 NORMALIZEDPEAKVOLTAGEAND dV dt (RL + 0, M + 1, IRRM + 0) NORMALIZED dV dt + dVńdt E w0 NORMALIZED VPK + VPK E Figure 6.18. Trade-Off Between VPK and dV dt DAMPING FACTOR (ρ) 0 0−63%E 1 10−63 % 0.80.60.40.2 1.2 1.81.4 1.6 2 2.8 2.6 2.4 2.2 1.8 1.6 1.4 2 1 1.2 0.8 0.6 0.4 0.2 0 dV dt ǒdV dt Ǔ o VPK dV dt 10−63% ǒdV dt ǓMAX A variety of wave parameters (Figure 18) describe dV dt Some are easy to solve for and assist understanding. These include the initial dV dt , the maximum instantaneous dV dt , and the average dV dt to the peak reapplied voltage. The 0 to 63% ǒdV dt Ǔ s and 10 to 63% ǒdV dt Ǔ c definitions on device data sheets are easy to measure but difficult to compute. NON-IDEAL BEHAVIORS CORE LOSSES The magnetic core materials in typical 60 Hz loads introduce losses at the snubber natural frequency. They appear as a resistance in series with the load inductance and winding dc resistance (Figure 19). This causes actual dV dt to be less than the theoretical value. Figure 6.19. Inductor Model L R C L DEPENDS ON CURRENT AMPLITUDE, CORE SATURATION R INCLUDES CORE LOSS, WINDING R. INCREASES WITH FREQUENCY C WINDING CAPACITANCE. DEPENDS ON INSULATION, WIRE SIZE, GEOMETRY COMPLEX LOADS Many real-world inductances are non-linear. Their core materials are not gapped causing inductance to vary with current amplitude. Small signal measurements poorly char- acterize them. For modeling purposes, it is best to measure them in the actual application. Complex load circuits should be checked for transient voltages and currents at turn-on and off. With a capacitive load, turn-on at peak input voltage causes the maximum surge current. Motor starting current runs 4 to 6 times the steady state value. Generator action can boost voltages above the line value. Incandescent lamps have cold start currents 10 to 20 times the steady state value. Transformers generate voltage spikes when they are energized. Power factor correction circuits and switching devices create complex loads. In most cases, the simple CRL model allows an approximate snubber design. However, there is no substitute for testing and measuring the worst case load conditions. SURGE CURRENTS IN INDUCTIVE CIRCUITS Inductive loads with long L/R time constants cause asymmetric multi-cycle surges at start up (Figure 20). Trig- gering at zero voltage crossing is the worst case condition. The surge can be eliminated by triggering at the zero cur- rent crossing angle. i(AMPERES) Figure 6.20. Start-Up Surge For Inductive Circuit 240 VAC 20 MHY i 0.1 Ω TIME (MILLISECONDS) 40 ZERO VOLTAGE TRIGGERING, IRMS = 30 A 0 90 80 160120 200 Core remanence and saturation cause surge currents. They depend on trigger angle, line impedance, core charac- teristics, and direction of the residual magnetization. For example, a 2.8 kVA 120 V 1:1 transformer with a 1.0 ampere load produced 160 ampere currents at start-up. Soft starting the circuit at a small conduction angle reduces this current. Transformer cores are usually not gapped and saturate easily. A small asymmetry in the conduction angle causes magnetic saturation and multi-cycle current surges.
- 161. AN1048/D http://onsemi.com 161 Steps to achieve reliable operation include: 1. Supply sufficient trigger current amplitude. TRIACs have different trigger currents depending on their quadrant of operation. Marginal gate current or optocoupler LED current causes halfwave operation. 2. Supply sufficient gate current duration to achieve latching. Inductive loads slow down the main terminal current rise. The gate current must remain above the specified IGT until the main terminal current exceeds the latching value. Both a resistive bleeder around the load and the snubber discharge current help latching. 3. Use a snubber to prevent TRIAC ǒdV dt Ǔ c failure. 4. Minimize designed-in trigger asymmetry. Triggering must be correct every half-cycle including the first. Use a storage scope to investigate circuit behavior during the first few cycles of turn-on. Alternatively, get the gate circuit up and running before energizing the load. 5. Derive the trigger synchronization from the line instead of the TRIAC main terminal voltage. This avoids regenerative interaction between the core hysteresis and the triggering angle preventing trigger runaway, halfwave operation, and core saturation. 6. Avoid high surge currents at start-up. Use a current probe to determine surge amplitude. Use a soft start circuit to reduce inrush current. DISTRIBUTED WINDING CAPACITANCE There are small capacitances between the turns and lay- ers of a coil. Lumped together, they model as a single shunt capacitance. The load inductor behaves like a capacitor at frequencies above its self-resonance. It becomes ineffective in controlling dV dt and VPK when a fast transient such as that resulting from the closing of a switch occurs. This problem can be solved by adding a small snubber across the line. SELF-CAPACITANCE A thyristor has self-capacitance which limits dV dt when the load inductance is large. Large load inductances, high power factors, and low voltages may allow snubberless operation. SNUBBER EXAMPLES WITHOUT INDUCTANCE Power TRIAC Example Figure 21 shows a transient voltage applied to a TRIAC controlling a resistive load. Theoretically there will be an instantaneous step of voltage across the TRIAC. The only elements slowing this rate are the inductance of the wiring and the self-capacitance of the thyristor. There is an expo- nential capacitor charging component added along with a decaying component because of the IR drop in the snubber resistor. The non-inductive snubber circuit is useful when the load resistance is much larger than the snubber resistor. e(t + o)) + E ƪǒ RS RS ) RL Ǔe*tńt ) (1 * e*tńt)ƫ Figure 6.21. Non-Inductive Snubber Circuit Vstep + E R S R S ) R L RESISTOR COMPONENT TIME t = 0 e E τ = (RL + RS) CS e CS RS RL E CAPACITOR COMPONENT Opto-TRIAC Examples Single Snubber, Time Constant Design Figure 22 illustrates the use of the RC time constant design method. The optocoupler sees only the voltage across the snubber capacitor. The resistor R1 supplies the trigger current of the power TRIAC. A worst case design procedure assumes that the voltage across the power TRIAC changes instantly. The capacitor voltage rises to 63% of the maximum in one time constant. Then: R1 CS + t + 0.63 E ǒdV dt Ǔ s where ǒdV dt Ǔ s is the rated static dV dt for the optocoupler. DESIGN dV dt + (0.63) (170) (2400) (0.1 mF) + 0.45 Vńms φ CNTL MOC 3021 10 V/μs TIME 240 μs 0.63 (170) L = 318 MHY 1 A, 60 Hz Rin VCC C10.1 μF 170 V6 2.4 k1801 2N6073A 1 V/μs 4 2 dV dt (Vńms) Power TRIAC Optocoupler 0.99 0.35 Figure 6.22. Single Snubber For Sensitive Gate TRIAC and Phase Controllable Optocoupler (ρ = 0.67)
- 162. AN1048/D http://onsemi.com 162 The optocoupler conducts current only long enough to trigger the power device. When it turns on, the voltage between MT2 and the gate drops below the forward thresh- old voltage of the opto-TRIAC causing turn-off. The opto- coupler sees ǒdV dt Ǔ s when the power TRIAC turns off later in the conduction cycle at zero current crossing. Therefore, it is not necessary to design for the lower optocoupler ǒdV dt Ǔ c rating. In this example, a single snubber designed for the optocoupler protects both devices. Figure 6.23. Anti-Parallel SCR Driver (50 V/μs SNUBBER, ρ = 1.0) 120 V 400 Hz 1 MHY MCR265−4 430 100 MCR265−4 1N4001 0.022 μF 1 51 1N4001 100 VCC 6 5 4 3 2 MOC3031 Optocouplers with SCRs Anti-parallel SCR circuits result in the same dV dt across the optocoupler and SCR (Figure 23). Phase controllable opto-couplers require the SCRs to be snubbed to their lower dV dt rating. Anti-parallel SCR circuits are free from the charge storage behaviors that reduce the turn-off capability of TRIACs. Each SCR conducts for a half-cycle and has the next half cycle of the ac line in which to recover. The turn- off dV dt of the conducting SCR becomes a static forward blocking dV dt for the other device. Use the SCR data sheet ǒdV dt Ǔ s rating in the snubber design. A SCR used inside a rectifier bridge to control an ac load will not have a half cycle in which to recover. The available time decreases with increasing line voltage. This makes the circuit less attractive. Inductive transients can be sup- pressed by a snubber at the input to the bridge or across the SCR. However, the time limitation still applies. OPTO ǒdV dt Ǔ c Zero-crossing optocouplers can be used to switch inductive loads at currents less than 100 mA (Figure 24). However a power TRIAC along with the optocoupler should be used for higher load currents. LOADCURRENT(mARMS) Figure 6.24. MOC3062 Inductive Load Current versus TA CS = 0.01 CS = 0.001 NO SNUBBER (RS = 100 Ω, VRMS = 220 V, POWER FACTOR = 0.5) TA, AMBIENT TEMPERATURE (°C) 0 20 80 70 60 50 40 30 20 10 100908030 40 50 60 70 A phase controllable optocoupler is recommended with a power device. When the load current is small, a MAC97A TRIAC is suitable. Unusual circuit conditions sometimes lead to unwanted operation of an optocoupler in ǒdV dt Ǔ c mode. Very large cur- rents in the power device cause increased voltages between MT2 and the gate that hold the optocoupler on. Use of a larger TRIAC or other measures that limit inrush current solve this problem. Very short conduction times leave residual charge in the optocoupler. A minimum conduction angle allows recovery before voltage reapplication. THE SNUBBER WITH INDUCTANCE Consider an overdamped snubber using a large capacitor whose voltage changes insignificantly during the time under consideration. The circuit reduces to an equivalent L/R series charging circuit. The current through the snubber resistor is: i + V Rt ǒ1 * e*t tǓ, and the voltage across the TRIAC is: e + i RS. The voltage wave across the TRIAC has an exponential rise with maximum rate at t = 0. Taking its derivative gives its value as: ǒdV dt Ǔ 0 + V RS L .
- 163. AN1048/D http://onsemi.com 163 Highly overdamped snubber circuits are not practical designs. The example illustrates several properties: 1. The initial voltage appears completely across the circuit inductance. Thus, it determines the rate of change of current through the snubber resistor and the initial dV dt . This result does not change when there is resistance in the load and holds true for all damping factors. 2. The snubber works because the inductor controls the rate of current change through the resistor and the rate of capacitor charging. Snubber design cannot ignore the inductance. This approach suggests that the snubber capacitance is not important but that is only true for this hypothetical condition. The snubber resistor shunts the thyristor causing unacceptable leakage when the capacitor is not present. If the power loss is tolerable, dV dt can be controlled without the capacitor. An example is the soft-start circuit used to limit inrush current in switching power supplies (Figure 25). Figure 6.25. Surge Current Limiting For a Switching Power Supply ǒdV dt Ǔf + ERS L SNUBBER L G RS E Snubber With No C E C1AC LINE RECTIFIER BRIDGE SNUBBER L AC LINE RECTIFIER BRIDGE C1 G RS TRIAC DESIGN PROCEDURE ǒdV dt Ǔ c 1. Refer to Figure 18 and select a particular damping factor (ρ) giving a suitable trade-off between VPK and dV dt . Determine the normalized dV dt corresponding to the chosen damping factor. The voltage E depends on the load phase angle: E + 2Ǹ VRMS Sin (f) where f + tan*1ǒXL RL Ǔwhere φ = measured phase angle between line V and load I RL = measured dc resistance of the load. Then Z + VRMS IRMS RL 2 ) XL 2Ǹ XL + Z2 * RL 2Ǹ and L + XL 2 p fLine . If only the load current is known, assume a pure inductance. This gives a conservative design. Then: L + VRMS 2 p fLine IRMS where E + 2Ǹ VRMS. For example: E + 2Ǹ 120 + 170 V; L + 120 (8 A) (377 rps) + 39.8 mH. Read from the graph at ρ = 0.6, VPK = (1.25) 170 = 213 V. Use 400 V TRIAC. Read dV dt (ρ+0.6) + 1.0. 2. Apply the resonance criterion: w0 + ǒspec dV dt Ǔń ǒdV dt(P) EǓ. w0 + 5 106 VńS (1) (170 V) + 29.4 103 r ps. C + 1 w02 L + 0.029 mF 3. Apply the damping criterion: RS + 2ρ L C Ǹ + 2(0.6) 39.8 10*3 0.029 10*6 Ǹ + 1400ohms. ǒdV dt Ǔ c SAFE AREA CURVE Figure 26 shows a MAC15 TRIAC turn-off safe operating area curve. Turn-off occurs without problem under the curve. The region is bounded by static dV dt at low values of ǒdI dt Ǔ c and delay time at high currents. Reduction of the peak current permits operation at higher line frequency. This TRIAC operated at f = 400 Hz, TJ = 125°C, and ITM = 6.0 amperes using a 30 ohm and 0.068 μF snubber. Low damping factors extend operation to higher ǒdI dt Ǔ c , but capacitor sizes increase. The addition of a small, saturable commutation inductor extends the allowed current rate by introducing recovery delay time.
- 164. AN1048/D http://onsemi.com 164 dV dt()(V/s)μ c ǒdI dt Ǔ c AMPERESńMILLISECOND Figure 6.26. versus TJ = 125°CǒdV dt Ǔ c ǒdI dt Ǔ c 100 10 0.1 5010 1 WITH COMMUTATION L 3014 18 22 26 34 38 42 46 −ITM = 15 A ǒdI dt Ǔ c + 6 f ITM 10*3 Ańms ǒMAC 16-8, COMMUTATIONAL L + 33 TURNS #18, 52000-1A TAPE WOUND CORE 3ń4 INCH OD Ǔ STATIC dV dt DESIGN There is usually some inductance in the ac main and power wiring. The inductance may be more than 100 μH if there is a transformer in the circuit or nearly zero when a shunt power factor correction capacitor is present. Usually the line inductance is roughly several μH. The minimum inductance must be known or defined by adding a series inductor to insure reliable operation (Figure 27). Figure 6.27. Snubbing For a Resistive Load t 50 V/μs 0.33 μF10 LS1 100 μH 20 A 340 V 12 Ω HEATER One hundred μH is a suggested value for starting the design. Plug the assumed inductance into the equation for C. Larger values of inductance result in higher snubber resistance and reduced dI dt . For example: Given E = 240 2Ǹ + 340 V. Pick ρ = 0.3. Then from Figure 18, VPK = 1.42 (340) = 483 V. Thus, it will be necessary to use a 600 V device. Using the previously stated formulas for ω0, C and R we find: w0 + 50 106 VńS (0.73) (340 V) + 201450 rps C + 1 (201450)2 (100 10*6) + 0.2464 mF R + 2 (0.3) 100 10*6 0.2464 10*6 Ǹ + 12 ohms VARIABLE LOADS The snubber should be designed for the smallest load inductance because dV dt will then be highest because of its dependence on ω0. This requires a higher voltage device for operation with the largest inductance because of the corre- sponding low damping factor. Figure 28 describes dV dt for an 8.0 ampere load at various power factors. The minimum inductance is a component added to prevent static dV dt firing with a resistive load. LR MAC 218A6FP 8 A LOAD 68 Ω 120 V 60 Hz 0.033 μF ǒdV dt Ǔ s + 100 Vńms ǒdV dt Ǔ c + 5 Vńms ρ R L Vstep VPK dv dt Ω MHY V V V/μs 0.75 15 0.1 170 191 86 0.03 0 39.8 170 325 4.0 0.04 10.6 28.1 120 225 3.3 0.06 13.5 17.3 74 136 2.6 Figure 6.28. Snubber For a Variable Load
- 165. AN1048/D http://onsemi.com 165 EXAMPLES OF SNUBBER DESIGNS Table 2 describes snubber RC values for ǒdV dt Ǔ s . Figures 31 and 32 show possible R and C values for a 5.0 V/μs ǒdV dt Ǔ c assuming a pure inductive load. Table 2. Static Designs (E = 340 V, Vpeak = 500 V, ρ = 0.3) dV dt 5.0 V/μs 50 V/μs 100 V/μs L μH C μF R Ohm C μF R Ohm C μF R Ohm 47 0.15 10 100 0.33 10 0.1 20 220 0.15 22 0.033 47 500 0.068 51 0.015 110 1000 3.0 11 0.033 100 TRANSIENT AND NOISE SUPPRESSION Transients arise internally from normal circuit operation or externally from the environment. The latter is partic- ularly frustrating because the transient characteristics are undefined. A statistical description applies. Greater or smaller stresses are possible. Long duration high voltage transients are much less probable than those of lower amplitude and higher frequency. Environments with infre- quent lightning and load switching see transient voltages below 3.0 kV. Figure 6.29. Snubber Resistor For = 5.0 V/μsǒdV dt Ǔc R(OHMS)S 80 A 40 A 20 A 0 0.6 A RMS 2.5 A 5 A DAMPING FACTOR 10.90.80.70.60.50.40.30.20.1 10K 100 1000 10 10 A ǒPURE INDUCTIVE LOAD, V + 120 VRMS, IRRM + 0 Ǔ Figure 6.30. Snubber Capacitor For = 5.0 V/μsǒdV dt Ǔc C(F)Sμ 0.001 2.5 A0.01 0.6 A 5 A 10 A 20 A 1 0.1 80 A RMS 40 A 0 DAMPING FACTOR 10.90.80.70.60.50.40.30.20.1 ǒPURE INDUCTIVE LOAD, V + 120 VRMS, IRRM + 0 Ǔ The natural frequencies and impedances of indoor ac wiring result in damped oscillatory surges with typical fre- quencies ranging from 30 kHz to 1.5 MHz. Surge ampli- tude depends on both the wiring and the source of surge energy. Disturbances tend to die out at locations far away from the source. Spark-over (6.0 kV in indoor ac wiring) sets the maximum voltage when transient suppressors are not present. Transients closer to the service entrance or in heavy wiring have higher amplitudes, longer durations, and more damping because of the lower inductance at those locations. The simple CRL snubber is a low pass filter attenuating frequencies above its natural resonance. A steady state sinusoidal input voltage results in a sine wave output at the same frequency. With no snubber resistor, the rate of roll off approaches 12 dB per octave. The corner frequency is at the snubber’s natural resonance. If the damping factor is low, the response peaks at this frequency. The snubber resistor degrades filter characteristics introducing an up-turn at ω = 1 / (RC). The roll-off approaches 6.0 dB/octave at frequencies above this. Inductance in the snubber resistor further reduces the roll-off rate. Figure 32 describes the frequency response of the circuit in Figure 27. Figure 31 gives the theoretical response to a 3.0 kV 100 kHz ring-wave. The snubber reduces the peak voltage across the thyristor. However, the fast rise input causes a high dV dt step when series inductance is added to the snubber resistor. Limiting the input voltage with a transient suppressor reduces the step.
- 166. AN1048/D http://onsemi.com 166 Figure 6.31. Theoretical Response of Figure 33 Circuit to 3.0 kV IEEE 587 Ring Wave (RSC = 27.5 Ω) V(VOLTS)MT2-1 400 WITH 5 μHY 450 V MOV AT AC INPUT WITH 5 μHY AND WITHOUT 5 μHY 654210 TIME (μs) 3 −400 0 Figure 6.32. Snubber Frequency Response ǒVout Vin Ǔ VOLTAGEGAIN(dB) FREQUENCY (Hz) 10K WITH 5 μHY WITHOUT 5μHY −40 0.33 μF 10 5 μH 12 Vin 100 μH 1M +10 0 100K −30 −20 −10 Vout The noise induced into a circuit is proportional to dV dt when coupling is by stray capacitance, and dI dt when the coupling is by mutual inductance. Best suppression requires the use of a voltage limiting device along with a rate limiting CRL snubber. The thyristor is best protected by preventing turn-on from dV dt or breakover. The circuit should be designed for what can happen instead of what normally occurs. In Figure 30, a MOV connected across the line protects many parallel circuit branches and their loads. The MOV defines the maximum input voltage and dI dt through the load. With the snubber, it sets the maximum dV dt and peak voltage across the thyristor. The MOV must be large because there is little surge limiting impedance to prevent its burn-out. In Figure 32, there is a separate suppressor across each thyristor. The load impedance limits the surge energy deliv- ered from the line. This allows the use of a smaller device but omits load protection. This arrangement protects each thyristor when its load is a possible transient source. Figure 6.33. Limiting Line Voltage VMAX Figure 6.34. Limiting Thyristor Voltage It is desirable to place the suppression device directly across the source of transient energy to prevent the induc- tion of energy into other circuits. However, there is no protection for energy injected between the load and its con- trolling thyristor. Placing the suppressor directly across each thyristor positively limits maximum voltage and snub- ber discharge dI dt . EXAMPLES OF SNUBBER APPLICATIONS In Figure 35, TRIACs switch a 3 phase motor on and off and reverse its rotation. Each TRIAC pair functions as a SPDT switch. The turn-on of one TRIAC applies the differ- ential voltage between line phases across the blocking device without the benefit of the motor impedance to constrain the rate of voltage rise. The inductors are added to prevent static dV dt firing and a line-to-line short.
- 167. AN1048/D http://onsemi.com 167 Figure 6.35. 3 Phase Reversing Motor MOC 3081 SNUBBER ALL MOV’S ARE 275 VRMS ALL TRIACS ARE MAC218A10FP 0.15 μF 22 Ω 2 W WIREWOUND 43 4 6 G 1 2 91 1/3 HP 208 V 3 PHASE 100 μH REV φ1 91 G 12 300 6 FWD 4 SNUBBER N φ2 φ3 MOC 3081 91 G 12 300 64 SNUBBER MOC 3081 91 G 12 300 64 SNUBBER MOC 3081 91 G 12 300 46 SNUBBER REV FWD 100 μH MOC 3081 SNUBBER
- 168. AN1048/D http://onsemi.com 168 Figure 36 shows a split phase capacitor-run motor with reversing accomplished by switching the capacitor in series with one or the other winding. The forward and reverse TRIACs function as a SPDT switch. Reversing the motor applies the voltage on the capacitor abruptly across the blocking thyristor. Again, the inductor L is added to prevent ǒdV dt Ǔ s firing of the blocking TRIAC. If turn-on occurs, the forward and reverse TRIACs short the capacitors (Cs) resulting in damage to them. It is wise to add the resistor RS to limit the discharge current. Figure 6.36. Split Phase Reversing Motor 5.6 3.75 330 V MOTOR 1/70 HP 0.26 A 2N6073 115 500 μH LS REV 46 V/μs MAX FWD 0.191 CS 0.1 RS 91 Figure 37 shows a “tap changer.” This circuit allows the operation of switching power supplies from a 120 or 240 vac line. When the TRIAC is on, the circuit functions as a conventional voltage doubler with diodes D1 and D2 con- ducting on alternate half-cycles. In this mode of operation, inrush current and dI dt are hazards to TRIAC reliability. Series impedance is necessary to prevent damage to the TRIAC. The TRIAC is off when the circuit is not doubling. In this state, the TRIAC sees the difference between the line volt- age and the voltage at the intersection of C1 and C2. Tran- sients on the line cause ǒdV dt Ǔ s firing of the TRIAC. High inrush current, dI dt , and overvoltage damage to the filter capacitor are possibilities. Prevention requires the addition of a RC snubber across the TRIAC and an inductor in series with the line. THYRISTOR TYPES Sensitive gate thyristors are easy to turn-on because of their low trigger current requirements. However, they have less dV dt capability than similar non-sensitive devices. A non-sensitive thyristor should be used for high dV dt . TRIAC commutating dV dt ratings are 5 to 20 times less than static dV dt ratings. Figure 6.37. Tap Changer For Dual Voltage Switching Power Supply − C1 + RL 0 G CSRS 120 V 240 V SNUBBER INDUCTOR 120 VAC OR 240 VAC D1D2 D4 D3 − C2 + Phase controllable optocouplers have lower dV dt ratings than zero crossing optocouplers and power TRIACs. These should be used when a dc voltage component is present, or to prevent turn-on delay. Zero crossing optocouplers have more dV dt capability than power thyristors; and they should be used in place of phase controllable devices in static switching applications. APPENDIX A MEASURING ǒdV dt Ǔ s Figure 38 shows a test circuit for measuring the static dV dt of power thyristors. A 1000 volt FET switch insures that the voltage across the device under test (D.U.T.) rises rapidly from zero. A differential preamp allows the use of a N-channel device while keeping the storage scope chassis at ground for safety purposes. The rate of voltage rise is adjusted by a variable RC time constant. The charging resistance is low to avoid waveform distortion because of the thyristor’s self-capacitance but is large enough to pre- vent damage to the D.U.T. from turn-on dI dt . Mounting the miniature range switches, capacitors, and G-K network close to the device under test reduces stray inductance and allows testing at more than 10 kV/μs.
- 169. AN1048/D http://onsemi.com 169 Figure 6.38. Circuit For Static Measurement of Power ThyristorsdV dt X100 PROBE X100 PROBE DIFFERENTIAL PREAMP MOUNT DUT ON TEMPERATURE CONTROLLED Cμ PLATE DUT 2 1G RGK 2 W20 k VDRM/VRRM SELECT 2 W 27 0.33 1000 V 0.047 1000 V 1000 10 WATT WIREWOUND 1000 1/4 W 56 2 W VERNIER 82 2 W 100 2 W 470 pF 0.001 0.005 0.01 0.047 0.1 0.47 1.2 MEG 2 W EACH1 MEG POWER 2 W TEST MTP1N100 ALL COMPONENTS ARE NON-INDUCTIVE UNLESS OTHERWISE SHOWN 0−1000 V 10 mA 1N967A 18 V 1N914 f = 10 Hz PW = 100 μs 50 Ω PULSE GENERATOR 20 V dV dt APPENDIX B MEASURING ǒdV dt Ǔ c A test fixture to measure commutating dV dt is shown in Figure 39. It is a capacitor discharge circuit with the load series resonant. The single pulse test aids temperature con- trol and allows the use of lower power components. The limited energy in the load capacitor reduces burn and shock hazards. The conventional load and snubber circuit pro- vides recovery and damping behaviors like those in the application. The voltage across the load capacitor triggers the D.U.T. It terminates the gate current when the load capacitor volt- age crosses zero and the TRIAC current is at its peak. Each VDRM, ITM combination requires different compo- nents. Calculate their values using the equations given in Figure 39. Commercial chokes simplify the construction of the nec- essary inductors. Their inductance should be adjusted by increasing the air gap in the core. Removal of the magnetic pole piece reduces inductance by 4 to 6 but extends the cur- rent without saturation. The load capacitor consists of a parallel bank of 1500 Vdc non-polar units, with individual bleeders mounted at each capacitor for safety purposes. An optional adjustable voltage clamp prevents TRIAC breakdown. To measure ǒdV dt Ǔ c , synchronize the storage scope on the current waveform and verify the proper current amplitude and period. Increase the initial voltage on the capacitor to compensate for losses within the coil if necessary. Adjust the snubber until the device fails to turn off after the first half-cycle. Inspect the rate of voltage rise at the fastest passing condition.
- 170. AN1048/D http://onsemi.com 170 − + − + 2 W51 + 5CS 2N3904 0.1 2.2 k 1/2SYNC TRIAC UNDER TEST 56 2 WATT CASE CONTROLLED HEATSINK 0.1 2N3906 − 5 G 1 2 PEARSON 301 X 2N3904 1/2 W 120 2N3906 120 1/2 W 2N390 6 2N3904 RS 1/2 W − + 0.22 270 k 1N5343 7.5 V 0.22 Q1Q3 2N3906 2N3904 1/2 W360 1 k − 5 + 5 NON-INDUCTIVE RESISTOR DECADE 0−10 k, 1 Ω STEP 2 W51 k 51 k 2 W HG = W AT LOW LD10-1000-1000 + CLAMP MR760 − CLAMP 62 μF 1 kV LL 6.2 MEG 2 W 150 k 910 k 2 W 2 W 910 k RL Q3 Q1 70 mA 1.5 kV TRIAD C30X 50 H, 3500 Ω 2 W51 6.2 MEG 2 W 360 1 k 270 k 2N39042N390 6 Q3 Q1 0-1kV20mA C(NON-POLAR)L MR760MR760 2.2M2.2M 2.2M,2W 2.2M,2W2.2M 2.2M 0.01 Figure 6.39. Test Circuit For Power TRIACsǒdV dt Ǔ c μ ǒCL + IPK W0 VCi + Ip T 2 p VCi LL + VCi W0 IPK + T2 4 p 2CL W0 + I LLǸ ǒdI dt Ǔ c + 6f IPK 10*6 ǓAńms dV dt CAPACITORDECADE1−10F,0.01−1F,100pF−0.01Fμμ 0.01
- 171. AN1048/D http://onsemi.com 171 APPENDIX C dV dt DERIVATIONS DEFINITIONS 1.0 RT + RL ) RS + Total Resistance 1.1 M + RS RT + Snubber Divider Ratio 1.2 w0 + 1 L CSǸ + Undamped Natural Frequency w + Damped Natural Frequency 1.3 a + RT 2 L + Wave Decrement Factor 1.4 χ2 + 1ń2 LI2 1ń2 CV2 + Initial Energy In Inductor Final Energy In Capacitor 1.5 χ + I E L C Ǹ + Initial Current Factor 1.6 ρ + RT 2 C L Ǹ + a w0 + Damping Factor 1.7 V0L + E * RS I + Initial Voltage drop at t + 0 across the load 1.8 c + I CS – E RL L ǒdV dt Ǔ 0 + Initial instantaneous dV dt at t + 0, ignoring any initial instantaneous voltage step at t + 0 because of IRRM 1.9 ǒdV dt Ǔ 0 + VOL RT L ) c. For all damping conditions 2.0 When I + 0, ǒdV dt Ǔ 0 + E RS L ǒdV dt Ǔmax + Maximum instantaneous dV dt tmax + Time of maximum instantaneous dV dt tpeak + Time of maximum instantaneous peak voltage across thyristor Average dV dt + VPKńtPK + Slope of the secant line from t + 0 through VPK VPK + Maximum instantaneous voltage across the thyristor. CONSTANTS (depending on the damping factor): 2.1 No Damping (ρ + 0) w + w0 RT + a + ρ + 0 2.2 Underdamped (0 t ρ t 1) w + w0 2 * a2Ǹ + w0 1 * ρ2Ǹ 2.3 Critical Damped (ρ + 1) a + w0, w + 0, R + 2 L C Ǹ , C + 2 a RT 2.4 Overdamped (ρ u 1) w + a2 * w0 2Ǹ + w0 ρ2 * 1Ǹ Laplace transforms for the current and voltage in Figure 40 are: 3.0 i(S)+ EńL)SI S2)S RT L ) 1 LC ; e +E S * S V0L* c S2) RT L S) 1 LC INITIAL CONDITIONS I + IRRM VCS + 0 Figure 6.40. Equivalent Circuit for Load and Snubber t = 0 I RL L CS RS e The inverse laplace transform for each of the conditions gives: UNDERDAMPED (Typical Snubber Design) 4.0 e + E * V0L ƪCos (wt) * a w sin (wt)ƫe * at ) c w sin (wt) e*at 4.1 de dt + V0L ƪ2a Cos (wt) ) (w2–a2) w sin (wt)ƫe–at) c ƪ Cos (wt)– a w sin (wt) ƫe–at 4.2 tPK + 1 w tan*1ȧȧ ȱ Ȳ * 2a V0L ) c V0L ǒw2*a2 w Ǔ* ca w ȧȧ ȳ ȴ When M + 0, RS + 0, I + 0 : w tPK + p
- 172. AN1048/D http://onsemi.com 172 4.3 VPK + E ) a w0 * a tPK w0 2 V0L 2 ) 2ac V0L ) c2Ǹ When I + 0, RL + 0, M + 1: 4.4 VPK E + (1 ) e * a tPK) Average dV dt + VPK tPK 4.5 tmax + 1 w ATN ƪ w (2ac * V0L (w2 * 3a2)) V0L (a3 * 3aw2) ) c(a2 * w2) ƫ 4.6 ǒdV dt Ǔmax + V0L 2 w0 2)2ac V0L ) c2Ǹ e–atmax NO DAMPING 5.0 e + E (1 * Cos (w0t)) ) I C w0 sin (w0t) 5.1 de dt + E w0 sin (w0t) ) I C Cos (w0t) 5.2 ǒdV dt Ǔ 0 + I C + 0 when I + 0 5.3 tPK + p * tan*1ǒ I CE w0 Ǔ w0 5.4 VPK + E ) E2 ) I2 w02C2 Ǹ 5.5 ǒdV dt ǓAVG + VPK tPK 5.6 tmax + 1 w0 ƪtan*1ǒw0 EC I Ǔƫ+ 1 w0 p 2 when I + 0 5.7 ǒdV dt Ǔ max + I C E2w0 2 C2)I2Ǹ + w0E when I+0 CRITICAL DAMPING 6.0 e + E * V0L (1 * at)e*at ) cte*at 6.1 de dt + ƪa VOL (2 * at) ) c(1 * at)ƫe*at 6.2 tPK + 2 ) c 2 V0L a ) c V0L 6.3 VPK + E – ƪV0L (1–a tPK)–c tPK ƫe–a tPK 6.4 Average dV dt + VPK tPK When I + 0, RS + 0, M + 0 e(t) rises asymptotically to E. tPK and average dV dt do not exist. 6.5 tmax + 3aV0L ) 2c a2V0L ) ac When I + 0, tmax + 0 For RS RT y3ń4, then dV dt max + ǒdV dt Ǔ 0 6.6 ǒdV dt Ǔ max +ƪa V0L (2–a tmax) ) c (1–a tmax) ƫe–a tmax APPENDIX D SNUBBER DISCHARGE dI dt DERIVATIONS OVERDAMPED 1.0 i + VCS w LS a–at sinh (wt) 1.1 iPK + VCS CS LS Ǹ e–a t PK 1.2 tPK + 1 w tanh –1 ƪw a ƫ CRITICAL DAMPED 2.0 i + VCS LS te–at 2.1 iPK + 0.736 VCS RS 2.2 tPK + 1 a
- 173. AN1048/D http://onsemi.com 173 UNDERDAMPED 3.0 i + VCS w LS e–at sin (wt) 3.1 iPK + VCS CS LS Ǹ e–a t PK 3.2 tPK + 1 w tan –1 ǒw a Ǔ Figure 6.41. Equivalent Circuit for Snubber Discharge LSRS CS VCS i t = 0 INITIAL CONDITIONS : i + 0, VCS + INITIAL VOLTAGE NO DAMPING 4.0 i + VCS w LS sin (wt) 4.1 iPK + VCS CS LS Ǹ 4.2 tPK + p 2 w BIBLIOGRAPHY Bird, B. M. and K. G. King. An Introduction To Power Electronics. John Wiley Sons, 1983, pp. 250−281. Blicher, Adolph. Thyristor Physics. Springer-Verlag, 1976. Gempe, Horst. “Applications of Zero Voltage Crossing Optically Isolated TRIAC Drivers,” AN982, Motorola Inc., 1987. “Guide for Surge Withstand Capability (SWC) Tests,” ANSI 337.90A-1974, IEEE Std 472−1974. “IEEE Guide for Surge Voltages in Low-Voltage AC Power Circuits,” ANSI/IEEE C62.41-1980, IEEE Std 587−1980. Ikeda, Shigeru and Tsuneo Araki. “The dI dt Capability of Thyristors,” Proceedings of the IEEE, Vol. 53, No. 8, August 1967. Kervin, Doug. “The MOC3011 and MOC3021,” EB-101, Motorola Inc., 1982. McMurray, William. “Optimum Snubbers For Power Semiconductors,” IEEE Transactions On Industry Applica- tions, Vol. IA-8, September/October 1972. Rice, L. R. “Why R-C Networks And Which One For Your Converter,” Westinghouse Tech Tips 5-2. “Saturable Reactor For Increasing Turn-On Switching Capability,” SCR Manual Sixth Edition, General Electric, 1979. Zell, H. P. “Design Chart For Capacitor-Discharge Pulse Circuits,” EDN Magazine, June 10, 1968.
- 174. © Semiconductor Components Industries, LLC, 1999 November, 1999 − Rev. 0 174 Publication Order Number: AND8005/D AND8005/D Automatic AC Line Voltage Selector Prepared by: Alfredo Ochoa, Alex Lara Gabriel Gonzalez Thyristors Applications Engineers INTRODUCTION In some cases, appliances and equipment are able to operate when supplied by two different levels of AC line voltage to their main terminals (120V or 240V). This is why, it is very common that appliances and equipment have mechanical selectors or switches as an option for selecting the level of voltage needed. Nevertheless, it is also very common that these types of equipment can suffer extensive damage caused for not putting the selector in the right position. To prevent these kind of problems, thyristors can be used as a solution for making automatic voltage selectors in order to avoid possibilities of equipment damage due to over or low voltages AC line supplied to them. Thyristors can take many forms, but they have certain things in common. All of them are solid state switches, which act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low impedance current paths and remain in that condition (i.e. conduction) until the current either stops or drops below a minimum value called the holding level. A useful application of triacs is a direct replacement for mechanical selectors, relays or switches. In this application, the triac furnishes on−off control and the power regulating ability of the triac is not utilized. The control circuitry for these applications is usually very simple and these circuits are useful in applications where simplicity and reliability are important. In addition, as is well known, there is no arcing with the triac, which can also be very important in some applications. The main disadvantages of the mechanical switches or selectors appear when they are driving high current levels that can cause arcing and sparks on their contacts each time they are activated or de−activated. Because of these kind of effects the contacts of the switches get very significantly damaged causing problems in the functionality of the equipment or appliances. DEFINITIONS Control Transformers. This transformer consists of two or more windings coupled by a common or mutual magnetic field. One of these windings, the primary, is connected to an alternating voltage source. An alternating flux will be produced whose amplitude will depend on the primary voltage and number of turns. The mutual flux will link the other winding, the secondary, in which it will induce a voltage whose value will depend on the number of secondary turns. When the numbers of primary and secondary turns are properly proportioned, almost any desired voltage ratio or ratio of transformation can be obtained. This transformer is also widely used in low power electronic and control circuits. There it performs such functions as matching the source impedance and its load for maximum power transfer, isolating one circuit from another, or isolating direct current while maintaining AC continuity between two circuits. http://onsemi.com APPLICATION NOTE
- 175. AND8005/D http://onsemi.com 175 The following schematic diagram shows an automatic voltage selector for AC voltage supply of 110V/220V and load of 10 Amp rms max. Loads can be equipment or any kind of appliances: + − + − 110 V or 220 V? 330 W 330 mF 1N5349 1N4735 LM339 LM339 330 W 10 kW 10 kW 1 kW 470 W 1 kW 2N2222 2N2222 470 W TO LOAD EQUIPMENT 51 W MAC15A8 10 nF 1.6 kW 51 W MAC15A8 10 nF MOC3022MOC3022 2.4 kW 110 V 220 V Main Transformer 2.4 kW 820 W 1N4007 Control Transformer 220 V/24 V − 250 mA
- 176. AND8005/D http://onsemi.com 176 When the main terminals of the equipment are connected to the AC line voltage, one of the comparators (LM339) keeps its output at low level and the other one at high level because of the voltage references connected to their inverter and non−inverter input pins. Therefore, one of the transistors (2N2222) is activated allowing current through the LED of the optocoupler, and which triggers one of the triacs (MAC15A8) that then provides the right level of AC line voltage to the main transformer of the equipment by connecting one of the primary windings through the triac triggered. The operational range, in the previous circuit, in the low AC line voltage condition (110V) is from 100 Vrms to 150 Vrms. This means, the triac that is driving the winding of the main transformer for 110V would keep itself triggered whenever the input voltage in the control transformer is within 100 and 150 Vrms. The operation range in high AC line voltage condition (220V) is from 180 Vrms to 250 Vrms, therefore, the triac that is driving the winding of the main transformer for 220V would keep itself triggered whenever the voltage in the control transformer is within 180 and 250 Vrms. Another very important item to take into consideration is the operational range of environmental temperature which is from 0°C to 65°C. If the circuit is working outside of these temperature limits, it very probably will experience unreliable functionality. In conclusion, this automatic voltage selector provides a very important protection for any kind of voltage sensitive equipment or appliances against the wrong levels of AC line input voltages. It eliminates the possibility of any damage in the circuitry of the equipment caused by connecting low or high voltage to the main terminals. In addition, the total price of the electronic circuitry is inexpensive when compared to the cost of the equipment if it suffers any damage.
- 177. © Semiconductor Components Industries, LLC, 1999 November, 1999 − Rev. 0 177 Publication Order Number: AND8006/D AND8006/D Electronic Starter for Flourescent Lamps Prepared by: Alfredo Ochoa, Alex Lara Gabriel Gonzalez Thyristors Applications Engineers INTRODUCTION In lighting applications for fluorescent lamps the choice of the starter switch to be used is always very important for the designers: the cost, reliability, ruggedness, and ease to be driven must always be kept in mind. This is especially important in lighting circuits where the designer has to optimize the operating life of the fluorescent lamps by using the right starter switch. In the large family of electronic switches, the thyristor must be considered as a low cost and powerful device for lighting applications. Thyristors can take many forms, but they have certain features in common. All of them are solid state switches that act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low impedance current paths and remain in that condition (i.e. conduction) until the current either stops or drops below a minimum value called the holding level. Once a thyristor has been triggered, the trigger current can be removed without turning off the device. Silicon controlled rectifiers (SCRs) and triacs are both members of the thyristor family. SCRs are unidirectional devices while triacs are bi−directional. A SCR is designed to switch load current in one direction, while a triac is designed to conduct load currents in either direction. Structurally, all thyristors consist of several alternating layers of opposite P and N silicon, with the exact structure varying with the particular kind of device. The load is applied across the multiple junctions and the trigger current is injected at one of them. The trigger current allows the load current to flow through the device setting up a regenerative action which keeps the current flowing even after the trigger is removed. These characteristics make thyristors extremely useful in control applications. Compared to a mechanical switch, a thyristor has a very long service life and very fast turn on and turn off times. Because of their fast reaction times, regenerative action, and low resistance, once triggered, thyristors are useful as power controllers and transient over voltage protectors, as well as simply turning devices on and off. Thyristors are used to control motors, incandescent and fluorescent lamps, and many other kinds of equipment. Although thyristors of all sorts are generally rugged, there are several points to keep in mind when designing circuits using them. One of the most important parameters to respect is the devices’ rated limits on rate of change of voltage and current (dV/dt and di/dt). If these are exceeded, the thyristor may be damaged or destroyed. DEFINITIONS Ambient Sound Levels. Background noise generated by ballast and other equipment operating in a building. Arc. Intense luminous discharge formed by the passage of electric current across a space between electrodes. Ballast. An electrical device used in fluorescent and high intensity discharge (HID) fixtures. It furnishes the necessary starting and operating current to the lamp for proper performance. Electrode. Metal filament that emits electrons in a fluorescent lamp. Fluorescent lamp. Gas filled lamp in which light is produced by the interaction of an arc with phosphorus lining the lamp’s glass tube. Fluorescent light circuit. Path over which electric current flows to operate fluorescent lamps. Three major types of fluorescent lighting circuits are in use today, preheat, instant start (slimline) and rapid start. Instant start (slimline). A class of fluorescent. Ballast provides a high starting voltage surge to quickly light the lamp. All instant start lamps have a single pin base and can be used only with instant ballast. Rapid Start Lamps. Fluorescent lamps that glow immediately when turned on and reach full brightness in about 2 seconds. Preheat Lamp. A fluorescent lamp in which the filament must be heated before the arc is created. This application note is designed for Preheat Start Lamp circuit. The description of the functionality of this Lamp is described below: http://onsemi.com APPLICATION NOTE
- 178. AND8006/D http://onsemi.com 178 HOW THE LAMP WORKS (Using the conventional glow−tube starter) Starter Neon Gas Fluorescent Coating VAC Coated Filament (Argon Gas) Ballast Inductor Mercury Droplets The above Figure illustrates a fluorescent lamp with the conventional glow−tube starter. The glow−tube starter consists of a bimetallic switch placed in series with the tube filament which closes to energize the filaments and then opens to interrupt the current flowing through the ballast inductor, thereby, generating the high voltage pulse necessary for starting. The mechanical glow−tube starter is the circuit component most likely to cause unreliable starting. The principle disadvantage of the conventional glow−tube starter is that it has to open several times in the filament circuit to interrupt the current flowing through the ballast inductor in order to generate the high voltage necessary for turning−on the fluorescent lamp. However, those interactions decrease the life of the lamp considerably. Besides, the lamp turns−on in around 3 seconds when it is using the conventional glow−tube starter and it also causes degradation to the lamp. On the other hand, the following schematic diagrams show the electronic circuitry which substitutes the conventional glow−tube starter for fluorescent lamps applications of 20 Watts and 40 Watts using a diode, SCR, and a TVS or zener clipper(s): Switch Electronic Starter Fluorescent Lamp 20 W Coated Filaments Ballast Inductor Line (120 V; 60 Hz) A K Diode 1N4003 Gate MCR100−8 Clipper SA90A Switch Electronic Starter Fluorescent Lamp 40 W Coated FilamentsLine (120 V; 60 Hz) A K Diode 1N4003 Gate MCR100−8 Clipper SA170A30 W 0.1 mF Clipper SA30A Ballast Inductor Phase Neutral Blue Black White Fluorescent Lamp of 20 Watts Fluorescent Lamp of 40 Watts
- 179. AND8006/D http://onsemi.com 179 The main reason why the previous circuits are different is due to the high voltage must be generated for each kind of lamp. This means, the inductor ballast for fluorescent lamps of 40 Watts provides higher voltage than the inductor ballast for lamps of 20 Watts, that is why, the electronic circuits have to be different. As an observation, even the conventional glow−tube starters have to be selected according the power of the lamp, it means, there is not a general glow−tube starter who can operate for all kinds of fluorescent lamps. The following plots show the voltage and current waveform in the electronic starter circuitry when the fluorescent lamps is turned−on: Fluorescent Lamp of 20 Watts: Time before the Lamp turns−on Ch1 Voltage Ch2 Current Vp=160V Vp=78V Ip=1.2Amp When the switch is turned−on, the voltage across the Clipper (SA90A) is the same as the voltage of the AC Line (Vpeak=160V), and since the Clipper allows current−flow through itself only once its VBR is reached (100V peak), the SCR (MCR100−8) turns−on and closes the circuit to energize the filaments of the fluorescent lamp. At this time, the current across the circuit is around 1.2A peak, and once the lamp has got enough heat, it decreases its dynamic resistance and permits current−flow through itself which causes the voltage across the Clipper to decrease to around 78 Vpeak. This effect makes the clipper turn off, since the voltage is less than the VBR of the device (SA90A), and because the clipper turns off, the SCR also turns−off, and opens the circuit to interrupt the current flowing through the ballast inductor, thereby, generating the high voltage pulse necessary for starting the lamp. The time that the fluorescent lamp will take before to turn−on is around 400 msecs by using the electronic starter. It is a faster starter then when the lamp is using the conventional glow−tube starter.
- 180. AND8006/D http://onsemi.com 180 Fluorescent Lamp of 40 Watts: Time before the Lamp turns−on Ch1 Voltage Ch2 Current Vp=230V Vp=140V Ip=2.1Amp The operation of the electronic starter circuit of 40 watts is similar than for 20 watts, the only difference between them is that the Inductor Ballast of 40 watts generates higher voltage than the inductor ballast of 20 watts. That is why the schematic circuit for lamps of 40 watts has two clippers and one snubber inside its control circuit. Besides, the current flowing through this circuit is around 2.1A peak and it appears around 550 msecs (which is the time that the lamp takes before it turn itself on), longer than in the electronic starter circuit of 20 watts. In conclusion the electronic starter circuits (for 20 and 40 watts) are more reliable than the conventional glow−tube starters since the lamps turn−on faster and more efficiently increasing their life−time considerably. Besides, the total price of the electronic devices is comparable with the current starters (glow−tube). In summary, it is also important to mention that the range of the AC voltage supply to the electronic starter circuits must be from 115Vrms to 130Vrms for operating correctly. If it is not within this voltage range the circuits may not be able to operate in the correct way causing unreliable start- ing of the lamp. Also, extreme environmental temperatures could effect the right functionality of the electronic starters but it is a fact that they can operate between 15°C to 40°C.
- 181. © Semiconductor Components Industries, LLC, 1999 November, 1999 − Rev. 0 181 Publication Order Number: AND8007/D AND8007/D Momentary Solid State Switch for Split Phase Motors Prepared by: Alfredo Ochoa, Alex Lara Gabriel Gonzalez Thyristors Applications Engineers INTRODUCTION In control applications for motors the choice of the solid state switch to be used is always very important for the designers: the cost, reliability, ruggedness, and ease to be driven must always be kept in mind. This is especially important in motor control circuits where the designer has to optimize the circuitry for controlling the motors in the correct and efficient way. In the large family of electronic switches, the thyristor must be considered as a low cost and powerful device for motor applications. Thyristors can take many forms, but they have certain features in common. All of them are solid state switches which act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low impedance current paths and remain in that condition (i.e. conduction) until the current either stops or drops below a minimum value called the holding level. Once a thyristor has been triggered, the trigger current can be removed without turning off the device. Because Thyristors are reliable solid state switches, they have many applications, especially as controls. A useful application of triac is as a direct replacement for an AC mechanical relay. In this application, the triac furnishes on−off control and the power regulating ability of the triac is utilized. The control circuitry for this application is usually very simple, consisting of a source for the gate signal and some type of small current switch, either mechanical or electrical. The gate signal can be obtained from a separate source or directly from the line voltage at terminal MT2 of the triac. One of the most common uses for thyristors is to control AC loads such as electric motors. This can be done either by controlling the part of each AC cycle when the circuit conducts current (Phase control) or by controlling the number or cycles per time period when current is conducted (cycle control). In addition, thyristors can serve as the basis of relaxation oscillators for timers and other applications. DEFINITIONS Split−Phase Motor. Split−Phase motors have two stator windings, a main winding and an auxiliary winding, with their axes displaced 90 electrical degrees in space. The auxiliary winding has a higher resistance−to−reactance ratio than the main winding, so that the two currents are out of phase. The stator field thus first reaches a maximum about the axis of one winding and then somewhat later in time (about 80 to 85 electrical degrees) reaches a maximum about the axis of the winding 90 electrical degrees away in space. The result is a rotating stator field which causes the motor to start. At about 75 percent of synchronous speed, the auxiliary winding is cut out by a centrifugal switch. The below figure shows an schematic representation of a split−phase motor: Line Main Winding Auxiliary Winding Centrifugal Switch When the line voltage is applied, the current flows through both windings and the result is a rotating stator field which causes the motor to start. At about 75 percent of synchronous speed, the auxiliary winding is cut out by a centrifugal switch. http://onsemi.com APPLICATION NOTE
- 182. AND8007/D http://onsemi.com 182 The following figure shows a conventional schematic diagram using a relay for controlling a split−phase fractional horsepower motor (the compressor of a refrigerator for example): Line Thermostat Switch Bi−metal Switch Start Winding Main Winding Neutral Momentary Switch IS IO In the previous figure the thermostat−switch is controlling the working−cycle of the compressor and it is dependent on the set point of environment temperature which has to be selected according to the temperature needed. The bi−metal switch protects the compressor against overload and the relay controls the momentary switch which cuts out the starter winding once the motor has reached about 75 percent of the synchronous speed (after around 300 msecs). The below plot shows the current flowing through the compressor (1 Phase, 115Vac, 60Hz, 4.1Arms) when it starts to operate under normal conditions: This plot shows the total current flowing through the compressor when it starts to operate and the time in which the current reaches the maximum value (Is) due to the start of the motor. After this time (210 msecs) the start winding is cut out by the momentary switch and then the current decreases to reach the nominal current of the compressor (Io=4.1 Arms).
- 183. AND8007/D http://onsemi.com 183 The following schematic diagrams show the way triacs can substitute for the relay and how they can be triggered by using different control options: Line Thermostat Switch Bi−metal Switch Start Winding Normal Op. Winding Neutral “Momentary Solid State Switch” Main Winding Solid Connected to Neutral MT2 MT1 Gate MAC8D, M MT1 MT2 Gate −VCC Logic Signal Neutral Line Bi−metal Switch MT2 MT1 Gate MAC8SD, M RS CS Direct Negative Logic Driven by Microcontroller mC HC 0 −lg Negative Triggering for Quadrants 2 and 3 Non−sensitive Gate TRIAC
- 184. AND8007/D http://onsemi.com 184 In the first diagram, the triac (MAC8D,M) is making the function of the conventional relay’s momentary switch, and it can be triggered by using a transistor as shown in the above schematic or through the signals of a microcontroller. Since this triac (MAC8D,M) is a snubber−less device, it does not need a snubber network for protecting itself against dV/dt phenomena. In the second diagram the triac (MAC8SD,M) is also performing the function of the relay’s momentary switch, but since this device is a sensitive gate triac, it only needs a very low Igt current for triggering itself, therefore, this option is especially useful in applications where the level of the current signals are small. On the other hand, the following figure shows a practical solid state solution for controlling the compressor with the operating characteristics mentioned previously (1 Phase, 115Vac, 60Hz, 4.1 Arms) : + − 120 V/14 V Line Thermostat Switch Bi−metal Switch Start Winding Normal Op. Winding Neutral Main Winding Solid Connected to Neutral MT2 MT1 MAC8D, M Neutral Neutral 1000 mF 1000 mF 280 W 1.3 kW 10 mF 10 kW LM741C 1N4003 10 kW 510 W 10 kW 100 W 2N6520 + −
- 185. AND8007/D http://onsemi.com 185 When the thermostat switch is activated, the triac (MAC8D,M) turns−on and allows current flow through the starter winding. This current is around 20 Arms because at the start of the motor (see current plot shown previously), after around 210msec, the triac turns−off and blocks the current flowing through the starter winding. In that moment, the total current flowing through the motor decreases until it reaches the nominal current (4.1 Arms) and the motor continues operating until the thermostat switch is switched off. Since the triac operates for very short times (around 210 msec), it does not need a heat sink, therefore, it can be placed on the control board without any kind of problems. In the previous schematic diagram the triac of 8 Arms (MAC8D,M), was selected based on the nominal and start current conditions of the compressor previously described (1 Phase, 115Vac, 60Hz, 4.1Arms). Therefore, it is important to mention that in these kind of applications, the triacs must be selected taking into consideration the characteristics of each kind of motor to control (nominal and start currents, frequency, Vac, power, etc). Also, it is important to remember that it is not possible to have a general reference for selecting the right triacs for each motor control application. In conclusion, the solid state solution described previously, provides a more reliable control than the conventional momentary switch controlled by a relay since the thyristors do not cause any kind of sparks when they start to operate. In addition, the total price of the electronic components do not exceed the price of the conventional relay approach. In summary, it is also important to mention that extreme environmental temperatures could affect the functionality of this momentary solid state switch, but it is a fact that the triac solution is able to operate between 0°C to 65°C. Another important consideration is to include in the power circuit of the motor the right overload switch in order to protect the motor and the triacs against overload phenomena.
- 186. © Semiconductor Components Industries, LLC, 1999 November, 1999 − Rev. 0 186 Publication Order Number: AND8008/D AND8008/D Solid State Control Solutions for Three Phase 1 HP Motor Prepared by: Alfredo Ochoa, Alex Lara Gabriel Gonzalez Thyristors Applications Engineers INTRODUCTION In all kinds of manufacturing, it is very common to have equipment that has three phase motors for doing different work functions on the production lines. These motor functions can be extruders, fans, transport belts, mixers, pumps, air compressors, etc. Therefore, it is necessary to have equipment for controlling the start and stop of the motors and in some cases for reversing them. Actually, one of the most common solutions for performing this control functions is by using three phase magnetic starters. It consists of a block with three main mechanical contacts which provide the power to the three main terminals of the motor once its coil is energized. However, the magnetic starter has a lot of disadvantages and the most common appear when they are driving high current levels that can cause arcing and sparks on their contacts each time they are activated or de−activated. Because of these kind of effects the contacts of the magnetic starters get very significantly damaged causing problems in their functionality. With time it can cause bad and inefficient operation of the motors. This is why, thyristor should be considered as a low cost alternative and indeed a powerful device for motor control applications. Thyristors can take many forms but they have certain features in common. All of them are solid state switches that act as open circuits capable of withstanding the rated voltage until triggered. When they are triggered, thyristors become low impedance current paths and remain in that condition (i.e. conduction) until the current either stops or drops below a minimum value called the holding level. Once a thyristor has been triggered, the trigger current can be removed without turning off the device. DEFINITIONS Three phase induction motor. A three phase induction motor consists of a stator winding and a rotor of one of the two following types: one type is a squirrel−cage rotor with a winding consisting of conducting bars embedded in slots in the rotor iron and short circuited at each end by conducting end rings. The other type is a wound rotor with a winding similar to and having the same number of poles as the stator winding, with the terminals of the winding being connected to the slip rings or collector rings on the left end of the shaft. Carbon brushes bearing on these rings make the rotor terminals available at points external to the motor so that additional resistance can be inserted in the rotor circuit if desired. Three phase voltages of stator frequency are induced in the rotor, and the accompanying currents are determined by the voltage magnitude and rotor impedance. Because they are induced by the rotating stator field, these rotor currents inherently produce a rotor field with the same number of poles as the stator and rotating at the same speed with respect to the stationary rotor. Rotor and stator fields are thus stationary with respect to each other in space, and a starting torque is produced. If this torque is sufficient to overcome the opposition to rotation created by the shaft load the motor will come up to its operating speed. The operating speed can never equal the synchronous speed of the stator field. The following figure shows a three phase 1HP motor controlled through a conventional magnetic starter which has an over−load relay for protecting the motor against over−load phenomena. http://onsemi.com APPLICATION NOTE
- 187. AND8008/D http://onsemi.com 187 Power Schematic 3 Phase Motor 1 H.P. L3L2L1 220 Vrms 60 Hz A A A OL OL OLNC A A Start Stop When the start button is pushed on, the coil of the magnetic starter (A) is energized, thereby, the mechanical switch contacts close allowing current−flow through the motor which starts it to operate. If the stop button is pushed, the coil (A) will be de−energized causing the motor to stop because of the mechanical switch contacts opened. In addition, if an overload phenomena exists in the circuit of the motor, the switch contact (NC) of the overload relay will open de−energizing the coil and protecting the motor against any kind of damage. Magnetic starters have a lot of disadvantages like arcing, corrosion of the switch contacts, sparks, noisy operation, short life span, etc. Therefore, in some motor applications, it is not useful to control the motors by using magnetic starters since the results can be undesirable. On the other hand, the following schematic diagrams show how thyristors can perform the same control function for starting and stopping a three phase 1HP motor. In addi- tion, the diagrams below show an over load circuit for pro- tecting the motor against overload phenomena.
- 188. AND8008/D http://onsemi.com 188 510 W MOC3062 MAC8N 510 W MOC3062 MAC8N 510 W MOC3062 MAC8N 3 Phase Motor 1 H.P. L3L2L1 Line Voltage 220 Vrms 60 Hz To Over Load Protection Circuit for Line 3 To Over Load Protection Circuit for Line 1 Current Transformer Current Transformer Diagram 1 Diagram 1 shows how three triacs (MAC8M) substitute the mechanical contacts of the conventional magnetic starter (shown previously) for supplying the power to the three phase 1HP motor once the triacs are triggered. It is important to mention that the optocoupler devices (MOC3061) will supply the signal currents to the triacs and hence the motor keeping the same phase shifting (120 electrical degrees) between lines. This is because these optocuplers (MOC3061) have zero crossing circuits within them. Another important thing must be considered as a protection for the triacs (MAC8M) against fast voltage transients, is a RC network called snubber which consists of a series resistor and capacitor placed around the triacs. These components along with the load inductance from a series CRL circuit. Many RC combinations are capable of providing acceptable performance. However, improperly used snubbers can cause unreliable circuit operation and damage to the semiconductor device. Snubber design involves compromises. They include cost, voltage rate, peak voltage, and turn−on stress. Practical solutions depend on the device and circuit physics. Diagram 2 shows an electronic over−load circuit which provides very reliable protection to the motor against over load conditions. The control signals for the two electronic over−load circuits are received from the shunt resistors connected in parallel to the two current transformers placed in two of the three main lines (L1, L3) for sensing the current flowing through the motor when it is operating. The level of the voltage signals appearing in the shunt resistors is dependent on the current flowing through each main line of the motor. Therefore, if it occurs, that an over load condition in the power circuit of the motor, that voltage level will increase its value causing the activation of the electronic over−load circuits which will stop the motor by protecting it against the over−load condition experienced.
- 189. AND8008/D http://onsemi.com 189 + − LM324 22 kW +12 Vdc +12 Vdc 220 mF 2 k 4.3 kW 1 kW Output Signal Connected to OR Gate’s Input One + − LM324 +12 Vdc +12 Vdc 25 kW 1 kW + − LM324 +12 Vdc 10 kW + − +12 Vdc 10 kW Over Load Protection Circuit for Line 1 10 kW 2 kW 220 mF MUR160 MUR160 1 kW0.1 W Shunt 1 kW 1 kW −12 Vdc −12 Vdc −12 Vdc MUR160 −12 Vdc + − LM324 22 kW +12 Vdc +12 Vdc 220 mF 2 k 4.3 kW 1 kW Output Signal Connected to OR Gate’s Input Two + − LM324 +12 Vdc +12 Vdc 25 kW 1 kW + − LM324 +12 Vdc 10 kW + − +12 Vdc 10 kW Over Load Protection Circuit for Line 3 10 kW 2 kW 220 mF MUR160 MUR160 1 kW0.1 W Shunt 1 kW 1 kW −12 Vdc −12 Vdc −12 Vdc MUR160 −12 Vdc Wire Conductor Line 3 Wire Conductor Line 1 LM324 LM324 Diagram 2
- 190. AND8008/D http://onsemi.com 190 MC14013 2N2222 510 W Start/Stop Control Circuit 1.5 kW +12 Vdc SD CD MOC3062 MOC3062 +12 Vdc 1 kW 1 kW Stop Button +12 Vdc MC14075 Start Button Q MOC3062 Output Signal from Over Load Protection Line 1 Output Signal from Over Load Protection Line 3 Diagram 3 Diagram 3 shows the main electronic control circuit for controlling the start and stop of the motor each time it is needed. If the start button is pushed on, the Flip Flop (MC14013) is activated triggering the transistor (2N2222) which turns on the optocoupler’s LED’s which in turn the three triacs (MAC8M) get triggered and finally starts the motor. The motor will stop to operate, whenever the stop button is pushed or any overload condition occurs in the power circuit of the motor. The following plot shows the motor’s start current waveform on one of the three phases when the motor starts to operate under normal operation conditions and without driving any kind of mechanical load: Ipk = 28.8 Amp start current 128 msec Ipk = 2.8 Amp Normal operation
- 191. AND8008/D http://onsemi.com 191 This other plot shows the motor’s start current waveform of the three phases when the motor start to operate under normal operation conditions and without mechanical load. Phase R start current Waveform Phase S start current Waveform Phase T start current Waveform The previous plots show the maximum start current IPK of the motor when it starts to operate and how long it takes before the current reaches its nominal value. Here, It is important to mention that the triacs (MAC8N) were selected by taking into consideration the motor’s start current value as well as the ITSM capability of these devices. Therefore, if it is needed to control motors with higher power (more than 1HP), first, it would be necessary to characterize them in order to know their current characteristics. Next be able to select the right triacs for controling the motor without any kind of problems. Another important item must be considered if it is needed to control motors with higher power. These are the electronic over−load circuits, which have to be adjusted taking into consideration the level of overload current that is needed to protect, and is dependent on the kind of motor that is being controlled. Based in the previous diagrams and plots, it has been proven that triacs can substitute the function of the magnetic starters for starting and stopping a three phase 1HP motor as well as for protecting it against overload conditions. The following schematics show a solid state solution for controlling and reversing a three phase 1HP motor:
- 192. AND8008/D http://onsemi.com 192 + − LM339 2N2222 510 W MC14013 2N2222 510 W + − LM339 10 kW MC14013 Reverse Control Schematic Stop +12 Vdc +12 Vdc Right 1 kW 1 kW 1.5 kW 10 kW +12 Vdc +12 Vdc 220 mF 2 k 4.3 kW +12 Vdc +12 Vdc From Over Load Protection Circuit MC14075 MC14075 MC14075 R Q S R Q S 1 kW Left MUR160 MOC3062 5 MOC3062 4 Left MOC3062 1 MUR160 MOC3062 2 MOC3062 3 Right 1.5 kW 4.3 kW 10 kW 220 mF +12 Vdc +12 Vdc +12 Vdc +12 Vdc 2 k +12 Vdc 10 kW Schematic 1 Schematic 1 shows the control diagram for controlling and reversing the motor depending on which direction it is needed to operate. If the right−button is pushed−on, the triacs number 1, 2, and 3 (shown in the schematic 2) will be activated, thereby, the motor will operate in the right direction. If the left button is pushed−on, the triacs numbered 1, 4, and 5 will be activated causing the left operation of the motor. Because of the design of the control circuit, it is possible to reverse the motor without stopping it once it is operating in right direction. This means, it is not necessary to stop the motor in order to reverse itself. Nevertheless, it is important to mention that the control circuit takes a delay−time (of around 3 seconds) before it activates the other triacs (1,4,5) for reversing the motor. This delay is to assure that the triacs operating (1,2,3) will be completely in the off state before it turns−on those other triacs. This delay−time is very important because if the triacs for reversing the motor are activated before the other triacs triggered have reached their completely turned−off state, it may cause a big short circuit between phases. If this happens the triacs will be damaged.
- 193. AND8008/D http://onsemi.com 193 510 W Power Schematic MOC3062 1 51 W 10 nF MAC8N 510 W MOC3062 2 51 W 10 nF MAC8N 510 W MOC3062 3 51 W 10 nF MAC8N 510 W MOC3062 4 51 W 10 nF MAC8N 510 W MOC3062 5 51 W 10 nF MAC8N 3 Phase Motor 1 H.P. L3L2L1 220 Vrms 60 Hz To Over Load Circuit 2 To Over Load Circuit 1 Schematic 2 Schematic 2 shows the power diagram for reversing a three phase 1HP motor. The way it makes this reverse function control is by changing the phases−order supplied to the motor through the triacs (number 4 and 5) and it is based in the motorís principle for reversing itself. This diagram also shows two current transformer placed in two of the three main lines of the motor for sending the control signals to the electronic overload circuit described previously. So this means, that the same overload concept is applicable to these schematics as well as the motor’s start current waveforms and characteristics shown and explained previously. In conclusion, it is proven that thyristors can substitute to the magnetic starters for making three phase motor control function in more efficient ways. Because thyristors are very reliable power switches, they can offer many advantages in motor applications. Some of the advantages of triacs as replacements for relays include: • High Commutating di/dt and High Immunity to dv/dt @ 125°C • Small size and light weight. • Safety − freedom form arcing and spark initiated explosions. • Long life span − contact bounce and burning eliminated. • Fast operation − turn−on in microseconds and turn−off in milliseconds. • Quiet operation. The above mentioned points are only some of the big advantages that can be had if thyristors are used for making motor control function. Besides, the total cost of the previous control and power circuits does not exceed to the cost of the conventional magnetic starters. One more consideration is that extreme environmental temperatures could effect the functionality of the electronic control circuits described herein. Therefore, if the operation is needed under extreme ambient temperatures, the designer must evaluate the parameter variation of all the electronic devices in order to assure the right operation in the application circuit.
- 194. © Semiconductor Components Industries, LLC, 1999 January, 2000 − Rev. 0 194 Publication Order Number: AND8015/D AND8015/D Long Life Incandescent Lamps using SIDACs Prepared by: Alfredo Ochoa, Alex Lara Gabriel Gonzalez Thyristor Application Engineers Abstract Since the invention of the incandescent lamp bulb by the genius Thomas A. Edison in 1878, there has been little changes in the concept. Nowadays we are currently use them in our houses, and they are part of our comfort but, since we are more environmentally conscious and more demanding on energy cost saving products, along with their durability, we present here an application concept involved this simple incandescent lamp bulb in conjunction with the Bilateral Trigger semiconductor device called SIDAC, offering an alternative way to save money in energy con- sumption and also giving a longer life time to the lamp bulbs. Theory of the SIDAC The SIDAC is a high voltage bilateral trigger device that extends the trigger capabilities to significantly higher volt- ages and currents than have been previously obtainable, thus permitting new, cost effective applications. Being a bilateral device, it will switch from a blocking state to a conducting state when the applied voltage of either polarity exceeds the breakover voltage. As in other trigger devices, the SIDAC switches through a negative resistance region to the low voltage on−state and will remain on until the main terminal current is interrupted or drops below the holding current. SIDAC’s are available in the large MKP3V series and the economical, easy to insert, small MKP1V series axial lead packages. Breakdown voltages ranging from 110 to 250V are available. The MKP3V devices feature bigger chips and provide much greater surge capability along with some- what higher RMS current ratings. The high voltage and current ratings of SIDACs make them ideal for high energy applications where other trigger devices are unable to function alone without the aid of addi- tional power boosting components. The following figure shows the idealized SIDAC characteristics: VTM IH VDRM Slope = Rs IDRM Rs = (V(BO) − VS) (IS − I(BO)) ITM IS VS V(BO) I(BO) Once the input voltage exceeds V(BO), the device will switch on to the forward on−voltage VTM of typically 1.1 V and can conduct as much as the specified repetitive peak on state current ITSM of 20A (10μs pulse, 1KHz repetition frequency). SIDACs can be used in many applications as transient protectors, Over Voltage Protectors, Xeon flasher, relax- ation oscillators, sodium vapor lamp starters, etc. http://onsemi.com APPLICATION NOTE
- 195. AND8015/D http://onsemi.com 195 This paper explains one of the most typical applications for SIDACs which is a long life circuit for incandescent lamps. The below schematic diagrams show the configurations of a SIDAC used in series with an incandescent lamp bulb through a fixed phase for the most typical levels of ac line voltages: Option 1: ac line voltage 110V, 60Hz or 50Hz SIDAC MKP1V120RL 100 WATTS 110V AC Line 110V, 60 Hz Option 2: ac line voltage 220V, 60Hz or 50 Hz SIDAC MKP1V120RL 100 WATTS 220V AC Line 220V, 60 Hz This is done in order to lower the RMS voltage to the fila- ment, and prolong the life of the bulb. This is particularly useful when lamps are used in hard to reach locations such as outdoor lighting in signs where replacement costs are high. Bulb life span can be extended by 1.5 to 5 times depending on the type of lamp, the amount of power reduc- tion to the filament, and the number of times the lamp is switched on from a cold filament condition. The operating cost of the lamp is also reduced because of the lower power to the lamp; however, a higher wattage bulb is required for the same lumen output. The maximum possible energy reduction is 50% if the lamp wattage is not increased. The minimum conduction angle is 90° because the SIDAC must switch on before the peak of the line volt- age. Line regulation and breakover voltage tolerances will require that a conduction angle longer than 90° be used, in order to prevent lamp turn−off under low line voltage conditions. Consequently, practical conduction angles will run between 110° and 130° with corresponding power reductions of 10% to 30%. The following plots show the basic voltage and current waveforms in the SIDAC and load:
- 196. AND8015/D http://onsemi.com 196 Incandescent Lamp of 100W, 110V, 60Hz Ch1 Voltage Vpk = 123V V(BO) Ch2 Current Ipk = 0.96A −V(BO) Conduction Angle Incandescent Lamp of 50W, 220V, 60Hz Ch1 Voltage Vpk = 121V V(BO) Ch2 Current Ipk = 0.33A −V(BO) Conduction Angle In both previous cases, once the ac line voltage reaches the V(BO) of the SIDAC (MKP1V120RL), it allows cur- rent flow to the incandescent lamp causing the turn−on of this at some specific phase−angle which is determined by the SIDAC because of its V(BO). The fast turn−on time of the SIDAC will result in the gen- eration of RFI which may be noticeable on AM radios oper- ated in the vicinity of the lamp. This can be prevented by the use of an RFI filter. A possible filter can be the follow- ing: connect an inductor (100μH) in series with the SIDAC and a capacitor (0.1μF) in parallel with the SIDAC and inductor. This filter causes a ring wave of current through the SIDAC at turn on time. The filter inductor must be selected for resonance at a frequency above the upper fre- quency limit of human hearing and as low below the start of the AM broadcast band as possible for maximum harmonic attenuation. In addition, it is important that the filter induc- tor be non−saturating to prevent di/dt damage to the SIDAC. The sizing of the SIDAC must take into account the RMS current of the lamp, thermal properties of the SIDAC, and the cold start surge current of the lamp which is often 10 to 20 times the steady state load current. When lamps burn out, at the end of their operating life, very high surge cur- rents which could damage the SIDAC are possible because of arcing within the bulb. The large MKP3V device is rec- ommended if the SIDAC is not to be replaced along with the bulb. In order to establish what will be the average power that an incandescent lamp is going to offer if a SIDAC (MKP1V120RL) is connected in series within the circuit, some ideal calculations could be made for these purposes
- 197. AND8015/D http://onsemi.com 197 Example: Incandescent lamp of 100W (120V, 60Hz). 200 100 0 −100 −200 0.0080.0060.0040.0020 time in seconds v(t): Voltage waveform in the SIDAC l(t): Portion of current waveform applied to the load (Multiplied by a factor of 100 to make it more graphically visible) VL(t): Voltage waveform in the Load v(t): i(t) x 100: VL(t): Voltage/Current In this case, the conduction angle is around 130° (6 msecs) in each half cycle of the sinusoidal current wave- form, therefore, the average power of the lamp can be obtained by calculating the following operations: i eff + 2 T ŕ 8.33 10*3 0 i(t) 2 dtǸ v eff + 2 T ŕ 8.33 10*3 0 v(t) 2 dtǸ Pav = ieffVLeff Pav = 91.357 Based on this, it is possible to observe that the average power output is a little bit lower than the original power of the lamp (100W), even though the conduction angle is being reduced because of the SIDAC. In conclusion, when a SIDAC is used to phase control an incandescent lamp, the operation life of the bulb is going to be extended by 1.5 to 5 times which represents a big eco- nomical advantage when compared to the total cost of the lamp if it is changed. In addition, the original power of the lamp is not going to be reduced considerably which assures the proper level of illumination for the area in which the incandescent lamp is being used for. Finally, since the SIDACs are provided in a very small axial lead package, they can be mounted within the same place that the incan- descent lamp is placed.
- 198. © Semiconductor Components Industries, LLC, 1999 January, 2000 − Rev. 0 198 Publication Order Number: AND8017/D AND8017/D Solid State Control for Bi−Directional Motors Prepared by: Alfredo Ochoa, Alex Lara Gabriel Gonzalez Thyristor Application Engineers INTRODUCTION Some split phase motors are able to operate in forward and reverse directions since they have two windings for these purposes. Depending on which winding is energized, the motor operates in that direction. These motors are espe- cially used in applications for washing machines, transport belts, and all kinds of equipment in which the operation in both directions is needed. One of the most traditional way to control these kind of motors is through mechanical relays. Nevertheless, they have a lot of disadvantages which make them ineffective. This paper is going to show how triacs can substitute the function of the mechanical relays for controlling bi−direc- tional motors offering a higher level of quality and reliabil- ity for control purposes. The triac is a three terminal ac semiconductor switch that is triggered into conduction when a low energy signal is applied to its gate. Unlike the silicon controlled rectifier or SCR, the triac will conduct current in either direction when turned on. The triac also differs from the SCR in that either a positive or negative gate signal will trigger the triac into conduction. The triac may be thought of as two comple- mentary SCRs in parallel. The triac offers the circuit designer an economical and versatile means of accurately controlling ac power. It has several advantages over conventional mechanical switches. Since the triac has a positive ’on’ and a zero current ’off’ characteristics, it does not suffer from the contact bounce or arcing inherent in mechanical switches. The switching action of the triac is very fast compared to conventional relays, giving more accurate control. A triac can be trig- gered by dc, ac, rectified ac or pulses. Because of the low energy required for triggering a triac, the control circuit can use any of many low cost solid state devices such as transis- tors, sensitive gate SCRs and triacs, optically coupled drivers, and integrated circuits. DEFINITIONS The two−phase induction motor consists of a stator with two windings displaced 90 electrical degrees from each other in space and squirrel cage rotor or the equivalent. The ac voltages applied to the two windings are generally phase displaced from each other 90° in time. When the voltages magnitudes are equal, the equivalent of balanced two− phase voltages is applied to the stator. The resultant stator flux is then similar to a three−phase induction motor. The motor torque speed curves are also similar to those of a three−phase motor. The two−phase control motor is usually built with a high resistance rotor to give a high starting torque and a dropping torque speed characteristic. The following schematic diagram shows an ac split phase motor: Winding A Switch 1 Line Switch 2 Winding B http://onsemi.com APPLICATION NOTE
- 199. AND8017/D http://onsemi.com 199 If switch 1 is activated, rotation in one direction is obtained; if switch 2 is activated, rotation in the other direction results. Since the torque is a function of the volt- age supply, changing the magnitude of this changes the developed torque of the motor. The stalled torque is assumed to be linearly proportional to the rms control− winding voltage. It is very common to add a resonant L−C circuit connected between the motor windings in order to damp the energy stored by each motor winding inductance, avoiding damage to the switches when the transition from one direction to the other occurs. In addition, this resonant L−C circuit helps to have good performance in the motor’s torque each time it changes its rotation. The following schematic diagram shows how two triacs can control the rotation of a split phase motor depending in which winding is energized. In this case the motor selected for analysis purposes has the following technical characteristics: 230Vrms, 1.9 Arms, 1/4 Hp, 60Hz, 1400 RPM. MOC3042 2 k 220 VAC 60 Hz 51 W 10 nF MT1 MT2 MOV 10 k MAC210A10FP MOC3042 2 k 51 W 10 nF MT1 MT2 MOV 10 k MAC210A10FP mC HC Direct Negative Logic Driven by Microcontroller 15 mF 50 mH Winding 2Winding 1 Split Phase Motor 1/4 Hp, 230 V RPM 1400 G G The micro is controlling the trigger of the triacs through optocouplers (MOC3042). The optocoupler protects the control circuitry (Microcontroller, Logic Gates, etc.) if a short circuit condition occurs within the power circuitry since these optocouplers insolate the control part of the general circuit. The MOVs protects the triacs against to the high voltage transients caused because of the motor rota- tion changes, so it is very important to add them in the power circuit, otherwise the triacs could be damaged easily. The snubber arrangement provides protection against dV/dt conditions occurring within the application circuit and the resonant L−C circuit connected between the motor’s wind- ings helps to have good performance in the torque of the motor when it changes its rotation. In the case that the motor is locked due to some mechan- ical problem within the application field, the maximum current peak flowing through the triacs would be 7.2 Amps (5.02 Amps rms), therefore, the triacs (MAC210A10FP) would not be damaged since they are able to handle up to 12 A rms. Nevertheless, it is recommended to add an overload protector in the power circuit of the motor in order to protect it against any kind of overload conditions which
- 200. AND8017/D http://onsemi.com 200 could damage the motor in a short period of time since the current flowing would be higher than its nominal value. In conclusion, it has been shown how triacs (MAC210A10FP) substitute the mechanical relay’s functions to control bi−directional motors offering many important advantages like reliable control, quiet operation, long life span, small size, light weight, fast operation, among others. These are only some of the big advantages that can be obtained if thyristors are used to control bi−directional motors. Besides, the total cost of the electronic circuitry does not exceed to the cost of the conventional mechanical relays. A very important consideration is that extreme environment temperatures could affect the functionality of the electronic devices, therefore, if operation under extreme ambient temperatures is needed, the designer must take into consideration the parameter variation of the electronic devices in order to establish if any kind of adjustment is needed within the electronic circuitry. Another important item to be considered by the designer is that the triacs have to be mounted on a proper heatsink in order to assure that the case temperature of the device does not exceed the specifications shown in the datasheet.
- 201. http://onsemi.com 201 SECTION 7 MOUNTING TECHNIQUES FOR THYRISTORS Edited and Updated INTRODUCTION Current and power ratings of semiconductors are inseparably linked to their thermal environment. Except for lead-mounted parts used at low currents, a heat exchanger is required to prevent the junction temperature from exceeding its rated limit, thereby running the risk of a high failure rate. Furthermore, the semiconductor industry’s field history indicated that the failure rate of most silicon semiconductors decreases approximately by one half for a decrease in junction temperature from 160°C to 135°C.(1) Guidelines for designers of military power supplies impose a 110°C limit upon junction temperature.(2) Proper mounting minimizes the tempera- ture gradient between the semiconductor case and the heat exchanger. Most early life field failures of power semiconductors can be traced to faulty mounting procedures. With metal packaged devices, faulty mounting generally causes unnecessarily high junction temperature, resulting in reduced component lifetime, although mechanical dam- age has occurred on occasion from improperly mounting to a warped surface. With the widespread use of various plastic-packaged semiconductors, the prospect of mechanical damage is very significant. Mechanical damage can impair the case moisture resistance or crack the semiconductor die. (1) MIL-HANDBOOK — 2178, SECTION 2.2. (2) “Navy Power Supply Reliability — Design and Manufacturing Guidelines” NAVMAT P4855-1, Dec. 1982 NAVPUBFORCEN, 5801 Tabor Ave., Philadelphia, PA 19120. Figure 7.1 shows an example of doing nearly every- thing wrong. A tab mount TO-220 package is shown being used as a replacement for a TO-213AA (TO-66) part which was socket mounted. To use the socket, the leads are bent — an operation which, if not properly done, can crack the package, break the internal bonding wires, or crack the die. The package is fastened with a sheet-metal screw through a 1/4″ hole containing a fiber-insulating sleeve. The force used to tighten the screw tends to pull the package into the hole, causing enough distortion to crack the die. In addition the contact area is small because of the area consumed by the large hole and the bowing of the package; the result is a much higher junction temperature than expected. If a rough heatsink surface and/or burrs around the hole were displayed in the illustration, most but not all poor mounting practices would be covered. SPEED NUT (PART OF SOCKET) PLASTIC BODY LEADS EQUIPMENT HEATSINK PACKAGE HEATSINK SOCKET FOR TO-213AA PACKAGE SHEET METAL SCREW MICA WASHER Figure 7.1. Extreme Case of Improperly Mounting A Semiconductor (Distortion Exaggerated)
- 202. http://onsemi.com 202 In many situations the case of the semiconductor must be electrically isolated from its mounting surface. The isolation material is, to some extent, a thermal isolator as well, which raises junction operating temperatures. In addition, the possibility of arc-over problems is introduced if high voltages are present. Various regulating agencies also impose creepage distance specifications which further complicates design. Electrical isolation thus places additional demands upon the mounting procedure. Proper mounting procedures usually necessitate orderly attention to the following: 1. Preparing the mounting surface 2. Applying a thermal grease (if required) 3. Installing the insulator (if electrical isolation is desired) 4. Fastening the assembly 5. Connecting the terminals to the circuit In this note, mounting procedures are discussed in general terms for several generic classes of packages. As newer packages are developed, it is probable that they will fit into the generic classes discussed in this note. Unique requirements are given on data sheets pertaining to the particular package. The following classes are defined: Stud Mount Flange Mount Pressfit Plastic Body Mount Tab Mount Surface Mount Appendix A contains a brief review of thermal resistance concepts. Appendix B discusses measurement difficulties with interface thermal resistance tests. MOUNTING SURFACE PREPARATION In general, the heatsink mounting surface should have a flatness and finish comparable to that of the semiconduc- tor package. In lower power applications, the heatsink surface is satisfactory if it appears flat against a straight edge and is free from deep scratches. In high-power applications, a more detailed examination of the surface is required. Mounting holes and surface treatment must also be considered. Surface Flatness Surface flatness is determined by comparing the variance in height (Δh) of the test specimen to that of a reference standard as indicated in Figure 7.2. Flatness is normally specified as a fraction of the Total Indicator Reading (TIR). The mounting surface flatness, i.e., Δh/TIR, if less than 4 mils per inch, normal for extruded aluminum, is satisfactory in most cases. SAMPLE PIECE TIR = TOTAL INDICATOR READING ΔhTIR REFERENCE PIECE DEVICE MOUNTING AREA Figure 7.2. Surface Flatness Measurement Surface Finish Surface finish is the average of the deviations both above and below the mean value of surface height. For minimum interface resistance, a finish in the range of 50 to 60 microinches is satisfactory; a finer finish is costly to achieve and does not significantly lower contact resis- tance. Tests conducted by Thermalloy using a copper TO-204 (TO-3) package with a typical 32-microinch finish, showed that heatsink finishes between 16 and 64 μ-in caused less than ± 2.5% difference in interface thermal resistance when the voids and scratches were filled with a thermal joint compound.(3) Most commer- cially available cast or extruded heatsinks will require spotfacing when used in high-power applications. In general, milled or machined surfaces are satisfactory if prepared with tools in good working condition. Mounting Holes Mounting holes generally should only be large enough to allow clearance of the fastener. The large thick flange type packages having mounting holes removed from the semiconductor die location, such as the TO-3, may successfully be used with larger holes to accommodate an insulating bushing, but many plastic encapsulated pack- ages are intolerant of this condition. For these packages, a smaller screw size must be used such that the hole for the bushing does not exceed the hole in the package. Punched mounting holes have been a source of trouble because if not properly done, the area around a punched hole is depressed in the process. This “crater” in the heatsink around the mounting hole can cause two problems. The device can be damaged by distortion of the package as the mounting pressure attempts to conform it to the shape of the heatsink indentation, or the device may only bridge the crater and leave a significant percentage of its heat-dissipating surface out of contact with the heatsink. The first effect may often be detected immedi- ately by visual cracks in the package (if plastic), but usually an unnatural stress is imposed, which results in an early-life failure. The second effect results in hotter operation and is not manifested until much later. (3) Catalog #87-HS-9 (1987), page 8, Thermalloy, Inc., P.O. Box 810839, Dallas, Texas 75381-0839.
- 203. http://onsemi.com 203 Although punched holes are seldom acceptable in the relatively thick material used for extruded aluminum heatsinks, several manufacturers are capable of properly utilizing the capabilities inherent in both fine-edge blanking or sheared-through holes when applied to sheet metal as commonly used for stamped heatsinks. The holes are pierced using Class A progressive dies mounted on four-post die sets equipped with proper pressure pads and holding fixtures. When mounting holes are drilled, a general practice with extruded aluminum, surface cleanup is important. Chamfers must be avoided because they reduce heat transfer surface and increase mounting stress. However, the edges must be broken to remove burrs which cause poor contact between device and heatsink and may puncture isolation material. Surface Treatment Many aluminium heatsinks are black-anodized to improve radiation ability and prevent corrosion. Anodiz- ing results in significant electrical but negligible thermal insulation. It need only be removed from the mounting area when electrical contact is required. Heatsinks are also available which have a nickel plated copper insert under the semiconductor mounting area. No treatment of this surface is necessary. Another treated aluminum finish is iridite, or chromate- acid dip, which offers low resistance because of its thin surface, yet has good electrical properties because it resists oxidation. It need only be cleaned of the oils and films that collect in the manufacture and storage of the sinks, a practice which should be applied to all heatsinks. For economy, paint is sometimes used for sinks; removal of the paint where the semiconductor is attached is usually required because of paint’s high thermal resistance. However, when it is necessary to insulate the semiconductor package from the heatsink, hard anodized or painted surfaces allow an easy installation for low voltage applications. Some manufacturers will provide anodized or painted surfaces meeting specific insulation voltage requirements, usually up to 400 volts. It is also necessary that the surface be free from all foreign material, film, and oxide (freshly bared aluminum forms an oxide layer in a few seconds). Immediately prior to assembly, it is a good practice to polish the mounting area with No. 000 steel wool, followed by an acetone or alcohol rinse. INTERFACE DECISIONS When any significant amount of power is being dissipated, something must be done to fill the air voids between mating surfaces in the thermal path. Otherwise the interface thermal resistance will be unnecessarily high and quite dependent upon the surface finishes. For several years, thermal joint compounds, often called grease, have been used in the interface. They have a resistivity of approximately 60°C/W/in whereas air has 1200°C/W/in. Since surfaces are highly pock-marked with minute voids, use of a compound makes a significant reduction in the interface thermal resistance of the joint. However, the grease causes a number of problems, as discussed in the following section. To avoid using grease, manufacturers have developed dry conductive and insulating pads to replace the more traditional materials. These pads are conformal and therefore partially fill voids when under pressure. Thermal Compounds (Grease) Joint compounds are a formulation of fine zinc or other conductive particles in the silicone oil or other synthetic base fluid which maintains a grease-like consistency with time and temperature. Since some of these compounds do not spread well, they should be evenly applied in a very thin layer using a spatula or lintless brush, and wiped lightly to remove excess material. Some cyclic rotation of the package will help the compound spread evenly over the entire contact area. Some experimentation is neces- sary to determine the correct quantity; too little will not fill all the voids, while too much may permit some compound to remain between well mated metal surfaces where it will substantially increase the thermal resistance of the joint. To determine the correct amount, several semiconduc- tor samples and heatsinks should be assembled with different amounts of grease applied evenly to one side of each mating surface. When the amount is correct a very small amount of grease should appear around the perimeter of each mating surface as the assembly is slowly torqued to the recommended value. Examination of a dismantled assembly should reveal even wetting across each mating surface. In production, assemblers should be trained to slowly apply the specified torque even though an excessive amount of grease appears at the edges of mating surfaces. Insufficient torque causes a significant increase in the thermal resistance of the interface. To prevent accumulation of airborne particulate matter, excess compound should be wiped away using a cloth moistened with acetone or alcohol. These solvents should not contact plastic-encapsulated devices, as they may enter the package and cause a leakage path or carry in substances which might attack the semiconductor chip. The silicone oil used in most greases has been found to evaporate from hot surfaces with time and become deposited on other cooler surfaces. Consequently, manufacturers mustdetermine whetheramicroscopically thin coating of silicone oil on the entire assembly will pose any problems. It may be necessary to enclose components using grease. The newer synthetic base greases show far less tendency to migrate or creep than those made with a silicone oil base. However, their currently observed working temperature range are less,
- 204. http://onsemi.com 204 they are slightly poorer on thermal conductivity and dielectric strength and their cost is higher. Data showing the effect of compounds on several package types under different mounting conditions is shown in Table 7.1. The rougher the surface, the more valuable the grease becomes in lowering contact resis- tance; therefore, when mica insulating washers are used, use of grease is generally mandatory. The joint compound also improves the breakdown rating of the insulator. Conductive Pads Because of the difficulty of assembly using grease and the evaporation problem, some equipment manufacturers will not, or cannot, use grease. To minimize the need for grease, several vendors offer dry conductive pads which approximate performanceobtainedwithgrease.Datafora greased bare joint and a joint using Grafoil, a dry graphite compound, is shown in the data of Figure 7.3. Grafoil is claimed to be a replacement for grease when no electrical isolation is required; the data indicates it does indeed perform as well as grease. Another conductive pad available from Aavid is called KON-DUX. It is made with a unique, grain oriented, flake-like structure (pat- ent pending). Highlycompressible, itbecomesformedto the surface roughness of both of the heatsink and semiconductor. Manufacturer’s data shows it to provide an interface thermal resistance better than a metal interface with filled silicone grease. Similar dry conduc- tive pads are available from other manufacturers. They are a fairly recent development; long term problems, if they exist, have not yet become evident. Table 7.1 Approximate Values for Interface Thermal Resistance Data from Measurements Performed in ON Semiconductor Applications Engineering Laboratory Dry interface values are subject to wide variation because of extreme dependence upon surface conditions. Unless otherwise noted the case temperature is monitored by a thermocouple located directly under the die reached through a hole in the heatsink. (See Appendix B for a discussion of Interface Thermal Resistance Measurements.) Package Type and Data Interface Thermal Resistance (°C/W) JEDEC Outlines Description Test Torque In-Lb Metal-to-Metal With Insulator See NoteDry Lubed Dry Lubed Type DO-203AA, TO-210AA TO-208AB 10-32 Stud 7/16″ Hex 15 0.3 0.2 1.6 0.8 3 mil Mica DO-203AB, TO-210AC TO-208 1/4-28 Stud 11/16″ Hex 25 0.2 0.1 0.8 0.6 5 mil Mica DO-208AA Pressfit, 1/2″ — 0.15 0.1 — — — TO-204AA (TO-3) Diamond Flange 6 0.5 0.1 1.3 0.36 3 mil Mica 1 TO-213AA (TO-66) Diamond Flange 6 1.5 0.5 2.3 0.9 2 mil Mica TO-126 Thermopad 1/4″ x 3/8″ 6 2.0 1.3 4.3 3.3 2 mil Mica TO-220AB Thermowatt 8 1.2 1.0 3.4 1.6 2 mil Mica 1, 2 NOTES: 1. See Figures 3 and 4 for additional data on TO-3 and TO-220 packages. 2. Screw not insulated. See Figure 7. INSULATION CONSIDERATIONS Since most power semiconductors use are vertical device construction it is common to manufacture power semiconductors with the output electrode (anode, collec- tor or drain) electrically common to the case; the problem of isolating this terminal from ground is a common one. For lowest overall thermal resistance, which is quite important when high power must be dissipated, it is best to isolate the entire heatsink/semiconductor structure from ground, rather than to use an insulator between the semiconductor and the heatsink. Heatsink isolation is not always possible, however, because of EMI requirements, safety reasons, instances where a chassis serves as a heatsink or where a heatsink is common to several non-isolated packages. In these situations insulators are used to isolate the individual components from the heatsink. Newer packages, such as the ON Semiconductor Isolated TO-220 Full Pack, was introduced to save the equipment manufacturer the burden of addressing the isolation problem.
- 205. http://onsemi.com 205 Insulator Thermal Resistance When an insulator is used, thermal grease is of greater importance than with a metal-to-metal contact, because two interfaces exist instead of one and some materials, such as mica, have a hard, markedly uneven surface. With many isolation materials reduction of interface thermal resistance of between 2 to 1 and 3 to 1 are typical when grease is used. Data obtained by Thermalloy, showing interface resis- tance for different insulators and torques applied to TO-204 (TO-3) and TO-220 packages, are shown in Figure 7.3, for bare and greased surfaces. Similar materials to those shown are available from several manufacturers. It is obvious that with some arrangements, the interface thermal resistance exceeds that of the semiconductor (junction to case). Referring to Figure 7.3, one may conclude that when high power is handled, beryllium oxide is unquestion- ably the best. However, it is an expensive choice. (It should not be cut or abraided, as the dust is highly toxic.) Thermafilm is filled polyimide material which is used for isolation (variation of Kapton). It is a popular material for low power applications because of its low cost ability to withstand high temperatures, and ease of handling in contrast to mica which chips and flakes easily. (1) 65 (6) (2) (5) 0 (7) 2 (4) (3) 3 41 0.1 1 0 0.9 MOUNTING SCREW TORQUE (IN-LBS) 0.8 0.7 0.6 0.5 0.4 0.2 (c). TO-220 Without Thermal Grease 5 0 (1) 3 2 1 0 1 2 4 5 6(IN-LBS) (3) 4 435362290217 (7) 14572 (6) (5) (4) (3) (7) (4) (2) 1 (1) 5 4 3 2 (8) 0 1 MOUNTING SCREW TORQUE (IN-LBS) 654320 INTERFACE PRESSURE (psi) (7) (4) (2) MOUNTING SCREW TORQUE (IN-LBS) (3) (d). TO-220 With Thermal Grease (b). TO-204AA (TO-3) With Thermal Grease 0 (2) (1) (5) (8) (6) 1 1.6 65432 0 14572 0.4 0.2 0.6 0.8 1 1.2 1.4 2 0 4353622902170 MOUNTING SCREW TORQUE (IN-LBS) INTERFACE PRESSURE (psi) (a). TO-204AA (TO-3) Without Thermal Grease 0.3 Figure 7.3. Interface Thermal Resistance for TO-204, TO-3 and TO-220 Packages using Different Insulating Materials as a Function of Mounting Screw Torque (Data Courtesy Thermalloy) (1) Thermalfilm, .002 (.05) thick. (2) Mica, .003 (.08) thick. (3) Mica, .002 (.05) thick. (4) Hard anodized, .020 (.51) thick. (5) Aluminum oxide, .062 (1.57) thick. (6) Beryllium oxide, .062 (1.57) thick. (7) Bare joint — no finish. (8) Grafoil, .005 (.13) thick.* *Grafoil is not an insulating material. (1) Thermalfilm, .022 (.05) thick. (2) Mica, .003 (.08) thick. (3) Mica, .002 (.05) thick. (4) Hard anodized, .020 (.51) thick. (5) Thermalsil II, .009 (.23) thick. (6) Thermalsil III, .006 (.15) thick. (7) Bare joint — no finish. (8) Grafoil, .005 (.13) thick* *Grafoil is not an insulating material. THERMALRESISTANCEFROMTRANSISTORCASE TOMOUNTINGSURFACE,R(C/WATT)θCS° THERMALRESISTANCEFROMTRANSISTORCASE TOMOUNTINGSURFACE,R(C/WATT)θCS° THERMALRESISTANCEFROMTRANSISTORCASE TOMOUNTINGSURFACE,R(C/WATT)θCS° THERMALRESISTANCEFROMTRANSISTORCASE TOMOUNTINGSURFACE,R(C/WATT)θCS°
- 206. http://onsemi.com 206 A number of other insulating materials are also shown. They cover a wide range of insulation resistance, thermal resistance and ease of handling. Mica has been widely used in the past because it offers high breakdown voltage and fairly low thermal resistance at a low cost but it certainly should be used with grease. Silicone rubber insulators have gained favor because they are somewhat conformal under pressure. Their ability to fill in most of the metal voids at the interface reduces the need for thermal grease. When first introduced, they suffered from cut-through after a few years in service. The ones presently available have solved this problem by having imbedded pads of Kapton of fiberglass. By comparing Figures 7.3(c) and 7.3(d), it can be noted that Thermasil, a filled silicone rubber, without grease has about the same interface thermal resistance as greased mica for the TO-220 package. A number of manufacturers offer silicone rubber insulators. Table 7.2 shows measured performance of a number of these insulators under carefully controlled, nearly identical conditions. The interface thermal resis- tance extremes are over 2:1 for the various materials. It is also clear that some of the insulators are much more tolerant than others of out-of-flat surfaces. Since the tests were performed, newer products have been introduced. The Bergquist K-10 pad, for example, is described as having about 2/3 the interface resistance of the Sil Pad 1000 which would place its performance close to the Chomerics 1671 pad. AAVID also offers an isolated pad called Rubber-Duc, however it is only available vulca- nized to a heatsink and therefore was not included in the comparison. Published data from AAVID shows RθCS below 0.3°C/W for pressures above 500 psi. However, surface flatness and other details are not specified so a comparison cannot be made with other data in this note. Table 7.2 Thermal Resistance of Silicone Rubber Pads Manufacturer Product RθCS @ 3 Mils* RθCS @ 7.5 Mils* Wakefield Bergquist Stockwell Rubber Bergquist Thermalloy Shin-Etsu Bergquist Chomerics Wakefield Bergquist Ablestik Thermalloy Chomerics Delta Pad 173-7 Sil Pad K-4 1867 Sil Pad 400-9 Thermalsil II TC-30AG Sil Pad 400-7 1674 Delta Pad 174-9 Sil Pad 1000 Thermal Wafers Thermalsil III 1671 .790 .752 .742 .735 .680 .664 .633 .592 .574 .529 .500 .440 .367 1.175 1.470 1.015 1.205 1.045 1.260 1.060 1.190 .755 .935 .990 1.035 .655 * Test Fixture Deviation from flat from Thermalloy EIR86-1010. The thermal resistance of some silicone rubber insula- tors is sensitive to surface flatness when used under a fairly rigid base package. Data for a TO-204AA (TO-3) package insulated with Thermasil is shown on Figure 7.4. Observe that the “worst case” encountered (7.5 mils) yields results having about twice the thermal resistance of the “typical case” (3 mils), for the more conductive insulator. In order for Thermasil III to exceed the performance of greased mica, total surface flatness must be under 2 mils, a situation that requires spot finishing. Figure 7.4. Effect of Total Surface Flatness on Interface Resistance Using Silicon Rubber Insulators INTERFACETHERMALRESISTANCE(C/W)° 0.4 Data courtesy of Thermalloy 0.2 TOTAL JOINT DEVIATION FROM FLAT OVER TO-3 HEADER SURFACE AREA (INCHES) 0.0020 0.004 0.0080.006 0 0.6 0.8 1 0.01 1.2 (1) (1) Thermalsil II, .009 inches (.23 mm) thick. (2) Thermalsil III, .006 inches (.15 mm) thick. (2) Silicon rubber insulators have a number of unusual characteristics. Besides being affected by surface flatness and initial contact pressure, time is a factor. For example, in a study of the Cho-Therm 1688 pad thermal interface impedance dropped from 0.90°C/W to 0.70°C/W at the end of 1000 hours. Most of the change occurred during the first 200 hours where RθCS measured 0.74°C/W. The torque on the conventional mounting hardware had decreased to 3 in-lb from an initial 6 in-lb. With non-conformal materials, a reduction in torque would have increased the interface thermal resistance. Because of the difficulties in controlling all variables affecting tests of interface thermal resistance, data from different manufacturers is not in good agreement. Table 7.3 shows data obtained from two sources. The relative performance is the same, except for mica which varies widely in thickness. Appendix B discusses the variables which need to be controlled. At the time of this writing ASTM Committee D9 is developing a standard for interface measurements.
- 207. http://onsemi.com 207 Table 7.3 Performance of Silicon Rubber Insulators Tested per MIL-I-49456 Material Measured Thermal Resistance (°C/W) Thermalloy Data(1) Berquist Data(2) Bare Joint, greased BeO, greased Cho-Therm, 1617 Q Pad (non-insulated) Sil-Pad, K-10 Thermasil III Mica, greased Sil-Pad 1000 Cho-therm 1674 Thermasil II Sil-Pad 400 Sil-Pad K-4 0.033 0.082 0.233 — 0.263 0.267 0.329 0.400 0.433 0.500 0.533 0.583 0.008 — — 0.009 0.200 — 0.400 0.300 — — 0.440 0.440 1. From Thermalloy EIR 87-1030 2. From Berquist Data Sheet The conclusions to be drawn from all this data is that some types of silicon rubber pads, mounted dry, will out perform the commonly used mica with grease. Cost may be a determining factor in making a selection. Insulation Resistance When using insulators, care must be taken to keep the mating surfaces clean. Small particles of foreign matter can puncture the insulation, rendering it useless or seriously lowering its dielectric strength. In addition, particularly when voltages higher than 300 V are encountered, problems with creepage may occur. Dust and other foreign material can shorten creepage distances significantly; so having a clean assembly area is impor- tant. Surface roughness and humidity also lower insula- tion resistance. Use of thermal grease usually raises the withstand voltage of the insulating system but excess must be removed to avoid collecting dust. Because of these factors, which are not amenable to analysis, hi-pot testing should be done on prototypes and a large margin of safety employed. Insulated Electrode Packages Because of the nuisance of handling and installing the accessories needed for an insulated semiconductor mount- ing, equipment manufacturers have longed for cost-effec- tive insulated packages since the 1950’s. The first to appear were stud mount types which usually have a layer of beryllium oxide between the stud hex and the can. Although effective, the assembly is costly and requires manual mounting and lead wire soldering to terminals on top of the case. In the late eighties, a number of electrically isolated parts became available from various semiconductor manufacturers. These offerings presently consist of multiple chips and integrated circuits as well as the more conventional single chip devices. The newer insulated packages can be grouped into two categories. The first has insulation between the semicon- ductor chips and the mounting base; an exposed area of the mounting base is used to secure the part. Case 806 (ICePAK) and Case 388 (TO-258AA) (see Figure 7.6) are examples of parts in this category. The second category contains parts which have a plastic overmold covering the metal mounting base. The Fully Isolated, Case 221C, illustrated in Figure 7.8, is an example of parts in the second category. Parts in the first category — those with an exposed metal flange or tab — are mounted the same as their non-insulated counterparts. However, as with any mount- ing system where pressure is bearing on plastic, the overmolded type should be used with a conical compres- sion washer, described later in this note. FASTENER AND HARDWARE CHARACTERISTICS Characteristics of fasteners, associated hardware, and the tools to secure them determine their suitability for use in mounting the various packages. Since many problems have arisen because of improper choices, the basic characteristics of several types of hardware are discussed next. Compression Hardware Normal split ring lock washers are not the best choice for mounting power semiconductors. A typical #6 washer flattens at about 50 pounds, whereas 150 to 300 pounds is needed for good heat transfer at the interface. A very useful piece of hardware is the conical, sometimes called a Belleville washer, compression washer. As shown in Figure 7.5, it has the ability to maintain a fairly constant pressure over a wide range of its physical deflection — generally 20% to 80%. When installing, the assembler applies torque until the washer depresses to half its original height. (Tests should be run prior to setting up the assembly line to determine the proper torque for the fastener used to achieve 50% deflection.) The washer will absorb any cyclic expansion of the package, insulating washer or other materials caused by temperature changes. Conical washers are the key to successful mounting of devices requiring strict control of the mounting force or when plastic hardware is used in the mounting scheme. They are used with the large face contacting the packages. A new variation of the conical washer includes it as part of a nut assembly. Called a Sync Nut, the patented device can be soldered to a PC board and the semiconductor mounted with 6-32 machine screw.(4) (4) ITW Shakeproof, St. Charles Road, Elgin, IL 60120.
- 208. http://onsemi.com 208 PRESSUREONPACKAGE(LB-F) 240 1008060400 0 40 80 120 160 200 20 280 DEFLECTION OF WASHER DURING MOUNTING (%) Figure 7.5. Characteristics of the Conical Compression Washers Designed for Use with Plastic Body Mounted Semiconductors Clips Fast assembly is accomplished with clips. When only a few watts are being dissipated, the small board mounted or free-standing heat dissipators with an integral clip, offered by several manufacturers, result in a low cost assembly. When higher power is being handled, a separate clip may be used with larger heatsinks. In order to provide proper pressure, the clip must be specially designed for a particular heatsink thickness and semiconductor package. Clips are especially popular with plastic packages such as the TO-220 and TO-126. In addition to fast assembly, the clip provides lower interface thermal resistance than other assembly methods when it is designed for proper pressure to bear on the top of the plastic over the die. The TO-220 package usually is lifted up under the die location when mounted with a single fastener through the hole in the tab because of the high pressure at one end. Machine Screws Machine screws, conical washers, and nuts (or sync- nuts) can form a trouble-free fastener system for all types of packages which have mounting holes. However, proper torque is necessary. Torque ratings apply when dry; therefore, care must be exercised when using thermal grease to prevent it from getting on the threads as inconsistent torque readings result. Machine screw heads should not directly contact the surface of plastic packages types as the screw heads are not sufficiently flat to provide properly distributed force. Without a washer, cracking of the plastic case may occur. Self-Tapping Screws Under carefully controlled conditions, sheet-metal screws are acceptable. However, during the tapping process with a standard screw, a volcano-like protrusion will develop in the metal being threaded; an unacceptable surface that could increase the thermal resistance may result. When standard sheet metal screws are used, they must be used in a clearance hole to engage a speednut. If a self tapping process is desired, the screw type must be used which roll-forms machine screw threads. Rivets Rivets are not a recommended fastener for any of the plastic packages. When a rugged metal flange-mount package is being mounted directly to a heatsink, rivets can be used provided press-riveting is used. Crimping force must be applied slowly and evenly. Pop-riveting should never be used because the high crimping force could cause deformation of most semiconductor packages. Aluminum rivets are much preferred over steel because less pressure is required to set the rivet and thermal conductivity is improved. The hollow rivet, or eyelet, is preferred over solid rivets. An adjustable, regulated pressure press is used such that a gradually increasing pressure is used to pan the eyelet. Use of sharp blows could damage the semi- conductor die. Solder Until the advent of the surface mount assembly technique, solder was not considered a suitable fastener for power semiconductors. However, user demand has led to the development of new packages for this application. Acceptable soldering methods include conventional belt- furnace, irons, vapor-phase reflow, and infrared reflow. It is important that the semiconductor temperature not exceed the specified maximum (usually 260°C) or the die bond to the case could be damaged. A degraded die bond has excessive thermal resistance which often leads to a failure under power cycling. Adhesives Adhesives are available which have coefficients of expansion compatible with copper and aluminum.(5) Highly conductive types are available; a 10 mil layer has approximately 0.3°C/W interface thermal resistance. Different types are offered: high strength types for non-field-serviceable systems or low strength types for field-serviceable systems. Adhesive bonding is attractive when case mounted parts are used in wave soldering assembly because thermal greases are not compatible with the conformal coatings used and the greases foul the solder process. Plastic Hardware Most plastic materials will flow, but differ widely in this characteristic. When plastic materials form parts of the fastening system, compression washers are highly valuable to assure that the assembly will not loosen with time and temperature cycling. As previously discussed, loss of contact pressure will increase interface thermal resistance. (5) Robert Batson, Elliot Fraunglass and James P. Moran, “Heat Dissipation Through Thermalloy Conductive Adhesives, ” EMTAS ’83. Conference, February 1−3, Phoenix, AZ; Society of Manufacturing Engineers, One SME Drive, P.O. Box 930, Dearborn, MI 48128.
- 209. http://onsemi.com 209 FASTENING TECHNIQUES Each of the various classes of packages in use requires different fastening techniques. Details pertaining to each type are discussed in following sections. Some general considerations follow. To prevent galvanic action from occurring when devices are used on aluminum heatsinks in a corrosive atmosphere, many devices are nickel- or gold-plated. Consequently, precautions must be taken not to mar the finish. Another factor to be considered is that when a copper based part is rigidly mounted to an aluminium heatsink, a bimetallic system results which will bend with temperature changes. Not only is the thermal coefficient of expansion different for copper and aluminium, but the temperature gradient through each metal also causes each component to bend. If bending is excessive and the package is mounted by two or more screws the semiconductor chip could be damaged. Bending can be minimized by: 1. Mounting the component parallel to the heatsink fins to provide increased stiffness. 2. Allowing the heatsink holes to be a bit oversized so that some slip between surfaces can occur as temperature changes. 3. Using a highly conductive thermal grease or mounting pad between the heatsink and semicondutor to minimize the temperature gradient and allow for movement. Tab Mount The tab mount class is composed of a wide array of packages as illustrated in Figure 7.6. Mounting consider- ations for all varieties are similar to that for the popular TO-220 package, whose suggested mounting arrange- ments and hardware are shown in Figure 7.7. The rectangular washer shown in Figure 7.7(a) is used to minimize distortion of the mounting flange; excessive distortion could cause damage to the semiconductor chip. Use of the washer is only important when the size of the mounting hole exceeds 0.140 inch (6−32 clearance). Larger holes are needed to accommodate the lower insulating bushing when the screw is electrically con- nected to the case; however, the holes should not be larger than necessary to provide hardware clearance and should never exceed a diameter of 0.250 inch. Flange distortion is also possible if excessive torque is used during mounting. A maximum torque of 8 inch-pounds is suggested when using a 6−32 screw. Care should be exercised to assure that the tool used to drive the mounting screw never comes in contact with the plastic body during the driving operation. Such contact can result in damage to the plastic body and internal device connections. To minimize this problem, ON Semiconductor TO-220 packages have a chamfer on one end. TO-220 packages of other manufacturers may need a spacer or combination spacer and isolation bushing to raise the screw head above the top surface of the plastic. The popular TO-220 Package and others of similar con- struction lift off the mounting surface as pressure is applied to one end. (See Appendix B, Figure B1.) To counter this tendency, at least one hardware manufacturer offers a hard plastic cantilever beam which applies more even pressure on the tab.(6) In addition, it separates the mounting screw from the metal tab. Tab mount parts may also be effectively mounted with clips as shown in Figure 7.10(c). To obtain high pressure without cracking the case, a pressure spreader bar should be used under the clip. Interface thermal resistance with the cantilever beam or clips can be lower than with screw mounting. (6) Catalog, Edition 18, Richco Plastic Company, 5825 N. Tripp Ave., Chicago, IL 60546. Figure 7.6. Several Types of Tab-Mount Parts CASE 221A-07 (TO-220AB) CASE 221B-04 (TO-220AC) CASE 314B (5 PIN TO-220) CASE 314D CASE 339 CASE 340-02 (TO-218) CASE 387-01 (TO-254AA) CASE 388-01 (TO-258AA) CASE 806-05 (ICePAK)
- 210. http://onsemi.com 210 (1) Used with thin chassis and/or large hole. (2) Used when isolation is required. (3) Required when nylon bushing is used. (a). Preferred Arrangement for Isolated or Non-Isolated Mounting. Screw is at Semiconductor Case Potential. 6-32 Hardware is Used. Use Parts Listed Below (b). Alternate Arrangement for Isolated Mounting when Screw must be at Heat Sink Potential. 4-40 Hardware is used. Use Parts Listed below. 6-32 HEX NUT 4-40 HEX NUT (4) CONICAL WASHER COMPRESSION WASHER (3) FLAT WASHER (2) BUSHING HEATSINK HEATSINK RECTANGULAR INSULATOR (2) RECTANGULAR INSULATOR SEMICONDUCTOR (CASE 221,221A) (1) RECTANGULAR STEEL WASHER SEMICONDUCTOR (CASE 221, 221A) INSULATING BUSHING FLAT WASHER 6-32 HEX HEAD SCREW 4-40 PAN OR HEX HEAD SCREW Figure 7.7. Mounting Arrangements for Tab Mount TO-220 In situations where a tab mount package is making direct contact with the heatsink, an eyelet may be used, provided sharp blows or impact shock is avoided. Plastic Body Mount The Thermopad and fully isolated plastic power packages shown in Figure 7.8 are typical of packages in this group. They have been designed to feature minimum size with no compromise in thermal resistance. For the Thermopad (Case 77) parts this is accomplished by die-bounding the silicon chip on one side of a thin copper sheet; the opposite side is exposed as a mounting surface. The copper sheet has a hole for mounting; plastic is molded enveloping the chip but leaving the mounting hole open. The low thermal resistance of this construction is obtained at the expense of a requirement that strict attention be paid to the mounting procedure. The fully isolated power package (Case 221C-02) is similar to a TO-220 except that the tab is encased in plastic. Because the mounting force is applied to plastic, the mounting procedure differs from a standard TO-220 and is similar to that of the Thermopad. Several types of fasteners may be used to secure these packages; machine screws, eyelets, or clips are preferred. With screws or eyelets, a conical washer should be used which applies the proper force to the package over a fairly wide range of deflection and distributes the force over a fairly large surface area. Screws should not be tightened with any type of air-driven torque gun or equipment which may cause high impact. Characteristics of a suitable conical washer is shown in Figure 7.5. Figure 7.9 shows details of mounting Case 77 devices. Clip mounting is fast and requires minimum hardware, however, the clip must be properly chosen to insure that the proper mounting force is applied. When electrical isolation is required with screw mounting, a bushing inside the mounting hole will insure that the screw threads do not contact the metal base. The fully isolated power package, (Case 221C, 221D and 340B) permits the mounting procedure to be greatly simplified over that of a standard TO-220. As shown in Figure 7.10(c), one properly chosen clip, inserted into two slotted holes in the heatsink, is all the hardware needed. Even though clip pressure is much lower than obtained with a screw, the thermal resistance is about the same for either method. This occurs because the clip bears directly on top of the die and holds the package flat while the screw causes the package to lift up somewhat under the die. (See Figure B1 of Appendix B.) The interface should consist of a layer of thermal grease or a highly conductive thermal pad. Of course, screw mounting shown in Figure 7.10(b) may also be used but a conical compres- sion washer should be included. Both methods afford a major reduction in hardware as compared to the conven- tional mounting method with a TO-220 package which is shown in Figure 7.10(a). Figure 7.8. Plastic Body-Mount Packages CASE 77 (TO-225AA/ TO-126) (THERMOPAD) CASE 221C-02 (Fully Isolated) CASE 221D-02 (Fully Isolated) CASE 340B-03 (Fully Isolated)
- 211. http://onsemi.com 211 Figure 7.9. Recommended Mounting Arrangements for TO-225AA (TO-126) Thermopad Packages (c). Clips (b). Eyelet Mounting COMPRESSION WASHER INSULATING WASHER (OPTIONAL) EYELET (a). Machine Screw Mounting MACHINE OR SPEED NUT INSULATING WASHER (OPTIONAL) HEAT SINK SURFACE COMPRESSION WASHER MACHINE SCREW OR SHEET METAL SCREW THERMOPAD PACKAGE INSULATING BUSHING HEATSINK (c). Clip-Mounted Fully Isolated Figure 7.10. Mounting Arrangements for the Fully Isolated Power Package as Compared to a Conventional TO-220 CLIP COMPRESSION WASHER NUT (b). Screw-Mounted Fully Isolated HEATSINK PLAIN WASH- ER 6-32 SCREW (a). Screw-Mounted TO-220 INSULATOR HEATSINK COMPRESSION WASHER NUT PLAIN WASHER 4-40 SCREW
- 212. http://onsemi.com 212 Surface Mount Although many of the tab mount parts have been surface mounted, special small footprint packages for mounting power semiconductors using surface mount assembly techniques have been developed. The DPAK, shown in Figure 11, for example, will accommodate a die up to 112 mils x 112 mils, and has a typical thermal resistance around 2°C/W junction to case. The thermal resistance values of the solder interface is well under 1°C/W. The printed circuit board also serves as the heatsink. Standard Glass-Epoxy 2-ounce boards do not make very good heatsinks because the thin foil has a high thermal resistance. As Figure 7.12 shows, thermal resistance assymtotes to about 20°C/W at 10 square inches of board area, although a point of diminishing returns occurs at about 3 square inches. Boards are offered that have thick aluminium or copper substrates. A dielectric coating designed for low thermal resistance is overlayed with one or two ounce copper foil for the preparation of printed conductor traces. Tests run on such a product indicate that case to substrate thermal resistance is in the vicinity of 1°C/W, exact values depending upon board type.(7) The substrate may be an effective heatsink itself, or it can be attached to a conventional finned heatsink for improved performance. Since DPAK and other surface mount packages are designed to be compatible with surface mount assembly techniques, no special precautions are needed other than to insure that maximum temperature/time profiles are not exceeded. (7) Herb Fick, “Thermal Management of Surface Mount Power Devices,” Power conversion and Intelligent Motion, August 1987. Figure 7.11. Surface Mount D-PAK Parts CASE 369-07 CASE 369A-13 R,THERMALRESISTANCE(C/W)θJA° 8 10 Figure 7.12. Effect of Footprint Area on Thermal Resistance of DPAK Mounted on a Glass-Epoxy Board PCB PAD AREA (IN2) 2 0 20 40 60 80 100 4 6 PCB, 1/16 IN THICK G10/FR4, 2 OUNCE EPOXY GLASS BOARD, DOUBLE SIDED FREE AIR AND SOCKET MOUNTING In applications where average power dissipation is on the order of a watt or so, most power semiconductors may be mounted with little or no heatsinking. The leads of the various metal power packages are not designed to support the packages; their cases must be firmly supported to avoid the possibility of cracked seals around the leads. Many plastic packages may be supported by their leads in applications where high shock and vibration stresses are not encountered and where no heatsink is used. The leads should be as short as possible to increase vibration resistance and reduce thermal resistance. As a general practice however, it is better to support the package. A plastic support for the TO-220 Package and other similar types is offered by heatsink accessory vendors. In many situations, because its leads are fairly heavy, the CASE 77 (TO-225AA)(TO-127) package has sup- ported a small heatsink; however, no definitive data is available. When using a small heatsink, it is good practice to have the sink rigidly mounted such that the sink or the board is providing total support for the semiconductor. Two possible arrangements are shown in Figure 7.13. The arrangement of part (a) could be used with any plastic package, but the scheme of part (b) is more practical with Case 77 Thermopad devices. With the other package types, mounting the transistor on top of the heatsink is more practical.
- 213. http://onsemi.com 213 (a). Simple Plate, Vertically Mounted CIRCUIT BOARD HEATSINK HEATSINK Figure 7.13. Methods of Using Small Heatsinks With Plastic Semiconductor Packages TO-225AA CASE 77 HEATSINK SUR- FACE TWIST LOCKS OR SOLDERABLE LEGS TO-225AA CASE 77 HEATSINK SURFACE CIRCUIT BOARD (b). Commercial Sink, Horizontally Mounted In certain situations, in particular where semiconductor testing is required or prototypes are being developed, sockets are desirable. Manufacturers have provided sockets for many of the packages available from ON Semiconductor. The user is urged to consult manufac- turers’ catalogs for specific details. Sockets with Kelvin connections are necessary to obtain accurate voltage readings across semiconductor terminals. CONNECTING AND HANDLING TERMINALS Pins, leads, and tabs must be handled and connected properly to avoid undue mechanical stress which could cause semiconductor failure. Change in mechanical dimensions as a result of thermal cycling over operating temperature extremes must be considered. Standard metal, plastic, and RF stripline packages each have some special considerations. Plastic Packages The leads of the plastic packages are somewhat flexible and can be reshaped although this is not a recommended procedure. In many cases, a heatsink can be chosen which makes lead-bending unnecessary. Numerous-lead and tab- forming options are available from ON Semiconductor on large quantity orders. Preformed leads remove the users risk of device damage caused by bending. If, however, lead-bending is done by the user, several basic considerations should be observed. When bending the lead, support must be placed between the point of bending and the package. For forming small quantities of units, a pair of pliers may be used to clamp the leads at the case, while bending with the fingers or another pair of pliers. For production quantities, a suitable fixture should be made. The following rules should be observed to avoid damage to the package. 1. A leadbend radius greater than 1/16 inch is advisable for TO-225AA (CASE 77) and 1/32 inch for TO-220. 2. No twisting of leads should be done at the case. 3. No axial motion of the lead should be allowed with respect to the case. The leads of plastic packages are not designed to withstand excessive axial pull. Force in this direction greater than 4 pounds may result in permanent damage to the device. If the mounting arrangement imposes axial stress on the leads, a condition which may be caused by thermal cycling, some method of strain relief should be devised. When wires are used for connections, care should be exercised to assure that movement of the wire does not cause movement of the lead at the lead-to-plastic junctions. Highly flexible or braided wires are good for providing strain relief. Wire-wrapping of the leads is permissible, provided that the lead is restrained between the plastic case and the point of the wrapping. The leads may be soldered; the maximum soldering temperature, however, must not exceed 260°C and must be applied for not more than 10 seconds at a distance greater than 1/8 inch from the plastic case.
- 214. http://onsemi.com 214 CLEANING CIRCUIT BOARDS It is important that any solvents or cleaning chemicals used in the process of degreasing or flux removal do not affect the reliability of the devices. Alcohol and unchlori- nated Freon solvents are generally satisfactory for use with plastic devices, since they do not damage the package. Hydrocarbons such as gasoline and chlorinated Freon may cause the encapsulant to swell, possibly damaging the transistor die. When using an ultrasonic cleaner for cleaning circuit boards, care should be taken with regard to ultrasonic energy and time of application. This is particularly true if any packages are free-standing without support. THERMAL SYSTEM EVALUATION Assuming that a suitable method of mounting the semiconductor without incurring damage has been achieved, it is important to ascertain whether the junction temperature is within bounds. In applications where the power dissipated in the semi- conductor consists of pulses at a low duty cycle, the instantaneous or peak junction temperature, not average temperature, may be the limiting condition. In this case, use must be made of transient thermal resistance data. For a full explanation of its use, see ON Semiconductor Application Note, AN569. Other applications, notably RF power amplifiers or switches driving highly reactive loads, may create severe current crowding conditions which render the traditional concepts of thermal resistance or transient thermal impedance invalid. In this case, transistor safe operating area, thyristor di/dt limits, or equivalent ratings as applicable, must be observed. Fortunately, in many applications, a calculation of the average junction temperature is sufficient. It is based on the concept of thermal resistance between the junction and a temperature reference point on the case. (See Appendix A.) A fine wire thermocouple should be used, such as #36 AWG, to determine case temperature. Average operating junction temperature can be computed from the following equation: TJ + TC ) RqJC PD where TJ = junction temperature (°C) TC = case temperature (°C) RθJC = thermal resistance junction- to-case as specified on the data sheet (°C/W) PD = power dissipated in the device (W) The difficulty in applying the equation often lies in determining the power dissipation. Two commonly used empirical methods are graphical integration and substitution. Graphical Integration Graphical integration may be performed by taking oscilloscope pictures of a complete cycle of the voltage and current waveforms, using a limit device. The pictures should be taken with the temperature stabilized. Corre- sponding points are then read from each photo at a suitable number of time increments. Each pair of voltage and current values are multiplied together to give instantaneous values of power. The results are plotted on linear graph paper, the number of squares within the curve counted, and the total divided by the number of squares along the time axis. The quotient is the average power dissipation. Oscilloscopes are available to perform these measurements and make the necessary calculations. Substitution This method is based upon substituting an easily measurable, smooth dc source for a complex waveform. A switching arrangement is provided which allows operat- ing the load with the device under test, until it stabilizes in temperature. Case temperature is monitored. By throwing the switch to the “test” position, the device under test is connected to a dc power supply, while another pole of the switch supplies the normal power to the load to keep it operating at full power level. The dc supply is adjusted so that the semiconductor case temperature remains approxi- mately constant when the switch is thrown to each position for about 10 seconds. The dc voltage and current values are multiplied together to obtain average power. It is generally necessary that a Kelvin connection be used for the device voltage measurement.
- 215. http://onsemi.com 215 APPENDIX A THERMAL RESISTANCE CONCEPTS The basic equation for heat transfer under steady-state conditions is generally written as: q + hADT (1) where q = rate of heat transfer or power dissipation (PD) h = heat transfer coefficient, A = area involved in heat transfer, ΔT = temperature difference between regions of heat transfer. However, electrical engineers generally find it easier to work in terms of thermal resistance, defined as the ratio of temperature to power. From Equation 1, thermal resis- tance, Rθ, is Rq + DTńq + 1ńhA (2) The coefficient (h) depends upon the heat transfer mechanism used and various factors involved in that particular mechanism. An analogy between Equation (2) and Ohm’s Law is often made to form models of heat flow. Note that T could be thought of as a voltage thermal resistance corresponds to electrical resistance (R); and, power (q) is analogous to current (I). This gives rise to a basic thermal resistance model for a semiconductor as indicated by Figure A1. The equivalent electrical circuit may be analyzed by using Kirchoff’s Law and the following equation results: TJ + PD(RqJC ) RqCS ) RqSA) ) TA (3) where TJ = junction temperature, PD = power dissipation RθJC = semiconductor thermal resistance (junction to case), RθCS = interface thermal resistance (case to heatsink), RθSA = heatsink thermal resistance (heatsink to ambient), TA = ambient temperature. The thermal resistance junction to ambient is the sum of the individual components. Each component must be minimized if the lowest junction temperature is to result. The value for the interface thermal resistance, RθCS, may be significant compared to the other thermal-resis- tance terms. A proper mounting procedure can minimize RθCS. The thermal resistance of the heatsink is not absolutely constant; its thermal efficiency increases as ambient temperature increases and it is also affected by orientation of the sink. The thermal resistance of the semiconductor is also variable; it is a function of biasing and temperature. Semiconductor thermal resistance specifications are nor- mally at conditions where current density is fairly uniform. In some applications such as in RF power amplifiers and short-pulse applications, current density is not uniform and localized heating in the semiconductor chip will be the controlling factor in determining power handling ability. Figure A1. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor SOLDER TERMINAL FLAT WASH- ER NUT HEATSINK INSULATORS DIE TC, CASE TEMPERATURE TJ, JUNCTION TEMPERATURE TS, HEATSINK TEMPERATURE TA, AMBIENT TEMPERATURE RθSA RθCS RθJC REFERENCE TEMPERATURE PD
- 216. http://onsemi.com 216 APPENDIX B MEASUREMENT OF INTERFACE THERMAL RESISTANCE Measuring the interface thermal resistance RθCS appears deceptively simple. All that’s apparently needed is a thermocouple on the semiconductor case, a thermo- couple on the heatsink, and a means of applying and measuring DC power. However, RθCS is proportional to the amount of contact area between the surfaces and consequently is affected by surface flatness and finish and the amount of pressure on the surfaces. The fastening method may also be a factor. In addition, placement of the thermocouples can have a significant influence upon the results. Consequently, values for interface thermal resis- tance presented by different manufacturers are not in good agreement. Fastening methods and thermocouple loca- tions are considered in this Appendix. When fastening the test package in place with screws, thermal conduction may take place through the screws, for example, from the flange ear on a TO-3 package directly to the heatsink. This shunt path yields values which are artificially low for the insulation material and dependent upon screw head contact area and screw material. MIL-I-49456 allows screws to be used in tests for interface thermal resistance probably because it can be argued that this is “application oriented.” Thermalloy takes pains to insulate all possible shunt conduction paths in order to more accurately evaluate insulation materials. The ON Semiconductor fixture uses an insulated clamp arrangement to secure the package which also does not provide a conduction path. As described previously, some packages, such as a TO-220, may be mounted with either a screw through the tab or a clip bearing on the plastic body. These two methods often yield different values for interface thermal resistance. Another discrepancy can occur if the top of the package is exposed to the ambient air where radiation and convection can take place. To avoid this, the package should be covered with insulating foam. It has been estimated that a 15 to 20% error in RθCS can be incurred from this source. Another significant cause for measurement discrepan- cies is the placement of the thermocouple to measure the semiconductor case temperature. Consider the TO-220 package shown in Figure B1. The mounting pressure at one end causes the other end — where the die is located — to lift off the mounting surface slightly. To improve contact, ON Semiconductor TO-220 Packages are slightly concave. Use of a spreader bar under the screw lessens the lifting, but some is inevitable with a package of this structure. Three thermocouple locations are shown: a. The ON Semiconductor location is directly under the die reached through a hole in the heatsink. The thermo- couple is held in place by a spring which forces the thermocouple into intimate contact with the bottom of the semi’s case. b. The JEDEC location is close to the die on the top surface of the package base reached through a blind hole drilled through the molded body. The thermocouple is swaged in place. c. The Thermalloy location is on the top portion of the tab between the molded body and the mounting screw. The thermocouple is soldered into position. E.I.A. THERMALLOYDIE ON SEMICONDUCTOR Figure B1. JEDEC TO-220 Package Mounted to Heatsink Showing Various Thermocouple Locations and Lifting Caused by Pressure at One End Temperatures at the three locations are generally not the same. Consider the situation depicted in the figure. Because the only area of direct contact is around the mounting screw, nearly all the heat travels horizontally along the tab from the die to the contact area. Consequent- ly, the temperature at the JEDEC location is hotter than at the Thermalloy location and the ON Semiconductor location is even hotter. Since junction-to-sink thermal resistance must be constant for a given test setup, the calculated junction-to-case thermal resistance values decrease and case-to-sink values increase as the “case” temperature thermocouple readings become warmer. Thus the choice of reference point for the “case” temperature is quite important. There are examples where the relationship between the thermocouple temperatures are different from the pre- vious situation. If a mica washer with grease is installed between the semiconductor package and the heatsink, tightening the screw will not bow the package; instead, the mica will be deformed. The primary heat conduction path is from the die through the mica to the heatsink. In this case, a small temperature drop will exist across the vertical dimension of the package mounting base so that the thermocouple at the EIA location will be the hottest. The thermocouple temperature at the Thermalloy location will be lower but close to the temperature at the EIA location as the lateral heat flow is generally small. The ON Semiconductor location will be coolest.
- 217. http://onsemi.com 217 The EIA location is chosen to obtain the highest temperature on the case. It is of significance because power ratings are supposed to be based on this reference point. Unfortunately, the placement of the thermocouple is tedious and leaves the semiconductor in a condition unfit for sale. The ON Semiconductor location is chosen to obtain the highest temperature of the case at a point where, hopefully, the case is making contact to the heatsink. Once the special heatsink to accommodate the thermo- couple has been fabricated, this method lends itself to production testing and does not mark the device. How- ever, this location is not easily accessible to the user. The Thermalloy location is convenient and is often chosen by equipment manufacturers. However, it also blemishes the case and may yield results differing up to 1°C/W for a TO-220 package mounted to a heatsink without thermal grease and no insulator. This error is small when compared to the thermal resistance of heat dissipaters often used with this package, since power dissipation is usually a few watts. When compared to the specified junction-to-case values of some of the higher power semiconductors becoming available, however, the difference becomes significant and it is important that the semiconductor manufacturer and equipment manufac- turer use the same reference point. Another EIA method of establishing reference tempera- tures utilizes a soft copper washer (thermal grease is used) between the semiconductor package and the heatsink. The washer is flat to within 1 mil/inch, has a finish better than 63 μ-inch, and has an imbedded thermocouple near its center. This reference includes the interface resistance under nearly ideal conditions and is therefore application- oriented. It is also easy to use but has not become widely accepted. A good way to improve confidence in the choice of case reference point is to also test for junction-to-case thermal resistance while testing for interface thermal resistance. If the junction-to-case values remain relatively constant as insulators are changed, torque varied, etc., then the case reference point is satisfactory.
- 218. http://onsemi.com 218 SECTION 8 RELIABILITY AND QUALITY Edited and Updated USING TRANSIENT THERMAL RESISTANCE DATA IN HIGH POWER PULSED THYRISTOR APPLICATIONS INTRODUCTION For a certain amount of dc power dissipated in a semiconductor, the junction temperature reaches a value which is determined by the thermal conductivity from the junction (where the power is dissipated) to the air or heat sink. When the amount of heat generated in the junction equals the heat conducted away, a steady−state condition is reached and the junction temperature can be calculated by the simple equation: TJ = PD RθJR + TR (1a) where TJ = junction temperature TR = temperature at reference point PD = power dissipated in the junction RθJR = steady−state thermal resistance from RθJR = junction to the temperature reference RθJR = point. Power ratings of semiconductors are based upon steady− state conditions, and are determined from equation (1a) under worst case conditions, i.e.: PD(max) + TJ(max) – TR RqJR(max) (1b) TJ(max) is normally based upon results of an operating life test or serious degradation with temperature of an impor- tant device characteristic. TR is usually taken as 25°C, and RθJR can be measured using various techniques. The reference point may be the semiconductor case, a lead, or the ambient air, whichever is most appropriate. Should the reference temperature in a given application exceed the reference temperature of the specification, PD must be correspondingly reduced. Thermal resistance allows the designer to determine power dissipation under steady state conditions. Steady state conditions between junction and case are generally achieved in one to ten seconds while minutes may be required for junction to ambient temperature to become stable. However, for pulses in the microsecond and millisecond region, the use of steady−state values will not yield true power capability because the thermal response of the system has not been taken into account. Note, however, that semiconductors also have pulse power limitations which may be considerably lower − or even greater − than the allowable power as deduced from thermal response information. For transistors, the second breakdown portion of the pulsed safe operating area defines power limits while surge current or power ratings are given for diodes and thyristors. These additional ratings must be used in conjunction with the thermal response to determine power handling capability. To account for thermal capacity, a time dependent factor r(t) is applied to the steady−state thermal resistance. Thermal resistance, at a given time, is called transient thermal resistance and is given by: RθJR(t) = r(t) @ RθJR (2) The mathematical expression for the transient thermal resistance has been determined to be extremely complex. The response is, therefore, plotted from empirical data. Curves, typical of the results obtained, are shown in Figure 8.1. These curves show the relative thermal response of the junction, referenced to the case, resulting from a step function change in power. Observe that the total percentage difference is about 10:1 in the short pulse ( tǸ ) region. However, the values of thermal resistance vary over 20:1. Many ON Semiconductor data sheets have a graph similar to that of Figure 8.2. It shows not only the thermal response to a step change in power (the D = 0, or single pulse curve) but also has other curves which may be used to obtain an effective r(t) value for a train of repetitive pulses with different duty cycles. The mechanics of using the curves to find TJ at the end of the first pulse in the train, or to find TJ(pk) once steady state conditions have been achieved, are quite simple and require no background in the subject. However, problems where the applied power pulses are either not identical in amplitude or width, or the duty cycle is not constant, require a more thorough understanding of the principles illustrated in the body of this report.
- 219. http://onsemi.com 219 USE OF TRANSIENT THERMAL RESISTANCE DATA Part of the problem in applying thermal response data stems from the fact that power pulses are seldom rectangu- lar, therefore to use the r(t) curves, an equivalent rectangu- lar model of the actual power pulse must be determined. Methods of doing this are described near the end of this note. Before considering the subject matter in detail, an example will be given to show the use of the thermal response data sheet curves. Figure 8.2 is a representative graph which applies to a 2N5886 transistor. Pulse power PD = 50 Watts Duration t = 5 milliseconds Period τp = 20 milliseconds Case temperature, TC = 75°C Junction to case thermal resistance, RθJC = 1.17°C/W The temperature is desired, a) at the end of the first pulse b) at the end of a pulse under steady state conditions. For part (a) use: TJ = r(5 ms) RθJCPD + TC The term r(5 ms) is read directly from the graph of Figure 8.2 using the D = 0 curve, ∴TJ = 0.49 1.17 50 + 75 = 28.5 + 75 = 103.5 The peak junction temperature rise under steady conditions is found by: TJ = r(t, D) RθJC PD + TC D = t/τp = 5/20 − 0.25. A curve for D= 0.25 is not on the graph; however, values for this duty cycle can be interpo- lated between the D = 0.2 and D = 0.5 curves. At 5 ms, read r(t) ≈ 0.59. TJ = 0.59 1.17 50 + 75 = 34.5 + 75 = 109.5°C Figure 8.1. Thermal Response, Junction to Case, of Case 77 Types For a Step of Input Power 1.0 0.1 0.01 0.01 0.1 1.0 10 100 1000 D = 0.5 0.2 r(t),TransientThermalResistance (Normalized) 0.1 0.05 0.02 0.01 3,600 8,000 SINGLE PULSE 0.2 0.02 0.3 0.03 0.5 0.05 0.7 0.07 Figure 8.2. Thermal Response Showing the Duty Cycle Family of Curves 0.02 0.2 2.0 20 2000.05 0.5 5.0 50 500 1.0 0.1 0.01 0.1 1.0 10 100 1000 10,000 t, Time (ms) r(t),TransientThermalResistance (Normalized) 0.2 0.02 0.3 0.03 0.5 0.05 0.7 0.07 0.2 2.0 20 200 20000.5 5.0 50 500 5000 1 2 Case 77 Case 77 CASE DIE SIZE (Sq. Mils) 1 2 t, Time (ms)
- 220. http://onsemi.com 220 The average junction temperature increase above ambient is: TJ(average) − TC = RθJC PD D (3)= (1.17) (50) (0.25) = 14.62°C Note that TJ at the end of any power pulse does not equal the sum of the average temperature rise (14.62°C in the example) and that due to one pulse (28.5°C in example), because cooling occurs between the power pulses. While junction temperature can be easily calculated for a steady pulse train where all pulses are of the same amplitude and pulse duration as shown in the previous example, a simple equation for arbitrary pulse trains with random variations is impossible to derive. However, since the heating and cooling response of a semiconductor is essentially the same, the superposition principle may be used to solve problems which otherwise defy solution. Using the principle of superposition each power interval is considered positive in value, and each cooling interval negative, lasting from time of application to infinity. By multiplying the thermal resistance at a particular time by the magnitude of the power pulse applied, the magnitude of the junction temperature change at a particular time can be obtained. The net junction temperature is the algebraic sum of the terms. The application of the superposition principle is most easily seen by studying Figure 8.3. Figure 8.3(a) illustrates the applied power pulses. Fig- ure 8.3(b) shows these pulses transformed into pulses lasting from time of application and extending to infinity; at to, P1 starts and extends to infinity; at t1, a pulse (− P1) is considered to be present and thereby cancels P1 from time t1, and so forth with the other pulses. The junction temperature changes due to these imagined positive and negative pulses are shown in Figure 8.3(c). The actual junction temperature is the algebraic sum as shown in Figure 8.3(d). Problems may be solved by applying the superposition principle exactly as described; the technique is referred to as Method 1, the pulse−by−pulse method. It yields satisfac- tory results when the total time of interest is much less than the time required to achieve steady state conditions, and must be used when an uncertainty exists in a random pulse train as to which pulse will cause the highest temperature. Examples using this method are given in Appendix A under Method 1. For uniform trains of repetitive pulses, better answers result and less work is required by averaging the power pulses to achieve an average power pulse; the temperature is calculated at the end of one or two pulses following the average power pulse. The essence of this method is shown in Figure 8.6. The duty cycle family of curves shown in Figure 8.2 and used to solve the example problem is based on this method; however, the curves may only be used for a uniform train after steady state conditions are achieved. Method 2 in Appendix A shows equations for calculating the temperature at the end of the nth or n + 1 pulse in a uniform train. Where a duty cycle family of curves is available, of course, there is no need to use this method. Figure 8.3. Application of Superposition Principle Figure 8.4. Non−Repetitive Pulse Train (Values Shown Apply to Example in Appendix) Figure 8.5. A Train of Equal Repetitive Pulses (a) Input Power (b) Power Pulses Separated Into Components (c) TJ Change Caused by Components (d) Composite TJ P1 Pin Pin −P1 P1 P2 P2 −P2 P3 P3 −P3 P4 P4 −P4 TJ t0 t1 t2 t3 t4 t5 t6 t7 Time Time Time Time t0 t1 t2 t3 t4 t5 0 P1 P2 P3 1.0 2.0 3.0 4.0 t, Time (ms) 50 40 30 20 10 0 PPeakPower (Watts) PK1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 Po T5 (Conditions for numerical examples t Po = 5 Watts t = 5 ms t = 20 ms t 2t
- 221. http://onsemi.com 221 Figure 8.6. Model For a Repetitive Equal Pulse Train nth pulse n+1 pulse Po Pavg t t t Temperature rise at the end of a pulse in a uniform train before steady state conditions are achieved is handled by Method 3 (a or b) in the Appendix. The method is basically the same as for Method 2, except the average power is modified by the transient thermal resistance factor at the time when the average power pulse ends. A random pulse train is handled by averaging the pulses applied prior to situations suspected of causing high peak temperatures and then calculating junction temperature at the end of the nth or n + 1 pulse. Part c of Method 3 shows an example of solving for temperature at the end of the 3rd pulse in a three pulse burst. HANDLING NON−RECTANGULAR PULSES The thermal response curves, Figure 8.1, are based on a step change of power; the response will not be the same for other waveforms. Thus far in this treatment we have assumed a rectangular shaped pulse. It would be desirable to be able to obtain the response for any arbitrary waveform, but the mathematical solution is extremely unwieldy. The simplest approach is to make a suitable equivalent rectangular model of the actual power pulse and use the given thermal response curves; the primary rule to observe is that the energy of the actual power pulse and the model are equal. Experience with various modeling techniques has lead to the following guidelines: For a pulse that is nearly rectangular, a pulse model having an amplitude equal to the peak of the actual pulse, with the width adjusted so the energies are equal, is a conservative model. (See Figure 8.7(a)). Sine wave and triangular power pulses model well with the amplitude set at 70% of the peak and the width adjusted to 91% and 71%, respectively, of the baseline width (as shown on Figure 8.7(b)). A power pulse having a sin2 shape models as a triangular waveform. Power pulses having more complex waveforms could be modeled by using two or more pulses as shown in Figure 8.7(c). A point to remember is that a high amplitude pulse of a given amount of energy will produce a higher rise in junction temperature than will a lower amplitude pulse of longer duration having the same energy. Figure 8.7. Modeling of Power Pulses T1 P1T1 = A P1 t t PP PP 0.7 PP0.7 PP (b) (c) (a) P1 (t1 − t0) + P2 (t2 − t1) = A P1 P2 t0 t1 t2 0.91 t 0.71 t ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ A ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ A As an example, the case of a transistor used in a dc to ac power converter will be analyzed. The idealized wave- forms of collector current, IC, collector to emitter voltage, VCE, and power dissipation PD, are shown in Figure 8.8. A model of the power dissipation is shown in Figure 8.8(d). This switching transient of the model is made, as was suggested, for a triangular pulse. For example, TJ at the end of the rise, on, and fall times, T1, T2 and T3 respectively, will be found. Conditions: TO−3 package, RθJC = 0.5°C/W, IC = 60A, VCE(off) = 60 V TA = 50°C tf = 80 μs, tr = 20 μs VCE(sat) = 0.3 V @ 60 A Frequency = 2 kHz∴τ = 500 μs Pon = (60) (0.3) = 18 W Pf = 30 30 = 900 W = Pr
- 222. http://onsemi.com 222 Assume that the response curve in Figure 8.1 for a die area of 58,000 square mils applies. Also, that the device is mounted on an MS−15 heat sink using Dow Corning DC340 silicone compound with an air flow of 1.0 lb/min flowing across the heat−sink. (From MS−15 Data Sheet, RθCS = 0.1°C/W and RθSA = 0.55°C/W). Procedure: Average each pulse over the period using equation 1−3 (Appendix A, Method 2), i.e., Pavg + 0.7 Pr 0.71 tr t ) Pon ton t ) 0.7 Pf 0.71 tf t + (0.7) (900) (0.71) (20) 500 ) (18) (150) 500 ) (0.7) (900) (0.71) 80 500 + 17.9 ) 5.4 ) 71.5 + 94.8 W T1 = [Pavg + (0.7 Pr − Pavg) @ r(t1 − to)] RθJC From equation 1−4, Method 2A: At this point it is observed that the thermal response curves of Figure 8.1 do not extend below 100 μs. Heat transfer theory for one dimensional heat flow indicates that the response curve should follow the tǸ law at small times. Using this as a basis for extending the curve, the response at 14.2 μs is found to be 0.023. We then have: T1 = [94.8 + (630 − 94.8).023] (0.5) T1 = (107.11)(0.5) = 53.55°C For T2 we have, by using superposition: T2 = [Pavg − Pavg @ r(t2 − to) + 0.7 Pr @ T2 = r(t2 − to) − 0.7 Pr @ r(t2 − t1) + Pon @ T2 = r(t2 − t1)] RθJC T2 = [Pavg + (0.7 Pr − Pavg) @ r(t2 − to) + T2 = (Pon − 0.7 Pr) @ r(t2 − t1)] RθJC T2 = [94.8 + (630 − 94.8) @ r(164 μs) + (18 − 630) T2 = @ r(150 μs)] (0.5) T2 = [94.8 + (535.2)(.079) − (612)(.075)] (0.5) T2 = [94.8 + 42.3 − 45.9] (0.5) T2 = (91.2)(0.5) = 45.6°C Figure 8.8. Idealized Waveforms of IC, VCE and PD in a DC to AC Inverter (a) (b) (c) (d) PD Pon Pf t0 t1 t2 t3 Time Time t(Time) PD IC VCE Collector−EmitterVoltageCollectorCurrentPowerDissipation t(Time) Pon Pr T1 T2T3 0.7 Pf0.7 Pf 0.7 Pr 0.7 tr 0.7 tfton tontoff tf tr t For the final point T3 we have: T3 = [Pavg − Pavg @ r(t3 − to) + 0.7 Pr @ T3 = r(t3 − to) − 0.7 Pr @ r(t3 − t1) + Pon @ T3 = r(t3 − t1) − Pon @ r(t3 − t2) T3 = + 0.7 Pf @ r(t3 − t2)] RθJC T3 = [Pavg + (0.7 Pr − Pavg) @ r(t3 − to) + T3 = (Pon − 0.7 Pr) @ r(t3 − t1) + (0.7 Pf − Pon) T3 = @ r(t3 − t2)] RθJC T3 = [94.8 + (535.2) @ r(221 μs) + (−612) @ r(206.8 μs) T3 = + (612) @ r(56.8μs)] (0.5) T3 = [94.8 + (535.2)(0.09) − (612) (0.086) + T3 = (612)(0.045)] (0.5) T3 = [94.8 + 481.7− 52.63 + 27.54] (0.5) T3 = (117.88)(0.5) = 58.94°C
- 223. http://onsemi.com 223 The junction temperature at the end of the rise, on, and fall times, TJ1, TJ2, and TJ3, is as follows: TJ1 = T1 + TA + RθCA @ Pavg RθCA = RθCS = RθSA = 0.1 + 0.55 TJ1 = 53.55 + 50 + (0.65)(94.8) = 165.17°C TJ2 = T2 + TA + RθCA @ Pavg TJ2 = 45.6 + 50 + (0.65)(94.8) TJ2 = 157.22°C TJ3 = T3 + TA + RθCA @ Pavg TJ3 = 58.94 + 50 + (0.65)(94.8) TJ3 = 170.56°C TJ(avg) = Pavg (RθJC + RθCS + RθSA) + TA TJ(avg) = (94.8)(0.5 + 0.1 + 0.55) + 50 TJ(avg) = (94.8)(1.15) + 50 = 159.02°C Inspection of the results of the calculations T1, T2, and T3 reveal that the term of significance in the equations is the average power. Even with the poor switching times there was a peak junction temperature of 11.5°C above the average value. This is a 7% increase which for most applications could be ignored, especially when switching times are considerably less. Thus the product of average power and steady state thermal resistance is the determin- ing factor for junction temperature rise in this application. SUMMARY This report has explained the concept of transient thermal resistance and its use. Methods using various degrees of approximations have been presented to deter- mine the junction temperature rise of a device. Since the thermal response data shown is a step function response, modeling of different wave shapes to an equivalent rectangular pulse of pulses has been discussed. The concept of a duty cycle family of curves has also been covered; a concept that can be used to simplify calculation of the junction temperature rise under a repetitive pulse train. APPENDIX A METHODS OF SOLUTION In the examples, a type 2N3647 transistor will be used; its steady state thermal resistance, RθJC, is 35°C/W and its value for r(t) is shown in Figure A1. Definitions: P1, P2, P3 ... Pn = power pulses (Watts) T1, T2, T3 ... Tn = junction to case temperature at T end of P1, P2, P3 ... Pn t0, t1, t2, ... tn = times at which a power pulse begins or ends r(tn − tk) = transient thermal resistance factor at end of time interval (tn − tk). Table 8.1. Several Possible Methods of Solutions 1. Junction Temperature Rise Using Pulse−By−Pulse Method A. Temperature rise at the end of the nth pulse for pulses with unequal amplitude, spacing, and duration. B. Temperature rise at the end of the nth pulse for pulses with equal amplitude, spacing, and duration. 2. Temperature Rise Using Average Power Concept Under Steady State Conditions For Pulses Of Equal Amplitude, Spacing, And Duration A. At the end of the nth pulse. B. At the end of the (n + 1) pulse. 3. Temperature Rise Using Average Power Concept Under Transient Conditions. A. At the end of the nth pulse for pulses of equal amplitude, spacing and duration. B. At the end of the n + 1 pulse for pulses of equal amplitude, spacing and duration. C. At the end of the nth pulse for pulses of unequal amplitude, spacing and duration. D. At the end of the n + 1 pulse for pulses of unequal amplitude, spacing and duration. METHOD 1A − FINDING TJ AT THE END OF THE Nth PULSE IN A TRAIN OF UNEQUAL AMPLITUDE, SPACING, AND DURATION General Equation: Tn + ȍ n i+1 Pi [r(t2n−1 − t2i−2) (1−1) − r(tn−1 − t2i−1)]RθJC where n is the number of pulses and Pi is the peak value of the ith pulse. To find temperature at the end of the first three pulses, Equation 1−1 becomes: T1 = P1 r(t1) RθJC (1−1A) T2 = [P1 r(t3) − P1 r(t3 − t1) (1−1B) T2 = + P2 r(t3 − t2)] RθJC T3 = [P1 r(t5) − P1 r(t5 − t1) + P2 r(t5 − t2) (1−1C) T3 = − P2 r(t5 − t3) + P3 r(t5 − t4)] RθJC Example: Conditions are shown on Figure 4 as: P1 = 40 W P2 = 20 W P3 = 30 W t0 = 0 t1 = 0.1 ms t2 = 0.3 ms t3 = 1.3 ms t4 = 3.3 ms t5 = 3.5 ms Therefore, t1 − t0 = 0.1 ms t2 − t1 = 0.2 ms t3 − t2 = 1 ms t4 − t3 = 2 ms t5 − t4 = 0.2 ms t3 − t1 = 1.2 ms t5 − t1 = 3.4 ms t5 − t2 = 3.2 ms t5 − t3 = 2.2 ms
- 224. http://onsemi.com 224 Procedure: Find r(tn − tk) for preceding time intervals from Figure 8.2, then substitute into Equations 1−1A, B, and C. T1 = P1 r(t1) RθJC = 40 @ 0.05 @ 35 = 70°C T2 = [P1 r(t3) − P1 r(t3 − t1) + P2 r(t3 − t2)] RθJC T2 = [40 (0.175) − 40 (0.170) + 20 (0.155)] 35 T2 = [40 (0.175 − 0.170) + 20 (0.155)] 35 T2 = [0.2 + 3.1] 35 = 115.5°C T3 = [P1 r(t5) − P1 r(t5 − t1) + P2 r(t5 − t2) T3 = − P2 r(t5 − t3) + P3 r(t5 − t4)] θJC T3 = [40 (0.28) − 40 (0.277) + 20 (0.275) − 20 (0.227) T3 = + 30 (0.07)] 35 T3 = [40 (0.28 − 0.277) + 20 (0.275 − 0.227) T3 = + 30 (0.07)] 35 T3 = [0.12 + 0.96 + 2.1]{ 35 = 3.18 @ 35 = 111.3°C Note, by inspecting the last bracketed term in the equations above that very little residual temperature is left from the first pulse at the end of the second and third pulse. Also note that the second pulse gave the highest value of junction temperature, a fact not so obvious from inspection of the figure. However, considerable residual temperature from the second pulse was present at the end of the third pulse. METHOD 1B − FINDING TJ AT THE END OF THE Nth PULSE IN A TRAIN OF EQUAL AMPLITUDE, SPACING, AND DURATION The general equation for a train of equal repetitive pulses can be derived from Equation 1−1. Pi = PD, ti = t, and the spacing between leading edges or trailing edges of adjacent pulses is τ. General Equation: ȍ n i+1 r[(n − i) τ + t] (1−2) − r[(n − i) τ] Tn = PDRθJC Expanding: Tn = PD RθJC r[(n − 1) τ + t] − r[(n − 1) τ] Tn = + r[(n − 2) τ + t) − r[(n − 2) τ] + r[(n − 3) Tn = τ + t] − r[(n − 3) τ] + . . . + r[(n − i) τ + t] Tn = − r[(n − i) τ] . . . . . + r(t)] (1−2A) Relative amounts of temperature residual from P1, P2, and P3 respectively are indicated by the terms in brackets. { For 5 pulses, equation 1−2A is written: T5 = PD RθJC [r(4 τ + t) − r(4τ) + r(3τ + t)] T5 = − r(3τ) + r(2τ + t) − r(2τ) + r(τ + t) T5 = − r(τ) + r(t)] Example: Conditions are shown on Figure 8.5 substituting values into the preceding expression: T5 = (5) (35) [r(4.20 + 5) − r(4.20) + r(3.20 + 5) T5 = + r(3.20) + r(2.20 + 5) − r(2.20) + r(20 + 5) T5 = − r(20) + r(5)] T5 = (5) (35) [0.6 − 0.76 + 0.73 − 0.72 + 0.68 T5 = − 0.66 + 0.59 − 0.55 + 0.33] − (5)(35)(0.40) T5 = 70.0°C Note that the solution involves the difference between terms nearly identical in value. Greater accuracy will be obtained with long or repetitive pulse trains using the technique of an average power pulse as used in Methods 2 and 3. METHOD 2 − AVERAGE POWER METHOD, STEADY STATE CONDITION The essence of this method is shown in Figure 8.6. Pulses previous to the nth pulse are averaged. Temperature due to the nth or n + 1 pulse is then calculated and combined properly with the average temperature. Assuming the pulse train has been applied for a period of time (long enough for steady state conditions to be established), we can average the power applied as: Pavg + PD t t (1−3) METHOD 2A − FINDING TEMPERATURE AT THE END OF THE Nth PULSE Applicable Equation: (1−4)Tn = [Pavg + (PD − Pavg) r(t)] RθJC or, by substituting Equation 1−3 into 1−4, Tn + ƪt t ) ǒ1– t t Ǔ r(t)ƫPD RqJC (1−5) The result of this equation will be conservative as it adds a temperature increase due to the pulse (PD − Pavg) to the average temperature. The cooling between pulses has not been accurately accounted for; i.e., TJ must actually be less than TJ(avg) when the nth pulse is applied.
- 225. http://onsemi.com 225 Example: Find Tn for conditions of Figure 8.5. Procedure: Find Pavg from equation (1−3) and substitute values in equation (1−4) or (1−5). Tn = [(1.25) + (5.0 − 1.25)(0.33)] (35) Tn = 43.7 + 43.2 = 86.9°C METHOD 2B − FINDING TEMPERATURE AT THE END OF THE N + 1 PULSE Applicable Equation: Tn + 1 = [Pavg + (PD − Pavg) r(t + τ) Tn + 1 + PD r(t) − PD r(τ)] RθJC (1−6) or, by substituting equation 1−3 into 1−6, (1−7) t t ) ǒ1– t t Ǔr(t ) t)Tn + 1 = ) r(t) * r(t) PDRθJC Example: Find Tn for conditions of Figure 8.5. Procedure: Find Pavg from equation (1−3) and substitute into equation (1−6) or (1−7). Tn + 1 = [(1.25) + (5 − 1.25)(0.59) + (5)(0.33) Tn + 1 − (5)(0.56)] (35) = 80.9°C Equation (1−6) gives a lower and more accurate value for temperature than equation (1−4). However, it too gives a higher value than the true TJ at the end of the n + 1th pulse. The error occurs because the implied value for TJ at the end of the nth pulse, as was pointed out, is somewhat high. Adding additional pulses will improve the accuracy of the calculation up to the point where terms of nearly equal value are being subtracted, as shown in the examples using the pulse by pulse method. In practice, however, use of this method has been found to yield reasonable design values and is the method used to determine the duty cycle of family of curves − e.g., Figure 8.2. Note that the calculated temperature of 80.9°C is 10.9°C higher than the result of example 1B, where the tempera- ture was found at the end of the 5th pulse. Since the thermal response curve indicates thermal equilibrium in 1 second, 50 pulses occurring 20 milliseconds apart will be required to achieve stable average and peak temperatures; therefore, steady state conditions were not achieved at the end of the 5th pulse. METHOD 3 − AVERAGE POWER METHOD, TRANSIENT CONDITIONS The idea of using average power can also be used in the transient condition for a train of repetitive pulses. The previously developed equations are used but Pavg must be modified by the thermal response factor at time t(2n − 1). METHOD 3A − FINDING TEMPERATURE AT THE END OF THE Nth PULSE FOR PULSES OF EQUAL AMPLITUDE, SPACING AND DURATION Applicable Equation: (1−8)Tn + ƪt t r t(2n–1) ) ǒ1 – t t Ǔr(t)ƫ PD RθJC Conditions: (See Figure 8.5) Procedure: At the end of the 5th pulse (See Figure 8.7) . . . T5 = [5/20 @ r(85) + (1 − 5/20)r(5)] (5)(35) T5 = [(0.25)(0765) + (0.75)(0.33)] (175) T5 = 77°C This value is a little higher than the one calculated by summing the results of all pulses; indeed it should be, because no cooling time was allowed between Pavg and the nth pulse. The method whereby temperature was calculated at the n + 1 pulse could be used for greater accuracy. METHOD 3B − FINDING TEMPERATURE AT THE END OF THE N + 1 PULSE FOR PULSES OF EQUAL AMPLITUDE, SPACING AND DURATION Applicable Equation: (1−9) t t r(t2n–1) ) ǒ1 – t t ǓTn + 1 = r(t ) t) ) r(t) * r(t) PD RθJC Example: Conditions as shown on Figure 8.5. Find temperature at the end of the 5th pulse. For n + 1 = 5, n = 4, t2n−1 = t7 = 65 ms, 5 20 r(65 ms) ) ǒ1 – 5 20 Ǔ r(25 ms)T5 = ) r(5 ms) * r(20 ms) (5)(35) T5 = [(0.25)(0.73) + (0.75)(0.59) + 0.33 − 0.55](5)(35) T5 = 70.8°C
- 226. http://onsemi.com 226 The answer agrees quite well with the answer of Method 1B where the pulse−by−pulse method was used for a repetitive train. METHOD 3C − FINDING TJ AT THE END OF THE Nth PULSE IN A RANDOM TRAIN The technique of using average power does not limit itself to a train of repetitive pulses. It can be used also where the pulses are of unequal magnitude and duration. Since the method yields a conservative value of junction temperature rise it is a relatively simple way to achieve a first approximation. For random pulses, equations 1−4 through 1−7 can be modified. It is necessary to multiply Pavg by the thermal response factor at time t(2n − 1). Pavg is determined by averaging the power pulses from time of application to the time when the last pulse starts. Applicable Equations: ȍ n i+1 Pi (1−10)General: Pavg = t(2i−1)−t(2i−2) t(2n)−t(2i−2) For 3 Pulses: (1−11)Pavg = P1 t1 − t0 t4 − t0 t3 − t2 t4 − t2 + P2 Example: Conditions are shown on Figure 8.4 (refer to Method 1A). Procedure: Find Pavg from equation 1−3 and the junction temperature rise from equation 1−4. Conditions: Figure 8.4 Pavg 0.1 3.3 ) 20 1 3 + 1.21 ) 6.67= 40 @ = 7.88 Watts T3 = [Pavg r(t5) + (P3 − Pavg) r(t5 − t4)] RθJC = [7.88 (0.28) + (30 − 7.88) @ 0.07] 35 = [2.21 + 1.56] 35 = 132°C This result is high because in the actual case considerable cooling time occurred between P2 and P3 which allowed TJ to become very close to TC. Better accuracy is obtained when several pulses are present by using equation 1−10 in order to calculate TJ − tC at the end of the nth + 1 pulse. This technique provides a conservative quick answer if it is easy to determine which pulse in the train will cause maximum junction temperature. METHOD 3D − FINDING TEMPERATURE AT THE END OF THE N + 1 PULSE IN A RANDOM TRAIN The method is similar to 3C and the procedure is identical. Pavg is calculated from Equation 1−10 modified by r(t2n − 1) and substituted into equation 1−6, i.e., Tn + 1 = [Pavg r(t2n−1) + (PD − Pave) r(t2n−1 − Tn + 1 = t2n−2) + PD r(t2n+1 − t2n) − PD r(t2n+1 Tn + 1 = − t2n−1)] RθJC The previous example cannot be worked out for the n + 1 pulse because only 3 pulses are present. Table 8.2. Summary Of Numerical Solution For The Repetitive Pulse Train Of Figure 5 Temperature Desired Temperature Obtained, °C Pulse by Pulse Average Power Nth Pulse Average Power N + 1 Pulse At End of 5th Pulse 70.0 (1B) 77 (3A) 70.8 (3B) Steady State Peak − 86.9 (2A) 80.9 (2B) Note: Number in parenthesis is method used. Figure 8.9. 2N3467 Transient Thermal Response 1.0 0.1 0.01 0.01 0.1 1.0 10 100 1000 t, Time (ms) r(t),TransientThermalResistance (Normalized) 0.2 0.02 0.3 0.03 0.5 0.05 0.7 0.07 0.02 0.2 2.0 20 2000.05 0.5 5.0 50 500
- 227. http://onsemi.com 227 Figure 8.10. Case 77 and TO−220 Thermal Response 1.0 0.1 0.01 0.1 1.0 10 100 1000 10,000 t, Time (ms) r(t),TransientThermalResistance (Normalized) 0.2 0.02 0.3 0.03 0.5 0.05 0.7 0.07 0.2 2.0 20 200 20000.5 5.0 50 500 5000 Case 221 Case 77 Figure 8.11. TO−92 Thermal Response, Applies to All Commonly Used Die 1.0 0.1 0.01 r(t),TransientThermalResistance (Normalized) 0.2 0.02 0.3 0.03 0.5 0.05 0.7 0.07 0.1 1.0 10 100 1000 10,000 t, Time (ms) 0.2 2.0 20 200 20000.5 5.0 50 500 5000 1 2 8,100 16,900 MCR106−6 2N6344 DEVICE TYPE DIE SIZE (Sq. Mils) 1 2 As the price of semiconductor devices decreases, reli- ability and quality have become increasingly important in selecting a vendor. In many cases these considerations even outweigh price, delivery and service. The reason is that the cost of device fallout and warranty repairs can easily equal or exceed the original cost of the devices. Consider the example shown in Figure 8.12. Although the case is simplistic, the prices and costs are realistic by today’s standards. In this case, the cost of failures raised the device cost from 15 cents to 21 cents, an increase of 40%. Clearly, then, investing in quality and reliability can pay big dividends. With nearly three decades of experience as a major semiconductor supplier, ON Semiconductor is one of the largest manufacturers of discrete semiconductors in the world today. Since semiconductor prices are strongly influenced by manufacturing volume, this leadership has permitted ON Semiconductor to be strongly competitive in the marketplace while making massive investments in equipment, processes and procedures to guarantee that the company’s after−purchase costs will be among the lowest in the industry. Given: Purchase = 100,000 components @ 15¢ each Assumptions: Line Fallout = 0.1% Assumptions: Warranty Failures = 0.01% Components Cost =100,000 15¢ = $15,000 Line Fallout Cost = 100 $40 = 4,000 @ $40 per repair Warranty Cost = 10 $200 = 2,000 @ $200 per repair $21,000 Adjusted Cost Per Component = $21,000 100,000 = 21¢ Definitions: Line Fall out = Module or subassembly failure requiring troubleshooting, parts replacement and retesting Warranty Failure = System field failure requir- ing in warranty repair Figure 8.12. Component Costs to the User (Including Line Fallout and Warranty Costs)
- 228. http://onsemi.com 228 Quality and reliability are two essential elements in order for a semiconductor company to be successful in the marketplace today. Quality and reliability are interrelated because reliability is quality extended over the expected life of the product. Quality is the assurance that a product will fulfill customers’ expectations. Reliability is the probability that a product will perform its intended function satisfactorily for a prescribed life under certain stated conditions. The quality and reliability of ON Semiconductor thyris- tors are achieved with a four step program: 1. Thoroughly tested designs and materials 2. Stringent in−process controls and inspections 3. Process average testing along with 100% quality assur- ance redundant testing 4. Reliability verifications through audits and reliability studies ESSENTIALS OF RELIABILITY Paramount in the mind of every semiconductor user is the question of device performance versus time. After the applicability of a particular device has been established, its effectiveness depends on the length of trouble free service it can offer. The reliability of a device is exactly that — an expression of how well it will serve the customer. Reliability can be redefined as the probability of failure free performance, under a given manufacturer’s specifica- tions, for a given period of time. The failure rate of semiconductors in general, when plotted versus a long period of time, exhibit what has been called the “bath tub curve” (Figure 8.13). Figure 8.13. Failure Rate of Semiconductor INFANT MORTALITY RANDOM FAILURE MECHANISM WEAROUT PHENOMENON FAILURERATE RELIABILITY MECHANICS Since reliability evaluations usually involve only sam- ples of an entire population of devices, the concept of the central limit theorem applies and a failure rate is calculated using the λ2 distribution through the equation: l2 (a, 2r ) 2) 2 nt λ ≤ λ2 = chi squared distribution where a + 100 – cl 100 λ cl r n t = Failure rate = Confidence limit in percent = Number of rejects = Number of devices = Duration of tests The confidence limit is the degree of conservatism desired in the calculation. The central limit theorem states that the values of any sample of units out of a large population will produce a normal distribution. A 50% confidence limit is termed the best estimate, and is the mean of this distribution. A 90% confidence limit is a very conservative value and results in a higher λ which represents the point at which 90% of the area of the distribution is to the left of that value (Figure 8.14). Figure 8.14. Confidence Limits and the Distribution of Sample Failure Rates 50% CL X FREQUENCY 90% CL l, FAILURE RATE The term (2r + 2) is called the degrees of freedom and is an expression of the number of rejects in a form suitable to λ2 tables. The number of rejects is a critical factor since the definition of rejects often differs between manufacturers. Due to the increasing chance of a test not being representa- tive of the entire population as sample size and test time are decreased, the λ2 calculation produces surprisingly high values of λ for short test durations even though the true long term failure rate may be quite low. For this reason relatively large amounts of data must be gathered to demonstrate the real long term failure rate. Since this would require years of testing on thousands of devices, methods of accelerated testing have been developed.
- 229. http://onsemi.com 229 Years of semiconductor device testing have shown that temperature will accelerate failures and that this behavior fits the form of the Arrhenius equation: R(t) = Ro(t)e−o/KT Where R(t) = reaction rate as a function of time and temperature Ro = A constant t = Time T = Absolute temperature, °Kelvin (°C + 273°) o = Activation energy in electron volts (ev) K = Boltzman’s constant = 8.62 10−5 ev/°K This equation can also be put in the form: AF = Acceleration factor T2 = User temperature T1 = Actual test temperature The Arrhenius equation states that reaction rate increases exponentially with the temperature. This produces a straight line when plotted on log−linear paper with a slope expressed by o. o may be physically interpreted as the energy threshold of a particular reaction or failure mecha- nism. The overall activation energy exhibited by ON Semiconductor thyristors is 1 ev. RELIABILITY QUALIFICATIONS/EVALUATIONS OUTLINE: Some of the functions of ON Semiconductor Reliability and Quality Assurance Engineering are to evaluate new products for introduction, process changes (whether minor or major), and product line updates to verify the integrity and reliability of conformance, thereby ensuring satisfacto- ry performance in the field. The reliability evaluations may be subjected to a series of extensive reliability testing, such as in the tests performed section, or special tests, depending on the nature of the qualification requirement. AVERAGE OUTGOING QUALITY (AOQ) With the industry trend to average outgoing qualities (AOQ) of less than 100 PPM, the role of device final test, and final outgoing quality assurance have become a key ingredient to success. At ON Semiconductor, all parts are 100% tested to process average limits then the yields are monitored closely by product engineers, and abnormal areas of fallout are held for engineering investigation. ON Semiconductor also 100% redundant tests all dc parameters again after marking the device to further reduce any mixing problems associated with the first test. Prior to shipping, the parts are again sampled, tested to a tight sampling plan by our Quality Assurance department, and finally our outgoing final inspection checks for correct paperwork, mixed product, visual and mechanical inspec- tions prior to packaging to the customers. AVERAGE OUTGOING QUALITY (AOQ) AOQ = Process Average Probability of Acceptance 106 (PPM) Process Average + No. of Reject Devices No. of Devices Tested Probability of Acceptance + (1– No. of Lots Rejected No. of Lots Tested ) 106 = To Convert to Parts Per Million AOQ + No. of Reject Devices No. of Devices Tested (1 – No. of Lots Rejected No. of Lots Tested ) 106(PPM) THYRISTOR RELIABILITY The reliability data described herein applies to ON Semiconductor’s extensive offering of thyristor prod- ucts for low and medium current applications. The line includes not only the pervasive Silicon Controlled Rectifi- ers (SCRs) and TRIACs, but also a variety of Program- mable Unijunction Transistors (PUTs), SIDACs and other associated devices used for SCR and TRIAC triggering purposes. Moreover, these devices are available in different package styles with overlapping current ranges to provide an integral chip−and−package structure that yields lowest cost, consistent with the overriding consideration of high reliability. Some of the various packages and the range of electrical specifications associated with the resultant products are shown in Figure 8.15. To evaluate the reliability of these structures, production line samples from each type of package are being subjected to a battery of accelerated reliability tests deliberately designed to induce long−term failure. Though the tests are being conducted on a continuing basis, the results so far are both meaningful and impressive. They are detailed on the following pages in the hope that they will provide for the readers a greater awareness of the potential for thyristors in their individual application.
- 230. http://onsemi.com 230 TO−92 Case 029/TO−226AA Devices Available: SCRs, TRIACs, PUTs Current Range: to 0.8 A Voltage Range: 30 to 600 V TO−225AA Case 077/TO−126 Devices Available: SCRs, TRIACs Current Range: to 4 A Voltage Range: 200 to 600 V Case 267/Axial Lead (Surmetic 50) Devices Available: SIDAC Voltage Range: 120 to 240 V TO−220AB Case 221A Devices Available: SCRs, TRIACs Current Range: to 55 A Voltage Range: 50 to 800 V Figure 8.15. Examples of ON Semiconductor’s Thyristor Packages THYRISTOR CONSTRUCTION THROUGH A TIME TESTED DESIGN AND ADVANCED PROCESSING METHODS A pioneer in discrete semiconductor components and one of the world’s largest suppliers thereof, ON Semiconductor has pyramided continual process and material improvements into thyristor products whose inherent reliability meets the most critical requirements of the market. These improvements are directed towards long−term reliability in the most strenuous applications and the most adverse environments. DIE GLASSIVATION All ON Semiconductor thyristor die are glass−sealed with an ON Semiconductor patented passivation process making the sensitive junctions impervious to moisture and impurity penetration. This imparts to low−cost plastic devices the same freedom from external contamination formerly associated only with hermetically sealed metal packages. Thus, metal encapsulation is required primarily for higher current devices that would normally exceed the power−dissipation capabilities of plastic packages — or for applications that specify the hermetic package. VOID−FREE PLASTIC ENCAPSULATION A fifth generation plastic package material, combined with improved copper piece−part designs, maximize pack- age integrity during thermal stresses. The void−free encapsulation process imparts to the plastic package a mechanical reliability (ability to withstand shock and vibration) even beyond that of metal packaged devices. IN−PROCESS CONTROLS AND INSPECTIONS INCOMING INSPECTIONS Apparently routine procedures, inspection of incoming parts and materials, are actually among the most critical segments of the quality and reliability assurance program. That’s because small deviations from materials specifica- tions can traverse the entire production cycle before being detected by outgoing Quality Control, and, if undetected, could affect long−term reliability. At ON Semiconductor, piece−part control involves the services of three separate laboratories . . . Radiology, Electron Optics and Product Analysis. All three are utilized to insure product integrity: Raw Wafer Quality, in terms of defects, orientation, flatness and resistivity; Physical Dimensions, to tightly specified tolerances; Metal Hardness, to highly controlled limits; Gaseous Purity and Doping Level; Mold Compounds, for void−free plastic encapsulation. IN−PROCESS INSPECTIONS As illustrated in Figure 8.16, every major manufacturing step is followed by an appropriate in−process QA inspec- tion. Quality control in wafer processing, assembly and final test impart to ON Semiconductor standard thyristors a reliability level that easily exceeds most industrial, con- sumer and military requirements . . . built−in quality assurance aimed at insuring failure−free shipments of ON Semiconductor products.
- 231. http://onsemi.com 231 RELIABILITY AUDITS Reliability audits are performed following assembly. Reliability audits are used to detect process shifts which can have an adverse effect on long−term reliability. Extreme stress testing on a real−time basis, for each product run, uncovers process abnormalities that may have escaped the stringent in−process controls. Typical tests include HTRB/FB (high−temperature reverse bias and forward bias) storage life and temperature cycling. When abnormalities are detected, steps are taken to correct the process. OUTGOING QC The most stringent in−process controls do not guarantee strict adherence to tight electrical specifications. ON Semiconductor’s 100% electrical parametric test does — by eliminating all devices that do not conform to the specified characteristics. Additional parametric tests, on a sampling basis, provide data for continued improvement of product quality. And to help insure safe arrival after shipment, antistatic handling and packaging methods are employed to assure that the product quality that has been built in stays that way. From rigid incoming inspection of piece parts and materials to stringent outgoing quality verification, assem- bly and process controls encompass an elaborate system of test and inspection stations that ensure step−by−step adherence to a prescribed procedure designed to yield a high standard of quality. Figure 8.16. In−Process Quality Assurance Inspection Points for Thyristors IN− COMING INSP. WAFER CHEMICALS DIFFUSION, MOAT ETCH, PHOTOGLASS RESIS− TIVITY INSPECTION METALLIZATION, 100% DIE ELECT, TESTS SCRIBE BREAK ELEC. VISUAL INSPECTION INC. INSP. FORM CLEAN PC. PARTS QA INSPECTION DIE BOND QA INSPECTION QA INSPECTION LEAD ATTACHMENT INJECTION MOLD DEFLASH PLASTIC, CLEAN SOLDER DIP LEADS, CURE PLASTIC RELIA− BILITY AUDITS 100% ELECT. SELECTION, 100% BIN SPECIFICATION TEST, 100% QA INSPECTION LASER MARKING OUTGOING QC SAMPLING 100% ANTISTATIC HANDLING/PACKAGING FINAL VISUAL MECHANICAL SHIPPING RELIABILITY TESTS Only actual use of millions of devices, under a thousand different operating conditions, can conclusively establish the reliability of devices under the extremes of time, temperature, humidity, shock, vibration and the myriads of other adverse variables likely to be encountered in practice. But thorough testing, in conjunction with rigorous statisti- cal analysis, is the next−best thing. The series of torture tests described in this document instills a high confidence level regarding thyristor reliability. The tests are conducted at maximum device ratings and are designed to deliberately stress the devices in their most susceptible failure models. The severity of the tests compresses into a relatively short
- 232. http://onsemi.com 232 test cycle the equivalent of the stresses encountered during years of operation under more normal conditions. The results not only indicate the degree of reliability in terms of anticipated failures; they trigger subsequent investigations into failure modes and failure mechanisms that serve as the basis of continual improvements. And they represent a clear−cut endorsement that, for ON Semiconductor thyris- tors, low−cost and high quality are compatible attributes. BLOCKING LIFE TEST This test is used as an indicator of long−term operating reliability and overall junction stability (quality). All semiconductor junctions exhibit some leakage current under reverse−bias conditions. Thyristors, in addition, exhibit leakage current under forward−bias conditions in the off state. As a normal property of semiconductors, this junction leakage current increases proportionally with temperature in a very predictable fashion. Leakage current can also change as a function of time — particularly under high−temperature operation. Moreover, this undesirable “drift” can produce catastrophic failures when devices are operated at, or in excess of, rated temperature limits for prolonged periods. The blocking life test operates representative numbers of devices at rated (high) temperature and reverse−bias voltage limits to define device quality (as measured by leakage drifts) and reliability (as indicated by the number of catastrophic failures*). The results of these tests are shown in Table 8.3. Table 8.4 shows leakage−current drift after 1000 hours HTRB. Table 8.3. Blocking Life Test High Temperature Reverse Bias (HTRB) and High Temperature Forward Bias (HTFB) Case Test Conditions TA @ Rated Voltage Sample Size Duration (Hours) Total Device Hours Cata- strophic Failures* Case 029/TO−226AA (TO−92) 100°C 1000 1000 1,000,000 1 Case 077/TO−225AA (TO−126) 110°C 1000 1000 1,000,000 0 Case 221A/TO−220AB 100°C 1000 1000 1,000,000 0 Case 267/Axial Lead (Surmetic 50) 125°C 150 1000 150,000 0 * Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions. Table 8.4. Leakage−Current Drift after 1000 Hours HTRB The favorable blocking−life−test drift results shown here are attributed to ON Semiconductor’s unique “glassivated junction” process which imparts a high degree of stability to the devices. −40 μA −20 μA +20 μA +40 μA0 Leakage Shift from Initial Value VDRM = 400 V TA = 100°C HIGH TEMPERATURE STORAGE LIFE TEST This test consists of placing devices in a high−tempera- ture chamber. Devices are tested electrically prior to exposure to the high temperature, at various time intervals during the test, and at the completion of testing. Electrical readout results indicate the stability of the devices, their potential to withstand high temperatures, and the internal manufacturing integrity of the package. Readouts at the various intervals offer information as to the time period in which failures occur. Although devices are not exposed to such extreme high temperatures in the field, the purpose of this test is to accelerate any failure mechanisms that could occur during long periods at actual storage temperatures. Results of this test are shown in Table 8.5. Table 8.5. High Temperature Storage Life Case Test Conditions Sample Size Duration (Hours) Total Device Hours Cata- strophic Failures* Case 029/TO−226AA (TO−92) TA = 150°C 1000- 2000 400 1,500,000 0 Case 077/TO−225AA (TO−126) ** 1000- 2000 350 550,000 0 Case 221A/TO−220 1000 300 300,000 0 Case 267/Axial Lead (Surmetic 50) 1000 100 100,000 0 * Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions. ** Same for all.
- 233. http://onsemi.com 233 STRESS TESTING — POWER CYCLING AND THERMAL SHOCK POWER CYCLING TEST How do the devices hold up when they are repeatedly cycled from the off state to the on state and back to the off state under conditions that force them to maximum rated junction temperature during each cycle? The Power Cycling Test was devised to provide the answers. In this test, devices are subjected to intermittent operat- ing file (IOL), on−state power until the junction tempera- ture (TJ) has increased to 100°C. The devices are then turned off and TJ decreases to near ambient, at which time the cycle is repeated. This test is important to determine the integrity of the chip and lead frame assembly since it repeatedly stresses the devices. It is unlikely that these worst−case conditions would be continuously encountered in actual use. Any reduction in TJ results in an exponential increase in operating longevity. Table 8.6 shows the results of IOL testing. THERMAL SHOCK CONDITIONS BEYOND THE NORM Excesses in temperature not only cause variations in electrical characteristics, they can raise havoc with the mechanical system. Under temperature extremes, contrac- tion and expansion of the chip and package can cause physical dislocations of mechanical interfaces and induce catastrophic failure. To evaluate the integrity of ON Semiconductor thyristors under the most adverse temperature conditions, they are subjected to thermal shock testing. AIR−TO−AIR (TEMPERATURE CYCLING) This thermal shock test is conducted to determine the ability of the devices to withstand exposure to extreme high and low temperature environments and to the shock of alternate exposures to the temperature extremes. Results of this test are shown in Table 8.6. Table 8.6. Air−to−Air Case Test Conditions Sample Size Number of cycles Total Device Cycles Catastrophic Failures* Case 029/TO−226AA (TO−92) −40°C or −65°C to +150°C Dwell—15 minutes at each extreme Immediate Transfer 900 400 360,000 0 Case 077/TO−225AA (TO−126) 500 400 200,000 0 Case 221A/TO−220 400 400 160,000 0 Case 267/Axial Lead (Surmetic 50) 100 400 40,000 0 * Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions. ENVIRONMENTAL TESTING MOISTURE TESTS Humidity has been a traditional enemy of semiconduc- tors, particularly plastic packaged devices. Most moisture− related degradations result, directly or indirectly, from penetration of moisture vapor through passivating materi- als, and from surface corrosion. At ON Semiconductor, this erstwhile problem has been effectively controlled through the use of a unique junction “glassivation” process and selection of package materials. The resistance to moisture− related failures is indicated by the tests described here. BIASED HUMIDITY TEST This test was devised to determine the resistance of component parts and constituent materials to the combined deteriorative effects of prolonged operation in a high−tem- perature/high−humidity environment. H3TRB test results are shown in Table 8.7. Table 8.7. Biased Humidity Test High Humidity, High Temperature, Reverse Bias (H3TRB) Case Test Conditions Sample Size Duration Hours Total Device Cycles Catastrophic Failures* Case 029/TO−226AA (TO−92) Relative Humidity 85% TA = 85°C Reverse Voltage−Rated or 200 V Maximum 400 500−1000 300,000 0 Case 077/TO−225AA 200 500−1000 150,000 0 Case 221A/TO−220 100 500−1000 75,000 0 Case 267/Axial Lead (Surmetic 50) 30 1000 30,000 0 * Failures are at maximum rated values. The severe nature of these tests is normally not seen under actual conditions.
- 234. http://onsemi.com 234 SECTION 9 APPENDICES APPENDIX I USING THE TWO TRANSISTOR ANALYSIS DEFINITIONS: IC 5 IB 5 ICS 5 IA 5 IK 5 α 5 IG 5 Collector current Base current Collector leakage current (saturation component) Anode current Cathode current Current amplification factor Gate current The subscript “i” indicates the appropriate transistor. FOR TRANSISTOR #1: IC1 = α1 IA + ICSI and IB1 = IA − IC1 Combining these equations, IB1 = (1 − α1) IA − ICS1 (1) LIKEWISE, FOR TRANSISTOR #2 IC2 = α2IK + ICS2 (2) IB1 = IC2 and by combining Equations (1) and (2) and substituting IK = IA + IG, it is found that IA + a2IG ) ICS1 ) ICS2 1 – a1 – a2 (3) Equation (3) relates IA to IG, and note that as α1 + α2 = 1, IA goes to infinity. IA can be put in terms of IK and α’s as follows: IB1 = IC2 Combining equations (1) and (2): IA + ICS1 ) ICS2 1 – a1 – ( IK IA ) a2 IA — ∞ if denominator approaches zero, i.e., if IK IA + 1 – a1 a2 Note that just prior to turn−on there is a majority carrier build−up in the P2 “base.” If the gate bias is small there will actually be hole current flowing out from P2 into the gate circuit so that IG is negative, IK = IA + IG is less than IA so: (see Figure 3.2 for the directions of current components) IK IA 1 which corresponds to α1 + α2 1 Figure 9.1. Schematic Diagram of the Two Transistor Model of a Thyristor IA IB1 IC1 IC2 IK IB2IG A G K P1 N1 P2 N1 N2 P2 DEVICE #1 DEVICE #2
- 235. http://onsemi.com 235 APPENDIX II CHARGE AND PULSE WIDTH In the region of large pulse widths using current triggering, where transit time effects are not a factor, we can consider the input gate charge for triggering, Qin, as consisting of three components: 1. Triggering charge Qtr, assumed to be constant. 2. Charge lost in recombination, Qr, during current regeneration prior to turn−on. 3. Charge drained, Qdr, which is by−passed through the built−in gate cathode shunt resistance (the presence of this shunting resistance is required to increase the dv/dt capability of the device). Mathematically, we have Qin = Qtr + Qdr + Qr = IGτ (1) Qr is assumed to be proportional to Qin; to be exact, Qr = Qin (1 − exp−τ/τ1) (2) where IG = τ = τ1 = gate current, pulse width of gate current, effective life time of minority carriers in the bases The voltage across the gate to cathode P−N junction during forward bias is given by VGK (usually 0.6 V for silicon).* The gate shunt resistance is Rs (for the MCR729, typically 100 ohms), so the drained charge can be expressed by Qdr + VGC Rs t (3) Combining equations (1), (2), and (3), we get Qin + IGt + (Qtr ) VGC Rs t) exp. tńt1 (4) Note that at region A and C of Figure 3.3(c) Qin has an increasing trend with pulse width as qualitatively described by Equation (4). Assume life time at the temperature range of operation increases as some power of temperature τ1 = KTm (5) where K and m are positive real numbers. Combining Equations (4) and (5), we can get the slope of Qin with respect to temperature to be slope + dQin dT + – m(Qtr ) VGC Rs t) t t1 exp.tńt1 T (6) In reality, Qtr is not independent of temperature, in which case the Equation (6) must be modified by adding an additional term to become: slope + –m(Qtr ) VGC Rs t) t t1 exp.tńt1 T ) dQtr dT exptńt1 (7) Physically, not only does Qtr decrease with temperature so that dQtr/dT is a negative number, but also |dQtr/dTI decreased with temperature as does |dα/dTI in the tempera- ture range of interest. Equation (6) [or (7)] indicates two things: 1. The rate of change of input trigger charge decreases as temperature (life time) increases. 2. The larger the pulse width of gate trigger current, the faster the rate of change of Qin with respect to change in temperature. Figure 3.11 shows these trends. *VGC is not independent of IG. For example, for the MCR729 the saturation VGC is typically 1 V, but at lower IG’s the VGC is also smaller, e.g. for IG = 5 mA, VGC is typically 0.3 V.
- 236. http://onsemi.com 236 APPENDIX III TTL SOA TEST CIRCUIT Using the illustrated test circuit, the two TTL packages (quad, 2−input NAND gates) to be tested were powered by the simple, series regulator that is periodically shorted by the clamp transistor, Q2, at 10% duty cycle rate. By varying the input to the regulator V1 and the clamp pulse width, various power levels can be supplied to the TTL load. Thus, as an example, VCC could be at 5 V for 90 ms and 10 V for 10 ms, simulating a transient on the bus or a possibly shorted power supply pass transistor for that duration. These energy levels are progressively increased until the gate (or gates) fail, as detected by the status of the output LEDs, the voltage and current waveforms and the device case temperature. Figure 9.2. TTL SOA Test Circuit 1 k MJE220 Q1V1 VCC 2 W 220 5.6 V 1 W 1N4739 Q2 MJE230 VCC 1 k 2N3904 V1 100 μF V2 = 10 V 10 V 1N5240 10 M MC14011 470 Q3 3.9 M 0.1 μF 10 k 10 k 10 k 10 k10 k V2 V2 100 k 0.47 μF 1N914 1N914 2.2 M 1 k 2N3904 Q4 5 M500 k G1 G2 G3 G4 300 VCC VCC 300 LED LED 220 220 (2) MC7400 DUT SQUARE WAVE GENERATOR f [ 1 Hz 10% DUTY CYCLE GENERATOR T1 T2 5 ms T2 250 ms 50 ms T2 1.9 s 1A 2A 2D 1D
- 237. http://onsemi.com 237 APPENDIX IV SCR CROWBAR LIFE TESTING This crowbar life test fixture can simultaneously test ten SCRs under various crowbar energy and gate drive conditions and works as follows. The CMOS Astable M.V. (Gates 1 and 2) generate an asymmetric Gate 2 output of about ten seconds high, one second low. This pulse is amplified by Darlington Q22 to turn on the capacitor charging transistors Q1−Q10 for the ten seconds. The capacitors for crowbarring are thus charged in about four seconds to whatever power supply voltage to which VCC1 is set. The charging transistors are then turned off for one second and the SCRs are fired by an approximately 100 μs delayed trigger derived from Gates 3 and 4. The R−C network on Gate 3 input integrates the complementary pulse from Gate 1, resulting in the delay, thus insuring non−coincident firing of the test circuit. The shaped pulse out of Gate 4 is differentiated and the positive−going pulse is amplified by Q21 and the following ten SCR gate drivers (Q11−Q20) to form the approximate 2 ms wide, 1 μs rise time, SCR gate triggers, IGT. IGT is set by the collector resistors of the respective gate drivers and the supply voltage, VCC2; thus, for IGT ≈ 100 mA, VCC2 ≈ 30 V, etc. The LEDs across the storage capacitors show the state of the voltage on the capacitors and help determine whether the circuit is functioning properly. The timing sequence would be an off LED for the one−second capacitor dump period followed by an increasingly brighter LED during the capacitor charge time. Monitoring the current of VCC1 will also indicate proper operation. The fixture’s maximum energy limits are set by the working voltage of the capacitors and breakdown voltage of the transistors. For this illustration, the 60 V, 8400 μF capacitors (ESR ≈ 20 mΩ) produced a peak current of about 2500 A lasting for about 0.5 ms when VCC1 equals 60 V. Other energy values (lower ipk, greater tw) can be obtained by placing a current limiting resistor between the positive side of the capacitor and the crowbar SCR anode. Figure 9.3. Schematic for SCR Crowbar Life Test 10 k MJE803 MC14011B VDD 1N914 2.2 M +15 V 100 k 0.001 μF +15 V 22 M22 M 0.47 μF 2.2 k 2.2 k 2.2 k 2 W 2 W 2 W Q22 VSS 0.1 μF + 15 V 10 k 1N914 470 470 VCC1 VCC1 MJE803 Q21 MJE250 Q1 Q10 Q11 MJE250 MJE250 470 2.2 k VCC2 470 VCC2 270 2.7 k 1 W 5 W 100 5 W 100 2.7 k 1 W R1 270 2.2 k Q20 MJE250 8400 μF 8400 μF C1 C10(10) LED DUT #10 DUT #1 4 3 2 1
- 238. http://onsemi.com 238 APPENDIX V DERIVATION OF THE RMS CURRENT OF AN EXPONENTIALLY DECAYING CURRENT WAVEFORM Irms + 1 T ŕ i2(t)dtǸ T 0 + 1 T ŕ (Ipke–tńt)2dt 1ń2 T 0 + Ipk2 T e–2tńt (–2ńt) 1ń2 T 0 + Ipk2 T ǒ– t 2 Ǔ(e–2Tńt – e0) 1ń2 where T = 5τ, + – Ipk2 10 (e–10 – 1) 1ń2 Irms + Ipk 10Ǹ + 0.316 Ipk Ipk T = 5 τ i = Ipke−t/τ APPENDIX VI DERIVATION OF I2t FOR VARIOUS TIMES Thermal Equation Δt = Z(θ)PD where Z(θ) = r(t)RθJC and r(t) = K tǸ Therefore, for the same Δt, Dt + K t1 Ǹ RqJCPD1 + K t2 Ǹ RqJC PD2 , PD1 PD2 + t2 t1 Ǹ + I1 2 R I2 2R , I1 2 I2 2 + t2 t1 Ǹ Multiplying both sides by (t1/t2), I1 2 t1 I2 2t2 + ǒt2 t1 Ǔ 1ń2 t1 t2 + ǒt1 t2 Ǔ 1ń2 , I1 2t1 + I2 2t2 t1 t2 Ǹ
- 239. http://onsemi.com 239 APPENDIX VII THERMAL RESISTANCE CONCEPTS The basic equation for heat transfer under steady−state conditions is generally written as: q = hAΔT (1) where q = h = A = ΔT = rate of heat transfer or power dissipation (PD), heat transfer coefficient, area involved in heat transfer, temperature difference between regions of heat transfer. However, electrical engineers generally find it easier to work in terms of thermal resistance, defined as the ratio of temperature to power. From Equation (1), thermal resis- tance, Rθ, is Rθ = ΔT/q = 1/hA (2) The coefficient (h) depends upon the heat transfer mecha- nism used and various factors involved in that particular mechanism. An analogy between Equation (2) and Ohm’s Law is often made to form models of heat flow. Note that ΔT could be thought of as a voltage; thermal resistance corresponds to electrical resistance (R); and, power (q) is analogous to current (l). This gives rise to a basic thermal resistance model for a semiconductor (indicated by Figure 9.4). The equivalent electrical circuit may be analyzed by using Kirchoff’s Law and the following equation results: TJ = PD(RθJC + RθCS + RθSA) + TA (3) where TJ = PD = RθJC = RθCS = RθSA = TA = junction temperature, power dissipation, semiconductor thermal resistance (junction to case), interface thermal resistance (case to heat sink), heat sink thermal resistance (heat sink to ambient), ambient temperature. The thermal resistance junction to ambient is the sum of the individual components. Each component must be minimized if the lowest junction temperature is to result. The value for the interface thermal resistance, RθCS, is affected by the mounting procedure and may be significant compared to the other thermal−resistance terms. The thermal resistance of the heat sink is not constant; it decreases as ambient temperature increases and is affected by orientation of the sink. The thermal resistance of the semiconductor is also variable; it is a function of biasing and temperature. In some applications such as in RF power amplifiers and short−pulse applications, the concept may be invalid because of localized heating in the semiconduc- tor chip. Figure 9.4. Basic Thermal Resistance Model Showing Thermal to Electrical Analogy for a Semiconductor TC, CASE TEMPERATURE TJ, JUNCTION TEMPERATURE TS, HEAT SINK TEMPERATURE TA, AMBIENT TEMPERATURE RθSA RθCS RθJC REFERENCE TEMPERATURE PD
- 240. http://onsemi.com 240 APPENDIX VIII DERIVATION OF RFI DESIGN EQUATIONS The relationship of flux to voltage and time is E = N df dt or E = NAc dB dt since φ = BAc and Ac is a constant. Rearranging this equation and integrating we get: E dt = NAc (B2 − B1) = NAc Δ B (1)ŕ which says that the volt−second integral required deter- mines the size of the core. In an L−R circuit such as we have with a thyristor control circuit, the volt−second characteristic is the area under an exponential decay. A conservative estimate of the area under the curve may be obtained by considering a triangle whose height is the peak line voltage and the base is the allowable switching time. The area is then 1/2 bh or Eptr 2 . Substituting in Equation (1): (2) Eptr 2 + N Ac D B where: Ep is the peak line voltage tr is the allowable current rise time N is the number of turns on the coil Ac is the usable core area in cm2 Δ B is the maximum usable flux density of the core material in W/m2 Rewriting Equation (2) to change ΔB from W/m2 to gauss, substituting 2Ǹ Erms for Ep and solving for N, we get: N + 2 ErmsǸ tr 2 Ac D B 108 + 0.707 Erms tr 108 BMAX Ac Ac in this equation is in cm2. To change to in2, multiply Ac by 6.452. Then: (3)N + 10.93 Erms tr 106 BMAX Ac where: N is total turns Erms is line voltage tr is allowable current rise time in seconds BMAX is maximum usable flux density of core material Ac is usable core area in square inches Window area necessary is: (4)Aw = N Awire3 The factor of 3 is an approximation which allows for insulation and winding space not occupied by wire. Substituting equation (3) in (4): Aw + 10.93 Erms tr 106 BMAX Ac Awire 3 (The factor 10.93 may be rounded to 11 since two significant digits are all that are necessary.) The factor AcAw can easily be found for most cores and is an easy method for selecting a core. AcAw + 33 Erms trAwire 106 BMAX In this equation, the core area is in in2. To work with circular mils, multiply by 0.78 10−6 so that: AcAw + 26 Erms trAwire BMAX where Awire is the wire area in circular mils. Inductance of an iron core inductor is L + 3.19 N2 Ac 10–8 Ig ) 1c m Rearranging terms, Ig + 3.19 N2 Ac 10–8 L – 1c m APPENDIX IX BIBLIOGRAPHY ON RFI Electronic Transformers and Circuits, Reuben Lee, John Wiley and Sons, Inc., New York, 1955. Electrical Interference, Rocco F. Ficchi, Hayden Book Company, Inc., New York, 1964. “Electromagnetic−Interference Control,” Norbert J. Sladek, Electro Technology, November, 1966, p. 85. “Transmitter−Receiver Pairs in EMI Analysis,” J. H. Vogelman, Electro Technology, November, 1964, p. 54. “Radio Frequency Interference,” Onan Division of Studebaker Corporation, Minneapolis, Minnesota. “Interference Control Techniques,” Sprague Electric Company, North Adams, Massachusetts, Technical Paper 62−1, 1962. “Applying Ferrite Cores to the Design of Power Magnetics,” Ferroxcube Corporation of America, Saugerties, New York, 1966.