Unit v.tms320 cs6x
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This document summarizes the TMS320C6X digital signal processor (DSP) architecture. It describes the key features of the TMS320C6X including its advanced very long instruction word (VLIW) architecture that can execute up to eight 32-bit instructions per cycle, achieving speeds up to 6000 million instructions per second. The CPU contains eight functional units including two multipliers and six arithmetic logic units. It also has 32 or 64 general purpose registers depending on the specific chip. The internal architecture includes the 32-bit CPU, on-chip program and data memory, and on-chip peripherals.
Unit v.tms320 cs6x
- 1. UNIT V: TMS320C6X By: Dr.Sudhir N. Shelke Principal, Guru Nanak Institute of Technology, Nagpur
- 2. Introduction • The TMS320C6X DSP uses VelociTI architecture, the first DSP to use advanced VLIW architecture to achieve high performance through instruction parallelism. • The VelociTI architecture is a highly deterministic architecture having reduced code size. • The TMS320C62X, TMS320C64X, TMS320C67X are family of DSPs in 6X generation. • The C62X & C64X are fixed point DSPs & C67X are floating point DSPS. Dr. Sudhir N Shelke 2
- 3. Features of TMS320C6X • The C6X devices execute up to eight 32 instructions per cycle with execution speed of 6000 Million instructions per second. • The C6X CPU(advanced VLIW) consist of • Eight Functional Units • Two Multipliers • Six ALUs & some general purpose registers • The CPU of C62X(Fixed Point) & C67X(Floating Point) device consists of 32 general purpose registers of 32 bits , where as C64X devices have 64 general purpose registers of 32 bit size. • Efficient Code execution of independent functional units. • Conditional Execution of all Instructions. • Support 8/16/32-bit data format.Dr. Sudhir N Shelke 3
- 4. Internal Architecture Dr. Sudhir N Shelke 4
- 5. The C6X device contains: 32 bit CPU On Chip Program & Data Memory On Chip Peripherals (EMIF, DMA, McBSP, HPI) Legends: External Memory Interface (EMIF),DMA(Direct Memory Access),Multi channel buffered serial port (McBSP),Host Port interface(HPI) Dr. Sudhir N Shelke 5
- 6. 32 bit CPU Program Fetch Unit Instruction Dispatch Unit Instruction Decode Unit 2 Data paths Register File for each data path Control Registers Control Logic Dr. Sudhir N Shelke 6
- 7. CPU 1. The C6X is based on advanced VLIW architecture ,which accepts eight 32 bit instructions at a time. 2. Program fetch unit generate the address of eight instruction and send it to the program memory for each packet fetch. 3. Instruction Dispatch Unit: receives the fetch packet and split it into execute packets. 4. Data path: the instruction in the execute packet(8 Ins) are assigned to the appropriate 8 functional units in the data path. 5. Control registers: During the instruction decode, the source registers, destination registers, and associated paths are decoded for the execution of the instruction in the functional units. 6. Finally, The instructions are executed by functional units. 7. The functional units are divided into two groups of four. 8. The .L, .S .D units are arithmetic & logic units & .M unit is multiplier unit. Dr. Sudhir N Shelke 7
- 8. Functional Units •Performs the arithmetic & logical instructions .L Unit •Performs the arithmetic & logical instructions as well as branch ,shift, move operations..S Unit •Performs add & sub operations . Dedicated for load store operations, linear & circular address calculations..D Unit • Dedicated to perform Multiply Operations .M Unit Dr. Sudhir N Shelke 8
- 9. Functional Units • The C6X CPU consists of eight functional units .L1 .S1 .M1 .D1 .L2 .S2 .M2 .D2 Dr. Sudhir N Shelke 9
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- 12. General Purpose Register File C62X/C67X each register file contains 16 number of 32 bit registers. A0-A15 for register file A B0-B15 for register file B C64X Each register file contains 64 number of 32 bit registers A0-A31 for register file A B0-B31 for register file B Dr. Sudhir N Shelke 12
- 13. Thank YOU!! Dr. Sudhir N Shelke 13