Assic 8th Lecture
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This document discusses behavioral modeling in Verilog using procedures. It covers: 1. Procedures are sections of code intended for a specific task and execute sequentially like hardware blocks. 2. Modules can contain multiple procedures that execute concurrently. Everything in behavioral modeling uses procedural blocks. 3. Procedural blocks can use "initial" blocks that execute once at time zero or "always" blocks that execute forever during simulation. Initial blocks are for test benches while always blocks model hardware.
Assic 8th Lecture
- 1. 1 Verilog HDLVerilog HDL ASIC DESIGN USING FPGA BEIT VII KICSIT Sept 19 2012 Lecture 8
- 2. 2 Behavioral Model - Procedures Sept 19 2012 • Sections of code intended for a specific task. • Similar to a Hardware block. • Procedural statements • statements inside a procedure. • they execute sequentially. • e.g. 2-to-1 mux Lecture 8
- 3. 3 Behavioral Model - Procedures Sept 19 2012 • Modules can contain any number of procedures • Procedures execute in parallel (in respect to each other) • In behavioral modeling, everything comes in a procedural block Lecture 8
- 4. 4 Behavioral Model - Procedures Sept 19 2012 • Procedural block can be expressed in two types of blocks: • initial → they execute only once • always → they execute forever (until simulation finishes) Lecture 8
- 5. 5 “Initial” Blocks Sept 19 2012 • This block starts with initial keyword • This is not used in RTL • This is non synthesizable • All initial blocks execute concurrently in order independent • They execute only once • This block is used only in Test Bench Lecture 8
- 6. 6 “Initial” Blocks Sept 19 2012 • Start execution at sim. time zero and finish when their last statement executes. module nothing; initial $display (“I’m the first”); initial begin #50; $display(“Really?”); end endmodule Lecture 8
- 7. 7 “Always” Blocks Sept 19 2012 • This block starts with always keyword • This block is more like H/W. • Always Blocks execute forever until simulation finishes. • The always block can be viewed as continuously repeated activity in a digital circuit starting from power on. Lecture 8
- 8. 8 “Always” Blocks Sept 19 2012 • Start execution at sim time zero and continue until sim finishes. Lecture 8
- 9. 9 Procedural assignments Sept 19 2012 • Blocking assignment = • Regular assignment inside procedural block • Assignment takes place immediately • LHS must be a register Lecture 8
- 10. 10 Procedural assignments Sept 19 2012 • Nonblocking assignment <= • Compute right hand side • Assignment takes place at the end of block • LHS must be a register Lecture 8
- 11. 11 Procedural assignments Sept 19 2012 • Nonblocking statements are used; • whenever it is desired to make several register assignments within the same time step without regard to order or dependence upon each other. • They are executed in two steps: • The simulator evaluates the RHS. • The assignment occurs at the end of the time step. Lecture 8
- 12. 12 Procedural assignments Sept 19 2012 • The order of concurrent evaluation is indeterminate • Concurrent blocking assignments have unpredictable results always @(posedge clk) #5 A = A + 1; always @(posedge clk) #5 B = A + 1; • new value of B could be evaluated before or after A changes Lecture 8
- 13. 13 Procedural assignments Sept 19 2012 • Concurrent non-blocking assignments have predictable results always @(posedge clk) #5 A <= A + 1; always @(posedge clk) #5 B <= A + 1; • New value of B will always be evaluated before A changes. Lecture 8
- 14. 14 Example: Blocking/Non-blocking Sept 19 2012 Lecture 8