Evatronix track h
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The document discusses software-based verification and firmware development. It summarizes Evatronix's work developing IPs and drivers for hardware/software convergence. It describes building a testbench environment in SystemC to functionally verify IPs using ANSI C tests, which can then be reused from virtual prototyping to FPGA prototypes. The document also outlines developing a USB mass storage firmware in C using various abstraction layers, starting in the verification environment and finishing on an FPGA prototype with few modifications.
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Evatronix track h
- 1. From Software Based Verification to Firmware Development Ireneusz Sobański Evatronix SA
- 2. Outline About Evatronix Hardware/Software Convergence USB Mass Storage Application Test Bench Environment Overview Software Based Verification Firmware Development Summary
- 3. Company Overview Set up in 1997, over a dozen years of IP experience Over 400 successful silicon designs to date More than 30 products in the IP catalog 8051, USB, NAND Flash, SDIO, Multimedia 70+ experienced engineers Member of many technical organizations USB-IF, SD Card Association, OCP-IP and other Active participation in European projects
- 4. Demands for SoC Users expect interface flexibility Communication Devices (Ethernet, Bluetooth, …) Peripheral Devices (USB, SDIO, SPI, …) Mass Storage (HDD, Flash, …) Applications need computational power Display Acceleration (MPEG, 3D, …) Cryptographic Devices (3DES, AES, …) SoC suppliers must balance the cost (M$) One SoC – many applications More functionality goes to software (RT)OS gain in popularity (flexibility & cost !)
- 5. Hardware/Software Convergence Hardware/software meeting Software plays the glue logic role (communication) Hardware accelerates software routines (computation) In both cases every IP needs a DRIVER! Requirements for IP provider Drivers become the integral part of the hardware IP Integration verification facilities (integration tests) Support for virtual prototyping (TLM models)
- 6. External hard disk example Microprocessor USB Protocol layer USB PHY layer SATA device USB HAL USB Framework USB Mass Storage Layer SATA Stack Software Stack
- 7. TB Environment Overview General objectives Support for virtual prototyping (TLM Model) Layered architecture (link/protocol/…) Extensive usage of randomization Self checking testbench Functional coverage Further goals Early software development (before FPGA) Software based tests (reused on prototyping)
- 8. TB Architecture (SystemC)
- 9. Software Based Verification Drive & test DUT with (ANSI) C functions Provides functional verification of the DUT By default runs in native mode (on the PC) ANSI C guarantees portability Reuse in an FPGA prototype Can be compiled for the CPU (real device) Some tests may be reused at this stage Reuse at the system integrator’s site Can be compiled for the CPU (ISS model) Simplify tests reuse
- 10. TB Environment issues Mimic CPU mechanisms program/interrupts switching Choose memory modeling method physical memory/memory model Define DUT access through macros Access through address / function call Assign portable layers Hardware Abstraction Layer for device management Manage randomization routines All SCV (SystemC) must be outside of the HAL
- 11. Software Tests Architecture Regs Access USB Endpoint Data USB Framework Test (randomization, configuration, direct tests) Interrupts Regs Access CPU (switch) MEM (physical memory) OCP-IP OCP-IP SystemC SystemC USB Host
- 12. Firmware Development USBSS Mass Storage Firmware USB device registers access (USB HAL) USB endpoint data manipulation (USB HAL) USB framework (USB Stack) USB Mass Storage Class (Firmware) Disk abstraction layer (Disk HAL) RAM disk (emulation functions) ATA device driver (ATA HAL) Software development flow Start i n a virtual prototype (in verification environment) Finish i n an FPGA prototype (with single modifications)
- 13. Firmware Architecture Regs Access USB Endpoint Data USB Mass Storage Class USB Device Framework Disk Abstraction Layer Firmware (main) RAM Disk emulation SATA Stack Regs Acc.. USB SS -DEV RAM ATA-IF
- 14. Summary Use of C in verification process is not a new idea Software based verification brings new benefits The same tests for TLM/RTL/FPGA prototype… Not everything is ideal Perfect for normal work, but not for corners Randomization must be done carefully Good starting point for software development Basic tests could be run in an FPGA prototype Hardware Abstraction Layer is fully reusable The firmware is truly verified and ahead of schedule
- 15. Thank You [email_address] www.evatronix-ip.com