Magma trcak b
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1) Timing closure is becoming increasingly challenging due to rising complexity in chip designs including more process variations, operational modes, and timing scenarios. 2) Traditional multi-machine signoff approaches are inefficient for advanced nodes below 28nm. A new single-machine timing closure approach enables concurrent multi-mode multi-corner analysis and layout-aware ECO optimization. 3) Tight integration of placement and routing, statistical timing analysis, and extraction allows for faster turnaround times, more accurate signoff, and reduced design margins and ECO cycles.
Magma trcak b
- 1. Timing Closure Using One Machine Rajeev Madhavan Chairman and CEO Magma Design Automation May 4, 2010
- 2. New Challenges for Digital Design Improved productivity required to meet market-driven design costs and schedules 1997 2001 2004 2008 2010 Silicon Tech. 250nm 130nm 90nm 45nm 32nm Max Design (Inst.) 1M 4M 12M 16M >50M Functional Modes 2 3 4 5 >10? Power Consumption 1W 500mW 200mW 50mW <25mW? Parasitics C L C L R L C C R D C C , R D C CVia , R DVia Process Variation 1X 1.1X 1.4X 1.8X >2X? Nominal Yield 95% 85% 75% 50% %? Investment $2M $5M $20M $50M $100M? Engineers 2 5 10 25 50? Productivity 1X 1.5X 2X 3X 5X?
- 3. Digital Design Complexity Increasing Exponentially Operational Modes: 5 @ 65nm 15 @ 22nm PVT Corners: 25 @ 65nm 50 @ 22nm Increasing Gate Count Multi-Modes Multi-Corners More Timing Scenarios Gate Count: 20M @ 65nm 400M @ 22nm
- 4. 28nm Challenges: Rising # of PVT Corners & Modes Temperature 125 o C 0 o C 40 o C Process SS Typ FF Interconnect C max C typ C min Voltage .94V 1.34V 1.025V Func_setup Func_hold Func_bypass_setup Func_bypass_hold Scan_hold Scan_setup Scan_capture_hold Scan_capture_setup Bist_hold Bist_setup Bist_pll_setup Bist_pll_hold Pbist_hold Pbist_setup Low_power_setup Low_power_hold Tfault_shift_setup Tfault_shift_hold Tfault_capture_setup Tfault_capture_hold DDR_write_setup DDR_write_hold DDR_read_setup DDR_read_hold Many Corners Many Modes Increase in process variation requires multiple PVT corners Greater functionality requires multiple modes Many more timing scenarios required for signoff
- 5. 28nm Challenges: Pessimistic OCV Margins OCV Margins Lead to PRO: More robust design CON: AREA Increase - More buffers - Larger cells CON: Worse TAT - More timing fixes Traditional OCV margins are too pessimistic Setup: 12% Hold: 8% Setup: 12% Hold: 8% Setup: 12% Hold: 8%
- 6. Solving the increasing variability problem Approach 1 - SSTA Block based and path based SSTA Challenges in characterization New approach – analyzing, interpreting statistical data No real integration to P&R, STA, extraction
- 7. Solving the increasing variability problem Approach 2 - Enabling Timing Closure in 1 Computer Breakthrough in STA Performance for large designs New approach to MMMC No new learning curve Tight integration: P&R, STA, extraction Reduce ECO fixes
- 8. New STA Architecture Required to Address Complexity Old STA architectures exhibit performance problems on a single CPU for designs with: - large # of instances - large # of constraints New STA Architecture enables single-CPU performance that scales with design sizes that are increasing by 2x every 18 mos Minutes 1 10 Millions of Instances 5 60 Hours New STA architecture’s single CPU scales well for any design
- 9. New STA Architecture Near-linear Multi-threading New Architecture combines single-CPU performance and near-linear scaling for multi-CPU machine Minutes 1 10 Millions of Instances 5 60 Hours Single CPU Performance 3x on 4-CPUs 6x on 8-CPUs 4-CPU 8-CPU
- 10. 28nm Solution: The Future of MMMC is on One Machine Traditional MMMC - Lots of reports - Lots of machines - Lots of ECO’s Concurrent MMMC - One Machine ... Scenario 1 Scenario 4 Scenario 3 Scenario 2 Scenario 5 Scenario n Scenario 7 Scenario 6 SDC-1 SDC-n spef-1 spef-n LIB-1 LIB-n 1 Server ... ... ...
- 11. 28nm Solutions: Concurrent MMMC on a Single Machine set modes "func bisr_g0 bisr_g1 bisr_g1_pll bisr_g3 bisr_g4 mbist scan_bisr scan_bisr_shift scan_flush_shift scan scan_shift" foreach mod $modes { force timing scenario create $m ${mod}_scenario –mode $mod –enable –check both –ocv on –crpr on –xtalk on } enable/disable setup/hold/both on/off on/off on/off Flexible configuration of timing scenarios (timing modes * PVT corners) One script no no no Configure “on-the-fly” – with updated results in seconds 1 Server setup hold setup
- 12. MMMC Cockpit Enables Fast Analysis, Efficient ECO’s All Timing Scenarios on One Machine MMMC Cockpit: Pre-ECO Implement ECOs for all timing modes, PVT corners on One Machine 1 Server MMMC Cockpit: Post-ECO
- 13. 28nm Solutions: Tight Integration of P&R, Extraction, and STA Traditional Approach: Separate extraction & STA tools result in TCL-based “What-if” ECO’s Timing Closure on One Machine: Layout-aware ECO’s New Approach: Tight P&R & extraction & STA integration results in faster, more accurate ECO’s Extraction tool P&R tool P&R ECO Cycles Sign-off Tapeout Extraction STA
- 14. 28nm Solutions: Reducing Timing Margins Larger Die Size More timing fixes Setup: 12% Hold: 8% Setup: 12% Hold: 8% Setup: 12% Hold: 8% Smaller Die Size Less timing fixes Setup: 12% Hold: 6% Setup: 10% Hold: 7.8% Setup: 10.3% Hold: 6.2% Traditional OCV Advanced OCV
- 15. 28nm Solutions: SPICE Reduces Timing Margins Smaller geometries & increased design complexity force designers to pad timing analysis with margins Integrated SPICE engine enables Reduced margins Increased accuracy SPICE Models Process Variation Cell Characterization NLDM/CCSModels Sign-off Characterization Margin Modeling Margin Design Margin + + = over design! Design Critical paths
- 16. Summary Timing closure on one machine: The Future is Now Breakthrough in STA MMMC timing closure on one machine Tight integration of P&R, STA, and extraction Reduce margins, reduces ECO fixes Extraction tool P&R tool
Editor's Notes
- #4: Gate count is Max gate count, our estimate. Cisco will move from 20M gates @ 65nm to 60M gates @ 40nm. Corners & modes example is actual TI data.
- #16: These are the design margins that designer’s use to make sure the design will work. These are pointed out in the Chip picture graphic: Process variation OCV margins Any interface Margin-based interfaces IP integration IP models (with margin)