Xilinx track g
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1. FPGAs allow balancing computation between an embedded processor and custom application-specific data processing pipelines. 2. Offloading streaming data tasks to an FPGA data plane can meet performance needs by freeing the processor for other tasks. 3. An FPGA implementation combining an embedded processor control plane and custom data plane reduces costs and development time compared to separate chips.
Xilinx track g
- 1. Managing High Performance Data Pipeline Execution with an FPGA Processor Presenter: Ben Hor – Xilinx, Inc Authors: Glenn Steiner, Dan Isaacs – Xilinx, Inc. David Pellerin – Impulse Accelerated Technologies
- 2. Agenda What is Control Plane/Data Plane Processing and Why Might I Need It? FPGA’s Enable Balancing Computation Between a Processor and Application Specific Logic Implementation of a Control/Data Plane System is Straightforward Case Study: An HD Video Recognition System Connecting the Embedded Processor to the FPGA with Linux Summary
- 3. What is Control Plane / Data Plane Processing and Why Might I Need It?
- 4. Challenge Example: HD Video Streaming 720P 74.25 MHz Pixel Rate 222.75 MBs data rate Hypothetical Dual Core – 2.5GHz, Dual Issue (2 instructions per clock) 10 GHz Instruction Rate 22.4 instructions per byte of data processed What about OS overhead Task switching times Interrupt latency All bus bandwidth eaten up with video data Can’t Do It With a Standard Processor
- 5. Coprocessing: An Effective Way of Accelerating Software Distributes the load Move computational load where it belongs Dedicated processing element(s) provide dramatic acceleration
- 6. A Look at Coprocessing Architectures Fully Decoupled Common, but not interesting for this topic Single / Multi-Instruction Accelerator FPU Loosely Coupled - Separated Functions Message / Control Passing Typically Used for Control Plane / Data Plane Processing
- 7. What is Control Plane / Data Plane Data In Data Out User Interface Processor Bus or Dedicated Control Channel(s) Control Plane Data Plane Control Plane Processor (OS) Coprocessor Coprocessor Coprocessor
- 8. Control / Data Plane Example Control plane: controls the state of network elements Route selection RSVP, capability signaling, etc. Exception handling Data plane: manages data packets Packet forwarding Packet differentiation Buffering, link scheduling Adapted from: Active correlation between the control and data plane – Z. Morley Mao
- 9. FPGA’s Enable Computation Balancing Between a Processor and Application Specific Logic
- 10. FPGAs: Ideal for Coprocessing Tight integration between FPGA & Processor Reduced Latency Matched clock rates Configure the processors to meet system requirements Configure Processors Configure the Coprocessors Flexible logic enables experimentation
- 11. External Processor Challenges Latency for control signals to coprocessor Pin challenges Many pins reduce latency but at higher power & part cost High speed serial (PCIe) minimizes pins at cost of latency & power May not be the lowest cost solution FPGA embedded processors solve these challenges and enable performance balancing
- 12. Implementation of A Control Plane / Data Plane System is Straight Forward
- 13. Building The Control Plane / Data Plane System Assemble the Control Plane processor Assemble the Data Pipeline Combining IP generated by multiple tools C to HDL Tools may be an effective option Control the Pipe with Processor and OS
- 14. Assemble the Control Plane Processor
- 17. Multiple Languages/Tools/Flows to create Coprocessors Low Level Hand Crafted - RTL (VHDL/Verilog) High Level Matlab / Simulink ‘ C’ to FPGA (HDL) ‘ C’ Variants Assemble and Connect the Data Plane
- 18. CASE STUDY: HD VIDEO RECOGNITION SYSTEM
- 19. The Case Study Problem 720P HD Video Stream DVI Input and DVI Output Locate the clown fish in the video Highlight the clown fish Continuously track the fish Adjust spotlight size based upon likelihood of match
- 20. The Architected Solution How Control Plane Processor Was Created How the Data Processing Pipeline Was Created
- 21. Base Processor Reference Design Linux Xilinx MicroBlaze Processor Block RAM SystemAce Compact Flash ICC GPIO LEDs GPIO DIP Switch Debug Module UART Multiport Memory Controller DDR2 Memory GPIO Push Buttons Clock Generator Reset Module
- 22. DVI Pass-through Reference Design Basic “real-time” video processing DVI Input DVI Output Image Processing
- 23. DVI Pass-through Reference Design Basic “real-time” video processing Image Processing DVI Input DVI Output Streaming pixel processing Streaming video data MicroBlaze controls filter coefficients in “real-time” Simple design example for customer IP integration System Generator Custom video accelerator pcore
- 24. Integrated Control/Data Plane System DVI The processor is used to dynamically configure filters Processor Local Bus (PLB) DVI Filter control (UART) New Pipeline Element DVI In Gamma In Gamma Out DVI Out Xilinx MicroBlaze Processor System 2D FIR Filter Object Detection
- 25. HD Object Detection & Highlighting
- 26. Connecting the Embedded Processor to the FPGA with Linux
- 27. Control the Pipe with Linux Linux is Now the #1 OS for Embedded FPGA Systems Newest Generation Is More “Real-Time” Large Public Code Base Mostly Free FPGA IO Drivers Available
- 28. Configure Linux for the IO Device // Load the custom driver into Linux kernel module_init(xll_example_init); // Register driver to specific device number - 253 err = register_chrdev_region(devno, 1, "custom_io_example"); bash# mknod /dev/custom_io_example0 c 253 0
- 29. Controlling the Data Pipe with the Linux Application // Open custom I/O device from Linux application int custom_io_ex_ open (struct inode *inode, struct file *filp) // Read / Write to custom peripheral I/O using standard Linux read/function function calls ssize_t custom_io_ex_ read (struct file *filp, char __user *buf, size_t count, loff_t *f_pos) ssize_t custom_io_ex_ write (struct file *filp, const char __user *buf, size_t count, loff_t *f_pos)
- 30. SUMMARY FPGAs enable computational balancing between an FPGA based processor and a data processing pipeline reducing development risks Offloading streaming data processing tasks to an FPGA data-plane processing pipeline can enable meeting performance objectives An FPGA based single chip control-plane and data-plane processing solution can reduce cost and development time Offloading enables Processor to handle multitude of other tasks
- 31. Thank You Glenn Steiner, Dan Isaacs – Xilinx, Inc. David Pellerin – Impulse Accelerated Technologies
Editor's Notes
- #23: Example of a “real-time” non-frame buffer based processing solution. There are several products that require a specialized streaming processing, and this example provide a quick and easy method for the developer to quickly the existing design with their algorithm. The fully integrated HW-CoSim environment enables a faster validation cycle with the hardware in the loop functionality.
- #24: DE Gen - Data Enable Generator - Example of a “real-time” non-frame buffer based processing solution. There are several products that require a specialized streaming processing, and this example provide a quick and easy method for the developer to quickly the existing design with their algorithm. The fully integrated HW-CoSim environment enables a faster validation cycle with the hardware in the loop functionality.